HS-26CLV31RH_12 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Electrically screened to SMD # 5962-96663
- QML qualified per MIL-PRF-38535 requirements
- 1.2 micron radiation hardened CMOS - Single event latch-up immune IH > (0.7)(VDD); VIL < (0.3)(VDD)
- High impedance outputs when disabled or powered down
- Full -55°C to +125°C military temperature range
- Pb-Free (RoHS Compliant)
Applications
- Line transmitter for MIL-STD-1553 serial data bus
Ordering Information
(Note) INTERNAL MKT. NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962F9666302QEC HS1-26CLV31RH-8 Q 5962F96 66302QEC -55 to +125 16 Ld SBDIP D16.3 5962F9666302QXC HS9-26CLV31RH-8 Q 5962F96 66302QXC -55 to +125 16 Ld FLATPACK K16.A 5962F9666302VEC HS1-26CLV31RH-Q Q 5962F96 66302VEC -55 to +125 16 Ld SBDIP D16.3 5962F9666302VXC HS9-26CLV31RH-Q Q 5962F96 66302VXC -55 to +125 16 Ld FLATPACK K16.A 5962F9666302V9A HS0-26CLV31RH-Q -55 to +125 Die HS1-26CLV31RH/PROTO HS1-26CLV31RH/PROTO HS1-26CLV31RH/PROTO -55 to +125 16 Ld SBDIP D16.3 HS9-26CLV31RH/PROTO HS9-26CLV31RH/PROTO HS9-26CLV31RH/PROTO -55 to +125 16 Ld FLATPACK K16.A 5962F9666304VEC HS1-26CLV31EH-Q Q 5962F96 66304VEC -55 to +125 16 Ld SBDIP D16.3 5962F9666304VXC HS9-26CLV31EH-Q Q 5962F96 66304VXC -55 to +125 16 Ld FLATPACK K16.A 5962F9666304V9A HS0-26CLV31EH-Q -55 to +125 Die HS0-26CLV31RH/SAMPLE HS0-26CLV31RH/SAMPLE -55 to +125 Die NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. December 12, 2012 FN4898.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc.2000, 2008, 2009, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
HS-26CLV31RH, HS-26CLV31EH Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4898.3 December 12, 2012 For additional products, see www.intersil.com/product_tree Pin Configurations HS1-26CLV31RH, HS1-26CLV31EH (16 LD SBDIP) CDIP2-T16 TOP VIEW HS9-26CLV31RH, HS9-26CLV31EH (16 LD FLATPACK) CDFP4-F16 TOP VIEW Logic Diagram AIN AO AO ENABLE BO BO GND BIN VDD DO DO ENABLE CO CO CIN DIN AIN AO AO ENABLE BO BO BIN GND 11 6 VDD DIN DO DO ENABLE CO CO CINENABLE ENABLE AIN AO BIN BO CIN CO DIN DO DO CO BO AO
TABLE 1. HS-26CLV31RH, HS-26CLV31EH PAD COORDINATES