HS-26C32RH RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Renesas Electronics Corporation
- PDF pages: 9
Technical content
Features
- Electrically screened to SMD # 5962-95689
- QML qualified per MIL-PRF-38535 requirements
- 1 . 2 m i c r o n r a d i a t i o n h a r d e n e d C M O S
- EIA RS-422 compatible inputs
- CMOS compatible outputs
- I n p u t f a i l - s a f e c i r c u i t r y
- High impedance inputs when disabled or powered-down
- Low power dissipation 138mW standby (max)
- Radiation acceptance testing - HS-26C32RH
- Radiation acceptance testing - HS-26C32EH 2/mg
- Full -55°C to +125°C military temperature range
- Pb-free (RoHS compliant)
HS-26C32RH, HS-26C32EH FN3402 Rev 6.00 Page 2 of 8 Oct 21, 2021
Ordering Information
NUMBER (Note 1)P A R T N U M B E R ( Note 2) RADIATION HARDNESS (Total Ionizing Dose) PACKAGE DESCRIPTION (RoHS COMPLIANT) PKG. DWG. # CARRIER TYPE TEMP. RANGE 5962F9568901QEC HS1-26C32RH-8 HDR to 300krad( Si) 16 Ld SBDIP D16.3 Tube -55 to +125°C 5962F9568901QXC HS9-26C32RH-8 16 Ld FLATPACK K16.A Tray 5962F9568901VEC HS1-26C32RH-Q 16 Ld SBDIP D16.3 Tube 5962F9568901VXC HS9-26C32RH-Q 16 Ld FLATPACK K16.A Tray 5962F9568901V9A HS0-26C32RH-Q ( Note 3 )D i e N / A N / A 5962F9568901VYC HS9G-26C32RH-Q ( Notes 4, 5) 16 Ld FLATPACK K16.A Tray N/A HS0-26C32RH/SAMPLE (Notes 3, 5) N/A Die N/A N/A HS1-26C32RH/PROTO (Note 5) 16 Ld SBDIP D16.3 Tube HS9-26C32RH/PROTO (Note 5) 16 Ld FLATPACK K16.A Tray HS9G-26C32RH/PROTO (Notes 4, 5) 16 Ld FLATPACK K16.A Tray 5962F9568903VEC HS1-26C32EH-Q HDR to 300krad(Si) LDR to 50krad(Si) 16 Ld SBDIP D16.3 Tube 5962F9568903VXC HS9-26C32EH-Q 16 Ld FLATPACK K16.A Tray 5962F9568903V9A HS0-26C32EH-Q ( Note 3)D i e N / A N / A NOTES: 1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. 2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb- free soldering operations. 3. Die product tested at T A = + 25°C. The wafer probe test includes functional and parametric testing sufficient to make the die capable of meeting the electrical performance outlined in SMD. 4. The lid of these packages are connect ed to the ground pin of the device. 5. The /PROTO and /SAMPLE are not rated or certified for Total Ioni zing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the DLA SMD. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types do not come with a certificate of conformance because they are not DLA qualified devices.
- For details on input output stru ctures refer to application note AN9520.
- For details on package dimensions refer MIL-STD-1835.
TABLE 1. TRUTH TABLE
TABLE 4. HS-26C32RH, HS-26C32EH PAD COORDINATES
HS-26C32RH, HS-26C32EH FN3402 Rev 6.00 Page 6 of 8 Oct 21, 2021 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Oct 21, 2021 6.00 In the Features section on page 1 added Ra diation acceptance testing bullets for RH and EH parts. Updated Ordering Information table on by adding carrier type and radiation testing information columns, verified part numbers in table are correct, and added Notes 1, 3, and 5. Added Notes 6 and 7. Added Truth Table. Updated the Die Characteristics information as follows: -Updated die dimensions -Updated Glassivation Type and Thickness -Updated Metallization M1 thickness by adding ±1kÅ and updated M2 thickness to 10kÅ ±1kÅ -Updated Worst Case Current Density -Added Substrate, Backside finish, Substrate potential, and Transistor count Added Table 4 to the Metallization Mask Layout section. Added Revision History. Added POD drawings.
HS-26C32RH, HS-26C32EH FN3402 Rev 6.00 Page 7 of 8 Oct 21, 2021 Package Outline Drawing For the most recent package outline drawing, see K16.4. K16.A
16 Lead Ceramic Metal Seal Flatpack Package
Rev 2, 1/10 SIDE VIEW TOP VIEW SECTION A-A -D- -C- SEATING AND BASE PLANE -H- BASE LEAD FINISH METAL PIN NO. 1 ID AREA 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 BSC) 0.440 (11.18) 0.005 (0.13) MIN MAX 0.115 (2.92) 0.026 (0.66) 0.285 (7.24) 0.245 (6.22) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) MIN 0.13 (3.30) MIN 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 LEAD FINISH adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. shall be molded to the bottom of the package to cover the leads. meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. NOTES: Dimensioning and tolerancing per ANSI Y14.5M - 1982. Controlling dimension: INCH. Index area: A notch or a pin one identification mark shall be located If a pin one identification mark is used in addition to a tab, the limits Measure dimension at all four corners. For bottom-brazed lead packages, no organic or polymeric materials Dimension shall be measured at the point of exit (beyond the
HS-26C32RH, HS-26C32EH FN3402 Rev 6.00 Page 8 of 8 Oct 21, 2021 For the most recent package outline drawing, see D16.3. NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa CA - BM DS Sccc CA - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 Lead Ceramic Dual-In-Line Metal Seal Package
(SBDIP) SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N1 6 1 6 8 Rev. 0 4/94
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