HS-2520RH INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Electrically Screened to SMD # 5962-95685
  • QML Qualified per MIL-PRF-38535 Requirements 4RAD(Si)

Applications

  • Data Acquisition Systems
  • RF Amplifiers
  • Video Amplifiers
  • Signal Generators
  • Pulse Amplifiers

Ordering Information

MKT. NUMBER TEMP. RANGE (oC) HS0-2520RH-Q HS0-2520RH-Q 25 5962D9568501VGA HS2-2520RH-Q -55 to 125 5962D9568501VPA HS7-2520RH-Q -55 to 125 5962D9568501VPC HS7B-2520RH-Q -55 to 125 Pinouts HS7-2520RH (CERDIP) GDIP1-T8 OR HS7B-2520RH (SBDIP) CDIP2-T8 TOP VIEW HS2-2520RH (CAN) MACY1-X8 TOP VIEW COMP OUT BAL BAL -IN +IN COMP OUTIN- BAL IN+ BAL Data Sheet August 1999

FIGURE 1. SIMPLIFIED TEST CIRCUIT FIGURE 2. SLEW RATE WAVEFORM FIGURE 3. TRANSIENT RESPONSE WAVEFORM NOTE: Measured on both positive and negative transitions. Capacitance at Compensation pin should be minimized. FIGURE 4. INPUT BIAS AND OFFSET CURRENT vs FIGURE 5. EQUIVALENT INPUT NOISE vs BANDWIDTH

0 SOURCE RESISTANCE

NOTES: 1. R1 = 1MΩ ,±5%, 1/4W (Min) 2. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min) 3. C3 = 0.01µF (±10%)/Socket 4. D1 = D2 = 1N4002 or equivalent (per board) HS2-2520 METAL CAN NOTES: 6. R1 = 1MΩ ,±5%, 1/4W (Min) 7. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min) 8. C3 = 0.01µF (±10%)/Socket 9. D1 = D2 = 1N4002 or equivalent (per board) C2D2 C1 D1 C2 D2 Irradiation Circuits IRRADIATION CIRCUIT NOTES: 11. V1 = +15V±10% 12. V2 = -15V±10% 13. C = 0.1µF ±10% C C 1M Ω -5% (1/4W MIN) C BAL COMP +IN -IN BAL OUT HS-2520RH

+INPUT -INPUT OFFSET Q30 Q22 Q14 Q28 Q3A Q3B Q4A Q4B Q1BQ1A Q2BQ2A Q21A Q21B Q18 Q19 Q20 R6A R18 30Q8 Q11B Q12B R2B 1.8K R2A 1.8K Q12A OUTPUTQ13B R17 1pF Q15 R11 200 R21 R13 Q16 R15 11.13K R16 960 200 R2A 200 R2B R12 200 R20 Q23 1.1K R10 740 R19 1.48K R3B 1.48K R3A 1.48K 1.68K R1A R1B 1.68K R6B BW CONTROL OFFSET Q13A HS-2520RH

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 65 mils x 50 mils x 19 mils (1660µm x 1270µm x 483µm) INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 7kÅ ±0.7kÅ Top Metallization: Type: Aluminum Thickness: 16kÅ ±2kÅ Substrate: Linear Bipolar, DI Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential(Powered Up): Unbiased ADDITIONAL INFORMATION: Worst Case Current Density: <2 x 105 A/cm2 Transistor Count: Metallization Mask Layout HS-2520RH -IN COMP +INBAL OUT BAL HS-2520RH