HS-1825ARH INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Electrically Screened to DESC SMD # 5962-99558
- QML Qualified per MIL-PRF-38535 Requirements
- Radiation Environment - Vertical Architecture Provides Low Dose Rate Immunity - DI RSG Process Provides Latch-Up Immunity
- 12V to 30V Operation
- 1A (Peak) Dual Output Drive Capability
- 5.1V Reference
- Undervoltage Lockout
- Programmable Soft-Start
- Switching Frequencies to 500kHz
- Latched Overcurrent Comparator with Full Cycle Restart
- Programmable Leading Edge Blanking Circuit
Applications
- Current or Voltage Mode Switching Power Supplies
- Motor Speed and Direction Control Pinout HS-1825ARH SBDIP (CDIP2-T16) AND FLATPACK (CDFP4-F16) TOP VIEW NOTE: Grounding the Soft-Start pin does not inhibit the outputs. The outputs may be inhibited by applying >1.26V to the ILIM/SD pin. INV NON-INV E/A OUT CLOCK RT CT SOFT START RAMP VREF 5.1V OUTPUT B VC POWER GND OUTPUT A GND ILIM/SD V CC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Data Sheet September 25, 2008 FN4561.8
2 FN4561.8 September 25, 2008 Typical Performance Curves
Ordering Information
MKT. NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. # 5962F9955801V9A HS0-1825ARH-Q -50 to +125 HS0-1825ARH/Sample HS0-1825ARH/Sample -50 to +125 5962F9955801VEC HS1-1825ARH-Q -50 to +125 16 Ld SBDIP D16.3 5962F9955801QEC HS1-1825ARH-8 -50 to +125 16 Ld SBDIP D16.3 5962F9955801VXC HS9-1825ARH-Q -50 to +125 16 Ld Flatpack K16.A 5962F9955801QXC HS9-1825ARH-8 -50 to +125 16 Ld Flatpack K16.A HS1-1825ARH/Proto HS1-1825ARH/Proto -50 to +125 16 Ld SBDIP D16.3 HS9-1825ARH/Proto HS9-1825ARH/Proto -50 to +125 16 Ld Flatpack K16.A FIGURE 1. OSCILLATOR FREQUENCY vs R t AND Ct FIGURE 2. MAXIMUM DUTY CYCLE vs R t
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4561.8 September 25, 2008 Die Characteristics DIE DIMENSIONS 4710µm x 3570µm (185 mils x 140 mils) Thickness: 483µm ±25.4µm (19 mils ±1 mil) INTERFACE MATERIALS Glassivation Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ±1.0kÅ Top Metallization Type: ALSiCu Thickness: 16.0kÅ ±2kÅ Substrate Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density <2.0 x 105 A/cm2 Transistor Count 225 Metallization Mask Layout HS-1825ARH NOTES: 1. This is the oscillator ground (OSCGND) bond pad and must be connected to GND. 2. PGND and VC each require two bond pad connections. PGND (12) OUTA (11) GND (10) OSCGND ILIM (9) SS (8) RAMP (7) CT (6) RT (5) (NOTE 1) (1) IN- (16) VREF (15) VCC (14) OUTB (13) VC (3) EAOUT (4) CLK/LEB (2) IN+ VC (13) (NOTE 2) (NOTE 2) (12) PGND (NOTE 2) (NOTE 2) HS-1825ARH