HS-1825ARH RENESAS | Alldatasheet

Document overview

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  • PDF pages: 6

Technical content

Features

  • Electrically screened to DLA SMD # 5962-99558
  • QML qualified per MIL-PRF-38535 Requirements
  • R a d i a t i o n e n v i r o n m e n t - Vertical architecture provides low dose rate immunity - DI RSG process provides latch-up immunity
  • 12V to 30V operation
  • 1A (peak) dual output drive capability
  • 5.1V reference
  • Undervoltage lockout
  • P r o g r a m m a b l e s o f t - s t a r t
  • Switching frequencies to 500kHz
  • Latched overcurrent comparat or with full cycle restart
  • Programmable leading ed ge blanking circuit

Applications

  • Current or voltage mode switching power supplies
  • Motor speed and direction control Pin Configuration HS-1825ARH, HS-1825AEH SBDIP (CDIP2-T16) AND FLATPACK (CDFP4-F16) TOP VIEW INV NON-INV E/A OUT CLOCK RT CT SOFT START RAMP VREF 5.1V OUTPUT B VC POWER GND OUTPUT A GND ILIM/SD VCC NOTE: Grounding the soft-start pin does not inhibit the outputs. The outputs may be inhibited by applying >1.26V to the ILIM/SD pin.

HS-1825ARH, HS-1825AEH FN4561 Rev 10.00 Page 2 of 6 August 5, 2016

Ordering Information

(Note 2) INTERNAL MKT. NUMBER (Note 1) TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962F9955801V9A HS0-1825ARH-Q -50 to +125 Die 5962F9955802V9A HS0-1825AEH-Q -50 to +125 Die HS0-1825ARH/Sample HS0-1825ARH/Sample -50 to +125 Die 5962F9955801VEC HS1-1825ARH-Q -50 to +125 16 Ld SBDIP D16.3 5962F9955802VEC HS1-1825AEH-Q -50 to +125 16 Ld SBDIP D16.3 5962F9955801QEC HS1-1825ARH-8 -50 to +125 16 Ld SBDIP D16.3 5962F9955801VXC HS9-1825ARH-Q -50 to +125 16 Ld Flatpack K16.A 5962F9955802VXC HS9-1825AEH-Q -50 to +125 16 Ld Flatpack K16.A 5962F9955801QXC HS9-1825ARH-8 -50 to +125 16 Ld Flatpack K16.A HS1-1825ARH/Proto HS1-1825ARH/Proto -50 to +125 16 Ld SBDIP D16.3 HS9-1825ARH/Proto HS9-1825ARH/Proto -50 to +125 16 Ld Flatpack K16.A NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table must be used when ordering. Typical Performance Curves FIGURE 1. OSCILLATOR FREQUENCY vs R t AND Ct FIGURE 2. MAXIMUM DUTY CYCLE vs R t

HS-1825ARH, HS-1825AEH FN4561 Rev 10.00 Page 3 of 6 August 5, 2016 Die Characteristics DIE DIMENSIONS 4860µm x 3410µm (185 mils x 140 mils) Thickness: 483µm ±25.4µm (19 mils ±1 mil) INTERFACE MATERIALS Glassivation Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ±1.0kÅ Top Metallization Type: ALSiCu Thickness: 16.0kÅ 2kÅ Substrate Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density <2.0 x 105 A/cm2 Transistor Count 225 Metallization Mask Layout HS-1825ARH, HS-1825AEH NOTES: 3. This is the oscillator ground (OSCGND) bond pad and must be connected to GND. 4. PGND and VC each require two bond pad connections. CLK/LEB EAOUT IN+ IN- VREF VCC OUTB PGND VC RT CT RAMP SS ILIM K^GND GND OUTA PGND VC (Note 3) (Note 4) (Note 4) (Note 4) (Note 4)

FN4561 Rev 10.00 Page 4 of 6 August 5, 2016 HS-1825ARH, HS-1825AEH Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 5, 2016 FN4561.10 Updated the die plot in the datasheet. Changed the die dimensions from 4710µm x 3570µm to 4860µm x 3410µm. Added Revision History and About Intersil sections. Added applicable PODs.

HS-1825ARH, HS-1825AEH FN4561 Rev 10.00 Page 5 of 6 August 5, 2016 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead di mensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa C A - BM DS Sccc C A - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)

16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7  90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N1 6 1 6 8 Rev. 0 4/94

HS-1825ARH, HS-1825AEH FN4561 Rev 10.00 Page 6 of 6 August 5, 2016 Package Outline Drawing K16.A

16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

Rev 2, 1/10 SIDE VIEW TOP VIEW SECTION A-A -D- -C- SEATING AND BASE PLANE -H- BASE LEAD FINISH METAL PIN NO. 1 ID AREA 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 BSC) 0.440 (11.18) 0.005 (0.13) MIN MAX 0.115 (2.92) 0.026 (0.66) 0.285 (7.24) 0.245 (6.22) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) MIN 0.13 (3.30) MIN 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 LEAD FINISH adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. shall be molded to the bottom of the package to cover the leads. meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. NOTES: Dimensioning and tolerancing per ANSI Y14.5M - 1982. Controlling dimension: INCH. Index area: A notch or a pin one identification mark shall be located If a pin one identification mark is used in addition to a tab, the limits Measure dimension at all four corners. For bottom-brazed lead packages, no organic or polymeric materials Dimension shall be measured at the point of exit (beyond the