HS-117RH_V01 RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Electrically screened to DLA SMD # 5962-99547
- Superior temperature stability
- Overcurrent and over-temperature protection
- QML qualified per MIL-PRF-38535 requirements
- Radiation environment * Product capability established by initial characterization. The EH version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate. Related Literature For a full list of related documents, visit our website
- HS-117RH, HS-117EH device pages
FIGURE 1. TYPICAL APPLICATION FIGURE 2. V OUT SHIFT vs HIGH and LOW DOSE RATE RADIATION
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 3 of 15 Aug 12, 2025
Ordering Information
(Note 2) PART NUMBER (Note 1) TEMPERATURE RANGE (°C) PACKAGE DESCRIPTION (RoHS Compliant) PKG. DWG. # 5962F9954702V9A HS0-117EH-Q -55 to +125 DIE - 5962F9954701V9A HS0-117RH-Q -55 to +125 DIE - HS0-117RH/SAMPLE HS0-117RH/SAMPLE ( Note 3) -55 to +125 DIE - 5962F9954702VUC HS2-117EH-Q -55 to +125 3 Ld METAL CAN T3.C 5962F9954701VUC HS2-117RH-Q -55 to +125 3 Ld METAL CAN T3.C 5962F9954701QUC HS2-117RH-8 -55 to +125 3 Ld METAL CAN T3.C HS2-117RH/PROTO HS2-117RH/PROTO ( Note 3 ) -55 to +125 3 Ld METAL CAN T3.C 5962F9954702VYC HSYE-117EH-Q -55 to +125 3 PAD CLCC J3.A 5962F9954701VYC HSYE-117RH-Q -55 to +125 3 PAD CLCC J3.A 5962F9954701QYC HSYE-117RH-8 -55 to +125 3 PAD CLCC J3.A HSYE-117RH/PROTO HSYE-117RH/PROTO ( Note 3 ) -55 to +125 3 PAD CLCC J3.A 5962F9954701VXC HS9S-117RH-Q -55 to +125 3 Ld TO-257 T3.D 5962F9954701QXC HS9S-117RH-8 -55 to +125 3 Ld TO-257 T3.D 5962F9954702VXC HS9S-117EH-Q -55 to +125 3 Ld TO-257 T3.D HS9S-117RH/PROTO HS9S-117RH/PROTO ( Note 3 ) -55 to +125 3 Ld TO-257 T3.D NOTES: 1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. 3. The /PROTO and /SAMPLE are not rated or certified for Total Ioni zing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the DLA SMD at +25°C only. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types do not come with a Certificate of Conformance because they are not DLA qualified devices.
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 4 of 15 Aug 12, 2025 Pin Configurations HS2-117RH (TO-39 CAN) BOTTOM VIEW HSYE-117RH (SMD.5 CLCC) BOTTOM VIEW NOTE: No current JEDEC outline for the SMD.5 package. See SMD for package dimensions. The TO-257 is a totally isolated metal package. HS9S-117RH (TO-257AA FLANGE MOUNT) TOP VIEW 1 3 OUT ADJUST IN 1 - ADJUST 2 - IN 3 - OUT ADJUST OUT IN3 Pin Descriptions HS2-117RH (TO-39) HS9S-117RH (TO-257AA) HSYE-117RH (SMD.5 CLCC) PIN NAME DESCRIPTION 13 2 I N R e g u l a t o r I n p u t 2 1 1 ADJUST Voltage Adjust Feedback Input 3 2 3 OUT Regulator Output IN OUT ADJ
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 5 of 15 Aug 12, 2025 Absolute Maximum Ratings Thermal Information Maximum Power Dissipation TC = +25°C Maximum Power Dissipation T C = +100°C (Note 7) ESD Rating Human Body Model (HBM) (Tested per MIL-PRF-883 3015.7). . . 1500V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maxi mum ratings listed for extended periods of time. Exposure to such conditions can adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 6. The maximum supply limit specified is for operation in a heavy ion environment at an LET = 87.4MeV•cm 2/mg. Electrical Specifications VDIFF = 3V, TA = 25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8)T Y P MAX (Note 8)U N I T Reference Voltage V REF VDIFF = 3V, VDIFF = 40V, 5.0mA ≤ IOUT ≤ 5.5mA 1.20 1.255 1.30 V Line Regulation R LINE VREF = VOUT - VADJ, 3V ≤ VDIFF ≤ 40V, 5.0mA ≤ IOUT ≤ 5.5mA -0.02 0.005 0.02 % Load Regulation R LOAD VDIFF = 3V, 5mA ≤ IOUT ≤ 1.25A TO-257AA and SMD.5 packages only -1.5 -0.1 1.5 % VDIFF = 3V, 5mA ≤ IOUT ≤ 500mA TO-39 package -1.5 -0.8 1.5 % Adjust Pin Current I ADJ VDIFF = 3V, VDIFF = 40V, 5.0mA ≤ IOUT ≤ 5.5mA 64 100 µA Adjust Pin Current Change dI ADJ 3V IADJ - 40V IADJ 5.0mA ≤ IOUT ≤ 5.5mA -6 2.36 6 µA Maximum Output Current I OUT TO-257AA and SMD.5 packages only 1.25 A TO-39 package 0.5 A VIN Applied to VOUT Turn-On T ON 0.2 ms Max. Output Short-Circuit Current Limit I sc VOUT = 0V 3 A Over-Temperature Shutdown OT 150 175 °C Over-Temperature Hysteresis OT_HYS 20 °C
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 9 of 15 Aug 12, 2025 Functional Description Functional Overview The radiation hardened HS-117RH and HS-117EH are adjustable positive voltage linear regulators capable of operating with input voltages up to 40VDC. The output voltage is adjustable from 1.25V (VREF) to 37V with two external resistors. The device is capable of sourcing from 5mA to 1.25APEAK (0.5APEAK for the TO-39 can package). Dual mode protection is provided by the on-chip +175°C thermal shutdown at output current limiting circuitry. The HS-117xH's advantage over other industry types is its incorporated circuitry that minimizes the effects of radiation and temperature on device stability providing < 0.2% shifts in output voltage over 300krad(Si) of High Dose Rate (HDR) and 100krad(Si) of Low Dose Rate (LDR) gamma radiation. The HS-117RH and HS-117EH are constructed in the dielectrically isolated Rad Hard Silicon Gate (RSG) process and are both immune to single event latch-up and are specifically designed to provide highly reliable performance providing power in harsh radiation environments. Output Voltage Adjustment The HS-117 is an adjustable output voltage regulator operating with a 1.25V reference voltage developed between the OUT and ADJUST pins. The ADJ current (IADJ) is typically 64μA at +25°C and 100μA maximum over temperature. The HS-117's minimum current load for the regulation amplifier feedback to maintain stability is 5mA. To ensure stability in all situations, the minimum resistor between the VOUT and ADJ should be 120Ω. Referring to Figure 1 on page 1 , the reference voltage is programmed to a constant current source by resistor R1, and this current flows through R2 to ground to set the output voltage. See Equation 1. In practical applications the R2 value is in the range of a few kΩ, so that the IADJ x R2 contribution can be ignored in the VOUT calculation; simplifying the VOUT calculation to Equation 2: CURRENT LIMITING The HS-117 has internal current limiting that is activated whenever the output current exceeds the lower limit of the Maximum Output Current parameter shown in the “Electrical Specifications” on page 5, (typically limiting to ~1.5A) to a maximum limit of typically 3A in an output short-circuit condition. During a short-circuit condition, if the regulator's differential voltage exceeds the Absolute Maximum Rating of 40V (for example, VIN ≥ 40V, VOUT = 0V), the device can be damaged. Performance and PCB Layout Considerations To optimize load regulation performance, implement Kelvin connections for the R1 and R2 resistors. In practice, the R1 connection must be close to the OUT and ADJUST pins. This connection eliminates PCB trace resistance being included in the constant current determination. In contrast, place the R2 to ground connection as close as possible to the negative load pin to ensure that the voltage being delivered to the load is as designed for by the choice of R1 and R2 values. Ripple rejection can be improved by placing a 10μF capacitor across the R2 resistor. At low output voltage, increasing this capacitor value further decreases output ripple. Input Capacitor Input bypass capacitance is recommended to enhance regulator stability if the device is located more than a few inches from its power source. Mount the input bypass capacitor (C1) with the shortest possible track length directly across the regulator's input and ground terminals. A 30µF tantalum capacitor should be adequate for most applications. Output Capacitor Frequency compensation for the regulator is provided by the output capacitor (C2) and is required to ensure output stability. A minimum (C2) capacitance value of 30µF is recommended for SEE tolerance. Higher values of output capacitance can be used to enhance loop stability, transient response, and output noise, but they must have sufficient ESR. Use Equation 3 to calculate your ESR zero and adjust the capacitance or ESR to ensure the zero is 13.3kHz or lower to ensure adequate phase and gain margin. This can be achieved by using a 30µF capacitor with ESR of 400mΩ or greater. Adjust Capacitor In typical resistor-adjusted voltage regulator applications (Figures 1 and 3), adding a capacitor between the ADJUST pin and the circuit GND can improve load transient stability. A 100nF ceramic capacitor is adequate. Thermal Considerations The HS-117 has a thermal limiting circuit that is designed to protect the regulator when the junction temperature is typically > +150°C. The regulator output turns off and then on again as the die cools. If the device is continuously operated in an over-temperature condition, this feature provides protection from catastrophic device damage due to accidental or prolonged overheating. The HS-117 is available in a TO-39 3 pin can, a TO-257AA flange mount, and a SMD.5 CLCC surface mount package. These packages represent a wide range of thermal resistance to the die and thus a wide range of power dissipation (P D) capabilities. See “Thermal Information” on page 5 for the relevant package thermal impedances. The “Absolute Maximum Ratings” on page 5 lists the power dissipation limitations by package. VOUT 1.25 1 R 2 R1+ IADJ R2+= (EQ. 1) VOUT 1.25 1 R 2 R1+= (EQ. 2) fESRzero
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 10 of 15 Aug 12, 2025 When developing circuits using the HS-117, test thermal performance and limitations to ensure acceptable performance. As with all tabbed packaged devices, flange mounting to a thermal heat-sink is recommended for the TO-257AA best practices. Characteristics Weight of Packaged Device 4.50g (Typical) Case Characteristics Finish: Gold Potential: Unbiased Weight of Packaged Device 0.91g (Typical) Case Characteristics Finish: Steel, Gold Potential: Unbiased SMD.5 CLCC Package Characteristics Weight of Packaged Device 0.91g (Typical) Case Characteristics Finish: Gold, Ceramic Potential: Unbiased Die Characteristics Die Dimensions 2616µm x 2794µm (103 mils x 110 mils) Thickness: 483µm ±25µm (19 mils ±1 mil) Interface Materials GLASSIVATION Type: PSG Thickness: 8kÅ ± 1kÅ TOP METALLIZATION Type: Al/Cu/Si (98.75%/0.5%/0.75%) Thickness: 16kÅ BACKSIDE FINISH Gold Assembly Related Information SUBSTRATE POTENTIAL Unbiased (DI) Additional Information WORST CASE CURRENT DENSITY < 2 x 105 A/cm2 PROCESS Dielectrically Isolated RH - Si-GATE TRANSISTOR COUNT:
TABLE 1. DIE LAYOUT X-Y COORDINATES ( Notes 9, 10)
- Origin of coordinates is the centroid of pad ADJ.
- Bond Pads sized for is 5mil diameter wire.
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 12 of 15 Aug 12, 2025 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Aug 12, 2025 11.01 Updated Figure 18 label. Replaced the External Bypass Capacitors section with three new sections. Updated POD J3.A to the latest revision; changes are as follows: -On bottom view, removed the termination numbering (“1”, “2”, “3”) -Updated note 4. Mar 28, 2019 11.00 Updated links throughout document. Updated Related Literature section. Updated SEL/SEB LET TH information in Features section on page 1. Added Note 3. Updated Figure 16. Removed About Intersil section. Updated POD J3.A to the latest revision, changes are as follows: -Updated Max value for Symbol A from: 0.124inches/3.15mm to: 0.122inches/3.10mm Updated Disclaimer Mar 25, 2014 10.00 Updated “Ordering Information on page 3. Expanded content in datasheet from 3 to 15 pages. Sep 4, 2012 9.00 Added HS-117EH as Device # to datasheet (EH FG s already added to the Ordering Information table), making this a 2-part datasheet: HS-117RH, HS-117EH. Global search/change HS-117RH to HS-117RH, HS-117EH. Dec 15, 2011 8.00 Added parts to datasheet: HS2-117 EH-Q, HS0-117EH-Q, HS9S-117EH-Q and HSYE-117EH-Q Oct 10, 2003 7.00 Revised datasheet includes a new date and file number.
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 13 of 15 Aug 12, 2025 Package Outline Drawings E Top View D Side View Bottom View A A 0.004 C (3 Places) C b b3 (2 Places) b2 (2 Places) (2 Places)e
0.014 M CA
B J3.A 3 Pad Hermetic SMD.5 Package Bottom Terminal Ceramic Leadless Chip Carrier (CLCC) Symbol Inches Millimeters NotesMin Max Min Max A 0.112 0.122 2.84 3.10 3 A1 0.010 0.020 0.25 0.51 - b 0.281 0.291 7.13 7.39 - b1 0.220 0.230 5.58 5.84 - b2 0.090 0.100 2.28 2.54 - b3 0.115 0.125 2.92 3.18 - D 0.395 0.405 10.03 10.28 - E 0.291 0.301 7.39 7.64 - e 0.075 BSC 1.91 BSC - Rev. 6 8/2025 Notes: 1. Controlling dimensions are in inches (mm for reference only). 2. Dimensioning and tolerance per ANSI Y14.5M - 1982. 3. The maximum “A” dimension is package height before being solder dipped. 4. Patterned after MIL-STD-1835 CBCC1-N3 (C-B1). For the most recent package outline drawing, see J3.A.
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 14 of 15 Aug 12, 2025 Metal Can Package Øb ØD1ØD F REFERENCE PLANE A L Øb1 k1k CL BASE METAL LEAD FINISH SECTION A-A Øb1 Øb2 A A T3.C
3 LEAD TO-39 (TO-205) METAL CAN PACKAGE
A 0.160 0.180 4.07 4.58 - Øb 0.016 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 Øb2 0.016 0.024 0.41 0.61 - ØD 0.350 0.370 8.89 9.40 - ØD1 0.315 0.335 8.00 8.51 - e 0.200 BSC 5.08 BSC - e1 0.100 BSC 2.54 BSC - F 0.009 0.050 0.23 1.27 - k 0.027 0.034 0.69 0.086 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.750 12.70 19.05 1 L1 -0 . 0 5 0 -1 . 2 7 1 L2 0.250 - 6.35 - 1 45° BSC 45° BSC 3 90° BSC 90° BSC - N3 3 4 Rev. 0 6/01 NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. is the basic spacing from the centerline of the tab to terminal 1 looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Controlling dimens ion: Millimeter. For the most recent package outline drawing, see T3.C.
HS-117RH, HS-117EH FN4560 Rev.11.01 Page 15 of 15 Aug 12, 2025 Hermetic Metal Package D L Øb e E A ØP LEAD #1 LEAD #3 AA Øb1 Øb 3 PLC T3.D
3 LEAD JEDEC TO-257AA HERMETIC METAL PACKAGE
A 0.188 0.200 4.78 5.08 7 A1 0.035 0.045 0.89 1.14 - A2 0.120 BSC 3.05 BSC - D 0.645 0.665 16.39 16.89 - D1 0.410 0.430 10.41 10.92 - D2 -0 . 0 3 8 -0 . 9 7- e 0.100 BSC 2.54 BSC - e1 0.200 BSC 5.08 BSC - E 0.410 0.420 10.41 10.67 - Øb 0.025 0.040 0.64 1.02 1, 2 Øb1 0.025 0.035 0.64 0.89 1, 2 L 0.500 0.750 12.70 19.05 - L1 0.527 0.537 13.39 13.64 - P 0.140 0.150 3.56 3.81 - N3 3 5 Rev. 2 3/09 NOTES: 1. Dimension Øb 1 applies to base metal only. Dimension Øb applies to plated part. 2. Section A-A dimension apply between 0.100 inch (2.54mm) to 0.150 inch (3.81mm) from lead tip. 3. Die to base BeO isolated, terminals to case is plated. 4. Controlling dimensions are in inches (mm for reference only). 5. N is the maximum number of terminal positions. 6. Patterned after MIL-STD-1835 MSFM1-P3AA. 7. “A” minimum dimension not meeting the MIL-STD 0.190 mini- mum dimension. For the most recent package outline drawing, see T3.D.
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