HR1211

HR1211 MPS | Alldatasheet

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Multi-Mode PFC and Current Mode LLC Controller with Configurable Audible Noise Reduction Control HR1211 Rev. 1.0 www.MonolithicPower.com 1 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

DESCRIPTION

The HR1211 is a multi-mode PFC and current mode LLC combo controller that is configurable via UART interface. Power-saving technology helps achieve optimized efficiency across the full operating range. The PFC controller employs a patented, digital average current control scheme to achieve hybrid CCM/DCM operation. Under heavy loads, CCM reduces the peak MOSFET current so the controller can be used across a wider load range. Under light load s, DCM reduces the switching frequency for better efficiency. Burst mode has configurable, digital soft switching to improve both light-load efficiency and audible noise. Current mode control is implemented in the LLC stage to achieve good stability and fast response. Three operation modes are implemented based on the different load conditions: steady state, skip, and burst mode . This allows different load conditions to be independently optimized for efficiency . At light loads, digital, frequency-controlled burst mode is applied to reduce both switching power loss and audible noise. Adaptive dead -time adjustment (ADTA) and capacitive mode protection (CMP) is also applied to guarantee zero-voltage switching (ZVS) without capacitive mode operation. The HR1211 has an internal, high-voltage current source for start -up, meaning that a traditional start-up resistor or external circuit is not required . The high-voltage (HV) current source can be implemented as an X-capacitor discharger when the AC input is in dropout, so a capacitor resistor is not required. Protections include thermal shutdown (TSD), PFC open-loop protection (OLP), over-voltage protection (OVP), over-current limit (OCL) and LLC over-current protection (OCP), SO pin protection, and over-power protection (OPP). The HR1211 is available in SOIC -20 and TSSOP-20 packages.

FEATURES

 General System Features: o HV Current Source for Start-Up o Smart X-Capacitor Discharge during AC Dropout, Approved by IEC62368 and IEC60950 o UART Interface for Configurations o User-Friendly GUI for Digital PFC  PFC Controller: o CCM/DCM Multi-Mode PFC Control with High Efficiency across All Loads o Operating Frequency Up to 250kHz o High PF due to Input Capacitor Current Compensation o Configurable Frequency Jittering o Configurable Soft Start and Burst On o Configurable AC Input Brown-In/Out o Cycle-by-Cycle Current Limiting o OLP, OVP  LLC Controller: o 600V High Side Gate Driver with Bootstrap Diode and High dV/dt Immunity o Current Mode Control o Up to 500kHz in Steady State o Adaptive Dead-Time Adjustment with Minimum and Maximum Limit o Burst/Skip Mode Switching at Light Load o Configurable Burst Frequency with Low Audible Noise o Configurable Soft Start o Configurable DC Input Brown In/Out o Capacitive Mode Protection o OCP, OPP with Auto-Restart or Latch o Configurable Protection on SO Pin

APPLICATIONS

 Desktop PCs and ATX Power Supplies  All-in-One and Gaming Power Supplies  Notebook Adapters  LCD TV and Plasma TV Power Supplies  Power Tools Power Supply LED Drivers All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 2 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION LCM1 CX1 CX2 LPFCD3 CBUS VOUT FBL LSG HSG GND FBP HR1211 GATEP CSP VCC VREG CSHB HV MP692x Feedback Network BST D1D2 C2CBST RCS CR Lr Q3C11 RIN1 RIN2 ACIN SO SW UART C7R6C4 CR C10 IL C5 C6 R5

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 3 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL Rating HR1211GM-xxxx* TSSOP-20 See Below 2 HR1211GY-xxxx SOIC-20 See Below 3 * For Tape & Reel, add suffix –Z (e.g. HR1211GM-xxxx–Z). * For Tape & Reel, add suffix –Z (e.g. HR1211GY-xxxx–Z). *−xxxx is for internal code version control. For customer-specific projects, MPS will assign a special 4-digit number. TOP MARKING MPS: MPS prefix YY: Year code WW: Week code HR1211: Part number LLLLLLLLL: Lot number PACKAGE REFERENCE SOIC-20 TSSOP-20

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 4 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description

1 FBP

PFC output voltage sense. The FBP pin sense s the PFC output voltage to calculate the PFC switch on time, monitor for over -voltage protection (OVP) and open -load protection (OLP), and calculate the digital current reference (IREF(N)) that determines the PFC switching frequency. A 3.3MΩ pull-down resistor is connected to FBP internally. It is recommended to connect a capacitor (around 4.7nF) to FBP for noise immunity.

2 ACIN

AC input voltage sense. The ACIN pin senses the AC input voltage to calculate the PFC switch on time calculation, monitor for brown-in/out protection , and calculate the digital current reference (IREF(N)) that determines the PFC switching frequency. It is recommended to connect a capacitor (around 2.2nF) to ACIN for noise immunity.

3 CSP

PFC switching current sense. CSP defines the PFC switch on time, switching frequency, and cycle-by-cycle current limit protection. Connect a 500 Ω resistor in series between the current-sense resistor and the CSP pin via the internal ESD clamping capability. This resistor prevents the CSP pin from overstress under AC plug-in or surge conditions. Another solution is to add an external clamping component to CSP. 4 PGND Ground reference for the PFC and LLC low-side gates. 5 GATEP PFC gate driver output. 6 VREG Provides a regulated voltage for the PFC and LLC gate drivers and internal circuits. 7 LSG LLC low-side gate driver output. 8 VCC IC supply power . VCC can be charged by an internal current source through HV or an external power supply. 9 NC No connection.

10 HV High-voltage supply input for internal HV start -up source and X-capacitor discharger

when the AC input voltage drops out.

11 BST

Voltage bootstrap. An internal bootstrap diode is connected between the BST and VCC pins. Connect an external capacitor between the BST and SW pins to drive the high -side MOSFET of the half-bridge LLC. 12 HSG LLC high-side gate driver output. 13 SW High-side switch source. SW is the current return for the high-side gate driver current. SW requires additional layout considerations to avoid creating large spikes below ground. 14 NC No connection. 15 GNDD Ground reference for the digital PFC core.

16 CSHB

Half-bridge current sense. Use a sense resistor or a capacitive divider to sense the primary current. The CSHB pin has the following functions:  Over-current protection (OCP) : If the current continues to rise despite the increasing frequency and VCSHB > VCS-OCP, OCP is triggered. The IC initiates its configured protection mode (auto-retry or latch-off mode).  Capacitive mode protection (CMP): The voltage on CSHB is compared to VCSNR and VCSPR to determine whether the LLC current is in a positive or negative polarity. The IC terminates the high-side gate driver (HSG) if the current goes into negative polarity (VCSHB < VCSPR). The IC terminates the low-side gate driver (LSG) if the current goes into positive polarity (VCSHB > VCSNR).

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 5 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PIN FUNCTIONS (continued) Pin # Name Description

17 UART

Half-duplex communication IO interface. UART provides a half-duplex communication IO interface. UART is internally pull ed up to 3.3V with a 1.6kΩ resistor (RUART). It is not recommended to rely on real-time communication in application. Do not pull UART high when VCC drops below VCCUVP2.

18 FBL

LLC output voltage feedback input. FBL is internally pulled up by a voltage source with an internal resistor. FBL defines the LLC switching frequency according to the load condition. The voltage on FBL activates LLC skip mode, burst mode, and over-power protection (OPP). 19 CR LLC capacitor voltage-sense input. CR senses the divided resonant capacitor voltage to determine the LLC switching frequency. 20 SO External protection input. If the sensed SO voltage exceeds VSO_OVP, a protection is triggered and the IC initiates its configured mode (auto-retry or latch-off mode). To achieve external over-temperature protection (OTP), attach an external NTC to this pin (see Figure 39).

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 6 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) BST internal diode average forward current (5) CSP input current limit at negative voltage overstress (clamped by internal ESD device) (6) Continuous power dissipation (TA = 25°C) (3) ESD Ratings (1) Recommended Operating Conditions (2) Operating junction temp (TJ) .... -40°C to +125°C Thermal Resistance (4) θJA θJC Notes: 1) The device is not guaranteed to function outside of its operating conditions. 2) Exceeding these ratings may damage the device. 3) The maximum allowable power dissipation is a function of the maximum junction temperature , TJ (MAX), the junction -to- ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (T J (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can cause excessive die temperature, and the regulator may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) Measured on JESD51-7, 4-layer PCB. 5) Guaranteed by design. 6) Guaranteed by characterization.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 7 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VCC = 25V, TJ = -40°C to +125°C, min and max values are guaranteed by characterization, typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units High-Voltage Start-Up Current Source (HV Pin) Breakdown voltage VHVBR 700 V Normal charge current IHVNOR VCCSCP < VCC < 15V, TJ = 25°C 5.9 7 9 mA Extra charge current from the VCC pin IVCCON_OUT VCC = VCCON(HV) - 0.1V, TJ = 25°C 2 mA Supply current when a fault occurs IHVLIMIT VCC < VCCSCP 1.5 2.2 3 mA Leakage current at off state IHVOFF VHV = 400V, VCC = 24V 4.5 10 μA IC Power Supply (VCC Pin) IC turn-on threshold voltage with HV detected VCCON(HV) VHV > VHVON 20 21.5 23 V UV protection threshold 1 VCCUVP1 10 10.8 11.5 V UV protection threshold 2 VCCUVP2 13.5 14.4 15.2 V IC release threshold VCCRST 8 8.8 9.3 V X-capacitor discharge regulation voltage (7) VCCXCD 17 V Short-circuit protection VCCSCP 0.76 0.94 1.4 V Normal operating current ICC(NOR) CGATEP = 1nF, fPFC = 100kHz, CHSG = 1nF, CLSG = 1nF, fLLC = 200kHz 15 mA No switch, TJ = 25°C 8 10 Start-up current ICC-START1 VCC = 20V 2.1 3 mA Burst-mode current ICC-BURST During burst off, TJ = 25°C 2.2 2.7 mA X-Capacitor Discharger (HV Pin) Discharge current IHVXCD TJ = 25°C 5.9 7 9 mA Discharge clock time tX-D 0.8 1.6 2.6 ms PFC Gate Driver (GATEP Pin) Minimum gate high voltage VOH CGATEP = 1nF, source 20mA, VREG = 11.5V 11.3 V Maximum gate low voltage VOL CGATEP = 1nF, sink 20mA, VREG = 11.5V 0.1 V Gate on resistance RON(H) Source 20mA 4.5 7.5 Ω RON(L) Sink 20mA 2.5 5 Ω Voltage fall time tF CGATEP = 1nF 20 40 ns Voltage rise time tR CGATEP = 1nF 20 40 ns Sourcing capacity (7) IGATE_SR 650 mA Sinking capacity (7) IGATE_SK 800 mA

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 8 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VCC = 25V, TJ = -40°C to +125°C, min and max values are guaranteed by characterization, typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Regulated Power Supply (VREG Pin) Regulated output voltage VREG IREG = 0mA 11 12 13 V IREG = 20mA 10.8 11.9 12.8 V Turn-on threshold VREGON 9 10 10.9 V UVP VREGUVP 6.5 7.3 8.1 V System Clock Clock frequencies fOSC_LLC Normal operation 180 200 223 MHz fOSC_PFC Normal operation 16.6 17.5 18.7 fOSC_NOPWM (7) During burst off or if a fault occurs 1 AC Input Sensing (ACIN Pin) Voltage range 0 1.6 V PFC Feedback (FBP Pin) Voltage range 0 1.6 V Current Sense (CSP Pin) Voltage range -1.4 0 V Internal biased voltage VBIAS_CSP VCSP = 0V 0.19 0.2 0.21 V UART Interface (UART Pin) Internal pull-up voltage 3.3 V Internal pull-up resistor 1.6 kΩ ADC for CSP ADC voltage reference 1.585 1.6 1.61 V TJ = 25°C 1.595 1.6 1.605 V ADC resolution (8) 12 bits Acquisition time (7) 300 ns Offset error (8) ±0.5 LSB Gain error (8) ±1.5 LSB ADC for ACIN, FBP, FBL ADC voltage reference 1.585 1.6 1.61 V TJ = 25°C 1.595 1.6 1.605 V ADC resolution (8) 10 bits Acquisition time (7) 300 ns Offset error (8) ±0.5 LSB Gain error (8) ±1.5 LSB

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 9 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VCC = 25V, TJ = -40°C to +125°C, min and max values are guaranteed by characterization, typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units DAC for OVP OCL, BI/BO of PFC; OPP, ADOFF of LLC DAC voltage reference 1.585 1.6 1.61 V TJ = 25°C 1.595 1.6 1.605 V Resolution (8) 8 bits Offset error (8) ±0.2 LSB Gain error (8) ±1.5 LSB DAC for PFC Set Signal DAC voltage reference 1.585 1.6 1.61 V TJ = 25°C 1.595 1.6 1.605 V Resolution (8) 10 bits Offset error (8) ±0.5 LSB Gain error (8) ±1.5 LSB DAC for LLC Set Signal DAC voltage reference 1.77 1.8 1.825 V TJ = 25°C 1.788 1.8 1.812 V Resolution (8) 10 bits Offset error (8) ±0.5 LSB Gain error (8) ±1.5 LSB High-Side Floating Gate Driver Supply (BST and SW Pins) BST pin leakage current ILKBST VBST = 600V 10 µA SW pin leakage current ILKSW VSW = 582V 10 µA Half-Bridge Current Sense (CSHB Pin) OCP threshold VCS-OCP 1.475 1.5 1.52 V Current polarity comparator reference when HSG is on VCSPR TJ = 25°C 60 80 100 mV Current polarity comparator reference when LSG is on VCSNR TJ = 25°C -100 -80 -60 mV Output Voltage Sense (SO Pin) Over-voltage protection (OVP) on SO VSO-OVP 1.475 1.5 1.52 V ADTA (SW Pin) Minimum voltage slew rate that can be detected (7) dVMIN/dt 85 V/µs Turn-on delay (7) tD Slope finished to turn-on delay 150 ns

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 10 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VCC = 25V, TJ = -40°C to +125°C, min and max values are guaranteed by characterization, typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Feedback Section (FBL Pin) Internal pull-up resistor on FBL RFBL_LOW TJ = 25°C 7 8 9.6 kΩ Internal pull-up resistor on FBL in power-save mode RFBL_HIGH 38 47 56 kΩ Internal voltage reference VFBL_SOURCE TJ = 25°C 2.35 2.41 2.5 V VCOMP offset voltage from the FBL voltage VFBL_OFFSET 0.995 1 1.005 V Current-Sense Input Section (CR Pin) Slope compensation amplitude per LSB VCR_SLOPE TJ = 25°C 1.54 2.35 3.16 mV/µs Zero-voltage detection threshold VCR_ZERO 15 20 25 mV On-time comparator delay to HG driver off (7) tD_CR 150 ns Current-sense input leakage current ICR_LEAKAGE VCR = 2V ±1 µA Leading-edge blanking time (7) tLEB 300 ns Low-Side Gate Driver (LSG Pin) Peak source current (7) ISOURCEPK 0.75 A Peak sink current (7) ISINKPK 0.87 A Source resistor RSOURCE 5 8 Ω Sink resistor RSINK 2.5 5 Ω Fall time tF 20 40 ns Rise time tR 20 40 ns High-Side Gate Driver (HSG Pin, Referenced to the SW Pin) Peak source current (7) ISOURCEPK 0.74 A Peak sink current (7) ISINKPK 0.87 A Source resistor RSOURCE 5 8 Ω Sink resistor RSINK 2.5 5 Ω Fall time tF 20 40 ns Rise time tR 20 40 ns Voltage Bootstrap (BST Pin, Referenced to the SW Pin) VREG-to-BST internal diode forward voltage (7) VF IF = 1mA, TJ = 25°C 1.2 V Thermal Shutdown Thermal shutdown threshold (7) 145 °C Thermal shutdown recovery threshold (7) 120 °C Notes: 7) Guaranteed by design. 8) Guaranteed by characterization.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 11 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VCC On and Under-Voltage Protection (UVP) vs. Temperature VCC RST Threshold vs. Temperature VREG Voltage vs. Temperature VREG On Threshold vs. Temperature VREG UVP Threshold vs. Temperature 12-Bit ADC Reference vs. Temperature -50 0 50 100 150 VCC THRESHOLD AND UVP (V) TEMPERATURE (°C) 8.4 8.5 8.6 8.7 8.8 8.9 9.0 -50 0 50 100 150 VCC RST THRESHOLD (V) TEMPERATURE (°C) 11.8 11.9 12.0 12.1 12.2 12.3 12.4 -50 0 50 100 150 VREG VOLTAGE (V) TEMPERATURE (°C) 9.6 9.7 9.8 9.9 10.1 10.2 -50 0 50 100 150 VREG ON THRRESHOLD (V) TEMPERATURE (°C) 7.0 7.1 7.2 7.3 7.4 7.5 7.6 -50 0 50 100 150 VREG UVP THRESHOLD (V) TEMPERATURE (°C) 1.580 1.585 1.590 1.595 1.600 1.605 1.610 -50 0 50 100 150 12-BIT ADC REFERENCE (V) TEMPERATURE (°C) VCCON(HV) VCCUVP2 VCCUVP1

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 12 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) 10-Bit ADC Reference vs. Temperature 8-Bit DAC Reference vs. Temperature 10-Bit DAC Reference vs. Temperature SO and CSHB Threshold vs. Temperature CSP Bias vs. Temperature FBL Low Pull-Up Resistance vs. Temperature 1.580 1.585 1.590 1.595 1.600 1.605 1.610 -50 0 50 100 150 10-BIT ADC REFERENCE (V) TEMPERATURE (°C) 1.580 1.585 1.590 1.595 1.600 1.605 1.610 -50 0 50 100 150 8-BIT DAC REFERENCE (V) TEMPERATURE (°C) 1.780 1.785 1.790 1.795 1.800 1.805 1.810 -50 0 50 100 150 10-BIT DAC REFERENCE (V) TEMPERATURE (°C) 1.480 1.485 1.490 1.495 1.500 1.505 1.510 -50 0 50 100 150 SO AND CSHB THRESHOLD (V) TEMPERATURE (°C) 0.197 0.198 0.199 0.200 0.201 0.202 0.203 -50 0 50 100 150 CSP BIAS (V) TEMPERATURE (°C) 7.8 7.9 8.0 8.1 8.2 8.3 8.4 -50 0 50 100 150 FBL LOW PULL-UP RESISTANCE (kΩ) TEMPERATURE (°C)

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 13 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) FBL High Pull-Up Resistance vs. Temperature CR Zero-Detection Threshold vs. Temperature Negative Current Polarity Threshold vs. Temperature Positive Current Polarity Threshold vs. Temperature 45.0 45.5 46.0 46.5 47.0 47.5 48.0 -50 0 50 100 150 FBL HIGH PULL-UP RESISTANCE (kΩ) TEMPERATURE (°C) -50 0 50 100 150 CR ZERO-DETECTION THRESHOLD (mV) TEMPERATURE (°C) -100 -95 -90 -85 -80 -75 -70 -50 0 50 100 150 NEGATIVE CURRENT POLARITY THRESHOLD (mV) TEMPERATURE (°C) 100 -50 0 50 100 150 POSITIVE CURRENT POLARITY THRESHOLD (mV) TEMPERATURE (°C)

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 14 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 85VAC to 265VAC, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted. Steady State at Input VIN = 110VAC at POUT = 240W Steady State at Input VIN = 230VAC at POUT = 240W CH1: IIN 2A/div. CH2: VIN 100V/div. CH3: VBUS 100V/div. CH1: IIN 1A/div. CH2: VIN 250V/div. CH3: VBUS 100V/div. 4ms/div. 4ms/div. Steady State at PFC Choke VIN = 110VAC at POUT = 240W Steady State at PFC Choke VIN = 230VAC at POUT = 240W CH4: IPFC 2A/div. 4µs/div. CH4: IPFC 1A/div. 4µs/div. Steady State at LLC POUT = 240W Input Start-Up/Shutdown at PFC VIN = 110VAC, POUT = 240W CH1: VHSG 10V/div. CH4: IR 2A/div. CH3: VSW 200V/div. CH2: VLSG 10V/div. CH1: VGATEP 10V/div. CH2: VOUT 5V/div. CH3: VBUS 100V/div. CH4: IPFC 5A/div. 4µs/div. 20ms/div.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 15 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 85VAC to 265VAC, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted. Input Start-Up/Shutdown at PFC VIN = 230VAC, POUT = 240W Input Start-Up at LLC POUT = 240W CH1: VGATEP 10V/div. CH2: VOUT 5V/div. CH3: VBUS 100V/div. CH4: IPFC 5A/div. CH1: VOUT 5V/div. CH3: VSW 500V/div. CH4: IR 5A/div. CH2: VLSG 10V/div. 2ms/div. 40ms/div. Input Shutdown at LLC POUT = 240W Load Dynamic at PFC VIN = 85VAC, POUT = 0W to 240W, 1A/µs CH1: VOUT 5V/div. CH3: VSW 500V/div. CH4: IR 5A/div. CH2: VLSG 10V/div. 10ms/div. CH1: VGATEP 10V/div. CH2: VIN_REC 100V/div. CH3: VBUS 100V/div. CH4: IPFC 5A/div. 200ms/div. Load Dynamic at PFC VIN = 265VAC, POUT = 0W to 240W, 1A/µs Load Dynamic at LLC POUT = 0W to 240W, 6A/µs CH1: VGATEP 10V/div. CH3: VBUS 100V/div. CH2: VIN_REC 100V/div. CH4: IPFC 5A/div. CH2: VOUT AC COUPLED 500mV/div. CH4: IR 2A/div. 200ms/div. 4ms/div.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 16 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM CSHB MTP UART UART FBP CSP FBL ADC Mux Digital Control Core SET OCP_LLC LLC_CURRENT DIRECTION DAC OVP_PFC DAC BST HG SW LG Power Management GATEP LLC Driver PFC Driver 3.3V ADTA PWM_PFC HSG LSG DAC OCL CR VFBL LLC_RESET SOLLC_SO ADC DAC VCOMP UVLO X-Capacitor Discharger VSLOPE HS_DEAD LS_DEAD PG VCAP_ZERO BI/BO_PFC DAC DAC LLC_ADOFF DACOSC LLC_OLP GND ACIN VFBL VFBL - VFBL_OFFSET VSO_OVP RFBL_LOW RFBL_HIGH VFBL_SOURCE VCR_ZERO VCSPR / VCSNR VLLC_SCP VFBL - VFBL_OFFSET VREG VCCHV VREG VREG 3.3VRUART RFBP_I Figure 1: Functional Block Diagram

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 18 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. IC Supply Input (VCC) VCC provides power to all of the internal circuits, including VREG and the V3.3 internal supply. VCC can be powered either by the half-bridge (HB) transformer’s auxiliary winding or byan external power supply. If VCC drops below the under-voltage protection (UVP) level, the following process occurs: 1. The IC stops operating, and the PFC driver stops switching immediately. The HB LLC continues to operate until the low -side MOSFET (LS-FET) turns on. 2. The VREG LDO is disabled. There are two VCC UVP thresholds. If the LLC does not start switching, the UVP level goes to VCCUVP2. If the LLC starts switching, the UVP level goes to VCCUVP1. If the IC enters latch -off mode, the device remains latched until VCC falls below VCCRST. Regulated Output (VREG Pin) An internal LDO is adopted to stabilize the VREG pin so that VREG can achieve the following:  Power the internal PFC driver  Power the internal low-side driver of the HB LLC  Charge the bootstrap capacitor, which powers for the internal high-side driver of the HB LLC  Be used as a voltage reference for external circuits When VCC reaches VCCON(HV), the internal LDO is enabled to charge the VREG capacitor . After VREG is completely charged, the IC starts operating if there is no fault. The LDO is enabled only when VCC exceeds VCCON(HV). This ensures that any optional external circuitry connected to VREG does not dissipate additional current before the IC starts up. Once VREG exceeds VREGON, the HR1211 starts working. If V REG falls below VREGUVP, the IC stops, and the PFC controller stops switching immediately. The HB LLC controller continues operating until the low-side gate becomes active. V3.3 for Digital Logic V3.3 is an internal, stabilized 3.3V power supply for digital circuits. It is derived from VCC via an internal LDO from VCC. When V CC exceeds VCCRST plus a hysteresis, the V3.3 LDO is enabled. It can be disabled only when VCC is below VCCRST. V3.3 can also be used as the input for an internal 1.8V LDO, which is also the power supply for the digital core. Internal Under-Voltage Lockout (UVLO) Signal Under-voltage lockout ( UVLO) is an internal enable signal for both the PFC and LLC digital controllers. When V CC exceeds VCCUVP1, and VREG exceed VREGON, UVLO goes high. The UVLO signal is pulled low if VREG falls below VREGUVP. Internal Power Good Indicator (PG) The internal power good (PG) signal indicates to the digital core that the power supply (V CC) voltage is regulated. When UVLO goes high, there is a 200µs delay (tPG-DELAY) and then the PG signal is pulled high. SYSTEM FUNCTIONS X-Capacitor Discharge X-capacitors are critical components placed at the power supply input terminals to filter out differential EMI noise. If the AC line is removed, the energy stor ed in the X -capacitor can pose risks. Safety standards require that the voltage must be discharged to a safe level within a certain timeframe. Typically, resistors are placed in parallel with the X-capacitor across the AC line to provide a discharge path. However, additional resistors lead to continuous power consumption while the AC input is connected . This is a significant contributor to the power consumption under no- load or standby conditions. The HV current source in the HR1211 acts as a smart X-capacitor discharger when the AC input is removed , which means traditional discharge resistors are not required. Figure 5 shows the X- capacitor operating waveforms.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 25 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. The new switching period can be calculated with Equation (11): PK S REF S _MAX 1I (n) t (n) I (n) t2 (11) As tON changes, the peak inductor current value is relatively unchanged, a nd can be estimated with Equation (12): PK PKI (t) I (t)  (12) The switching period can be calculated with Equation (13): REF S S _MAX PK 2I (n)t (n) t I (n)   (13) The new turn -on time can be estimated with Equation (14): O _REF IN ON S O _REF V V (n)t (n) t (n) V (14) The delay time can be calculated with Equation (15): REF D S_MAX S S_MAX PK

2 I (n)t (n) t t (n) 1 t I (n)

(15) The calculated delay time also has a digital filter with a configurable cross-frequency. Soft-Start Procedure Once the AC brown-in is triggered, the VIN_OK signal goes high and the HR1211 initiates a soft start (see Figure 22). VIN_OK PWM SOFT_START_FLAG VIN VOUT_REF Soft_Start Time VOUT_TARGET VOUT_START Figure 22: Soft-Start Sequence During soft start, the internal voltage reference slowly ramp s up to the regulation target. The ramp slew rate is determined by the soft -start time setting’s high and low line s, which can be configured via the GUI. When t he voltage reference on FBP reaches the regulation target value, SOFT_START_FLAG is set high and the soft-start sequence is complete. Generally, the VOUT cannot rise during soft start, so it is regulated afterward. Note that the slew rate is different at the high line and low line. Burst Mode At light loads, the IC is always designed to run in burst mode for better efficiency and decreased no-load power consumption . Once the output load drops below the threshold (a percentage of the rated load), the PFC enters burst mode. The threshold can be configured via the GUI for both the high line and low line. In burst mode, the switching duty is calculated based on the set threshold , and the output is regulated to VO_TARGET with a typical 5V hysteresis. The PFC stops switching when VOUT ramps up to VO_TARGET + 5V, and resumes switching when VOUT drops below VO_TARGET. Generally, the HR1211 is designed to exit burst mode only at the peak point of the AC line to minimize the current stress. Additionally, a threshold voltage can be selected via the GUI to prevent the bus voltage from dropping too low under transient. I f the bus voltage drops below the threshold, the IC exits burst mode immediately without waiting for peak point detection. Power Factor Compensation (PFC) Traditional power factor compensation (PFC) control schemes only regulate the inductor current to match the value of VIN. However, the input capacitor current is not controlled , which can cause power factor (PF) deterioration and a suboptimal phase delay. With a larger capacitor or a higher VIN, t he PF worsens, especially under light-load conditions. To improve the PF, the HR1211 implements a patented method to compensate the input capacitor current. There are four VIN ranges and input capacitors for the compensation setting, which can be configured via the GUI and stored in the MTP. With this function , the PF can be improved across the whole VIN range.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 31 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. OCP is typically triggered when the CSHB pin voltage continues to rise during a short circuit (see Figure 36). LSG HSG VCSHB VCS_OCP 1 n2 ……. OCP Figure 36: OCP Timing Sequence The IC can be set for latch-off or auto-retry mode if LLC OCP occurs. The GUI can be used to select the protection mode. For details on the latch-off and auto-retry protection modes, see the Open-Loop Protection section. Over-Power Protection (OPP) Over-power protection (OPP) protects the LLC converter from excessive over-power conditions. If VFBL exceeds V OPP_LLC (configurable via the GUI), an internal configurable timer turns on. This timer is reset once VFBL falls below VOPP_LLC. OPP is triggered if the timer counts to the end without resetting. VOPP_LLC should not exceed the minimum value of VFBL_SOURCE. OPP can activate latch -off mode or auto -retry mode. This parameter is configured via the GUI. For details on the latch -off and auto -retry protection modes, see the Open-Loop Protection section.

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 35 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUITS Figure 43: 90-265 V AC Input and 12V/34A Output Application

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 36 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

PACKAGE INFORMATION

NOTES: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MS-013, VARIATION AC. 6) DRAWING IS NOT TO SCALE. 0.013(0.33) 0.020(0.51) 0.496(12.60) 0.512(13.00) SEATING PLANE 0.050(1.27) BSC PIN 1 ID 0.291 (7.40) 0.299 (7.60) 0.394 (10.00) 0.418 (10.60) 1 10 1120 0.093(2.35) 0.104(2.65) 0.004(0.10) 0.012(0.30) TOP VIEW FRONT VIEW SIDE VIEW RECOMMENDED LAND PATTERN 0.370 (9.40) 0.079 (2.00) 0.024 (0.61) 0.050 (1.27) SEE DETAIL "A" 0o-8o DETAIL "A" 0.010(0.25) 0.030(0.75) x 45o 0.010(0.25) BSC GAUGE PLANE

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 37 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PACKAGE INFORMATION (continued) TSSOP-20 NOTES: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AC. 6) DRAWING IS NOT TO SCALE. 0.19 0.30 6.40 6.60 SEATING PLANE

0.65 BSC

4.30 4.50 6.20 6.60 1 10 1120 0.80 1.05 1.20 MAX 0.05 0.15 TOP VIEW FRONT VIEW SIDE VIEW RECOMMENDED LAND PATTERN 5.80 TYP 1.60 TYP 0.40 TYP 0.65 BSC DETAIL A 0o-8o

0.25 BSC

SEE DETAIL "A"

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER HR1211 Rev. 1.0 www.MonolithicPower.com 38 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package xxxx–Z SOIC-20 (wide body) 1000 37 N/A 13in 24mm 12mm HR1211GM- xxxx–Z TSSOP-20 2500 75 N/A 13in 16mm 8mm Pin1 ABCD ABCD ABCD ABCD1 1 1 1 Feed Direction

HR1211 – MULTI-MODE PFC AND CURRENT MODE LLC COMBO CONTROLLER Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. HR1211 Rev. 1.0 www.MonolithicPower.com 39 1/4/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 1/4/2021 Initial Release -