HR1200

HR1200 MPS | Alldatasheet

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Digital PFC+LLC Combo Controller HR1200 Rev 1.02 www.MonolithicPower.com 1 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

DESCRIPTION

The HR1200 is a high -performance controller that integrates an advanced digital PFC controller and a half-bridge LLC resonant controller. It requires quite low input power at no load or ultra -light load , making it compliant with Energy using Product Directive (EuP) Lot 6 and Code of Conduct Version 5 Tier 2 specifications. The PFC of the HR1200 employs a patented average current control scheme , which can operate both in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) according to the instantaneous condition of the input voltage and output load. The IC exhibits excellent efficiency and high power factor (PF) at light load. In CCM, the HR1200 can be used in applications up to 500W with minimal board size limitations. The performance of the PFC can be optimized by programming multiple parameters through an I2C GUI. Programming can be completed either by the factory or by the customer referring to a detailed user guide. The half-bridge LLC resonant converter achieves high efficiency with zero-voltage switching (ZVS). The HR1200 implements an adaptive dead-time adjustment (ADTA) function to guarantee ZVS in different load conditions . Additionally, the HR1200 can prevent the LLC converter from operating in capacitive mode, making it more robust and easier to design. The HR1200 integrates a high -voltage (HV) current source i nternally for start-up. When the AC input is removed, the HV current source also functions as an X-cap discharger. Such features are helpful to reduce related d evices, thus reduce power consumption at no load. The HR1200 has multiple protection features including thermal shutdown (TSD), open-loop protection (OLP), over-current protection (OCP), over-voltage protection (OVP) , and brown- in/brown-out protection.

FEATURES

 Meets EuP Lot 6 and COC Version 5 Tier 2 Specifications  HV Current Source for Start-Up  Smart X-Cap Discharger  Standard I2C Interface  1k EEPROM to Store Parameters  User-Friendly GUI for Digital PFC PFC Controller  High Efficiency from Light Load to Full Load by CCM/DCM Multi-Mode Control  High PF Due to Patented Input Capacitor Current Compensation  Programmable Frequency Jittering  Programmable Brown-In and Brown-Out  Programmable Soft Start  Cycle-by-Cycle Current Limit  Open-Loop Protection LLC Controller  600V High-Side Gate Driver with Integrated Bootstrap Diode and High dv/dt Immunity  Adaptive Dead-Time Adjustment of HB LLC with Minimum and Maximum Limit  Burst Mode Switching  Safe Start-Up in Case of System Fault  Two-Level Over-Current Protection (OCP)  Latch Shutdown Protection  Over-Temperature Protection (OTP)  Capacitive Mode Protection

APPLICATIONS

 Notebook Adapters  All-in-One or Gaming Power Supply  Desktop PC and ATX Power  General AC/DC Power Supply up to 600W  LCD TV and Plasma TV Power Supply MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under quality assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. Analog digital adaptive modulation (ADAM) and advanced asynchronous mode (AAM) are trademarks of Monolithic Power Systems, Inc.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 2 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL APPLICATION LCM1 CX1 CX2 C1 LPFC D3 Cbus Vbus=400V Vout- FSET HBVS LSG HSG GNDP FBP HR1200 GATEP CSP TIMER VCC Vreg CSHB HV MP6922 Feedback Network BSTD1 D2 C2 Cbst Rsp Cr Lr C10 Rin1 Rin2 ACIN CHBVS BURST Rfmin Rfmax R10 C9SO SS CSS RSS SW V3.3 GNDD RES CT CT SDA SCL R8 C8 Cf Rf C6 GNDS Vout+ 90-264VAC 47-63Hz V3.3 RHV Figure 1: Typical Application

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 3 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking HR1200GM−XXXX* TSSOP-28 See Below HR1200GY−XXXX* SOIC-28 *−XXXX: internal code version control. For customer-specific projects, MPS will assign a special 4-digit number. For Tape & Reel, add suffix −Z (e.g. HR1200GM−XXXX−Z) For Tape & Reel, add suffix −Z (e.g. HR1200GY−XXXX−Z) TOP MARKING MPS: MPS prefix YY: year code WW: week code HR1200: first six digits of the part number LLLLLLLLL: lot number EVALUATION KIT EVKT-1200-TSSOP EVKT-1200-TSSOP Kit contents: (Items below can be ordered separately). # Part Number Item Quantity

1 EVHR1200-M-02A HR1200 evaluation board (HR1200 in TSSOP-28) 1

2 EVHR1200 PMBUS Kit-01A Programming dongle 1

3 T-USB Isolation Block-00A USB isolator 1

4 Tdrive-HR1200 USB flash drive that stores the GU I installation file

and supplemental documents 1 5 - USB cable 1 6 - Ribbon cable 1 EVALUATION KIT EVKT-1200-SOIC EVKT-1200-SOIC Kit contents: (Items below can be ordered separately). # Part Number Item Quantity

1 EVHR1200-S-01C HR1200 evaluation board (HR1200 in SOIC-28) 1

4 Tdrive-HR1200 USB flash drive that stores the GUI installation file

and supplemental documents 1 5 - USB cable 1 6 - Ribbon cable 1 Order direct from MonolithicPower.com or our distributors.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 4 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PACKAGE REFERENCE FBP RES FSET TIMER SDA SCL SS HV HSG BST SW HBVS GNDS BURST GNDD CT V3.3 CSHB CSP ACIN SO VCC VREG GATEP GNDP LSG HR1200 FBP RES FSET TIMER SDA SCL SS HV HSG BST SW HBVS GNDS BURST GNDD CT V3.3 CSHB CSP ACIN SO VCC VREG GATEP GNDP LSG HR1200 NC 18 NC TSSOP-28 SOIC-28

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 5 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Recommended Operating Conditions(1) Thermal Resistance(4) θJA θJC ABSOLUTE MAXIMUM RATINGS(2) Parameter Symbol Condition Min Max Units General Total power dissipation(3) Ptotal Tamb = 125°C 1.56 W Storage temperature Tstg -55 +150 C Junction temperature TJ -40 +150 C Lead temperature TLEAD 260 C Voltage Voltage on HV VHV Continuous -0.5 +700 V Floating supply voltage VBST -1 +618 V Floating ground voltage VSW -3 +618 V Voltage on high-side gate driver VHSG +618 V Floating ground max. slew rate dVSW/dt 50 V/ns Voltage on VCC VCC -0.5 +38 V Voltage on VREG Vreg -0.5 +14 V Voltage on low-side gate driver VLSG -0.5 +14 V Voltage on PFC gate driver VPFCG -0.5 +14 V Voltage on CS VCS -6.5 +6.5 V Voltage on HBVS VHBVS -0.3 Self-limited V Other analog pins -0.5 6.5 V Other digital pins -0.5 2 V Analog ground to digital ground GNDP/GNDS to GNDD -0.3 +0.3 V Current Current on HBVS IHBVS -65 +65 mA Source current of FSET IFSET 2 mA ESD(4) All pins Human body model 2000 V All pins Machine model 200 V All pins Charged device model 500 V NOTES: 1) The device is not guaranteed to function outside of its operating conditions. 2) Exceeding these ratings may damage the device. 3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-to-ambient thermal resistance θJA, and the ambient temperature T A. The maximum allowable continuous po wer dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) Measured on JESD51-7, 4-layer PCB.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 6 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed by characterization, typical is tested under 25°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units High-Voltage Start-Up Current Source (HV) Breakdown voltage VHVBR 700 V Normal charge current IHVNOR VHV = 100V, VCC = 15V, TJ = 25°C 5.5 7 8.5 mA Normal charge current IHVNOR VHV = 100V, VCC = 15V 4.5 7 8.9 mA Supply current when fault occurs IHVLimit VHV = 100V, VCC = 0V 0.8 1.4 2.1 mA Leakage current when turned off IHVoff VHV = 400V, VCC = 24V 7 10 µA IC Power Supply (VCC) IC turn-on threshold voltage when HV is detected VCCON(HV) VHV > VHVON 20 21.5 23.1 V UV protection threshold 1 VCCUVP1 LLC operation 10.5 11.3 12.1 V UV protection threshold 2(5) VCCUVP2 LLC disabled 13.9 15 16.2 V IC release threshold VCCRST 8.4 9 9.9 V Operation current at normal ICC(nor) RRES =20kΩ fPFC = 120kHz fLLC = 200kHz 14 mA Start-up current ICC-start1 VCC = 20V 0.55 0.7 mA Current at fault (LLC fault, PFC operation)(5) ICC-Disable1 TIMER = 4V PFC burst 2 mA Current at fault (LLC fault, PFC fault)(5) ICC-Disable2 TIMER = 4V 0.5 mA Regulated Power Supply (VREG) Regulated output voltage Vreg Ireg = 0mA 11 12 12.8 V Ireg = 30mA 10.8 11.8 12.6 V IC enable threshold VregON 10.2 10.8 11.5 V UVP VregUVP 7.7 8.2 8.8 V Power Supply for Digital Core (V3.3) Voltage regulation range V3V3 I3V3 = 0mA 2.95 3.15 3.45 V I3V3 = 15mA 2.85 3.1 3.35 V X-Cap Discharger (HV) X-cap discharger current(5) IX-d 5.5 mA X-cap discharger clock time TX-d 0.9 1.5 2.4 ms PFC Gate Driver Sourcing capacity(5) Igate_sr CGate = 1nF 750 mA Sinking capacity(5) Igate_sk CGate = 1nF -800 mA Gate-on resistor Ron(H) Sourcing 20mA 4.5 Ω Ron(L) Sinking 20mA 2.5 Ω Voltage fall time Tf CGate = 1nF 10 ns Voltage rise time Tr CGate = 1nF 15 ns

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 7 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed by characterization, typical is tested under 25°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units Reference Current (RES) Voltage regulation range VRT TJ = 25°C 1.245 1.25 1.255 V System Clock Clock frequency fosc_nor At normal 19 MHz fosc_nopwm At fault or burst off 1 MHz AC Input Sensing (ACIN) Voltage range KACIN = 0.0032 0 1.6 V PFC Feedback (FBP) Voltage range KACIN = 0.0032 0 1.6 V Current Sense (CSP) Voltage range KACIN = 0.0032 0 1.6 V Bias current in CSP Icsp-bias RRES = 20kΩ 61 62.5 64 µA ADC for ACIN, FB, and CSP ADC voltage reference TJ = 25°C 1.593 1.600 1.607 V ADC resolution(6) 10 bits Acquisition time(6) 350 ns Integral non-linearity (INL)(6) ±7.0 LSB Differential non-linearity (DNL)(6) ±4.5 LSB Offset error(6) ±0.5 LSB Gain error(6) ±1.5 LSB DAC for OVP and OCL Reference voltage TJ = 25°C 1.593 1.600 1.607 V Resolution(6) 7 bits Integral non-linearity (INL)(6) ±1.5 LSB Differential non-linearity (DNL)(6) ±0.3 LSB Offset error(6) ±0.2 LSB Gain error(6) ±1.5 LSB Output setting time(5) 5 µs DAC for Set Comparator Reference voltage TJ = 25°C 1.593 1.600 1.607 V Resolution(6) 10 bits Integral non-linearity (INL)(6) ±4.5 LSB Differential non-linearity (DNL)(6) ±2.0 LSB Offset error(6) ±0.5 LSB Gain error(6) ±1.5 LSB

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 8 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed by characterization, typical is tested under 25°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units Comparator for Set Signal, OVP, and OCL Offset voltage 60 360 mV I2C Characteristics (SCL/SDA)(5) Input high voltage (VIH) 2.1 V Input low voltage (VIL) 0.8 V Output low voltage (VOL) 0.4 V I2C Timing Characteristics(5) Operating frequency range 100 400 kHz Bus free time Between stop and start 4.7 μs Holding time 4.0 μs Repeated start condition setup time 4.7 μs Stop condition setup time 4.0 μs Data hold time 0 ns Data setup time 250 ns Clock low time out 25 35 ms Clock low period 4.7 μs Clock high period 4.0 50 μs Clock/Data fall time 300 ns Clock/Data rise time 1000 ns High-Side Floating Gate Driver Supply (BST, SW) BST leakage current ILKBST VBST = 600V 10 µA SW leakage current ILKSW VSW = 582V 10 µA Current Sensing of the Half-Bridge (CSHB) Frequency shift threshold VCS-OCR OCR 0.7 0.77 0.83 V OCP threshold VCS-OCP OCP 1.41 1.48 1.55 V Current polarity comparator reference when HSG is on VCSPR 80 mV Current polarity comparator reference when LSG is on VCSNR -80 mV Output Voltage Sense (SO) Latch protection on SO VSO-Latch 3.22 3.42 3.6 V Start-up failure protection on SO VSO-SFP 1.85 1.96 2.08 V Pull-up current on SO ISO-PU 100 nA Oscillator (FSET, CT) Output duty cycle D TJ = 25°C 48 50 52 % TJ = -40°C to 125°C 47 50 53 %

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 9 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed by characterization, typical is tested under 25°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units Oscillation frequency fosc 600 kHz CT peak value VCTP 3.54 3.74 3.94 V CT valley value VCTV 0.79 0.87 0.95 V Voltage reference at FSET VREF 1.88 1.97 2.06 V Dead time tDMIN CHBVS = 5pF 240 ns tDMAX 0.82 1.1 1.38 µs Timer for CMP tD_float HBVS floating 230 300 390 ns tD_CMP 50 µs Half-Bridge Voltage Sensing (HBVS) Voltage clamp VHBVS-C 7.5 V Minimum voltage for the change rate to be detected dvmin/dt CHBVS = 5pF, typically 190 V/µs Turn-on delay Td Slope finish to turn -on delay 130 ns Soft-Start Function (SS) Discharge resistance Rd VCS > VCS-OCR 120 Ω Threshold for OCP VSS-OCP VCS > VCS-OCP 1.61 1.72 1.82 V Standby Function (BURST) Disable threshold Vth 1.18 1.23 1.28 V Hysteresis Vhys 40 mV Delayed Shutdown (TIMER) Charge current ICHARGE VTIMER = 1V, VCS = 0.85V, SO = 3V 90 140 180 µA Charge current for SFP ICHARGE_SFP SO < 2.5V 25 µA Threshold for forced operation at maximum frequency Vth1 1.87 1.97 2.07 V Shutdown threshold Vth2 3.25 3.45 3.65 V Restart threshold Vth3 0.23 0.29 0.35 V Low-Side Gate Driver (LSG) Peak source current(5) Isourcepk 0.75 A Peak sink current(5) Isinkpk 0.87 A Sourcing resistor Rsource 4 Ω Sinking resistor Rsink 2 Ω Fall time tf 20 ns Rise time tr 20 ns

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 10 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed by characterization, typical is tested under 25°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units High-Side Gate Driver (HSG, Referenced to SW) Peak source current(5) Isourcepk 0.74 A Peak sink current(5) Isinkpk 0.87 A Sourcing resistor Rsource 4 Ω Sinking resistor Rsink 2 Ω Fall time tf 20 ns Rise time tr 20 ns Thermal Shutdown Thermal shutdown threshold 145 °C Thermal shutdown recovery threshold 100 °C NOTE: 5) Guaranteed by design. 6) Guaranteed by characterization.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 11 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 12 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued)

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 13 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 85V to 265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 14 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 85V to 265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 15 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 85V to 265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 16 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PIN FUNCTIONS Package Pin # Name Description 1 SDA I2C data bus. Connect a suitable pull-up resistor from SDA to V3.3.

2 ACIN

Input voltage sensing . ACIN is connected to ADC internally. The voltage is used for on-time calculation and brown-in/brown-out protection. The ratio of the external resistor divider should be 0.0032 . It is recommended to connect a 680pF cap acitor from ACIN to GNDD.

3 RES

Reference current for producing system clock and bias voltage on CSP. RES connects to a precise reference voltage of 1.25 V internally. The reference current is produced by connecting a 20kΩ, 0.5% resistor externally from RES to GNDD. 4 CSP Sensing of the PFC inductor current . Connect a 20kΩ, 0.5 % resistor to CS to produce a bias voltage of 1.25V. 5 GNDD Ground reference for the digital core of the PFC. 6 GNDP Ground reference of the PFC gate driver and the LLC low-side gate driver. 7 GATEP Gate driver output of the PFC MOSFET. 8 VREG Regulated power supply. VREG provides a regulated power supply for the PFC and LLC gate drivers or external circuits.

9 LSG

Low-side gate driver of HB. The driver is capable of a minimum 0. 7A sourc ing current and a minimum 0.8A peak sinking current to drive the lower MOSFET of the half-bridge leg. LSG is actively tied to GND during UVLO. 10 TIMER Setting of protection and recovery time. Connect a capacitor and a resistor from TIMER to GNDS to set both over-current protection delay and recovery delay. 11 SO Latch function for OVP and OTP . If the SO voltage exceeds VSO-Latch, the IC stops switching immediately and remains latched off until VCC drops below VCCRST. When the LLC is enabled during start -up, if the SO voltage is still below VSO-SFP after the TIMER voltage reaches Vth2, the IC stops operating. Connect SO and GNDS with a noise-decoupling capacitor more than 100nF placed as close to the IC as possible. 12 VCC IC supply power . When the power is on, VCC is charged up by HVCS internally at first and then by the auxiliary power supply. 13, 18 NC Not connected. NC is not connected in SOIC28 package and removed in TSSOP28 package to increase creepage distance. 14 HV High-voltage current so urce for the IC start -up. HV also acts as an X-cap discharger when the input voltage drops out. 15 BST Voltage bootstrap . BST is connected externally to a capacitor to build a power supply to drive the high-side MOSFET of the HB LLC. 16 HSG High-side gate driver of HB . HSG is the gate driver output for the high-side MOSFET of the HB LLC. 17 SW Reference of the high-side gate driver and bootstrap capacitor.

19 HBVS

Slope sensing to achieve adaptive dead -time adjustment. Detect the dv/dt of the half-bridge mid -point. A 5pF high -voltage capacitor is recommended between SW and HBVS. LLC works with fixed dead-time (about 300ns) when HBVS is floating. Connecting HBVS to GNDS disables the LLC switching. 20 GNDS Ground reference of LLC and power management circuits.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 17 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PIN FUNCTIONS (continued) Package Pin # Name Description

21 CSHB

Current sense of half -bridge. The LLC current can be sensed by a sense resistor or a capacitive divider. CSHB has the following functions: 1. Over-current regulation: As the voltage exceeds the VCS-OCR threshold, the soft-start capacitor on SS discharges internally . The frequency increases, limiting the output power. An output short circuit results in a nearly constant peak primary current. A timer set on ACIN limits the duration of this condition. 2. Over-current protection: If the current continues to build up (despite the frequency increase) when the CSHB voltage reaches VCS-OCP, CSS is discharged continuously, and OCP is not triggere d immediately until VSS < VSS-OCP. If the condition for VCS > VCS-OCP remains once VSS drops below VSS-OCP, the IC shuts down. CTIMER continues to be charged by an internal 140µA current source until the TIMER voltage reaches Vth2. The IC resumes operation when the TIMER voltage falls below Vth3. 3. Capacitive mode protection : The moment LSG is turned off, the CSHB voltage level is compared with a -80mV CMP threshold. If CSHB > -80mV, it blocks the HSG gate output until the slope comes down or the CMP time r runs out. Once HSG is turned off, CSHB is compared with a +80mV CMP threshold. If CSHB < +80mV, it blocks the LSG gate output until the slope comes up or the CMP timer run s out. As soon as capacitive mode is detected, the soft -start capacitor on SS discharges internally and the frequency increases. All functions are disabled when CSHB is connected to GND.

22 BURST

Burst mode control. If the voltage on BURST is lower than Vth (1.23V), the IC is disabled and resumes when the voltage exceeds 1.23V with a h ysteresis of about 40mV. During burst mode, s oft-start is not activated. This function helps reduce power loss at a lighter load.

23 FSET

Switching frequency set. Provide a precise and stable V REF (1.97V) reference voltage. Current flow ing out of FSET regu lates the LLC switching frequenc y and output voltage. The minimum frequency is set via a resistor connected to GND. The resistor connecting the optocoupler and FSET sets the maximum frequency. An RC series connected from FSET to GND determines the specific operating frequency. 24 CT Time set . Current flow ing out of FSET is mirrored to charge and discharge the capacitor connected from CT to GNDS, which determines LLC switching frequency. 25 SS Soft-start for LLC. Connect an external capacitor from SS to GND and a resistor to FSET to set both the maximum oscillator frequency and the time constant for the frequency shift during start-up. An internal switch discharges the capacitor when the chip is turned off to guarantee soft-start (all protections are listed except CMP). 26 V3.3 A stable 3.3V voltage for digital PFC core or external circuit . A 10µF decoupling ceramic capacitor is recommended to connect V3.3 and GNDS.

27 FBP

Voltage sensing of PFC output. The voltage of FBP is sampled by ADC . FBP is also used in on-time calculation, OVP , OLP, and digital PI. The ratio of the external resistor divider should be 0.0032. It is recommended to connect a 680pF capacitor from FBP to GNDD. 28 SCL I2C serial clock input. Connect a suitable pull-up resistor from SCL to V3.3.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 18 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. BLOCK DIAGRAM X-Cap Discharger VREG OSC BST HG SW LG GNDS CSHB EEPROM I2C SDASCL V3.3 FBP GNDP FSET ADCMUX PFC Control Logic SS CCM Off-Time/OCL LDO LDO GATEP Vreg Vreg Slope Detection VCS-OCP VCS-OCR Vreg OCR OCP Current Direction +/-80mV SO SFP VSO-Latch VSO-SFP Latch DAC Level Shifter OVP_PFC OLP_PFC DAC CSP Power Supply Management VULO_3.3V ACIN LLC Control Logic OCP Vth IfminSS_Ctrl HBVS CCO VREF RES 100µA LLC_Sych (3.3V) GNDP GNDP GNDS Vcc 1.25V Ibias Ibias K*Ibias TIMER V3.3 Set/OCL GNDD Pgood LDO V1.8V 100pF Vcc LLC_BO/BI (3.3V) PWM(3.3V) BURST VCCHV IHVNOR=7mA Figure 2: Functional Block Diagram

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 28 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. (n)I(n)I pkpk  (14) The new turn -on time can be calculated with Equation (15): (n)TV (n)VV(n)t s o_ref ino_ref on (15) The delay time is calculated with Equation (16): s_max pk ref ss_maxd T(n)I (n)I21)n(TT(n)t  (16) Soft Start (SS) Once the AC input voltage is larger than VIN_BI, the Vin_ok sig nal pulls high , and the HR1200 initiates a soft-start sequence (see Figure 24). Vin_ok PWM softstart_flag Vin Vout Vo_start Vo_target Tss Figure 24: Soft-Start Sequence The output voltage rises from the rectified output voltage to the target value. When softstart_flag is set high, the soft-start sequence is completed. The soft -start time can be calculated with Equation (17): slewrateV 12)VV(T adc_ref bit_num (17) where Vo_target is the target value of the output voltage, Vo_start is the soft -start value of the output voltage, bit_num is the ADC data bit (12 typically), Vadc_ref is the reference voltage of ADC (1.6V typically). The s lew rate is different at high line and low line. The slew rate at high line is programmable in register 1Ch; the slew rate at the low line is programmable in register 1Dh. Burst-Mode Operation At light load, the IC is always designed to run in burst mode for better efficiency or less no -load power consumption. Once the output load is lower than the threshold (e.g. 3% rated load), the PFC enters burst mode. The threshold can be programmed in register 2Dh for high line and register 2Fh f or low line. In burst mode, the switching duty is calculated based on the 3% rated load . The output is regulated to Vo_target with a 5V hysteresis. The PFC keeps switching when the output v oltage is below Vo_target-5V. The PFC stops switching when the output voltage ramps up to Vo_target. Burst-mode operation is synchronized with the LLC_sync signal. If the LLC_sync signal is high, the PFC PWM switching is turned off. Once the output voltag e is lower than Vo_target-5V, the PFC is turned on again even if the LLC_sync signal is high . This status continues until the output voltage ramps up to Vo_target. When the PFC recovers from burst mode, it operates in critical conduction mode (CRM) for the first five switching cycles. Capacitor Current Compensation Traditional PFC control schemes only regulate the inductor current to match the shape of the input voltage. However, the input capacitor current is not controlled which may cause PF deterioration and undesired delay. With a larger capacitor or a higher input voltage, t he PF even worsens. To improve the PF, the HR1200 implements a patented method to compensate for PF deterioration. Relevant data are stored in registers from 4Bh to 4Eh , corresponding to different input voltage level s. With this function, the PF is improved at all input voltage levels. Frequency Jittering In order to reduce the EMI noise, t he switching frequency is designed to be modulated by a triangular waveform with the frequency o f f m. The switching frequency is modulated to the maximum value at the peak of the triangle and to the minimum value at its valley. Figure 2 5 shows the algorithm modulat ing the switching frequency.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 30 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. where R FSET represents the total equivalent resistor on FSET. The minimum and maximum freq uency can be calculated with Equation (19) and Equation (20): min min RfCT3 1f  (19) )Rf||Rf(CT3 maxmin max  (20) The values of Rfmin and Rfmax can be extracted: min min fCT3 1Rf  (21) f RfRf min max min max (22) Soft Start (SS) For the resona nt half -bridge converter, the power delivered is inversely proportional to the switching frequency. To ensure the converter starts or restart s safely, the soft -start function sets the switching frequency at a high value until the value is controlled by the closed loop. The soft-start can be easily achieved using an external RC series circuit. At the beginning of the start-up sequence, the SS voltage is 0V. The soft-start resistor RSS is in parallel with Rfmin. So Rfmin and R SS determine the initial frequency: )R||Rf(CT3 ssmin start  (23) During start-up, CSS is charged until its voltage reaches the reference VREF, and the current flowing through RSS drops to zero. This period takes about 5RSSCSS. During this period, the switching frequency changes following an exponential curve . Initially, the C SS charging process decays relatively quick ly, but the rate slows progressively. After this period, the output voltage is still not close to the setting value, so the feedback loop take s over after start-up. With a soft-start function, the input current increases gradually until the output voltage reaches the setting point with little overshoot. The parameters of the soft-start RC network can be chosen according to Equation (24) and Equation (25): f RfR min start min ss (24) ss ss R 103C  (25) Select the initial frequency fstart at least four times the minimum value fmin. When selecting CSS, there is a trade-off between the desired soft-start operation and the OCP speed. Adaptive Dead-Time Adjustment (HBVS) The dead -time period between HSG and LSG drivers is always needed in half -bridge topologies in order to prevent any cross - conduction through the power stage MOSFETs, which may result in excessive current, high EMI noise and destructions in practical applica tions. Traditional fixed dead -time control scheme is often used in resonant converters as it is simple to implement. However, this method can cause hard switching in light load or large L m design condition which eventually leads to thermal and reliability issues. The HR120 0 incorporates an intelligent ADTA logic circuit, which is capable of detecting the dv/dt of SW and automatically inserting a proper dead -time with respect to the actual operating conditions of the converter. To achieve this, a 5pF high -voltage capacitor is recommended between SW and HBVS. With ADTA, the MOSFET body diode conduction time can be minimized which enables the LLC converter to achieve high efficiency from light load to full load due to ZVS. Moreover, the design of thermal manage ment and L m of the transformer can be easier. Figure 28 shows the simplified block diagram of ADTA. Once HSG switches off, SW begins swinging from a high voltage to a low voltage due to the resonant tank current I r. A negative d v/dt draws a current from HB VS via CHBVS. HBVS is pulled down depending on d v/dt and C HBVS. If the differential current is higher than the internal comparator current, HBVS will be pulled down to zero and clamped. When SW stops slewing , the differential current elapses accordingly . HBVS starts to ramp up. LSG switches on after a minimum dead-time.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 36 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. driver wire, the MOSFET parasitic capacitance, and the small gate -driver resistor. The voltage spike may cause damage to LSG. Although there is suppression internally in the chip, it is better to add a 13V Zener diode close to LSG and GND to prevent damage to the chip pins (see Figure 40). Low Side Driver LSG Vreg Rg 13V Cgs Cgd Cds SW GNDP Figure 40: Low-Side Gate Driver

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 37 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PROTECTION SUMMARY Pin Symbol Description Affected Action VCC VCC_UVP Under-voltage protection for VCC System Disable VCC VCC_SCP Short-circuit protection for VCC System Disable and limit IHV VREG Vreg_UVP Under-voltage protection for VREG System Disable and limit Ich (Vreg) SO VSO_Latch Latch protection System Shutdown and latch SO VSO_SFP Start-up failure protection System Restart with timer out OTP Over-temperature protection System Disable ACIN Brown-out Line input under-voltage protection System Suspend switching CSP OCP_PFC Current limit of PFC PFC Program with restart or latch off FBP OVP_PFC Over voltage of PFC PFC Suspend switching FBP OLP_PFC Open-loop protection System Restart with recovery FBP UVP_PFC Under-voltage protection for PFC out HBC Suspend switching LLC brown-in/-out LLC stage under-voltage protection HBC Suspend switching CSHB OCR_HBC Over-current regulation of HBC HBC Restart with timer out CSHB OCP_HBC Over-current protection HBC HBC Shutdown, restart with timer out CSHB CMR Capacitive mode regulation HBC Increasing switching frequency CSHB ADT Adaptive dead time HBC Prevent hard switching

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 38 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUIT Figure 41: Application Circuit

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 39 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

PACKAGE INFORMATION

PACKAGE OUTLINE DRAWING FOR 28-TSSOP MF-PO-D-0024 revision 1.0 0.19 0.30 9.60 9.80 SEATING PLANE

0.65 BSC

4.30 4.50 6.20 6.60 1 14 1528 0.80 1.05 1.20 MAX 0.05 0.15 TOP VIEW FRONT VIEW SIDE VIEW 0.09 0.20 SEE DETAIL "A" RECOMMENDED LAND PATTERN 5.80 TYP 1.60 TYP 0.40 TYP 0.65 BSC DETAIL “A” 0.45 0.750o-8o

0.25 BSC

NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AE. 6) DRAWING IS NOT TO SCALE.

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 40 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PACKAGE INFORMATION (continued) SOIC-28 PACKAGE OUTLINE DRAWING FOR 28-SOIC MF-PO-D-0022 revision 2.0 NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MS-013, VARIATION AE. 6) DRAWING IS NOT TO SCALE. 0.013(0.33) 0.020(0.51) 0.697(17.70) 0.713(18.10) SEATING PLANE 0.050(1.27) BSC PIN 1 ID 0.291 (7.40) 0.299 (7.60) 0.394 (10.00) 0.418 (10.60) 1 14 1528 0.093(2.35) 0.104(2.65) 0.004(0.10) 0.012(0.30) TOP VIEW FRONT VIEW SIDE VIEW 0.009(0.23) 0.013(0.33) RECOMMENDED LAND PATTERN 0.370 (9.40) 0.079 (2.00) 0.024 (0.61) 0.050 (1.27) SEE DETAIL "A" 0.016(0.41) 0.050(1.27)0o-8o DETAIL "A" 0.010(0.25) 0.030(0.75) x 45o 0.010(0.25) BSC GAUGE PLANE

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 41 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. APPENDIX A: I2C COMMANDS AND REGISTERS VOUT_CMD_H (02/01h, 10bits) Set the normal value of the output voltage target at high line. The default setting for the -0001 version is 1100011110. Command VOUT_CMD_H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w VOUT_CMD_L (04/03h, 10bits) Set the normal value of the output voltage target at low line. The default setting for the -0001 version is 1100011110. Command VOUT_CMD_L Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w VIN_HL_LINE (05h, 8bits) Set the threshold of high line and low line. The default setting for the -0001 version is 01110001. Command VIN_HL_LINE Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUT_VCOMP1 (07/06h, 14bits) Set the Load Level1 of the auto-output voltage . The default setting for the -0001 version is 011111111100. Command AUTO_VOUT_VCOMP1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUT_VCOMP2 (09/08h, 14bits) Set the Load Level2 of the auto-output voltage . The default setting for the -0001 version is 001100110010. Command AUTO_VOUT_VCOMP2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUT_VCOMP3 (0B/0Ah, 14bits) Set the Load Level 3 of the auto-output voltage . The default setting for the -0001 version is 000110011001. Command AUTO_VOUT_VCOMP3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUT_CMPHYS (0D/0Ch, 14bits) Set the load hysteresis of the auto-output voltage . The default setting for the -0001 version is 000011110101. Command AUTO_VOUT_CMPHYS Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 42 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. AUTO_VOUTH_CMD1_L (0Eh, 8bits) Set the low byte of the output voltage level one at high line. The default setting for the -0001 version is 00011110. Command AUTO_VOUTH_CMD1_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUTH_CMD2_L (0Fh, 8bits) Set the low byte of the output voltage level two at high line. The default setting for the -0001 version is 00011110. Command AUTO_VOUTH_CMD2_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUTH_CMD3_L (10h, 8bits) Set the low byte of the output voltage level three at high line. The default setting for the -0001 version is 00011110. Command AUTO_VOUTH_CMD3_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUTH_CMD_H (11h, 6bits) Set the high byte of the output voltage at high line. The default setting for the -0001 version is 111111. Bit Item Description 5:4 AUTO_VOUTH_CMD3_H High bits of output voltage level three at high line. 3:2 AUTO_VOUTH_CMD2_H High bits of output voltage level two at high line. 1:0 AUTO_VOUTH_CMD1_H High bits of output voltage level one at high line. Command AUTO_VOUTH_CMD_H Bit 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w AUTO_VOUTL_CMD1_L (12h, 8bits) Set the low byte of the output voltage level one at low line. The default setting for the -0001 version is 00011110. Command AUTO_VOUTL_CMD1_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUTL_CMD2_L (13h, 8bits) Set the low byte of the output voltage level two at low line. The default setting for the -0001 version is 00011110. Command AUTO_VOUTL_CMD2_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w AUTO_VOUTL_CMD3_L (14h, 8bits) Set the low byte of the output voltage level three at low line. The default setting for the -0001 version is 00011110. Command AUTO_VOUTL_CMD3_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 43 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. AUTO_VOUTL_CMD_H (15h, 6bits) Set the high byte of the output voltage at low line. The default setting for the -0001 version is 111111. Bit Item Description 5:4 AUTO_VOUTL_CMD3_H High bits of output voltage level three at low line. 3:2 AUTO_VOUTL_CMD2_H High bits of output voltage level two at low line. 1:0 AUTO_VOUTL_CMD1_H High bits of output voltage level one at low line. Command AUTO_VOUTL_CMD_H Bit 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w LLC_ENABLE_HIGH (17/16h, 10bits) Set the enable threshold voltage of the LLC. The default setting for the -0001 version is 1100101010. Command LLC_ENABLE_HIGH Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w LLC_ENABLE_LOW (19/18h, 10bits) Set the disable threshold voltage of the LLC. The default setting for the -0001 version is 1001010001. Command LLC_ENABLE_LOW Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ZCD_PERIOD_H (1Ah, 7bits) Set the oscillation period of the turn-off current at high line. The default setting for the -0001 version is 0010100. Command ZCD_PERIOD_H Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w ZCD_PERIOD_L (1Bh, 7bits) Set the oscillation period of the turn-off current at low line. The default setting for the -0001 version is 0101000. Command ZCD_PERIOD_L Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w SLEWRATE_HIGH (1Ch, 8bits) Set the soft-start slew rate at high line. The default setting for -0001 version is 00000110. Command SLEWRATE_HIGH Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w SLEWRATE_LOW (1Dh, 8bits) Set the soft-start slew rate at low line. The default setting for the -0001 version is 00001101. Command SLEWRATE_LOW Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 44 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TS1_L (1Eh, 8bits) Set the low byte of the switching period at level one of the input voltage. The default setting for the -0001 version is 11001000. Command TS1_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w TS2_L (1Fh, 8bits) Set the low byte of the switching period at level two of the input voltage. The default setting for the -0001 version is 11001000. Command TS2_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w TS3_L (20h, 8bits) Set the low byte of the switching period at level three of the input voltage. The default setting for the -0001 version is 11001000. Command TS3_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w TS4_L (21h, 8bits) Set the low byte of the switching period at level four of the input voltage. The default setting for the -0001 version is 10100111. Command TS4_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w TS_H (22h, 4bits) Set the high byte of the switching period. The default setting for the -0001 version is 0000. Bit Item Description 3 TS4_H High bit of switching period at level four of the input voltage. 2 TS3_H High bit of switching period at level three of the input voltage. 1 TS2_H High bit of switching period at level two of the input voltage. 0 TS1_H High bit of switching period at level one of the input voltage. Command TS_H Bit 7 6 5 4 3 2 1 0 Access r r r r r/w r/w r/w r/w TS_MIN1_L (23h, 8bits) Set the low byte of the maximum switching period at level one of the input voltage. The default setting for the -0001 version is 00100000. Command TS_MIN1_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w TS_MIN2_L (24h, 8bits) Set the low byte of the maximum switching period at level two of the input voltage. The default setting for the -0001 version is 00100000. Command TS_MIN2_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 45 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TS_MIN3_L (25h, 8bits) Set the low byte of the maximum switching period at level three of the input voltage. The default setting for the -0001 version is 00100000. Command TS_MIN3_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w TS_MIN4_L (26h, 8bits) Set the low byte of the maximum switching period at level four of the input voltage. The default setting for the -0001 version is 11110100. Command TS_MIN4_L Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w TS_MIN_H (27h, 8bits) Set the high byte of the maximum switching period. The default setting for the -0001 version is 01111111. Bit Item Description 7:6 TS_MIM4_H High bit of the maximum switching period at level four. 5:4 TS_MIN3_H High bit of the maximum switching period at level three. 3:2 TS_MIN2_H High bit of the maximum switching period at level two. 1:0 TS_MIN1_H High bit of the maximum switching period at level one. Command TS_MIN_H Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w JITTER_AMPLITUDE (28h, 8bits) Set the peak -to-peak amplitude of the switching frequency jitter . The default setting for the -0001 version is 00000010. Command JITTER_AMPLITUDE Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w JITTER_FS (30/29h, 13bits) Set the step value and the period of step of the switching frequency jitter. The default setting for -0001 version is 0100000011110. Bit Item Description 12:11 JITTER_STEP Step value. 10:0 STEP_PERIOD Step period. Command JITTER_FS Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w TON_MIN (2Bh, 5bits) Set the minimum turn-on time. The default setting for the -0001 version is 01100. Command TON_MIN Bit 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 46 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. MIN_OFF_TIME (2Ch, 5bits) Set the minimum turn-off time. The default setting for the -0001 version is 01100. Command MIN_OFF_TIME Bit 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r/w BURST_POINT_H (2E/2Dh, 13bits) Set the PFC burst load at high line. The default setting for the -0001 version is 0000111101011. Command BURST_POINT_H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w BURST_POINT_L (30/2Fh, 13bits) Set the PFC burst load at low line. The default setting for the -0001 version is 0000111101011. Command BURST_POINT_L Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w NORMAL_KI (31h, 8bits) Set the Ki value at normal operation mode. The default setting for the -0001 version is 00010010. Command NORMAL_KI Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w NORMAL_KP (32h, 8bits) Set the Kp value at normal operation mode. The default setting for the -0001 version is 01111000. Command NORMAL_KP Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w FAST_KI (34/33h, 10bits) Set the Ki value at fast-loop operation mode. The default setting for the -0001 version is 0001001000. Command FAST_KI Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w FAST_KP (36/35h, 10bits) Set the Kp value at fast-loop operation mode. The default setting for the -0001 version is 0100100000. Command FAST_KP Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w FASTLOOP_VOLTAGE (37h, 7bits) Set the fast -loop level below the output voltage target. The default setting for the -0001 version is 0011111. Command FASTLOOP_VOLTAGE Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 47 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. VIN_BI_LEVEL (39/38h, 10bits) Set the brown-in voltage of the input voltage. The default setting for the -0001 version is 0011101101. Command VIN_BI_LEVEL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w VIN_BO_LEVEL (3B/3Ah, 10bits) Set the brown-out voltage of the input voltage. The default setting for the -0001 version is 0011011001. Command VIN_BO_LEVEL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w VIN_BIBO_TIME (3Ch, 8bits) Set the brown -in and brown -out time of the input voltage. The default setting for the -0001 version is 00000101. Bit Item Description 7:4 VIN_BI_TIME Brown-in time. 3:0 VIN_BO_TIME Brown-out time. Command VIN_BIBO_TIME Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w IREF_LEVEL1 (3E/3Dh, 9bits) Level one of the input current reference. The default setting for the -0001 version is 010001001. Command IREF_LEVEL1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w IREF_LEVEL2 (40/3Fh, 9bits) Level two of the input current reference. The default setting for the -0001 version is 001000101. Command IREF_LEVEL2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w IREF_HYS (41h, 8bits) Set the hysteresis of the level of the input current reference. The default setting for the -0001 version is 00010111. Command IREF_HYS Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w VIN_BO_TRIM1 (42h, 6bits) Set the trim value of the brown-out level of the input voltage at level one. The default setting for the -0001 version is 000000. Command VIN_BO_TRIM1 Bit 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 48 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. VIN_BO_TRIM2 (43h, 6bits) Set the trim value of the brown -out level of the input voltage at level two. The default setting for the -0001 version is 000000. Command VIN_BO_TRIM2 Bit 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w OCP_LIMIT (44h, 7bits) Set the over-current limit of the inductor current. The default setting for the -0001 version is 0000100. Command OCP_LIMIT Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w OCP_MODE (45h, 4bits) Set the over-current protection mode. The default setting for the -0001 version is 0000. Bit Item Description

3 OCP_MODE_EN 1: enable

0: disable 2:0 OCP_MODE 000: latch 111: hiccup other: retry number Command OCP_MODE Bit 7 6 5 4 3 2 1 0 Access r r r r r/w r/w r/w r/w OCP_RETRY_DELAY (47/46h, 10bits) Set the delay time of the system recovery after the OCP event is cleared. The default setting for the -0001 version is 0111110100. Command OCP_RETRY_DELAY Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w OVP_LIMIT_H (48h, 7bits) Set the over-voltage limit of the output voltage at high line. The default setting for the -0001 version is 1101101. Command OVP_LIMIT_H Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w OVP_LIMIT_L (49h, 7bits) Set the over -voltage limit of the output voltage at low line. The default setting for the -0001 version is 1101101. Command OVP_LIMIT_L Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 49 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. CODE ID (4Ah, 8bits) Store customer code ID. The default setting for the -0001 version is 00000001. Bit Item Description 7:2 CUSTOMER_ID Customer number 1:0 PROGRAMMED CODE_ID Programmed code number Command CODE ID Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w IREF_COMP_VALUE1 (4Bh, 7bits) Set the first compensation amplitude of the input current reference. The default setting for the -0001 version is 0000001. Command IREF_COMP_VALUE1 Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w IREF_COMP_VALUE2 (4Ch, 7bits) Set the second compensation amplitude of the input current reference. The default setting for the -0001 version is 0000011. Command IREF_COMP_VALUE2 Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w IREF_COMP_VALUE3 (4Dh, 7bits) Set the third compensation amplitude of the input current reference. The default setting for the -0001 version is 0001101. Command IREF_COMP_VALUE3 Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w IREF_COMP_VALUE4 (4Eh, 7bits) Set the fourth compensation amplitude of the input current reference. The default setting for the -0001 version is 0001100. Command IREF_COMP_VALUE4 Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w VIN_LEVEL_SEL1 (4Fh, 8bits) Set the first voltage level of the input voltage. The default setting for the -0001 version is 10011001. Command VIN_LEVEL_SEL1 Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w VIN_LEVEL_SEL2 (50h, 8bits) Set the second voltage level of the input voltage. The default setting for the -0001 version is 01001000. Command VIN_LEVEL_SEL2 Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 50 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. VCOMP_MAX_L (52/51h, 16bits) Set the maximum load. The default setting for the -0001 version is 0110110011010010. Command VCOMP_MAX_L Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w VCOMP_MAX_H (53h, 8bits) Set the maximum load. The default setting for the -0001 version is 01011001. Command VCOMP_MAX_H Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w IREF_MAX (55/54h, 9bits) Set the maximum value of the input current reference. The default setting for the -0001 version is 111100100. Command IREF_MAX Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w SYS_CONFIG (56h, 8bits) Configure the system. The default setting for the -0001 version is 00110100. Bit Item Description

7 BURST_LLC_SYNC_EN

Synchronize PFC with LLC in burst mode. 1: enable 0: disable

5 POWER_ON

Power on the system. 1: enable 0: disable

4 LLC_EN

Enable LLC part. 1: enable 0: disable

3 AUTO_VOUT_EN

Output voltage target is determined by the load. 1: enable 0: disable

2 IREF_COMP_EN

Compensate the current of the input capacitance. 1: enable 0: disable

1 JITTER_EN

Switching frequency jitter. 1: enable 0: disable

0 ZCD_EN

Valley turn on. 1: enable 0: disable Command SYS_CONFIG Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 51 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. AD_SLEEP_FS (58/57h, 10bits) Set the ADC sample rate when PWM is off. The default setting for the -0001 version is 1100100000. Command AD_SLEEP_FS Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w TON_AHEAD (59h, 4bits) Set the peak-current sample point. The default setting for the -0001 version is 0010. Command TON_AHEAD Bit 7 6 5 4 3 2 1 0 Access r r r r r/w r/w r/w r/w OLP_HIGH (5Ah, 7bits) Set the open-loop protection at high level. The default setting for the -0001 version is 1011100. Command OLP_HIGH Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w OLP_LOW (5Bh, 7bits) Set the open-loop protection at low level. The default setting for the -0001 version is 0111101. Command OLP_LOW Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w SOFT_TON (5Ch, 7bits) Set the soft turn-on time when the system recovers from OVP. The default setting for the -0001 version is 0101000. Command SOFT_TON Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w SOFT_SWITCH_CNT (5Dh, 4bits) Set the number of switching events during soft turn on. The default setting for the -0001 version is 0111. Command SOFT_SWITCH_CNT Bit 7 6 5 4 3 2 1 0 Access r r r r r/w r/w r/w r/w MFR_MERGE_REG (5Eh, 8bits) The default setting for the -0001 version is 00100001. Bit Item Description 7:3 SWITCH_BLANK_TIME1 PWM off blanking time 2:1 CURRENT_MIRROR_GAIN Set the current mirror gain. The reference current is 62.5µA. 00: GAIN =1 01: GAIN = 1.4 10: GAIN = 1.6 11: GAIN = 2

0 I2C_FILTER_EN

I2C filter. 1: enable 0: disable Command MFR_MERGE_REG Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 52 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. SWITCH_BLANK_TIME (5Fh, 8bits) Set the PWM on blanking time. The default setting for the -0001 version is 00110101. Bit Item Description 7:4 SWITCH_BLANK_TIME2 PWM off blanking time for OCP. 3:0 SWITCH_BLANK_TIME3 PWM off blanking time for OCL. Command SWITCH_BLANK_TIME Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w OVP_DELAYTIME (60h, 6bits) Set the blanking time of OVP. The default setting for the -0001 version is 110010. Command OVP_DELAYTIME Bit 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w BURST_MODE_HYS (61h, 6bits) Set the hysteresis of the output voltage in burst mode. The default setting for the -0001 version is 001010. Command BURST_MODE_HYS Bit 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w ERROR_ZERO_REGION (62h, 5bits) Set the non-regulation region of the output voltage. The default setting for the -0001 version is 00000. Command ERROR_ZERO_REGION Bit 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r/w VIN_ZERO_POINT (63h, 7bits) Set the period detection point of the input voltage. The default setting for the -0001 version is 1010010. Command VIN_ZERO_POINT Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w VIN_PEAK_VALUE (64h, 7bits) Set the value to detect the top of the input voltage. The default setting for the -0001 version is 0010100. Command VIN_PEAK_VALUE Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w VIN_VALLEY_VALUE (65h, 7bits) Set the value to detect the valley of the input voltage. The default setting for the -0001 version is 0111101. Command VIN_VALLEY_VALUE Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER HR1200 Rev 1.02 www.MonolithicPower.com 53 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. IPK_BIAS_TRIM (66h, 8bits) Trim the bias voltage at CSP. The default setting for the -0001 version is 00000000. Bit Item Description

7 CSP_FAULT_MODE

Determine the control mode when CSP is open or shorted. 1: hiccup 0: latch

6 IPK_BIAS_SAMPLE_EN

Enable sampling of the CSP bias voltage when power is on. 1: enable 0: disable 5:0 IPK_BISA_TRIM Trim the bias voltage at CSP. Command IPK_BIAS_TRIM Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w ADC_OFFSET_TRIM (67h, 5bits) Trim the ADC offset. The default setting for the -0001 version is 00000. Command ADC_OFFSET_TRIM Bit 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r/w DELTA_VOLTAGE (68h, 7bits) Set the minimum delta voltage between the input voltage and output voltage for CSP bias voltage sampling. The default setting for the -0001 version is 0101001. Command DELTA_VOLTAGE Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w VIN_LEVEL1 (69h, 7bits) Input voltage leve l one for the CSP bias voltage sample. The default setting for the -0001 version is 0010100. Command VIN_LEVEL1 Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w VIN_LEVEL2 (6Ah, 7bits) Input voltage level two for the CSP bias voltage sample. The default setting for the -0001 version is 0101001. Command VIN_LEVEL2 Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w VIN_LEVEL3 (6Bh, 7bits) Input voltage level three for the CSP bias voltage sample. The default setting for the -0001 version is 0111101. Command VIN_LEVEL3 Bit 7 6 5 4 3 2 1 0 Access r r/w r/w r/w r/w r/w r/w r/w

HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER NOTICE: The information in this document is subject to change without not ice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. HR1200 Rev 1.02 www.MonolithicPower.com 54 4/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. VIN_LEVEL4 (6D/6Ch, 10bits) Input voltage level four for the CSP bias voltage sample. The default setting for the -0001 version is 0100110011. Command VIN_LEVEL4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w VIN_HL_HYS (6Eh, 8bits) Set the hysteresis of the input voltage for adaptive control. The default setting for the -0001 version is 00000101. Command VIN_HL_HYS Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w ZCD_VIN_HYS (6Fh, 6bits) Set the hysteresis of the input voltage for valley turn on. The default setting for the -0001 version is 010100. Command ZCD_VIN_HYS Bit 7 6 5 4 3 2 1 0 Access r r r/w r/w r/w r/w r/w r/w

Summary

High-Performance Digital PFC+LLC Combo Controller

Description