HR1000A

HR1000A MPS | Alldatasheet

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Technical content

Resonant Half-Bridge Controller HR1000A Rev. 1.01 www.MonolithicPower.com 1 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. The Future of Analog IC Technology

DESCRIPTION

The HR1000A is a controller designed specifically for the resonant half-bridge topology. It provides two drive-signal channels that output complementary signals at a 50% duty cycle. An internal fixed dead-time of 350ns between the two complementary gate signals guarantees zero-voltage switching during the transient and enables high-frequency operation. The integrated bootstrap diode simplifies the external driving circuit for the high-side switch. It can withstand up to 600V with immunity against high dV/dt noise. Modulating the switching frequency regulates the topology output voltage. A programmable oscillator can set both the maximum and minimum switching frequencies. The IC starts up at the programmed maximum switching frequency and gradually slows until the control loop takes over to prevent excessive inrush current The IC can be forced to enter a controlled burst- mode operation at light-load to minimize the power consumption and tighten output regulation. Protections features—including latched shutdown, auto-recovery, brown-out protection, and over- temperature protection—improve converter design safety without engendering additional circuit complexity. The IC provide 1.5A/2A source/sink capability for both high-side and low-side gate drivers. The HR1000A is available in a SO-16 package.

FEATURES

• 50% Duty Cycle, Variable Frequency Control For Resonant Half-Bridge Converter
• 600V High-Side Gate Driver with Integrated Bootstrap Diode and High dV/dt Immunity
• 1.5A/2A Source/Sink Capability for Both High-Side and Low-Side Gate Drivers
• High-Accuracy Oscillator
• Operates at up to 600kHz
• Two-Level Over-Current Protection: Frequency-Shift and Latched Shutdown with Programmable Duration Time
• Remote ON/OFF Control and Brown-Out Protection through the BO Pin
• Latched-Disable Input for Easy Protections Implementation
• Interfaces with PFC Controller
• Programmable Burst-Mode Operation at Light-Load
• Non-Linear Soft-Start for Monotonic Output Voltage Rise
• SO-16 package

APPLICATIONS

• LCD and PDP TVs
• Desktop PCs and Servers
• Telecom SMPS
• AC-DC Adapter, Open-Frame SMPS
• Video Game Consoles
• Electronic Lighting Ballast All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithi c Power Systems, Inc.

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 2 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. TYPICAL APPLICATION BLOCK DIAGRAM

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 3 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking HR1000AGS SOIC16 HR1000A * For Tape & Reel, add suffix –Z (e.g. HR1000AGS–Z). PACKAGE REFERENCE SS TIMER CT Fset BST HG SW N.C. VCC LG GND PFC Burst CS BO LATCH TOP VIEW ABSOLUTE MAXIMUM RATINGS (1) Symbol Pin Parameter Value Unit VBST 16 Floating supply voltage -1 to 618 V VSW 14 Floating ground voltage -3 to V BST-18 V dVSW/dt 14 Floating ground max. slew rate 50 V/ns VCC 12 IC supply voltage (I CC<25mA) Self-limited V VPFC 9 Maximum voltage (pin open) -0.3 to VCC V IPFC 9 Maximum sink current (pin low) Self-limited A IFset 4 Maximum source current 2 mA LG 11 Maximum voltage -0.3 to 16 V 1 to 8 Analog inputs and outputs -0.3 to 6 V PIC Continuous power dissipation (TA = +25°C) (2) 1.56 W TJ Junction Temperature 150 °C TLead Lead Temperature (Solder) 260 °C TStorage Storage Temperature -55 to +150 °C Recommended Operating Conditions (3) Operating Junction Temp (TJ). -40°C to + 125°C Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J(MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by D(MAX)=(T J(MAX)- T A)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circui try protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 4 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

TJ=25°C, VCC=13V, CHG=CLG=1nF; CT=470pF, RFset=12kΩ, unless otherwise specified. Parameter Symbol Min Typ Max Unit IC supply voltage (VCC) VCC operating range 8.9 15.5 V VCC high threshold, IC switch-on V CCH 10.3 11 11.7 V VCC low threshold, IC switch-off V CCL 7.5 8.2 8.9 V Hysteresis V hys 2.5 V VCC clamp current during fault condition (VCC=16V, Latch=2V) IClamp 6 mA VCC clamp voltage during fault condition (VCC>16V or VLATCH>1.85V or VCS>1.5V or VTIMER>3.5V or VBO<1.25V or VBO>5.5V or OTP) VClamp 15.3 V IC supply current (VCC) Start-up current (Before the device turns on, VCC=VCCH-0.2V) Istart-up 250 300 µA Quiescent current (Device on, VBurst=1V) I q 1.5 2 mA Operating current (Device on, VBurst=VFset) I op 3 5 mA Residual consumption (VCC>16V or VCC<8V VLATCH>1.85V or VCS>1.5V or VTIMER>3.5V or VBO<1.25V or VBO>5.5V or OTP) Ir 350 400 µA High-side floating-gate-driver supply (BST, SW) BST pin leakage current (VBST=600V) I LKBST 10 µA SW pin leakage current (VSW=582V) I LKSW 10 µA Input bias current (VCS=0 to VCSlatch) I CS 1 µA Leading-edge blanking t LEB 250 ns Frequency shift threshold V CSx 0.75 0.8 0.85 V Latch-off threshold V CSlatch 1.41 1.5 1.59 V Line voltage sensing (BO) Threshold voltage V th 1.2 1.25 1.3 V Clamp level V clamp 5.1 5.5 5.8 V Current Hysteresis (VCC>5V, VBO=0.3V) I Hyst 9 12 15 µA Latch function (LATCH) Input bias current (VLATCH=0 to Vth) I LATCH 1 µA LATCH threshold V th 1.75 1.85 1.95 V Oscillator Output duty cycle D 48 50 52 % Oscillation frequency f osc 600 kHz Dead-time t D 300 350 400 ns CT peak value V CFp 3.8 V CT valley value V CFv 0.9 V Voltage reference at Fset pin V REF 1.92 2 2.08 V PFC function (PFC) Low saturation level (IPFC=1mA, VLATCH=2V) V L 0.2 V Soft start function (SS) Discharge resistance (VCS>VCSx) R 120 Ω Standby function (Burst) Disable threshold V th 1.18 1.23 1.28 V Hysteresis V hys 100 mV

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 5 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) TJ=25°C, VCC=13V, CHG=CLG=1nF; CT=470pF, RFset=12kΩ, unless otherwise specified. Parameter Symbol Min Typ Max Unit Delayed shutdown (TIMER) Charge current (VTIMER=1V, VCS=0.85V) I CHARGE 80 130 180 µA Threshold for forced operation at maximum frequency Vth1 1.88 2 2.08 V Shut down threshold V th2 3.3 3.5 3.7 V Restart threshold V th3 0.25 0.3 0.35 V Low-side gate driver (LG, referenced to GND) Peak source current I sourcepk 1.5 A Peak sink current I sinkpk 2 A Sourcing resistor R source 4 Ω Sinking resistor R sink 2 Ω Fall time t f 20 ns Rise time t r 20 ns UVLO saturation (VCC=0 to VCCH, Isink=2mA) 1.1 V High side gate driver (HG, referenced to SW) Peak source current I sourcepk 1.5 A Peak sink current I sinkpk 2 A Sourcing resistor R source 4 Ω Sinking resistor R sink 2 Ω Fall time t f 20 ns Rise time t r 20 ns Thermal Shutdown Thermal shutdown threshold 150 °C Thermal shutdown recovery threshold 120 °C

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 6 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS Performance waveforms are generated using the evaluation board built with design example on page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted. 0.01 0.1 100 0 5 10 15 20 0.1 1.0 10.0 -50 0 50 100 150 ICC (mA) Operating @50kHz Residual Quiescent Start-up -50 0 50 100 150 -50 0 50 100 150 0.5 1.0 1.5 2.0 -50 0 50 100 150 OCP THRESHOLD (V) -50 0 50 100 150 1.6 1.7 1.8 1.9 2.0 -50 0 50 100 150 0.9 0.95 1.05 1.1 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (C) BO THRESHOLD (V) Clamp Enable Current Sense Threshold vs. TJ 14.9 15.0 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 Rising Falling VCC Falling VCC Rising

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 7 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are generated using the evaluation board built with design example on page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted. Reference Voltage vs. TJ Standby Threshold vs. TJCurrent Mirror Ratio vs. TJ OCP Delay Threshold vs. TJ Delay Shutdown Charge Current vs. TJ 0.8 0.9 1.1 1.2 -50 0 50 100 150 100 1000 1 10 100 Fsw (kHz) 220pF 330pF 470pF 680pF 1nF2.2nF 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 0 50 100 150 CT VOLTAGE (V) Peak value Valley value 0.98 0.99 1.00 1.01 1.02 1.03 1.04 -50 0 50 100 150 1.7 1.8 1.9 2.0 2.1 2.2 2.3 -50 0 50 100 150 REFERENCE VOLTAGE (V) CURRENT MIRROR RATIO (V) 1.15 1.20 1.25 1.30 1.35 1.40 1.45 -50 0 50 100 150 STANDBY THRESHOLD (V) Restart Disable -50 0 50 100 150 TEMPERATURE (C) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 0 50 100 150 TEMPERATURE (C) DELAY SHUTDOWN THRESHOLD (V) Shut down Restart Force to Max Fsw 100 120 140 160 180 Oscillator Frequency vs. Frequency-Set Resistance

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 8 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are generated using the evaluation board built with design example on page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted. Efficiency VSW 100V/div. VLG 10V/div. IR 1A/div. VSW 100V/div. VLG 10V/div. IR 1A/div. Steady State VOUT = 19V, IOUT = 4.7A Steady State VOUT = 19V, IOUT = 0A VOUT_RIPPLE /AC 100mV/div. VOUT_RIPPLE /AC 100mV/div. Steady State VOUT = 19V, IOUT = 4.7A Steady State VOUT = 19V, IOUT = 0A VLG 5V/div. VOUT 10V/div. IR 2A/div. Start-up VOUT = 19V, IOUT = 0A VLG 5V/div. VOUT 10V/div. IR 2A/div. VLG 5V/div. VOUT 10V/div. IR 2A/div. VLG 5V/div. VOUT 10V/div. IR 2A/div. Start-up VOUT = 19V, IOUT = 4.7A Shutdown VOUT = 19V, IOUT = 0A Shutdown VOUT = 19V, IOUT = 4.7A IOUT (A)

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 9 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are generated using the evaluation board built with design example on page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted. VLG 10V/div. VOUT 10V/div. IR 2A/div. VLG 10V/div. VOUT 10V/div. IR 2A/div. VLG 10V/div. VOUT 10V/div. IR 2A/div. SCP Entry VOUT = 19V, IOUT = 0A SCP Entry VOUT = 19V, IOUT = 4.7A SCP then Power-on VOUT = 19V

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 10 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 SS Soft-start. Connect an external capacitor with this pin to GND and a resistor to Fset pin to set the maximum oscillator frequency and the ti me constant for the frequency shift during start-up. An internal switch discharges the capacitor when the chip turns off (VCC < UVLO, VCC > 16V, BO < 1.25V or > 5.5V, LATCH > 1.85V, CS >1.5V, TIMER > 2V, thermal shutdown) to guarantee soft-start when the current sense pin voltage exceeds 0.8V, and as long as it stays above 0.75V.

2 TIMER

Period between over-current and shutdown. Connect a capacitor and a resistor from this pin to GND to set both the maximum duration from an over-current condition before the IC stops switching, and the delay before the IC resumes switching. Each time the CS pin voltage exceeds 0.8V, an internal 130µA source charges the capacitor; an external resistor slowly discharges this capacitor. If the pi n voltage reaches 2V, the soft-start capacitor discharges completely, pushing the switchi ng frequency to its maximum value; the 130µA source remains on. When the voltage exceeds 3.5V the IC stops switching and the internal current source turns off so that the pin vo ltage decays. The IC enters soft-started when the voltage drops below 0.3V. This allows the conver ter to work intermittently with very low average input power under short-circuit conditions. 3 CT Time-Set. An internal current source programmed by the external network connected to pin 4 charges and discharges a capacitor connected to GND. Determines the converter’s switching frequency.

4 Fset

Switching Frequency Set. Provides a precise 2V reference. A resistor connected from this pin to GND defines a current that sets t he minimum oscillator frequency. Connect the phototransistor of an opto-coupler to this pin through a resistor to close the feedback loop that modulates the oscillator frequency to r egulate the converter output voltage. The value of this resistor will set the maximum operati ng frequency. An R-C se ries connected from this pin to GND sets frequency shift at star t-up to prevent excessive energy inrush (soft- start).

5 Burst

Burst-Mode Operation Threshold. The pin se nses some voltage related to the feedback control, which is compared to an internal re ference (1.25V). If the voltage on the pin is lower than the reference, the IC enters an idle state and reduces its quiescent current. The chip resumes switching when the voltage exceed s the reference by 50mV. Soft-start is not invoked. This function enables burst-mode operation when the load falls below a programmed level, determined by connecting an a ppropriate resistor to the opto-coupler to pin Fset (see block diagram). Tie the pin to Fset if burst-mode is not used. 6 CS Primary-Current Sense. Uses a sense resistor or a capacitive divider to sense the primary current. The voltage signal requires an averaging filter because this input is not intended for cycle-by-cycle control. As the voltage exceeds a 0.8V threshold (with 50mV hysteresis), the soft-start capacitor on pin 1 discharges inte rnally: The frequency increases, limiting the power throughput. Under an output short circuit, th is normally results in a nearly-constant peak-primary current. A timer set on pin 2 limits t he duration of this condition. If the current continues to build up despite the frequency increase, a second comparator referenced at 1.5V latches the device off and brings its co nsumption up to about pre-start-up levels. The information is latched, requiring cycling t he IC supply voltage to restart: The latch is removed as the VCC voltage drops below the UV LO threshold. Tie the pin to GND if the function is not used.

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 11 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. PIN FUNCTIONS (continued) Pin # Name Description 7 BO Input Voltage Sense. Connect to the high-volt age input bus through the tap of a resistor divider to perform either AC or DC (in syst ems with PFC) brownout protection. A voltage below 1.25V shuts down (without latching) the IC, lowers its consumption and discharges the soft-start capacitor. The IC operati on resumes (with soft-start) when the voltage exceeds 1.25V. The comparator has current hyst eresis: An internal 12µA current source is ON as long as the applied voltage is below 1. 25V, and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. An internal Zener diode top-limits the pin voltage. Activating the Zener diode causes the IC to shut down (without latching). Bias the pin between 1.25V and 5.5V if the function is not used.

8 LATCH

IC Latch. Connects internally to a comparat or that—when the pin voltage exceeds 1.85V— shuts the IC down and brings its consumptio n to near pre-start-up levels. The latch is removed as the VCC voltage goes below the UVLO threshold. Tie the pin to GND if the function is not used.

9 PFC

Interface to the front-end PFC. This pin— normally high—stops the PFC controller for protection purposes or during burst-mode opera tion. It goes low when the IC shuts down from the following conditions: VCC > 16V, LATCH > 1.85V, CS > 1.5V, BO > 5.5V, thermal shutdown and BURST < 1.25V. The pin also goes low when the voltage on TIMER exceeds 2V, and goes back open as the voltage fa lls below 0.3V. During UVLO, it is open. Leave the pin unconnected if not used.

10 GND

Ground. Current return for both the low-side gate-driver current and the IC bias current. Tie all bias component ground connections to a trace to this pin. Keep separate from any pulsed current return. 11 LG Low-Side Gate Driver. The driver is capable of a minimum 0.5A source and a minimum 1A sink-peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND during UVLO. 12 VCC Supply Voltage. Supplies both the IC signal and the low-side gate driver. Sometimes a small bypass capacitor (e.g., 0.1µF) can help provide a clean bias voltage for the IC signal. 13 N.C. High-Voltage Spacer. Not internally conne cted—isolates the high-voltage pin and eases compliance with safety regulations (creepage-distance) on the PCB. 14 SW High-Side Switch Source. Current return fo r the high-side gate-drive current. Requires careful layout to avoid large spikes below ground. 15 HG High-Side Floating Gate-Driver. Capable of minimum 0.5A source and minimum 1A sink- peak current to drive the upper MOSFET of the half-bridge leg. An internal resistor connected to pin 14 (SW) ensures that the pin does not floating during UVLO.

16 BST

High-Side Gate Driver for Floating Voltage S upply. Connect a bootstrap capacitor between this pin and pin 14 (SW)—fed by an internal boot strap diode driven in-phase with the low- side gate-drive.

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 12 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. BLOCK DIAGRAM Figure 1: Functional Block Diagram

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 14 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 2. Under normal operation, the phototransistor modulates the current flow through Rf max to modulate the frequency for output voltage regulation. When the phototransistor is saturated, the current flow through Rf max is at its maximum, setting the frequency at its maximum 3. A series RC circuit connected between Fset and GND determines the frequency shift at start-up. (Please see the soft-start section for details.) Based on the previous principles, the following equations describe the minimum and maximum frequency: min min 1f 3C TR f= ⋅⋅ max min max 1f 3 CT (Rf || Rf )= ⋅⋅ Typically, the CT capacitance is between 0.1nF and 1nF, so the values of Rfmin and Rfmax are: min min 1Rf 3C Tf= ⋅⋅ min max max min RfRf f 1f For the CT capacitance selection, here is a note for low temperature and high switching frequency application: when the temperature is low, the source current capability of Fset pin drops a little due to the property of internal transistor circuit, which means there might be not big enough current to charge/discharge the large CT capacitor. So a small CT cap (<=330pF) is recommended for such application. Burst-Mode Operation Under light-load or in the absence of a load, the maximum frequency limits the resonant half- bridge switching frequency. To control the output voltage and limit power consumption, the HR1000A can enable compatible converters to operate in burst-mode to sharply reduce the average switching frequency, thus reducing the average residual magnetizing current and the associated losses. Operating in burst-mode requires setting the Burst pin on the HR1000A; if the voltage on the Burst pin drops below 1.25V, HR1000A will shut down the HG and LG gate drive outputs, leaving only the 2V reference voltage on the Fset pin and the SS pin to retain the previous state and minimize HR1000A’s power consumption. When the voltage on the Burst pin exceeds 1.25V by 50mV, HR1000A resumes normal operation. Based on the Burst-mode operating principle, the Burst pin voltage must connect to the feedback loop. Figure 4 shows a typical circuit connect the Burst pin to the feedback signal for narrow-input–voltage range applications: Figure 4: Bust-Mode Operation Set-Up In addition to setting the oscillator, Rf max also determines the maximum switching frequency that HR1000A operates in burst-mode. After confirming f max, calculate Rfmax as below: min max max min Rf3Rf f8 1f Here, f max corresponds to a load point, P Burst, where the peak current flow through the transformer is too low to cause audible noise. The above introduction is based on a narrow input voltage range. As a property of the resonant circuit, input voltage also determines the switching frequency. That means the P Burst has a large variance over the wide input voltage range. To stabilize P Burst over the input range, use the circuit in Figure 5 to insert the input voltage signal into feedback loop.

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 21 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. FLOW CHART START VCC capacitor is charged through pull-up resistor N VCC>10.5V Soft Start Y Normal Operation switching frequency is modulated by IFset Monitor BOMonitor ThermalMonitor CSMonitor LATCH BO>4.7V or BO<1.25V Y Monitor BurstMonitor TIMER NN Y CS>1.5VN CS>0.8V Y 1. Latch off the switching pulse 2. Soft start capacitor fully discharged 3. PFC pin pulled low 1. Stop the switching pulse 2. Soft start capacitor fully discharged TIMER>2VN Y 1. Increase the switching frequency 2. Soft start capacitor begin to discharge 3. TIMER capacitor is charged by an internal 150uA current source 1. Switching frequency is pushed to maximum value 2. Soft start capacitor fully discharge 3. TIMER capacitor is charged by an internal 150uA current source

4 PFC pin pulled

N TIMER>3.5V Y 1. Stop the switching pulse 2. Soft start capacitor fully discharged 3. TIMER capacitor discharged by external resistor 4. PFC pin pulled low TIMER<0.3V N N Y 1. Stop the switching pulse 2. Soft start capacitor fully discharged 3. PFC pin pulled low >10ºC <120ºC N Burst<1.25VN Y 1. Stop the switching pulse 2. PFC pin pulled low Burst>1.3V Y N 1. Resume the switching pulse 2. PFC pin pulled high 1.25V<BO<6V N Y Y Y LATCH>1.85V N Y 1. Latch off the switching pulse 2. Soft start capacitor fully discharged 3. PFC pin pulled low VCC<6.4V VCC<6.4V N N Y Y Monitor VCC N Y 1. Stop the switching pulse 2. Soft start capacitor fully discharged VCC<8V VCC>12V N Y Latched Shutdown OCP OTP Brown-out UVLO Burst ModeOCP

HR1000A – RESONANT HALF-BRIDGE CONTROLLER HR1000A Rev. 1.01 www.MonolithicPower.com 22 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. TYPICAL WAVEFORMS VCC LG/HG Soft Start PFC LATCH CS TIMER BO Burst Soft Start OCPOCP Latch Shutdown Brown- out OTP Burst Mode 12V 1.85V 1.5V 0.8V 0.3V 3.5V 1.25V Unplug from main input Over temperature

HR1000A – RESONANT HALF-BRIDGE CONTROLLER NOTICE: The information in this document is subject to change wi thout notice. Please contact M PS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights ar e not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. HR1000A Rev. 1.01 www.MonolithicPower.com 23 8/30/2012 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved.

PACKAGE INFORMATION

0.016(0.41) 0.050(1.27)0o-8o DETAIL "A" 0.010(0.25) 0.020(0.50) x 45 o SEE DETAIL "A" 0.0075(0.19) 0.0098(0.25) 0.150 (3.80) 0.157 (4.00) PIN 1 ID 0.050(1.27) BSC 0.013(0.33) 0.020(0.51) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.386( 9.80) 0.394(10.00) 0.053(1.35) 0.069(1.75) TOP VIEW FRONT VIEW 0.228 (5.80) 0.244 (6.20) SIDE VIEW 1 8 16 9 RECOMMENDED LAND PATTERN 0.213 (5.40) 0.063 (1.60) NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AC. 6) DRAWING IS NOT TO SCALE. 0.010(0.25) BSC GAUGE PLANE