HF01B00 MPS | Alldatasheet
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HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 1 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
DESCRIPTION
The HF01B00/01/02/03/04 is a flyback regulator with Green Mode Operation. Its high efficiency feature over the entire input/load range meet s the stringent world-wide energy-saving requirements. The HF01B00/01/02/03/04 is an integrated current mode controller with a 700V FET. Its valley switching detector ensures minimum Drain-Source voltage switching every cycle, per Quasi-resonant operation. When the output power falls below a given level, the regulator enters the burst mode to lower the stand-by power consumption. An internal minimum off time limiter prevents the switching frequency from exceeding 1 50 kHz, which is below the CISPR-22 EMI start limit. Internal 2 .4ms soft start prevents the excessive inrush current during start up The HF01B00/01/02/03/04 provides various protections, such as Thermal Shutdown (TSD), VCC Under Voltage Lockout (UVLO), Over Load Protection (OLP), Over Voltage Protection (OVP) and so on. The HF01B00/01/02/03 is available in PDIP8-7B package. And HF01B04 is available in PDIP8-7B and SOIC8-7B packages. P/N Maximum Output Power4 230Vac±15%3 85Vac~265Vac Adapter1 Open Frame2 Adapter1 Open Frame2 HF01B00DP 35W 54W 23W 30W HF01B01DP 29W 45W 18W 23W HF01B02DP 24W 33W 14W 17W HF01B03DP 22W 30W 11W 13W HF01B04DP 19W 23W 8W 11W HF01B04DS 19W 23W 8W 11W Notes: 1. Maximum continuous power in a non-ventilated enclosed adapter measured at 50℃ ambient temperature. 2. Maximum continuous power in an open frame design at 50 ℃ ambient temperature. 3. 230Vac or 110/115Vac with doubler. 4. The junction temperature can limit the maximum output power.
FEATURES
Internal Integrated 700V MOSFET High Level of Integration, Requires Very Few External Components Universal Input Voltage (85~265VAC) Quasi-Resonant Operation over the Entire Input and Load Range Maximum Switching Frequency Limited Valley Switching for High Efficiency a nd Better EMI Performance Active Burst M ode for Low Standby Power Consumption Internal High-Voltage Current Source for Start-Up Internal Soft Start Internal 320ns Leading Edge Blanking Thermal Shutdown (Auto Restart with Hysteresis) V CC Under Voltage Lockout with Hysteresis (UVLO) Over Voltage Protection Over Load Protection. No Load Consumption at 265Vac HF01B00<100mW HF01B01<80mW HF01B02/03<50mW HF01B04<30mW
APPLICATIONS
Battery charger for consumer and home equipment. Standby power supply. Small power SMPS for white goods and consumer electronics. Low/Medium power AC/DC adapter. For MPS green status, please visit MPS website under Quality Assurance . “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc.
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 2 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL APPLICATION RTN Input 85-265VAC T1 Output VSD1 S DS GND FB VCC HF01B00/01/02/03/04 Figure 1—Typical Application
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 3 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number Package Top Marking Free Air Temperature (TA) HF01B00DP* PDIP8-7B HF01B00 -40C to +85C HF01B01DP HF01B01 HF01B02DP HF01B02 HF01B03DP HF01B03 HF01B04DP HF01B04 HF01B04DS** SOIC8-7B HF01B04 -40C to +85C *For RoHS, compliant packaging, add suffix –LF (e.g. HF01B00DP–LF). ** For Tape & Reel, add suffix –Z (e.g. HF01B04DS–Z); For RoHS, compliant packaging, add suffix –LF (e.g. HF01B04DS–LF–Z). PACKAGE REFERENCE PDIP8-7B & SOIC8-7B ABSOLUTE MAXIMUM RATINGS (1) Continuous Drain Switch Current (2) ESD Capability Human Body Model (All Pins Recommended Operation Conditions (3) Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) Continuous Drain switch current when inductor load is assumed: limited by maximum duty and maximum junction temperature. And the data get from the following conditions: D=50% Fs=100kHz Ipeak 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 4 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VCC =12V, TA=+25℃, unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit Start-up Current Source (Pin D) Supply current from Pin D Icharge VCC =6V; VD=400V 1.4 2 2.6 mA Leakage current from Pin D Ileak VCC =13V; VD=400V 20 μA Break Down Voltage V(BR)DSS 700 -- V On-State Resistance HF01B00 RDS(ON) VCC =10V; ID=100mA 1.9 Ω HF01B01 3.3 HF01B02 5.5 HF01B03 7.7 HF01B04 11 Supply Voltage Management (Pin Vcc) VCC Upper Level at which the Internal High Voltage Current Source Stops VCCH 10.6 11.8 13 V VCC Lower Level at which the Internal High Voltage Current Source Triggers VCCL 7.2 8 8.8 V VCC Decreasing Level at which the Latchoff Phase Ends Vcclatch 5.5 V Internal IC Consumption, Latchoff Phase ILatch VCC =6.0V 400 μA Feedback Management (Pin FB) Internal Pull Up Resistor RFB 10 kΩ Internal Pull Up Voltage Vup 4.5 V Pin8 to Current Set point Division Ratio Idiv 3.3 Internal Soft-Start Time Tss 2.4 ms FB Decreasing Level at which the Regulator enter the Burst Mode VBURL 0.5 V FB Increasing Level at which the Regulator leave the Burst Mode VBURH 0.7 V Over Load Set Point VOLP 3.7 V Valley Switching Detector (Pin VSD) Valley Point Detection Threshold Voltage VVSD 30 45 60 mV Valley Point Detection Hysteresis Vhys 10 mV Pin VSD Clamp Voltage VVSDH High State Ipin=3.0mA 7 7.8 8.6 V VVSDL Low State Valley Point Detection Delay TVSD Pull down from 2V to -100mV 90 150 210 ns Parasitical Capacitance at Pin VSD Cpar 10 pF Minimum Off Time Tmin 6.6 7.8 9 μs Re-start time After Last Valley Point Detection Transition Trestart 4.6 μs OVP Sampling Delay TOVPS 3.5 μs Pin VSD OVP reference level VOVP 6 V Internal Impedance Rint 24 kΩ Current Sampling Management (Pin S) Leading Edge Blanking TLEB 320 ns Maximum current set-point VCS 1 V
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 5 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description
1 VSD
Valley switching detector of the auxiliary flyback signal. It ensures Discontinuous Conduction Mode (DCM) operation with valley switching over the entire input/load range. This pin also offers OVP detection.
2 VCC
Supply voltage pin. Typically connect a 22 μF bulk capacitor and a 0.1uF ceramic capacitor to this Pin. When VCC is charged to 12V, the internal high voltage current source turns off and the IC starts switching; when it falls back to 8V, the high voltage current source turns on again and the IC stops switching. 3 N/C Not connected. This pin ensures adequate creepage distance. 4 D Drain of the internal MOSFET. Input for the start up high voltage current source. 5 S Source of the internal MOSFET. Input of the primary current sense signal. 6 S Source of the internal MOSFET. Input of the primary current sense signal. 7 GND The IC Ground. 8 FB This pin sets the primary peak current limit, by directly connecting an optocoupler to this pin to close the feedback loop. A feedback voltage of 3.7V on this pin will trigger an Over Load Protection while 0.5V will trigger a Burst Mode operation. The regulator leaves Burst Mode Operation and enters normal operation when the FB voltage reaches 0.7V
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 6 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 7 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued)
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 8 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. FUNCTION BLOCK DIAGRAM S (5) S (6) FB(8)GND(7) Vcc(2) D(4) VSD(1) Start Up Unit Valley Detector Protection Unit Peak Current Limitation Power Management Burst Mode Control Driving Signal Management Figure 2—Block Diagram
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 12 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. Leading Edge Blanking (LEB) In normal operation, the primary peak current is sensed by a shunt resistor between the Source pin and Ground. The turn-off threshold of the MOSFET is set by FB voltage, Vsense=V FB/3.3. When the voltage drop of shunt resistor reaches Vsense, the MOSFET turns off. During start-up and over-load condition, the primary peak current threshold is internally limited to 1V even if V FB voltage is larger than 3.3V to avoid excessive output power and lower the voltage rating of the switch. In order to avoid turning off the MOSFET by mis- trigger spikes shortly after the switch turns on, the IC implements a 320ns leading edge blanking. During blanking time, any trigger signal on source pin is blocked. Figure 11 shows the primary current sense waveform and the leading edge blanking. 320ns Figure 11—Leading Edge Blanking
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 13 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. Start Vcc>11.8V Vcc<8.5V? and OLP=Logic High Internal High Voltage Current Source ON Toff< 7.8uS Y N Soft Start Monitor VFB Monitor Vcc VFB>3.7V0.5V<VFB<3.7VVFB<0.5V Burst Mode Operation QR mode Operation Constraint Toff_min≥7.8uS VFB>0.7V Y NNY OLP=Logic High Y Thermal Monitor Y Vcc Decrease to 5.5V Shut Down Internal High Voltage Current Source Latch off the Switching Pulse N Continuous Fault Monitor Vcc<8V Y N OVP= Logic High? N Y OTP= Logic High? Y N UVLO, OTP & OLP are auto restart, OVP is latch Release from the latch condition , need to unplug from the main input . Pin Demag Monitor Vcc<3V? Y N Shut off the Switching Pulse Y Figure 12—Control Flow Chart
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 14 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11.8V 5.5V Vcc Driver IFault Flag OVP Fault Occurs Here Driver Pluses Regulation Occurs Here High voltage current source Start up Normal operation Normal operation Normal operationOLP Fault Occurs Here On Off Over Voltage Occurs Here Normal operation OTP Fault Occurs Here Normal operation Unplug from main input Normal operation Normal operation Figure 13—Evolution of the Signal in Presence of a Fault
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 15 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
PACKAGE INFORMATION
NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH AND WIDTH DO NOT INCLUDE MOLD FLASH, OR PROTRUSIONS. 3) JEDEC REFERENCE IS MS-001. 4) DRAWING IS NOT TO SCALE. 0.008(0.20) 0.014(0.36) 0.240(6.10) 0.260(6.60)PIN 1 ID 0.050(1.27) 0.065(1.65) 0.367(9.32) 0.387(9.83) TOP VIEW FRONT VIEW SIDE VIEW 1 4 8 5 0.300(7.62) 0.325(8.26) 0.320( 8.13) 0.400(10.16) 0.125(3.18) 0.145(3.68) 0.120(3.05) 0.140(3.56) 0.015(0.38) 0.021(0.53) 0.100(2.54) BSC 0.015(0.38) 0.035(0.89)
HF01B00/01/02/03/04–OFF LINE HIGH VOLTAGE QUASI RESONANT REGULATOR NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. HF01B00/01/02/03/04 Rev. 1.2 www.MonolithicPower.com 16 4/9/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. SOIC8-7B 0.016(0.41) 0.050(1.27)0o-8o DETAIL "A" 0.010(0.25) 0.020(0.50) x 45o SEE DETAIL "A" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00)PIN 1 ID 0.050(1.27) BSC 0.013(0.33) 0.020(0.51) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) TOP VIEW FRONT VIEW 0.228(5.80) 0.244(6.20) SIDE VIEW 1 4 8 5 RECOMMENDED LAND PATTERN 0.213(5.40) 0.063(1.60) NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) JEDEC REFERENCE IS MS-012. 6) DRAWING IS NOT TO SCALE. 0.010(0.25) BSC GAUGE PLANE