HDMP-1536 HP | Alldatasheet

Document overview

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Technical content

Features

  • ANSI X3.230-1994 Fibre Channel Compatible (FC-0)
  • Supports Full Speed (1062.5 MBd) Fibre Channel
  • Compatible with “Fibre Channel 10-Bit Interface” Specification
  • Low Power Consumption, 630 mW
  • Transmitter and Receiver Functions Incorporated onto a Single IC
  • Auto Frequency Lock
  • Small Package Profile HDMP-1536, 10x10 mm QFP HDMP-1546, 14x14 mm QFP
  • 10-Bit Wide Parallel TTL Compatible I/Os
  • Single +3.3 V Power Supply

Applications

  • 1062.5 MBd Fibre Channel Interface
  • FC Interface for Disk Drives and Arrays
  • Mass Storage System I/O Channel
  • Work Station/Server I/O Channel
  • High Speed Proprietary Interface
  • High Speed Backplane Interface

Description

The HDMP-1536/46 transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. It provides a low-cost, low-power physical layer solution for 1062.5 MBd Fibre Channel or proprietary link interfaces. It provides complete FC-0 functionality for copper transmission, incorporating both the Fibre Channel FC-0 transmit and receive functions into a single device. This chip is used to build a high- speed interface (as shown in Figure 1) while minimizing board space, power, and cost. It is compatible with both the ANSI X3.230-1994/AM 1 - 1996 document and the “Fibre Channel 10-bit Interface” specification. The transmitter section accepts 10-bit wide parallel TTL data and multiplexes this data into a high- speed serial data stream. The parallel data is expected to be 8B/10B encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the 106.25 MHz reference clock (used as the transmit byte clock). The transmitter section’s PLL locks to this user supplied 106.25 MHz byte clock. This clock is then multiplied by 10, to generate the 1062.5 MHz serial signal clock used to generate the high- speed output. The high-speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber-optic module for optical transmission. The receiver section accepts a serial electrical data stream at

1062.5 MBd and recovers the

original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high-speed serial clock and data. The serial data is 5965-8113E (4/97)

In normal operation, LOOPEN is set low and the serial data stream is placed at ± DOUT. When wrap- mode is activated by setting LOOPEN high, the ± DOUT pins are held static and the serial output signal is internally wrapped to the INPUT SELECT box of the receiver section. INPUT SELECT The INPUT SELECT block deter- mines whether the signal at ± DIN or the internal loop-back serial signal is used. In normal opera- tion, LOOPEN is set low and the serial data is accepted at ± DIN. When LOOPEN is set high, the high-speed serial signal is internally looped-back from the transmitter section to the receiver section. This feature allows for loop-back testing exclusive of the transmission medium. RX PLL/CLOCK RECOVERY The RX PLL/CLOCK RECOVERY block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. An automatic locking feature allows the Rx PLL to lock onto the input data stream without external controls. It does this by continually frequency locking onto the 106.25 MHz clock, and then phase locking onto the input data stream. An internal signal detection circuit monitors the presence of the input, and invokes the phase detection as the data stream appears. Once bit locked, the receiver generates the high speed sampling clock at 1062.5 MHz for the input sampler, and recovers the two 53.125 MHz receiver byte clocks (RBC1/ RBC0). These clocks are 180° out of phase with each other, and are converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment. The recovered parallel data is presented to the user at TTL compatible outputs. The receiver section also recovers two

53.125 MHz receiver byte clocks

that are 180 degrees out of phase with each other. The parallel data is properly aligned with the rising edge of alternating clocks. The transceiver provides for on- chip local loop-back functionality, controlled through an external input pin. Additionally, the byte synchronization feature may be disabled. This may be useful in proprietary applications which use alternative methods to align the parallel data. HDMP-1536/46 Block Diagram The HDMP-1536/46 was designed to transmit and receive 10-bit wide parallel data over a single high-speed line, as specified for the FC-0 layer of the Fibre Channel standard. The parallel data applied to the transmitter is expected to be encoded per the Fibre Channel specification, which uses an 8B/10B encoding scheme with special reserve characters for link management purposes. In order to accomplish this task, the HDMP-1536/46 incorporates the following:

  • TTL Parallel I/Os
  • High Speed Phase Lock Loops
  • Clock Generation/Recovery Circuitry
  • Parallel to Serial Converter
  • High-Speed Serial Clock and Data Recovery Circuitry
  • Comma Character Recognition Circuitry
  • Byte Alignment Circuitry
  • Serial to Parallel Converter INPUT LATCH The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0..9]. The user-provided reference clock signal, REFCLK, is also used as the transmit byte clock. The TX[0..9] and REFCLK signals must be properly aligned, as shown in Figure 3. TX PLL/CLOCK GENERATOR The transmitter Phase Lock Loop and Clock Generator (TX PLL/ CLOCK GENERATOR) block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the supplied reference byte clock (REFCLK). REFCLK is used as both the frequency reference clock for the PLL and the trans- mit byte clock for the incoming data latches. It is expected to be

106.25 MHz and properly aligned

to the incoming parallel data (see Figure 3). This clock is multiplied by 10 to generate the 1062.5 MHz clock necessary for the high speed serial outputs. FRAME MUX The FRAME MUX accepts the 10- bit wide parallel data from the INPUT LATCH. Using internally generated high speed clocks, this parallel data is multiplexed into the 1062.5 MBd serial data stream. The data bits are trans- mitted sequentially, from the least significant bit (TX[0]) to the most significant bit (TX[9]). OUTPUT SELECT The OUTPUT SELECT block provides for an optional internal loopback of the high speed serial signal, for testing purposes.

frequency acquisition process. the reference clock (REFCLK). frequency locked to 53.125 MHz. valid data once it is reapplied. Figure 5. These output data

TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol Parameter Units Min. Max. VCC Supply Voltage V -0.5 5.0 VIN,TTL TTL Input Voltage V -0.7 V CC + 0.7 VIN,HS_IN HS_IN Input Voltage V 2.0 V CC IO,TTL TTL Output Source Current mA 13 Tstg Storage Temperature °C -40 +130 Tj Junction Operating Temperature °C 0 +130 Guaranteed Operating Rates TA[1] = 0°C to +60°C, VCC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Serial Baud Rate (MBaud) Min. Max. Min. Max. 106.20 106.30 1062.0 1063.0 Note: 1. Device tested and characterized under T A conditions specified, with T C monitored at approximately 20 ° higher than TA. Transceiver Reference Clock Requirements TA[1] = 0°C to +60°C, VCC = 3.15 V to 3.45 V Symbol Parameter Unit Min. Typ. Max. f Nominal Frequency (for Fibre Channel Compliance) MHz 106.20 106.25 106.30 Ftol Frequency Tolerance ppm -100 +100 Symm Symmetry (Duty Cycle) % 40 60 Note: 1. Device tested and characterized under T A conditions specified, with T C monitored at approximately 20 ° higher than TA. TA[1] = 0°C to +60°C, VCC = 3.15 V to 3.45 V Symbol Parameter Unit Min. Typ. Max. VIH,TTL TTL Input High Voltage Level, Guaranteed High Signal V 2 V CC for All Inputs VIL,TTL TTL Input Low Voltage Level, Guaranteed Low Signal for V 0 0.8 All Inputs VOH,TTL TTL Output High Voltage Level, IOH = -400 µA V 2.2 V CC VOL,TTL TTL Output Low Voltage Level, IOL = 1 mA V 0 0.6 IIH,TTL Input High Current (Magnitude), VIN = VCC µA 0.004 40 IIL-TTL Input Low Current (Magnitude), VIN = 0 Volts µA -325 -600 ICC,TRx[2,3] Transceiver VCC Supply Current, TA = 25°C mA 220 Notes: 1. Device tested and characterized under T A conditions specified, with T C monitored at approximately 20 ° higher than TA. 2. Measurement Conditions: Tested sending 1062.5 MBd PRBS 2 7-1 sequence from a serial BERT with both DOUT outputs biased with 150 Ω resistors. 3. Typical specified with V CC = 3.3 volts, maximum specified with V CC = 3.45 volts.

Symbol Parameter Units Min. Typ. Max.

  1. Device tested and characterized under T A conditions specified, with T C monitored at approximately 20 ° higher than TA.
  2. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.

a. Differential HS_OUT Output (Dout+ Minus Dout-). Figure 7. Transmitter DOUT Eye Diagrams. b. Single-Ended HS_OUT Output (Dout+). as Captured on the HP 83480A Digital Communications Analyzer. Tested with PRBS = 2 7-1.

1.25 GHz

125 MHz ENBYTSYNC

  1. Defined by Fibre Channel Specification Rev 4.1, Annex A, Section A.4 and tested using measurement method shown in Figure 8.

Symbol Parameter Units Typ. Max.

  1. Device tested and characterized under T A conditions specified, with T C monitored at approximately 20 ° higher than TA.
  2. PD is multiplying the max VCC by the max ICC and subtracting the power dissipated outside the chip at the high speed bias resistors.
  3. Typical specified with V CC = 3.3 volts, maximum specified with V CC = 3.45 volts.
  4. Specified with high speed outputs biased with 150 Ω resistors and receiver TTL outputs driving 10 pF loads.
  5. Based on independant package testing by HP. Θ ja for these devices is 48 °C/Watt for the HDMP-1536 and 44 °C/Watt for the

the top center of the package and P D is the power being dissipated. Figure 8. Transmitter Jitter Measurement Method. a. Block Diagram of RJ Measurement Method. b. Block Diagram of DJ Measurement Method.

1.4 V 0011111000

1.0625 GHz

106.25 MHz

Figure 11. HDMP-1536/46 (TRx) Package Layout and Marking, Top View. *Note: Pin 26 is designated as a “no connect” pin and should be left unconnected.

BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of either a comma character or a K28.5 special character (0011111XXX). It is only active when ENBYTSYNC is enabled. -DIN 52 HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the +DIN 54 ± DIN inputs when LOOPEN is low. -DOUT 61 HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when +DOUT 62 LOOPEN is set low. When LOOPEN is set high, these outputs are held static. ENBYTSYNC 24 I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync function to allow clock synchronization to a comma character, or a K28.5 character (0011111XXX). When the line is low, the function is dis- abled and will not reset registers and clocks, or strobe the BYTSYNC line. GND 21 S Logic Ground: Normally 0 volts. This ground is used for internal PECL 25 logic. It should be isolated from the noisy TTL ground as well as possible. GND_RXA 51 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the receiver PLL and high-speed analog cells. GND_RXHS 56 S Ground: Normally 0 volts. GND_RXTTL 32 S TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells 33 of the receiver section. GND_TXA 15 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the PLL and high-speed analog cells. GND_TXHS 64 S Ground: Normally 0 volts. GND_TXTTL 1 S TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells 14 of the transmitter section. -LCKREF 27 I-TTL Lock to Reference: When low, causes the PLL to acquire frequency and phase lock on the external reference, supplied at REFCLK. When high, the Rx PLL will automatically frequency lock to REFCLK and phase lock to the high speed data stream. LOOPEN 19 I-TTL Loopback Enable Input: When set high, the high-speed serial signal is internally wrapped from the transmitter’s serial loopback outputs back to the receiver’s loopback inputs. Also, when in loopback mode, the ± DOUT outputs are held static. When set low, ± DOUT outputs and ± DIN inputs are active. RBC1 30 O-TTL Receiver Byte Clocks: The receiver section recovers two 53.125 MHz RBC0 31 receive byte clocks. These two clocks are 180 degrees out of phase. The receiver parallel data outputs are alternatively clocked on the rising edge of these clocks. The rising edge of RBC1 aligns with the output of the comma character (for byte alignment) when detected. REFCLK 22 I-TTL Reference Clock and Transmit Byte Clock: A 106.25 MHz clock supplied by the host system. The transmitter section accepts this signal as the frequency reference clock. It is multiplied by 10 to generate the serial bit clock and other internal clocks. The transmit side also uses this clock as the transmit byte clock for the incoming parallel data TX[0]..TX[9]. It also serves as the reference clock for the receive portion of the transceiver.

RX[0] 45 O-TTL Data Outputs: One 10 bit data byte. RX[0] is the first bit received. RX[1] 44 RX[0] is the least significant bit. RXCAP1 49 be connected across the RXCAP0 and RXCAP1 pins. (typical value = 0.1 µF). TX[1] 3 transmitted. TX[0] is the least significant bit. TXCAP0 17 the TXCAP1 and TXCAP0 pins (typical value = 0.1 µF). supply line for the PLL and high-speed analog cells. 59 logic. It should be isolated from the noisy TTL supply as well as possible. supply line for the PLL and high-speed analog cells. Figure 10. Due to high current transitions, this V high-speed circuitry. Noise on this line should be minimized for best operation. 10 transmitter input buffer cells.

Package Information

Lead Finish Material 85% Tin, 15% Lead Lead Finish Thickness 300-800 µm Lead Coplanarity Mechanical Dimensions Figure 13. Mechanical Dimensions of HDMP-1536/46.