HDMP-1012

HDMP-1012 HP | Alldatasheet

Document overview

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• PDF pages: 42

Technical content

Features

• Transparent, Extended Ribbon Cable Replacement
• Implemented in a Low Cost Aluminum M-Quad 80 Package
• High-Speed Serial Rate 150-

1500 MBaud

• Standard 100K ECL Interface 16, 17, 20, or 21 Bits Wide
• Reliable Monolithic Silicon Bipolar Implementation
• On-chip Phase-Locked Loops - Transmit Clock Generation - Receive Clock Extraction

Applications

• Backplane/Bus Extender
• Video, Image Acquisition
• Point to Point Data Links
• Implement SCI-FI Standard
• Implement Serial HIPPI Specification

Description

The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user’s viewpoint, these products can be thought of as providing a “virtual ribbon cable” interface for the transmission of data. Parallel data loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link. The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phase- locked-loop clock extraction circuit also transparently provides for frame synchronization - the user is not troubled with the periodic insertion of frame synchronization words. In addition, the dc balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction. The Rx chip also includes a state-machine controller (SMC) that provides a startup handshake protocol for the duplex link configuration. The serial data rate of the T/R link is selectable in four ranges (see tables on page 5), and extends from 120 Mbits/s up to 1.25 Gbits/s. The parallel data interface is 16 or 20 bit single-ended ECL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user’s control. The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection. The serial link is synchronous, and both frame synchronization HDMP-1012 Transmitter HDMP-1014 Receiver 5962-0049E (6/94)

and bit synchronization are maintained. When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup. User control space is also sup- ported. If Control Available is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available line will indicate the data as a Control Word. It is the intention of this data sheet to provide the design engineer all of the information regarding the HDMP-1012/1014 chipset necessary to design this product into their application. To assist you in using this data sheet, the following Table of Contents is provided. Table of Contents Topic Page Mechanical Dimensions and Appendix I: Additional Internal HDMP-1014 (Rx) Link Control State Simplex Method III: Simplex with

For timing diagrams for the standard configurations, see the Appendix section entitled Link Configuration Examples. The HDMP-1012/1014 chipset can support serial transmission rates from 150 MBd to 1.5 GBd for each of these configurations. The chipset requires the user to input the link data rate by asserting DIV1 and DIV0 accordingly. To determine the DIV1/DIV0 setting necessary for each application, refer to the section: Setting the Operating Data Rate Range on the next page. Setting the Operating Data Rate Range The HDMP-1012/1014 chipset can operate from 150 MBaud to 1500 MBaud. It is divided into four operating data ranges with each range selected by setting DIV1 and DIV0 as shown in the tables below. The purpose of following example is to help in understanding and using these tables. This specific example uses the table in figure 3 entitled “Typical 20-bit Mode Data Rates”. It is desired to transmit a 20 bit parallel word operating at 55 MHz (55 MWord/sec). Both the Tx and Rx must be set to a range that this word rate falls in-between. According to table entitled “Typical Operating Rates for 20 Bit Mode” on the next page, a setting of DIV1/DIV0 = logic ‘0/0’ allows a parallel input word rate of 32.9 to 62.5 MHz . This setting easily accommodates the required 55 MHz word rate. The user serial data rate can be calculated as: = 1100 MBits/sec The baud rate includes an additional 4 bits that G-LINK transmits for link control and error detection. The serial baud rate is calculated as: = 1320 MBaud The 55 MHz example is one in which the parallel word rate provides only one possible DIV1/ DIV0 setting. Some applications may have a parallel word rate that seems to fit two ranges. As an example, a 35 MHz (35 MWord/s) parallel data rate fall within two ranges (DIV0/ DIV1 = 0/0 and DIV0/DIV1 = 0/ 1) in 20 Bit Mode. Per the table, a setting of DIV1/DIV0 = 0/1 gives an upper rate of 53.3 MHz , while a setting of DIV1/DIV0 = 0/0 gives a lower rate of 32.9 MHz. These transition data rates are stated in the tables as typical values and may vary between individual parts. Each transmitter/ receiver has continuous band cover across its entire 150 to

1500 MBaud range and has

overlap between ranges. Each transmitter/receiver will permit a

35 MHz parallel data rate, but it is

suggested that DIV0 be a jumper that can be set either to logic ‘1’ (ground) or logic ‘0’ (open). This allows the design to accommodate both ranges for maximum flexibility. This technique is recommended whenever operating near the maximum and minimum of two word rate ranges. The above information also applies to the HDMP-1012/ 1014 chipset when operating in 16 bit mode.

necessary serial clock rate. speed serial clock at STRBIN.

• Parallel Word Input
• High Speed Clock Multiplication
• Frame Encoding
• Parallel to Serial Multiplexing PLL/Clock Generator The Phase Lock-loop and Clock Generator are responsible for generating all internal clocks needed by the transmitter to perform its functions. These clocks are based on a supplied frame clock (STRBIN) and control signals (M20SEL, MDFSEL, EHCLKSEL, DIV1, DIV0). In normal operation (MDFSEL=0), STRBIN is expected to be the incoming frame clock. The PLL/ Clock Generator locks on to this incoming rate and multiplies the clock up to the needed high speed serial clock. Based on M20SEL, which determines whether the incoming data frame is 16 or 20 bits wide, the PLL/Clock Generator multiplies the frame rate clock by 20 or 24 respectively (data bits + 4 control bits). DIV1/DIV0 are set to inform the transmitter of the frequency range of the incoming data frames. The internal frame rate clock is accessible through STRBOUT and the high speed serial clock is accessible through HCLK. When MDFSEL is set high, the transmitter is in Double Frame Mode. Using this option, the user may send a 32 or 40 bit wide data frame in two segments while supplying the original 32 or 40 bit frame clock at STRBIN. Doubling of the frame rate is performed by

Figure 4. HDMP-1012 Transmitter Block Diagram.

maintain frequency and phase lock. The type of fill frames sent (FF0 or FF1) is determined by the FF input. In a duplex system, FF is normally connected to the Rx’s STAT1 pin. The C-Field Encoder, based on the inputs at DAV*, CAV*, FLAGSEL, and FLAG, supplies four encoded bits to the frame mux. This encoded data contains the master transition (which the receiver uses for frequency locking), as well as information regarding the data type: control, data, or fill frame. In order for the FLAG bit to be used as an additional data bit, FLAGSEL must be set high for both the Tx and the Rx. D-Field Encoder The D-Field Encoder provides the remaining parallel word data to the frame mux. Based on control signals from the Control Logic, the D-Field Encoder either outputs the parallel information at its data inputs (D0..D19) or the designated Fill Frame. RST*, when set low, resets the internal chip registers. Frame Mux The Frame Mux accepts the output from the C-Field and D- Field Encoders. The four control bits are attached to the data bits, either 16 or 20 data bits based on the M20SEL input. This parallel information, now either 20 or 24 bits wide, is multiplexed to a serial line based on the internal high speed serial clock. SIGN The sign circuitry determines the cumulative sign of the outgoing data frame, containing the data and control bits. This is used by the accumulator/inverter to maintain DC balance for the transmission line. Accumulator/Invert The Accumulator/Invert block is responsible for maintaining the DC balance of the serial line. It determines, based on history and the sign of the current data frame, whether or not the current frame should be inverted to bring the line closer to the desired 50% duty cycle. INV is set high when the data frame is inverted. Output Select In normal operation, the serial data stream is placed at DOUT. By asserting LOOPEN, the user may also direct the serial data stream to LOUT, which may be used for loopback testing. When LOOPEN is not asserted, LOUT is disabled to reduce power consumption.

• Clock Recovery
• Data Recovery
• Demultiplexing
• Frame Decoding
• Frame Synchronization
• Frame Error Detection
• Link State Control Input Select The input select block determines which input line is used. In normal operation (LOOPEN=0), DIN is accepted as the input signal. For improved distance and BER using coax cable, an input equalizer may be used by asserting EQEN. By setting LOOPEN high, the receiver accepts LIN as the input signal. This feature allows for loop back testing exclusive of the transmission medium. Phase/Freq Detect This block compares either the phase or the frequency of the incoming signal to the internal serial clock, generated from the Clock Select block. The frequency detect disable pin (FDIS) is set high to disable the frequency detector and enable the phase detector. See HDMP-1014 (Rx) Phase Locked Loop for more details. The output of this block, PH1, is used by the filter to determine the control signal for the VCO. Filter This is a loop filter that accepts the PH1 output from the Phase/ Freq Detector and converts it into a control signal for the VCO. This control signal tells the VCO whether to increase or decrease its frequency. The Filter uses the PH1 input to determine a proportional signal and an integral signal. The proportional signal determines whether the VCO should increase or decrease its frequency. The integral signal filters out the high frequency PH1 signal and stores a historical PH1 output level. The two signals combined determine the magnitude of frequency change of the VCO. VCO This is the Voltage Controlled Oscillator that is controlled by the output of the Filter. It outputs a high speed digital signal to the Clock Select.

Figure 5. HDMP-1014 Receiver Block Diagram.

The Clock Select accepts the high speed digital signal from the VCO and outputs an internal high speed serial clock. The VCO frequency is divided, based on the DIV1/DIV0 inputs, to the input signal’s frequency range. The Clock Select output, accessible through BCLK, is an internal serial clock. It is phase and frequency locked to the incoming signal. This internal serial clock is used by the Input Sampler to sample the data. It is also used by the Clock Generator to generate the recovered frame rate clock. By setting TCLKSEL high, the user may input an external high speed serial clock at TCLK. The Clock Select accepts this signal and directly outputs it as the internal serial clock. Clock Generator The Clock Generator accepts the serial clock generated from the Clock Select and generates the frame rate clock, based on the setting of M20SEL. If M20SEL is asserted, the incoming encoded data frame is expected to be 24 bits wide (20 data bits and 4 control bits). The master transition in the control section of encoded data stream is expected every 24 bits, and used to ensure proper frame syn- chronization of the output frame clock, STRBOUT. Input Sampler The serial input signal is converted into a serial bit stream, using the extracted internal serial clock from the Clock Select. This output is sent to the frame demux. Frame Demux The Frame Demux demulti- plexes the serial bit stream from the Input Sampler into a 20 or 24 bit wide parallel data word, based on the setting of M20SEL. The most significant 4 bits are sent to the C-Field Decoder, while the remaining 16 or 20 bits are sent to the D-Field Decoder. C-Field Decoder The C-Field Decoder accepts the control information from the Frame Demux and determines what kind of frame is being received and whether or not it has to be inverted. The control bits are sent to the State Machine for error checking. The decoded information is sent to the D-Field Decoder. CAV* is set low if the incoming frame is control data. DAV* is set low if the information is data. If neither DAV* nor CAV* is set low, then the incoming frame is expected to be a fill frame. If FLAGSEL is asserted, the FLAG bit is restored to its original form. Otherwise, FLAG is used to differentiate between the even and odd frames in Double Frame Mode. For more information about this, refer to Double Frame Mode. D-Field Decoder The D-Field Decoder accepts the data field of the incoming data frame from the Frame Demux. Based on information from the C-Field Decoder, which deter- mines what type of data is being received, the D-Field Decoder restores the parallel data back to its original form. State Machine The State Machine is used in full duplex mode to perform the functions of link startup, link maintenance, and error check- ing. By setting the SMRST0* and SMRST1* low, the user, too, can reset the state machine and initiate link startup. SMRST1* is usually connected to the transmitters LOCKED output. STAT1 and STAT0 denote the current state of link during startup. ACTIVE is an input normally driven by the STAT1 and STAT0 outputs. This ACTIVE input is retimed by STRBOUT and presented to the user as LINKRDY*. LINKRDY* is an active low output that indicates when the link is ready to transmit data. Refer to The State Machine Handshake Protocol section on page 600 for more details.

HDMP-1012 (Tx), HDMP-1014 (Rx) Tc = 0°C to +85°C, GND = Ground, VEE = -4.5 V to -5.5 V Symbol Parameter Units Min. Typ. Max. VIH,ECL ECL Input High Voltage Level, Guaranteed high signal mV -1150 for all inputs VIL,ECL ECL Input Low Voltage Level, Guaranteed low signal mV -1500 for all inputs VOH,ECL ECL Output High Voltage Level, Terminated with mV -1050 300 Ω to -2.0 V VOL,ECL ECL Output Low Voltage Level, Terminated with mV -1600 300 Ω to -2.0 V VIP,H50 H50 Input Peak-To-Peak Voltage mV 200 VDC,BLL BLL Output Bias Voltage Level mV -900 VOP,BLL BLL Output Peak-To-Peak Voltage, Terminated mV +600 with 50 Ω , ac coupled IEE,Tx Transmitter VEE Supply Current, with HCLKSEL off mA +403 Tc = 50°C IEE,Rx Receiver VEE Supply Current, Tc = 50°C mA +512 Note: 1. BLL outputs are measured with external 150 Ω pull-up resistors to ground. Refer to Figure 23 for additional information. HDMP-1012 (Tx), HDMP-1014 (Rx) Tc = 25°C Symbol Parameter Units Min. Typ. Max. tr,ECL ECL Rise Time, Terminated with 300 Ω to -2.0 V nsec 1 tf,ECL ECL Fall Time, Terminated with 300 Ω to -2.0 V nsec 4.5 tr, BLL BLL Rise Time, Terminated with 50 Ω , ac coupled psec 200 tf,BLL BLL Fall Time, Terminated with 50 Ω , ac coupled psec 170 VSWRi,H50 H50 Input VSWR 2:1 VSWRo,BLL BLL Output VSWR 2:1 Note: 1. BLL outputs are measured with external 150 Ω pull-up resistors to ground. Refer to Figure 23 for additional information. HDMP-1012 (Tx), HDMP-1014 (Rx) Typical Lock-Up Time Tc = 25°C DIV1 DIV0 HDMP-1012, msec HDMP-1014, msec LINK [1], msec 0 0 2.0 2.2 2.5 0 1 3.0 3.2 3.5 1 0 4.5 4.7 5.0 1 1 8.0 11.0 12.0 Note: 1. Measured in Local Loop-Back mode with the state machine engaged and 0 cable length.

HDMP-1012 (Tx), HDMP-1014 (Rx) Absolute Maximum Ratings Tc = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol Parameter Units Min. Max. VEE Supply Voltage V -7 +0.5 VIN,ECL ECL Input Voltage V -3 +0.5 VIN,BLL H50 Input Voltage V -2 +1 IO,ECL ECL Output Source Current mA +50 Tstg Storage Temperature °C -40 +130 TJ Junction Temperature °C -40 +130 Tmax Maximum Assembly Temperature (for 10 seconds maximum) °C +260 HDMP-1012 (Tx) Thermal Characteristics, TA = 25°C Symbol Parameter Units Typ. Θ jc Thermal Resistance Die to Case °C/Watt 12 PD Power Dissipation, VEE = -5 volts Watt 2.0 HDMP-1014 (Rx) Thermal Characteristics, TA = 25°C Symbol Parameter Units Typ. Θ jc Thermal Resistance Die to Case °C/Watt 12 PD Power Dissipation, VEE = -5 volts Watt 2.6 I/O Type Definitions I/O Type Definition I-ECL Input ECL. Similar to 100 K ECL, but with pull-down. Thus if the input is left unconnected, the buffer generates a default value of “0”. The input can also be directly connected to ground to generate a “1”. O-ECL Output ECL. Similar to 100 K ECL but should be terminated with RTT ≥ 300 Ω , and do not exceed 10cm connection distance. O-BLL 50 matched output driver. Will drive AC coupled 50 Ω loads, with 150 Ω pull-up resistors for broad band matching. All unused outputs should have 150 Ω pull-up resistors, and AC coupled to a 50 Ω resistor to ground. I-H50 Input with internal 50 Ω terminations. Input is diode level shifted so that it can swing around ground. Can be driven with single-end configuration. Commonly used with input single-end AC coupling from an O-BLL driver or another 50 Ω source, or differential direct coupling from an O-BLL driver. C Filter capacitor node. S Power supply or ground.

CAP0A 2 C Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A CAP0B 1 should be shorted to CAP1B. A loop filter capacitor of 0.1 µF must be CAP1A 3 connected across the CAP0 and CAP1 inputs to increase the loop time CAP1B 4 constant. CAV* 69 I-ECL Control Word Available Input: This active-low input tells the chip that the user is requesting a control word be transmitted. This pin should only be asserted after the user has determined the RFD line is active for a given frame cycle. When this pin is asserted, the information on the Data inputs is sent as a control frame. If CAV and DAV are asserted simultaneously, CAV takes precedence. D0 59 I-ECL Data Inputs: 20 Bit data is encoded and transmitted when M20SEL D1 58 is active; otherwise the 16 least significant bits are encoded and D2 57 transmitted. The encoded bits are transmitted LSB first. (e.g.: D0 is D3 56 sent first, through to either D15 or D19, followed by the 4 coding bits D4 55 C0-C3.) D5 54 D6 53 D7 51 D8 50 D9 49 D10 48 D11 47 D12 46 D13 45 D14 40 D15 39 D16 38 D17 37 D18 36 D19 35 DAV* 70 I-ECL Data Available Input: This active-low input tells the chip that the user has valid data to be transmitted. This pin should be asserted only after the user has determined that the RFD line is active for a given frame cycle. When this pin is asserted, the information on the Data and Flag inputs is encoded and sent as a Data frame. DIV0 19 I-ECL VCO Divider Select: These two pins program the VCO divider chain DIV1 20 to operate at full speed, half speed, quarter speed or one-eighth speed. DOUT 17 O-BLL Normal Serial Data Output: Output used when LOOPEN is not DOUT* 18 active. This output is a special buffer line logic driver, which is a 50 Ω back-terminated ECL compatible output. ECLGND 33 S ECL Ground: Normally 0 volts. This ground is used for the ECL pad 66 drivers. For best performance, coupling of the noisy ECLGND to the 77 clean GND and HGND grounds be minimized. ED 67 I-ECL Enable Data: This signal comes from the Rx chip state machine and is used to control the RFD output of the Tx chip. The state machine only allows data to be enabled when both sides of the link have established stable lock.

Tx I/O Definition (cont’d.) Name Pin Type Signal EHCLKSEL 78 I-ECL EHCLK Enable: When active, this input causes the STRBIN inputs to be used for the transmit serial clock, rather than the internal VCO clock. This is useful for generating extremely low jitter test signals, or for operating the link at speeds that are not within the VCO range. When the STRBIN is active, it is necessary for the data source to take its clock from the link rather than the usual operation where the Link phase-locks onto the data source clock. FF 68 I-ECL Fill Frame Select: When neither CAV or DAV is asserted, or when ED is false, fill frames are automatically transmitted to allow the Rx chip to maintain lock. The type of fill frame sent is determined by the state of this pin. FF0s are sent if low, and either FF1a or FF1b is sent if FF is high. The choice of FF1a and FF1b is determined by the state of the cumulative line DC balance. FLAG 60 I-ECL Extra Flag Bit: When FLAGSEL is active, this input is sent as an extra data bit in addition to the normal Data inputs. When FLAGSEL is not asserted, this input is ignored and the transmitted Flag bit is internally alternated to allow the Rx chip to perform enhanced frame error detection. FLAGSEL 71 I-ECL Flag Bit Mode Select: When this input is high, the extra FLAG bit input is sent as an extra transparent data bit. Otherwise, the FLAG input is ignored and the transmitted flag bit is internally alternated by the transmitter. The Rx chip can provide enhanced frame error detection by checking for strict alternation of the flag bit during data frames. The FLAGSEL input on the Rx chip should be set to the same value as the Tx FLAGSEL input. GND 23 S Ground: Normally 0 volts. This ground is used for everything other 24 than the noisy ECL outputs. HCLK 11 O-BLL High Speed Clock Monitor: Used to monitor actual clock signal HCLK* 12 used to transmit the serial data. This signal will either be the divided VCO output, or the divided EHCLK external clock input, depending on the value of the EHCLKSEL input. HCLKON 10 I-ECL HCLK Power-down Control: When this pin is de-asserted, the HCLK, HCLK* outputs are powered down to reduce power dissipation. HGND 7 S High Speed Ground: Normally 0 volts. This ground is used to 13 provide a clean reference for STRBIN and STRBIN* inputs. For optimum impedance matching, it is suggested that the physical distance between this pin and the ground plane be minimized.

Tx I/O Definition (cont’d.) Name Pin Type Signal INV 25 O-ECL Invert Signal: A high value of INV implies that the current frame is being sent inverted to maintain long-term DC balance. With a buffer, or pulled down with a 1K resistor to V EE and ac coupled, this signal is useful as an aid to analyzing the serial output stream with an oscilloscope. LOCKED 75 O-ECL Loop In-lock Indication: This signal indicates the lock status of the Tx PLL. A high value indicates lock. This signal is normally connected to the SMTRST1 reset input of the Rx state machine to force the link into the start-up state until the Tx PLL has locked. This signal may give multiple false-lock indications during the acquisition process, so should be debounced if it is used for any other purpose than to drive the Rx chip. LOOPEN 16 I-ECL Loop Back Control: Input which controls whether the DOUT, DOUT*, or the LOUT, LOUT* outputs are currently enabled. If active, LOUT, LOUT* are enabled. The unused output is powered down to reduce dissipation. LOUT 14 O-BLL Loop Back Serial Data Output: Output used when LOOPEN is LOUT* 15 active. Typically this output will be used to drive the LIN, LIN* inputs of the Rx chip. M20SEL 73 I-ECL 16 or 20 Bit Word Select: When this signal is high, the link operates in 20 Bit data transmission mode. Otherwise, the link operates in 16 Bit mode. MDFSEL 74 I-ECL Select Double Frame Mode: When this signal is high, the PLL expects a 1/2 speed parallel clock at STRBIN. The chip then internally multiplies this clock and produces a full-rate parallel clock at STRBOUT. Note that the phase relationship of STRBIN to STRBOUT and the sampling point change with asserting MDFSEL, as shown in the Tx timing diagram. This feature is provided so that either a 40 bit or 32 bit word can be easily transmitted as two 20, or two 16 bit words. When MDFSEL is low, the PLL expects a full-rate parallel clock at STRBIN. RFD 65 O-ECL Ready for Data: Output to tell the user the Link is ready to transmit data. This pin is a retimed version of the ED input, which is driven by the Rx chip state machine controller. RST* 34 I-ECL Chip Reset: This active-low pin initializes the internal chip registers. It should be asserted during power up for a minimum of 5 parallel- rate clock cycles to ensure a complete reset. STRBIN 8 I-H50 Data Clock Input: When EHCLKSEL is low, this input is phase STRBIN* 9 locked and multiplied to generate the high speed serial clock. The chip expects a clock frequency which is equal to the input frame rate if MDFSEL (double frame mode) is low, and 1/2 the frame rate if MDFSEL is high. When EHCLKSEL is high, the PLL is bypassed, and STRBIN directly becomes the high speed serial clock. Refer to the Tx Timing diagram for the phase relationship between STRBIN, data and STRBOUT.

Tx I/O Definition (cont’d.) Name Pin Type Signal STRBOUT 76 O-ECL Frame-rate Data Clock Output: This output is always a frame rate clock derived from STRBIN. With a buffer or pulled down with a 1K resistor to V EE and ac- coupled, this output is ideal for triggering an oscilloscope for examining the serial output eye pattern DOUT or LOUT. VEE 21 S Power: Normally -5 V ± 10%.

ACTIVE 25 I-ECL Chip Enable: This input is normally driven by the Rx state machine output. The ACTIVE signal is internally retimed by STRBOUT and presented to the user as the LINKRDY signal. This is how the Rx state machine signals the user that the start-up sequence is complete. BCLK 9 O-BLL VCO Monitor Output: These pins provide access to the internal BCLK* 8 VCO clock. CAP0A 2 C Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A CAP0B 1 should be shorted to CAP1B. A loop filter capacitor of 0.1 µf must be CAP1A 3 connected across the CAP0 and CAP1 inputs to increase the loop time CAP1B 4 constant. CAV* 38 O-ECL Control Frame Available Output: This active-low output indicates that the Rx chip data outputs are receiving Control Frames. False CAV indications may be generated during link startup. D0 71 O-ECL Data Outputs: 20 Bit data is received and decoded when M20SEL is D1 70 active; otherwise 16 bit data is decoded and the D16-D19 bits D2 69 are undefined. D3 68 D4 67 D5 66 D6 65 D7 60 D8 59 D9 58 D10 57 D11 56 D12 55 D13 54 D14 51 D15 50 D16 49 D17 48 D18 47 D19 46 DAV* 37 O-ECL Data Available Output: This active-low output indicates that the Rx chip data outputs, D0..D19, have received data frames. Data should be latched on the rising edge of STRBOUT. Note that during link startup, false data indications may be given. The DAV* and LINKRDY outputs can be used together to avoid confusion during link startup. DIN 15 I-H50 Normal Serial Data Input: This is the input used when LOOPEN DIN* 14 is not active. When LOOPEN is high, the loop back data inputs LIN, LIN* are used instead. An optional cable equalizer may be enabled for the DIN, DIN* inputs by asserting EQEN. DIV0 6 I-ECL VCO Divider Select: These two pins program the VCO divider chain DIV1 7 to operate at full speed, half speed, quarter speed or one-eighth speed.

Rx I/O Definition (cont’d.) Name Pin Type Signal ECLGND 32 S ECL Ground: Normally 0 volts. This ground is used for the ECL pad 52 drivers. For best performance it is suggested that coupling of the noisy 53 ECLGND to the clean GND and HGND grounds be minimized. EQEN 19 I-ECL Enable Input for Cable Equalization: When asserted, this signal activates the cable equalization amplifier on the DIN, DIN* serial data inputs. ERROR 40 O-ECL Received Data Error: Asserted when a frame is received that does not correspond to either a valid Data, Control, or Fill frame encoding. When FLAGSEL is not active, the Rx chip also tests for strict alternation of flag bits during data frames. A flag bit alternation error will also cause an ERROR indication. FCLK 75 O-ECL Frame Clock Monitor: Leave unterminated in normal use. FDIS 20 I-ECL Frequency Detector Disable Input: When active, this input disables the Rx PLL Frequency detector and enables a phase detector. The Frequency detector is used during the start-up sequence to acquire wide-band lock on Fill Frames, but must be disabled prior to sending data patterns. This input is normally controlled by the Rx state machine. FF 39 O-ECL Fill Frame Status: During a given STRBOUT clock cycle, if neither DAV, CAV, or ERROR are active, then the currently received frame is a Fill frame. The type of fill frame received is indicated by the FF pin. If FF is low, then FF0 has been received. If FF is high, then either FF1a or FF1b has been received. FLAG 45 O-ECL Flag Bit: If both Tx and Rx have FLAGSEL asserted, this output indicates the value of the transmitted flag bit, then this received bit can be treated just like an extra data bit. If both Tx and Rx have FLAGSEL set to low, FLAG is used to differentiate the even frame from the odd frame in the line code. FLAGSEL 34 I-ECL Flag Bit Mode Select: When this input is high, the extra FLAG bit output is effectively an extra transparent data bit. Otherwise, the FLAG bit is checked for alternation during data frames. Any break in strict alternation results in an ERROR indication to the user. GND 5 S Ground: Normally 0 volts. This ground is used for all the core logic 23 other than the output drivers. HGND 13 S High Speed Ground: Normally 0 volts. This ground is used to provide clean references for the high speed DIN, DIN*, LIN, LIN*, TCLK, TCLK* inputs.

Rx I/O Definition (cont’d.) Name Pin Type Signal LIN LIN* 18 I-H50 Loop Back Serial Data Input: Use this input when LOOPEN is 17 active. Unlike the DIN, DIN* inputs, this input does not have a cable equalizer. In normal usage, this input will be connected to the Tx chip LOUT, LOUT* outputs. This allows the user to check the near-end functionality of the Tx and Rx pair independent of the transmission medium LOOPEN 16 I-ECL Loop Back Control: When asserted, this signal causes the loop back data inputs LIN, LIN* to be used instead of the normal data inputs DIN, DIN*. LINKRDY* 36 O-ECL Link Ready Indicator: This active-low output is a retimed version of the ACTIVE input. ACTIVE is normally driven by the Rx state machine output. LINKRDY* then indicates that the startup sequence is complete and that the data and control indications are valid. M20SEL 30 I-ECL 16 or 20 Bit Word Select: When this signal is high, the link operates in 20 Bit data reception mode. Otherwise, the link operates in 16 Bit mode and data outputs D16-D19 are undefined. NCLK 76 O-ECL Nibble Clock Monitor: Leave unterminated in normal use. TEMP 77 T Temperature Sense Diode: Used during wafer and package test only. It should be left open. PH1 79 O-ECL Phase Detector Test Output: The output from the phase/frequency detector in the Rx PLL. When PH1 is high, the VCO should increase frequency. When low, the VCO should decrease frequency. SMRST0* 28 I-ECL State Machine Reset Inputs: Each of these active-low input pins SMRST1* 29 reset the Rx state machine to the initial start-up state. This initiates a complete PLL restart and handshake at both ends of the duplex link. Normally, SMCRST0* is connected to a power-up reset circuit or a host system reset signal. The SMCRST1* input is normally connected to the Tx LOCKED output. The LOCKED signal holds the state-machine in the start-up state until the Tx PLL is locked. STAT0 27 O-ECL State Machine Status Outputs: These outputs indicate the current STAT1 26 state-machine state. They are used to directly control the Tx ED, Tx FF, Rx FDIS, and Rx ACTIVE lines. STRBOUT 35 O-ECL Recovered Frame-rate Data Clock Output: This output is the PLL recovered frame rate clock. D0-D19, FLAG, DAV, CAV, FF, LINKRDY, and ERROR should all be latched on the rising edge of STRBOUT. TCLK 12 I-H50 External VCO Replacement Test Clock: When TCLKSEL in TCLK* 11 enabled, this input is used in place of the normal VCO signal, effectively disabling the PLL and allowing the user to provide an external retiming clock for testing. TCLKSEL 10 I-ECL Enable Test Clock Input: When this input is active, the TCLK, TCLK* inputs are used in place of the normal VCO signal. This feature is useful both for synchronous systems and for chip testing.

VEE 21 S Power: Normally -5 V +10% Rx I/O Definition (cont’d.) Name Pin Type Signal

Figure 10. Mechanical Dimensions of HDMP-1012 and HDMP-1014.

7 DEG

ALL DIMENSIONS ARE IN MILLIMETERS (INCHES).

Figure 11. The CIMT line uses there is no input from the user. receivers clock recovery circuit. synchronization at the receiver. asserting the Rx ERROR output. (non-data bit fields) of the frame. Figure 11. HDMP-1012/1014 (Tx/Rx Pair) Line Code.

4 BITS

HDMP-1012 (Tx), HDMP-1014 (Rx) Data Frame Structure M20SEL Asserted (20 bit data mode) Data Status Flag bit D-Field C-Field True 0 D0 - D19 1101 Inverted 0 D0 - D19 0010 True 1 D0 - D19 1011 Inverted 1 D0 - D19 0100 HDMP-1012 (Tx), HDMP-1014 (Rx) Operating Modes M20SEL FLAGSEL Description 0 0 16 bit data plus error checking 0 1 16 bit data plus FLAG 1 0 20 bit data plus error checking 1 1 20 bit data plus FLAG HDMP-1012 (Tx), HDMP-1014 (Rx) Data Frame Structure M20SEL Not Asserted (16 bit data mode) Data Status Flag bit D-Field C-Field True 0 D0 - D15 1101 Inverted 0 D0 - D15 0010 True 1 D0 - D15 1011 Inverted 1 D0 - D15 0100 Control Frame Codes There are 218 control words provided in 20 bit mode. If the user desires to send a control word, his lower 9 bits (D0-D8) are sent as bits D0-D8 of the D- Field. The user’s next 9 bits (D9- D17) are sent as bits D11-D19 of the D-Field. The control frame is either inverted or not inverted as needed to maintain balance, with the coding bits 0011 used to indicate true control, and the bits 1100 used to indicate complement control. The bits d9 and d10 are always forced to 0 1 for true control frames and 1 0 for complement control frames. These middle bits are used to distinguish control frames from fill frames, which always have the middle bits set to either 00, 11, or 10. Similarly, there are 2 control words provided in 16 bit mode.

HDMP-1012 (Tx), HDMP-1014 (Rx) Control Frame Structure M20SEL Not Asserted (16 bit mode) D-Field C-Field D0 - D6 D7 D8 D9 - D15 C0 C1 C2 C3 D0 - D6 01 D7 - D13 001 1 D0 - D6 10 D7 - D13 110 0 HDMP-1012 (Tx), HDMP-1014 (Rx) Control Frame Structure M20SEL Asserted (20 bit mode) D-Field C-Field D0 - D8 D9 D10 D11-D19 C0 C1 C2 C3 D0 - D80 1 D9-D17 001 1 D0 - D81 0 D9-D17 110 0 occurring between C1 and C2. Logical FF1 toggles between two different physical codes, the first of which advances the falling edge of FF0 by one bit, the second of which retards the falling edge of FF0 by one bit. Two logical fill frame types are required for link start up in duplex mode. Fill Frame Codes Two logical fill frames are provided: FF0 and FF1. FF0 is physically a 50% duty cycle wave form with its sole rising edge HDMP-1012 (Tx), HDMP-1014 (Rx) Fill Frame Structure M20SEL Not Asserted (16 bit mode) Fill Frame D-Field C-Field 0 1111111 10 0000000 0011 1a 1111111 11 0000000 0011 1b 1111111 00 0000000 0011 HDMP-1012 (Tx), HDMP-1014 (Rx) Fill Frame Structure M20SEL Asserted (20 bit mode) Fill Frame D-Field C-Field 0 111111111 10 000000000 0011 1a 111111111 11 000000000 0011 1b 111111111 00 000000000 0011

HDMP-1014 (Rx) Detectable Error States M20SEL Not Asserted (16 bit mode) D-Field C-Field xxxxxxx xx xxxxxxx x00x xxxxxxx xx xxxxxxx x11x xxxxxxx 0x xxxxxxx 1100 xxxxxxx 11 xxxxxxx 1100 xxxxxxx xx xxxxxxx 1010 xxxxxxx xx xxxxxxx 0101 HDMP-1014 (Rx) Detectable Error States M20SEL Asserted (20 bit mode) D-Field C-Field xxxxxxxxx xx xxxxxxxxx x00x xxxxxxxxx xx xxxxxxxxx x11x xxxxxxxxx 0x xxxxxxxxx 1100 xxxxxxxxx 11 xxxxxxxxx 1100 xxxxxxxxx xx xxxxxxxxx 1010 xxxxxxxxx xx xxxxxxxxx 0101 Tx Operation Principles The HDMP-1012 (Tx) is imple- mented in a high performance silicon bipolar process. The Tx performs the following functions for link operation:

• Phase lock to frame rate clock
• Clock multiplication
• Frame encoding
• Multiplexing In normal operation, the Tx phase locks to a user supplied frame rate clock and multiplies the frequency to produce the high speed serial clock. When locked, the Tx indicates that it is locked by asserting the LOCKED output. When the ED input is asserted, the Tx asserts the RFD signal indicating that it is now ready to transmit data or control frames. The Tx can accept either 16 or 17 bit wide parallel data and produce a 20 bit frame. It also can accept 20 or 21 bit data and produce a 24 bit frame. Similarly, either 14 bit or 18 bit control words can be transmitted in a 20 bit or 24 bit frame respectively. Tx Encoding A simplified block diagram of the transmitter is shown in Figure 4. The PLL/Clock Generator locks onto the incoming frame rate (or one-half frame rate) clock and multiplies it up to the serial clock rate. It also generates all the internal clock signals required by the Tx chip. The data inputs, D0-D19, as well as the control signals; ED, FF, DAV* , CAV*, and FLAG are latched in on the rising edge of an internally generated frame rate clock. The data field is then encoded depending on the state of the control signals. At the same time, the coding field is generated. At this point, the entire frame has been constructed in parallel form and its sign is determined. This frame sign is compared with the accumulated sign of previously transmitted bits to decide whether to invert the frame. If the sign of the current frame is the same as the sign of the previously transmitted bits, then the frame is inverted. If the signs are opposite, the frame is not inverted. No inversion is

circuitry, and a lock indicator. center frequency of the VCO. differential clock to STRBIN. Figure 12. HDMP-1012 (Tx) Phase-Locked Loop.

the Rx is ready to receive data.

• ERROR=iERR.
• FLAG=iFLAG.
• If a Fill Frame is detected, then FLAG=0.
• If a Control Frame is detected, FLAG should be ignored. If FLAGSEL=0, the serial input is assumed to consist of alternating

Figure 14. HDMP-1014 (Rx) Phase-Locked Loop.

1 FF0

Figure 15. HDMP-1014 (Rx) State Machine State Diagram. controlled are FDIS and ACTIVE.

1. The local Tx transmits FF1 to

• Tx FF is driven by STAT1
• Tx ED is driven by STAT0
• Rx FDIS is driven by STAT1
• Rx ACTIVE is driven by STAT1
• TX RST and RX SMCRST0 are driven by a power-on, or user, reset circuit.

receive FF1, causing STAT0 to go high, which asserts the enable data (ED) pin on the Tx. The ED signal is retimed to signify to the host that the Tx is ready to send data (RFD). Other configurations for duplex mode are also possible with external user-defined state machines. Simplex operation using G-LINK is also possible. The following sections discuss three different types of simplex configurations. Simplex Method I. Simplex with Low-Speed Return Path Low-speed lines are used in the simplex method of Figure 17a. The remote Rx controls the states of both the Rx and the local Tx using these low speed lines. This is ideal for cases where these non- critical lines are available. Again, a power on reset is available to the user. This connection between the Tx and Rx is identical to one side of the duplex configuration. When the Tx is locked, the Rx is enabled via the LOCKED line. The Rx’s STAT0 and STAT1 outputs are low, causing the local Tx to send FF0. When the Rx is frame locked, STAT1 is raised, which disables its frequency detector, sets itself to active mode, and tells Tx to send FF1. Upon receiving FF1 from the Tx, the Rx’s STAT0 line is raised, which enables the Tx (ED) for data transmission. If desired, the Rx reset pin (SMCRST1) can be tied high, and Figure 17: Simplex Configurations. Tx DATA INTERFACE DOUT RST* LOCKED ED FF OPTIONS Rx DATA INTERFACE DIN ACTIVE FDIS STAT1 STAT0 SMCRST1* SMCRST0* LIN RxTx POWER-ON RESET LOUT POWER-ON RESET OPTIONS Tx DATA INTERFACE DOUT RST* LOCKED ED FF OPTIONS Rx DATA INTERFACE DIN ACTIVE FDIS STAT1 STAT0 SMCRST1* SMCRST0* LIN RxTx POWER-ON RESET LOUT POWER-ON RESET OPTIONS Tx DATA INTERFACE DOUT RST* LOCKED ED = 1 FF = 1 OPTIONS Rx DATA INTERFACE LIN ACTIVE FDIS STAT1 STAT0 SMCRST1* SMCRST0* DIN RxTx POWER-ON RESET LOUT POWER-ON RESET OPTIONS LOW SPEED LINES A) SIMPLEX METHOD I WITH LOW-SPEED RETURN PATH B) SIMPLEX METHOD II WITH PERIODIC SYNC PULSE PERIODIC SYNC PULSES LOOPENOSC C) SIMPLEX METHOD III WITH EXTERNAL REFERENCE OSCILLATOR FREQ = FRAME RATE

eliminated. Simplex Method II. Simplex with Periodic Sync Pulse. Another configuration of simplex operation is shown in Figure 17b. For frame lock, the Rx normally relies on either FF0 or FF1. In this example, the fill frame FF of the Tx is forced high with a connection to ground, and the enable data pin ED is pulsed periodically to force the Tx to send FF1. During this pulse, however, the link is not available for data transmission. The pulse width applied to ED should be long enough for the Rx to acquire lock. The typical Rx lock-up time is around 2.5 mS for the high frequency band, thus a 5 mS pulse is adequate in this case. For other bands, longer pulses are required. Typical lock-up times for all four data rate ranges can be found in the table Typical Lock-Up Time at the front of the data sheet. Note that these lock- up times assume a 0.1 µF inte- grating capacitor is being used on the PLL. Refer to the section on Supply Bypassing and Integrator Capacitor for more details. After G-LINK is locked, ED needs to go low only as often as needed to ensure that the link is locked. Lock can be lost if the serial line is broken, or if two consecutive frame errors are detected by the receiver’s state machine. The length of time between ED pulses will determine how long the user needs to wait before lock is re-established. Simplex Method III: Simplex with Reference Oscillator A third configuration for simplex operation is shown in Figure 17c. The high-speed serial line is brought into the receiver through the LIN input, and a reference clock at the frame rate is connected to the DIN input. The Rx uses the reference clock for frequency acquisition. Upon frequency lock, STAT1 goes high, and sets the detector from frequency to phase detection mode through FDIS. At the same time, it switches the input from the reference clock to the data stream. Since the relative phase of the reference clock to that of the data stream is random, the phase detector will lock onto a random transition in the data stream. Errors are detected if the phase lock is not locked to the master transition. If two consecutive errors occur, the STAT1 line is forced low, and the state machine switches the receiver back to the reference oscillator. This process is repeated until the master transition is found, and an error- free condition exists. Because of the nature of this hunting process, it is possible for a static code to emulate the master transition. Therefore, it is recommended that the flag bit be reserved for error detection. With FLAGSEL disabled, the flag bit is toggled internally by the Tx, and the Rx uses this strict alternation to detect errors, thus making the link much more reliable. The lock up time in this simplex configuration is dependent on the frequency match between the two local oscillators. This method relies on a slight difference between the two frequencies in order to guarantee a lock within a reasonable time. In theory, a perfect match could result in no lock due by causing the receiver to consistantly try and lock at the same non-master transition point in the incoming frames. Fortunately there is no such thing as a perfect match in the real world. It is recommended to select crystal oscillators between 0.1% to 0.001% matching. The above method uses the LIN line as the high-speed serial data line. This works well and is simple to implement, but it doesn’t take advantage of the coaxial equalizer on the DIN line. Adding an external ECL inverter to the Loop Back Control (LOOPEN) pin allows the reference oscillator to be injected into LIN and the serial data line (DIN) to be used as the high-speed data line. If the coaxial equalizer is needed in the DIN path, DIN and LIN inputs can be interchanged with an external ECL inverter before LOOPEN. Data Interface for Single/ Double Frame Mode. G-LINK is designed to work with single frame or double frame modes, in either 16 or 20 bits wide per frame. An extra flag bit is available with FLAGSEL and it is used to signify the first or second frames in double- frame mode. The 16/20 frame width option is selected with the M20SEL pin. In this discussion, a 20 bit width is assumed. In both single and double frame modes, the data frame (D0-D19), flag bit (FLAG), and the data/control word available pins (DAV*, CAV*), must appear before the setup time t s, and remain valid for the hold time th. Refer to HDMP-1012 Tx

Timing. Since the PLL of the Tx is designed with a very high-gain frequency/phase detector, the relative alignment of the internal clock and STRBIN is very tight, and is insensitive to temperature and other variations. The observed external changes are due mainly to variations in the buffers, which are relatively small. For convenience, the setup and hold times are referenced back to the user-supplied clock, STRBIN. The actual sampling clock is slightly advanced relative to STRBIN due to internal delays, and the hold time is typically negative. The user has to make sure that M20SEL, FLAGSEL, DIV0, and DIV1 have the same setting on both Tx and Rx. The word width of the parallel data from the host can be either 16 bits if M20SEL = 0, or 20 bits if M20SEL = 1. Also, the FLAG bit can be used as an additional bit by setting FLAGSEL=1. In the last case, the parallel data word width is either 17 bits or 21 bits. The local loopback test can be enabled by setting LOOPEN high. Single Frame Mode (MDFSEL=0) A block diagram showing the single-frame mode data interface for both the Tx and Rx, and their associated timing diagrams are shown in Figure xxx. In the Tx side, the expected frequency of the input clock STRBIN is the bit rate of the data frame. In this case, the setup and hold times are referenced to the rising edge of STRBIN. The internal clock is buffered to form STRBOUT which appears with a delay of T strb after STRBIN. In the Rx side, the data frame, flag bit, CAV*, DAV*, LINKRDY, and ERROR appear with a delay of t d1 after the falling edge of STRBOUT. The state machine outputs STAT0 and STAT1 appear with a delay of td2. Double Frame Mode (MDFSEL=1) A block diagram showing the double-frame mode data interface for both the Tx and Rx, and their associated timing diagrams are shown in Figure 17. This configuration works best if the duty cycle of STRBIN is 50%. In the Tx side, the expected frequency is 1/2 of the combined frame period. This combined frame, D0-D19, is formed by interlacing the two frames C0- C19 and C20-C39 with an external 2:1 multiplexer. The Tx locks onto STRBIN, which has the same frequency as the bit rate of C0-C39, and with an internal frequency doubler, generates the sampling clock to latch in D0- D19, DAV*, CAV*, and FLAG. STRBIN is also used to toggle the 2:1 multiplexer, and is fed into Figure 18: Tx and Rx Data Interface for Single Frame Mode (MDFSEL=0). Tx CONFIGURATIONS CAV*, DAV* PLL D00 - D19 FLAG STRBOUT STRBIN Rx CONFIGURATIONS CAV*, DAV*, FF LINKRDY, ERROR D00 - D19 FLAG STRBOUT STAT0, STAT1 ts th tstrb D00 - D19 CAV*, DAV* FLAG STRBOUT STRBIN td2 D00 - D19 FLAG CAV*, DAV*, FF LINKRDY, ERROR STAT0, STAT1 STRBOUT td1 ts = SETUP TIME th = HOLD TIME tstrb = STRBIN TO STRBOUT DELAY td1 = STRBOUT TO SYNCHRONOUS OUTPUTS DELAY td2 = STRBOUT TO STATE MACHINE OUTPUTS DELAY

inductance in the ECLGND leads. initial frequency lock-in process. Figure 20. Power Supply Bypass.

10 OHMS

and a 0.1 uF coupling capacitor. semiconductor manufacturers. keep a single clean ground plane. with the Vcc and ground planes. Figure 22. I-H50 and O-BLL Simplified Circuit Schematic.

Likewise, the Vtt plane must also be bypassed equally well. In the positive 5 V supply configuration, the logic outputs are in the PECL (positive ECL) states. Commercial translation chips are available which will translate PECL between TTL and CMOS. Mode Options The GLlink has several option pins which set the modes of operation. Common to both the Tx and the Rx are M20SEL, DIV0, and DIV1, FLAGSEL, and LOOPEN. Local to the Tx are MDFSEL, EHCLKSEL, and HCLKON. While local to the Rx are EQEN and TCLKSEL. These pins are all I-ECL, and can be set as described below. M20SEL = 0/1 sets the width of the frame to 16/20 bits. DIV1 / DIV0 = set the frequency bands of operation. Refer to the Setting the Operating Data Rate Range section for frequency band selection. It is recommended that applications near the ends of the bands have jumpers for DIV0 and DIV1 inputs, so that the board can accommodate possible lot-to- lot band variations over the life of the board design. FLAGSEL = 0/1 selects either the flag bit is reserved for error detection by the link, or as an extra bit available for the user. Figure 23: Methods of Interfacing O-BLL and I-H50. OBLL 150 Ω IH50 50 Ω 50 Ω 150 Ω ZO = 50 Ω OBLL 150 Ω IH50 150 Ω ZO = 50 Ω ZO = 50 Ω A) SINGLE-ENDED DRIVE O-BLL TO I-H50 INTERFACE B) DIFFERENTIAL DRIVE O-BLL TO I-H50 OBLL 150 Ω ECL 50 Ω 82 Ω 150 Ω ZO = 50 Ω VTT (-2 V) 130 Ω OBLL 150 Ω ECL 150 Ω ZO = 50 Ω ZO = 50 Ω 50 Ω 50 Ω -1.3 V -1.3 V C) DIFFERENTIAL DRIVE O-BLL TO ECL D) SINGLE-ENDED DRIVE O-BLL TO ECL

LOOPEN = 0/1 selects either the normal data or the loop channels the I/O. MDFSEL = 0/1 selects the Tx single or double frame modes. ECHKSEL = 0/1 selects either to lock onto a frame-rate clock at STRBIN or to use this clock as the high speed clock and bypass the PLL in the Tx. This input is used mainly for testing, and should be normally set low. HCLKON = 0/1 turns on the high speed serial clock outputs of the Tx. This option was added to conserve power. EQEN = 0/1 disables or enables the data equalizer in the Rx for cable applications. TCLKSEL = 0/1 selects the clock source from either be derived from the serial data stream or from the TCLK inputs for the Rx. This input is for testing only, and should normally be set low.