HDMP-0421 HP | Alldatasheet

Document overview

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Technical content

Features

  • Supports ANSI X3T11

1.0625 Gbps FC-AL Loop

  • Supports 802.3z 1.25 Gbps Gigabit Ethernet (GE) Rates
  • Single PBC, CDR, Dual Signal Detect (SD) in a Single Package
  • Bidirectional, Symmetric Bypass Capability
  • CDR in Bypass Path and Loop Path
  • CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending)
  • Envelope Detect on Cable Input (SD) for Both Directions
  • Equalizers On All Inputs
  • High Speed PECL I/Os Referenced to VCC
  • Buffered Line Logic (BLL) Outputs without External Bias Resistors
  • 0.4 W Typical Power at VCC = 3.3 V
  • 5 V Tolerant LVTTL I/O
  • 24 Pin SSOP Package

Applications

  • RAID, JBOD Cabinets
  • 1=>1 Gigabit Serial Buffer Pair (with and w/o CDR)
  • Multi-Initiator Loops Technical Data

Description

The HDMP-0421 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR), and dual Signal Detect (SD) capability. This configuration will control jitter accumulation while repeating incoming signals. Port Bypass Circuits are used to provide loops that are continuously on in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. Hard disks may be pulled out or swapped while other disks in the array are available to the system. This device may also be used in multi-initiator loop configurations. A Port Bypass Circuit is a 2:1 Multiplexer array with two modes of operation: DISK IN LOOP and DISK BYPASSED. In DISK IN LOOP mode, the loop goes into and out of the disk drive. Data go from the HDMP-0421’s TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC (for example, an HDMP-1536A) Rx± differential input pins. Data from the Disk Drive Transceiver IC Tx± differential output pins go to the HDMP-0421’s FM_NODE[n]± differential input pins. Figures 4 and 5 show connection diagrams for disk drive array applications. In DISK BYPASSED mode, the disk drive is either absent or non-functional and the loop bypasses the hard disk. DISK IN LOOP mode is enabled with a HIGH on the BYPASS[n]– pin and DISK BYPASSED mode is enabled with a LOW on the same pin. Multiple HDMP-0421s may be cascaded or connected to other members of the HDMP-04xx family through the FM_LOOP and TO_LOOP pins to create loops for arrays of disk drives. See Table 2 to identify which of the two cells (0:1) will provide FM_LOOP, TO_LOOP pins (cell connected to cable). ALL TO_NODE outputs of the HDMP-0421 are of equal strength. Combinations of HDMP-04xx may be utilized to accommodate any number of hard disks. The HDMP-0421 may also be used as a pair of 1=>1 buffers, one with a CDR and another without. For example, HDMP-0421 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (CDR- less path).

Figure 3: HDMP-0421 Package Layout and Marking, Top View. Table 2. Pin Connection Diagram to Achieve Desired

(TO_LOOP+). In other configurations, this pin is wired to the hard disk. (TO_LOOP–). In other configurations, this pin is wired to the hard disk. Input from Transceiver IC to Cell 1. Input from Transceiver IC to Cell 1. Output to Transceiver IC from Cell 1. Output to Transceiver IC from Cell 1. (FM_LOOP+). In other configurations, this pin is wired to the hard disk. (FM_LOOP–). In other configurations, this pin is wired to the hard disk. ground connect through a 1 KΩ resistor. ground connect through a 1 KΩ resistor. Reference Clock Input for Clock and Data Recovery (CDR) circuit. PLL cap pin. Connected to pin 13 with a 0.1 microFarad capacitor. PLL cap pin. Connected to pin 12 with a 0.1 microFarad capacitor. Cell 1 High Speed Output Pins Power Supply. Cell 0 High Speed Output Pins Power Supply. Table 3. Pinout

Clock and Data Recovery Circuit Reference Clock Requirements TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V Symbol Parameter Unit Min. Typ. Max. Min. Typ. Max. f Nominal Frequency MHz 106.25 125.00 Ftol Frequency Tolerance ppm –100 +100 –100 +100 Symm Symmetry (Duty Cycle) Absolute Maximum Ratings TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol Parameter Units Min. Max. VCC Supply Voltage V –0.7 4.0 VIN,LVTTL LVTTL Input Voltage V –0.7 4.0 VIN,HS_IN HS_IN Input Voltage V 2.0 VCC IO,LVTTL LVTTL Output Source Current mA ± 13 Tstg Storage Temperature –65 +150 Tj Junction Temperature +125 TA= 0°C to +70°C, VCC = 3.15 V to 3.45 V Symbol Parameter Unit Min. Typ. Max. VIH,LVTTL LVTTL Input High Voltage Range V 4.0 VIL,LVTTL LVTTL Input Low Voltage Range V 0.8 VOH,LVTTL LVTTL Output High Voltage Level, IOH = –400 µA V 2.2 3.45 VOL,LVTTL LVTTL Output Low Voltage Level, IOL = 1 mA V 0.6 IIH,LVTTL Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V µA 0.003 IIL,LVTTL Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V µA 300 600 ICC Total Supply Current, TA = 25°C mA 110 Guaranteed Operating Rates TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V Serial Clock Rate Serial Clock Rate FC (MBd) GE (MBd) Min. Max. Min. Max. 1040 1080 1240 1260

Min. Typ. Max. tdelay1 Total Loop Latency from FM_NODE[0] to TO_NODE[0] ns 4.0 tdelay2 Per Cell Latency from FM_NODE[4] to TO_NODE[0] ns 2.0 tr,LVTTLin Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V ns 2.0 tf,LVTTLin Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V ns 2.0 tr,LVTTLout Output LVTTL Rise Time Range, 0.8 V to 2.0 V, 10 pF Load ns 1.5 2.4 tf,LVTTLout Output LVTTL Fall Time Range, 2.0 V to 0.8 V, 10 pF Load ns 2.0 3.5 trs, HS_OUT HS_OUT Single-Ended Rise Time ps 200 350 tfs,HS_OUT HS_OUT Single-Ended Fall Time ps 200 350 trd, HS_OUT HS_OUT Differential Rise Time ps 200 350 tfd,HS_OUT HS_OUT Differential Fall Time ps 200 350 VIP,HS_IN HS_IN Input Peak-To-Peak Required Differential Voltage Range mV 200 1200 2000 VOP,HS_OUT HS_OUT Output Peak-To-Peak Differential Voltage mV 1100 1400 2000 (Z0=750 Ω, Figure 10) Power Dissipation and Thermal Resistance TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V Symbol Parameter Unit Typ. Max. PD Power Dissipation mW 360 Θjc Thermal Resistance, Junction to Case °C/W TA= 0°C to +70°C, VCC = 3.15 V to 3.45 V

Figure 6. Eye Diagram of a High Speed Differential Output. Please refer to Figures 7 and 8 for jitter measurement setup information.

1.063 GHz

Figure 8. Setup for Measurement of Deterministic Jitter. Figure 7. Setup for Measurement of Random Jitter.

106.25 MHz

1062.5 MHz

Figure 11. HDMP-04221 Package Drawings.

www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5968-5121E (11/99)