HDMIULC6-2X6 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Features
■ 2-line ESD protection (at 15 kV air and contact discharge, exceeds IEC 61000-4-2) ■ Ultra low capacitance: 0.6 pF @ 825 MHz ■ Ultra high bandwidth - no influence on signal rise and fall times - maximised number of signal harmonics ■ Very low leakage current: 0.5 µA max. ■ Fast response time compared with varistors ■ Protects VBUS when applicable ■ RoHS compliant Benefits ■ ESD standards compliance guaranteed at device level, thus greater immunity at system level ■ ESD protection of VBUS when applicable. ■ High efficiency due to low residual voltage when confronted by an ESD surge ■ Large bandwidth to minimize impact on data signal quality ■ Consistent D+ / D- signal balance: – Ultra low impact on intra- and inter-pair skew – Matching high bit rate HDMI requirements and ready for future evolution ■ Low PCB space occupation - 1.45 mm2 for µQFN ■ Low leakage current for longer operation of battery powered devices ■ Higher reliability offered by monolithic integration ■ 500 µm pitch for µQFN 6 leads Complies with these standards ■ IEC 61000-4-2 level 4 – 15 kV air discharge – 8 kV contact discharge ■ MIL STD883G-Method 3015-7
Applications
■ HDMI ports at 1.65 Gb/s and up to 3.2 Gb/s ■ IEEE 1394a, b, or c up to 3.2 Gb/s ■ USB 2.0 ports up to 480 Mb/s (Hi-Speed) ■ Ethernet port: 10/100/1000 Mb/s ■ Video line protection
Description
The HDMIULC6-2x6 is a monolithic, application specific discrete device dedicated to ESD protection of the HDMI connection. It also offers the same high level of protection for IEEE 1394a and IEEE 1394b/c, USB 2.0, Ethernet links, and video lines. Its ultra high cutoff frequency (5.9 GHz) secures a high level of signal integrity. The device topology provides this integrity without compromising the complete protection of ICs against the most stringent ESD strikes. µQFN (pin view) HDMIULC6-2M6 SOT-666 HDMIULC6-2P6
1 Characteristics
Figure 1. Functional diagram Table 1. Absolute ratings Table 2. Electrical characteristics (T amb = 25 °C) protect against backdrive current flow on data lines.
2 Application examples
Figure 12. HDMI single link application Figure 13. T1/E1/Ethernet protection
2.1 PCB layout considerations
Figure 14. PCB layout example Figure 15. TDR results for HDMIULC6-2M6 with PCB layout example
HDMIULC6-2x6 Technical information
3 Technical information
3.1 Surge protection
The HDMIULC6-2x6 is particularly optimized to perform ESD surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follows: with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) and VTRANSIL = VBR + Rd_TRANSIL . IP Calculation example We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 Ω and VT = 1.1 V. We assume that the value of the dynamic resistance of the transil diode is typically Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg= 8 kV, Rg= 330 Ω), VBUS = +5 V, and, in first approximation, we assume that: Ip = Vg / Rg = 24 A. We find: Note: The calculations do not take into account phenomena due to parasitic inductances.
3.2 Surge protection application example
If we consider that the connections from the pin VBUS to VCC, from I/O to data line, and from GND to PCB GND plane are two tracks 10 mm long and 0.5 mm wide, we can assume that the parasitic inductances, L VBUS, LI/O, and LGND, of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on the data line, due to the rise time of this spike (tr = 1 ns), the voltage V CL has an extra value equal to LI/O.dI/dt + LGND.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns for an IEC 61000-4-2 surge level 4 (contact discharge Vg = 8 kV, Rg = 330 Ω) The over voltage due to the parasitic inductances is: LI/O.dI/dt = LGND.dI/dt = 6 x 24 = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: We can reduce as much as possible these phenomena with simple layout optimization. VCL+ = VTRANSIL + VF for positive surges VCL- = - VF for negative surges VCL+ = +31.2 V VCL- = -13.1 V VCL+ = +31.2 + 144 +144 = 319.2 V
disturbance source (generally the connector).
3.3 Crosstalk behavior
Figure 22. Crosstalk phenomena high load impedance (few kΩ). Figure 20. Remaining voltage after the Figure 21. Remaining voltage after the
4 Recommendation on PCB assembly
4.1 Stencil opening design
- General recommendation on stencil opening design
Figure 26. Stencil opening dimensions. b) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 27. Recommended stencil window position (µQFN only)
Recommendation on PCB assembly HDMIULC6-2x6
4.2 Solder paste
- Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm.
4.3 Placement
- Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
4.4 PCB design preference
- To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
4.5 Reflow profile
Figure 28. ST ECOPACK® recommended soldering reflow profile for PCB mounting Note: Minimize air convection currents in the reflow oven to avoid component movement.
5 Package information
- Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
Figure 29. µQFN 6 leads footprint dimensions in mm [inches] 1 mark is to be used for this purpose. Table 3. Micro QFN 1.45x1.00 6L dimensions
Figure 30. Footprint (dimensions in mm) Table 4. SOT-666 dimensions
6 Ordering information
7 Revision history
Table 5. Ordering information
- The marking can be rotated by 90° to diferentiate assembly location
Table 6. Document revision history