HDMI2C1-14HD STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 32
Technical content
Datasheet sections
- 1 Functional description
- 2 Application information
- 2.1 CEC line description
- 2.2 DDC functional block description
- 2.3 HEAC link and HPD line description
- 2.3.1 HPD line description
- 2.3.2 HEAC functional block description
- 2.5 Back drive protection
- 2.6 TMDS channels ESD protection
- 2.7 Application block diagrams
- 3 Electrical characteristi cs
- 4 Package information
- 4.1 QFN package information
- 4.2 Packing information
- 5 Recommendation on PCB assembly
- 5.1 Stencil opening design
- 5.2 Solder paste
- 5.3 Placement
- 5.4 PCB design preference
- 5.5 Reflow profile
- 6 Ordering information
- 7 Revision history
Features
HDMI™ 2.0 (4K/2K 60fps) compliant from -40 to 85 °C TMDS high bandwidth and very low clamping voltage ESD protection 8 kV contact ESD protection on connector side Supports direct connection to low-voltage HDMI™ ASIC and/or CEC driver (down to 1.8 V) DDC capacitive decoupling between ASIC and HDMI™ connector and dynamic pull-up for long cable driving Back drive protection on 5 V, DDC bus and CEC CEC independent structure from main power supply HDMI™ Ethernet and audio return channel (HEAC) compatible HPD pull down and signal conditioning Short-circuit protection on 5 V output Proposed in QFN 36 leads 500 µm pitch Benefits Easy hardware design and speed-up certification of HDMI™ 2.0 Pin map sequence compliant with HDMI™ connector type A High integration level for minimal PCB footprint Efficient protection of sensitive HDMI™ ASICs Very low power consumption in stand-by mode Wake-up from stand-by through CEC bus Allow to drive long cable and poor quality cable Companion chip for STMicroelectronics’ STixxxx HDMI™ decoders Complies with the following standards HDMI™ 2.0 version IEC 61000-4-2 level 4 JESD22-A114D level 2
Applications
Consumer and computer electronics HDMI™ source device such as: – Set-top boxes / ADSL boxes – DVD and Blu-Ray disk systems – Notebook / PC graphic cards – Game console – Home theater
Description
The HDMI2C1-14HD is a fully integrated ESD protection and signal conditioning device for control links and TMDS data video channels of HDMI ™ transmitters (source). The HDMI2C1-14HD is a simple solution that provides HDMI™ designers with an easy and fast way to reach full compliance with the stringent HDMI ™ 2.0 (4K/2K 60fps) on a wide temperature range. TM: HDMI: the HDMI logo and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC.
1 Functional description
control links and TMDS data video channels of HDMI™ transmitters (source). Figure 1. Pin out, top view
Figure 2. Block diagram
2 Application information
2.1 CEC line description
Figure 3. CEC link functional diagram against hazardous back drive. source and when the sink drives the communication. Figure 4. Simplified view of the electrical parameters of the CEC block
component are put in high impedance mode. IEC61000-4-2 standard, level 4 (8kV contact).
2.2 DDC functional block description
(SCL). It is used to create a point to point communication link from the source to the sink. Figure 5. DDC bus functional diagram (SCL and SDA lines) The Figure 6 illustrates the electrical parameter of the DDC block specified in Table 8.
Figure 6. Simplified view of the electrical parameters of the DDC block illustrates the benefit of the dynamic pull-up integrated in the HDMI2C1-14HD device.
Figure 7. Benefit of the dynamic pull-up on the DDC bus line has to be activated one time. compliant with IEC61000-4-2 standard, level 4 (8 kV contact).
2.3 HEAC link and HP D line description
Figure 8. HEAC / HPD / Utility functional block diagram compliant with IEC61000-4-2 standard, level 4 (8 kV contact).
2.3.1 HPD line description
a high state level on the ASIC side, at the voltage level of the ASIC power supply VDD_IC. Otherwise, HPD_IC pin remains in low state. illustrated in the Figure 9.
Figure 9. Simplified view of the electrical parameters of the HPD block
2.3.2 HEAC functiona l block description
made of the Utility line and the HPD line. Two signals are transmitted through this link. necessary to use a coaxial cable from TV to audio amplifier.
that could occur on the cable side. is too high (short circuit), the device opens the +5 V. opened in order to protect the application. abnormal situation has been detected (option). The Figure 10 shows the functional diagram of the current limiter block. Figure 10. +5 V functional diagram in order to improve the user experience. power management state of the art.
2.5 Back drive protection
Figure 11. Back drive current diagram drive current is coming from +5V_OUT and/or DDC lines (see figure 11). against hazardous back drive.
2.6 TMDS channels ESD protection
transmit HD video data with no disturbance of the signal up to 5.94 Gbps per channel. ESD protection performances.
Figure 12. TMDS lines ESD protection functional diagram
2.7 Application block diagrams
Figure 13. Application block diagram
4 TMDS channels
Figure 14. PCB layout example compliant with HDMI connector type A. Table 1. Block diagrams references
4 TMDS c
Table 2. Pin description
1 SDA_IC DDC input ASIC side 19 DAT_CK- TMDS output Clock CK-
2 HPD_IC HPD output ASIC side 20 DAT_CK+ TMDS output Clock CK+
3 ESD_DISCH ESD protection enhancement
4 DAT_D2+_IC TMDS input Data D2+ 22 DAT_D0+ TMDS output Data D0+
5 DAT_D2-_IC TMDS input Data D2- 23 DAT_D1- TMDS output Data D1-
6 DAT_D1+_IC TMDS input Data D1+ 24 DAT_D1+ TMDS output Data D1+
7 DAT_D1-_IC TMDS input Data D1- 25 DAT_D2- TMDS output Data D2-
8 DAT_D0+_IC TMDS input Data D0+ 26 DAT_D2+ TMDS output Data D2+
9 DAT_D0-_IC TMDS input Data D0- 27 NC not connected
10 DAT_CK+_IC TMDS input Clock CK+ 28 5V_OUT +5V power supply HDMI cable side
11 DAT_CK-_IC TMDS input Clock CK- 29 VDD_5V +5V main power supply
12 HEAC+ HEAC+ output ASIC side 30 VDD_CEC CEC supply HDMI cable side
13 HEAC- HEAC- output ASIC side 31 V DD_CEC_IC CEC driver power supply
14 HPD HPD/HEAC- input HDMI
15 SDA DDC output HDMI cable side 33 VDD_IC HDMI ASIC power supply
16 SCL DDC output HDMI cable side 34 FAULT Fault line output ASIC side
17 Utility Utility/HEAC+ input HDMI
18 CEC CEC output HDMI cable side 36 SCL_IC DDC input ASIC side
Figure 15. Pin numbering
3 Electrical characteristics
Table 3. Absolute maximum ratings (limiting values)
- With a 100 nF capacitor connected to the 5V_OUT pin.
Table 4. Power supply characteristics (Tamb = 25 °C)
- In order to activate the DDC functional bloc k, the 3 following conditions have to be met:
Table 5. CEC electrical characteristics(1)
- T amb = 25 °C, VDD_CEC = 3.3 V, VDD_CEC_IC = 1.8 V, unless otherwise specified
- Test conditions are compliant wi th worst case CEC specification:
- Maximum capacitance allowed at connector output is 200 pF in HDMI 1.4 specification
Table 6. 5V_out current limiter electrical characteristics(1)
- T amb = 25°C, VDD_5V = 5 V, unless otherwise specified
- HDMI 1.4 specification requires a maximum of 100 mV voltage-drop
- HDMI 1.4 standard specifies a minimal current capability of 55 mA, and an over-current protection of no more than 500 mA
Table 7. HPD, HEAC, and utility line electrical characteristics(1)
- Tamb = 25°C, V DD_5V = 5 V, unless otherwise specified.
Table 8. DDC bus (SDA and SCL lines) electrical characteristics(1)
- T amb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified
- Maximum load capacitance allowed on I2C entire link (c able + connector) is 750 pF in HDMI 1.4 specification.
- Two pull-up resistors in parallel (sink 47 k + source 2 k).
- Maximum capacitance allowed at connector output is 50 pF in HDMI 1.4 specification
Figure 16. TMDS line S21 frequency curve Table 9. TMDS links electrical characteristics(1)
- Tamb =25°C, VDD_5V = 5V, unless otherwise specified
- The bandwidth is large enough to operate up to 340 MHz as HD MI clock frequency, corresponding to 10.2 Gbps total data
Figure 17. TMDS line differential far end crosstalk curve Figure 18. TMDS line: remaining voltage when positive 8 kV ESD surge applied Figure 19. TMDS line: remaining voltage when negative 8 kV ESD surge applies
20 V/div
4 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 QFN package information
Figure 29. QFN package outline
Figure 30. QFN footprint recommendation (dimensions in mm) Table 10. QFN package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
4.2 Packing information
Figure 31. Marking specification Figure 32. Tape and reel outline
5 Recommendation on PCB assembly
5.1 Stencil opening design
- General recommendation on stencil opening design
a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 33. Stencil opening dimensions b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 34. Recommended stencil window position
HDMI2C1-14HD Recommendation on PCB assembly
5.2 Solder paste
- Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particle s: powder particle size 20-45 µm.
5.3 Placement
- Manual positioning is not recommended. 2. It is recommended to use th e lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy , a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5.4 PCB design preference
- To control the solder paste amount, clos ed vias are recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. Symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
5.5 Reflow profile
Figure 35. ST ECOPACK® recommended soldering reflow profile for PCB mounting Note: Minimize air convection currents in the reflow oven to avoid component movement.
6 Ordering information
Figure 36. Ordering information scheme
7 Revision history
Table 11. Ordering information Table 12. Document revision history and reformatted to current standard.