HD-6409_05 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Converter or Repeater Mode
  • Independent Manchester Encoder and Decoder Operation
  • Static to One Megabit/sec Data Rate Guaranteed
  • Low Bit Error Rate
  • Digital PLL Clock Recovery
  • On Chip Oscillator
  • Low Operating Power: 50mW Typical at +5V
  • Pb-Free Plus Anneal Available (RoHS Compliant) Pinouts HD-6409 (PDIP, SOIC) TOP VIEW

Ordering Information

PKG. DWG. # PDIP -40°C to +85°C HD3-6409-9 E20.3 SOIC -40°C to +85°C HD9P6409-9 M20.3 SOIC (Pb-free) -40°C to +85°C HD9P6409-9Z (Note) M20.3 SOIC Tape & Reel (Pb-free) -40°C to +85°C HD9P6409-9Z96 (Note) M20.3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1BZI BOI UDI SD/CDS SDO SRST DCLK NVM RST GND VCC BZO SS ECLK BOO CTS MS OX IX CO FN2951.2Datasheet July 29, 2005 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2951.2 July 29, 2005 Block Diagram Logic Symbol EDGE DETECTOR COMMAND SYNC GENERATOR OUTPUT SELECT LOGIC BOI BZI UDI RST SD/CDS IX OX CO SS RESET 5-BIT SHIFT REGISTER AND DECODER DATA INPUT LOGIC INPUT/ OUTPUT SELECT OSCILLATOR COUNTER CIRCUITS MANCHESTER ENCODER SDO NVM BOO BZO CTS SRST MS ECLK DCLK SD CLOCK GENERATOR ENCODER CONTROL DECODER SS CO SD/CDS ECLK MS RST SDO DCLK NVM SRST OX IX BOO BZO CTS BOI BZI UDI HD-6409HD-6409

3 FN2951.2 July 29, 2005 Pin Description PIN NUMBER TYPE SYMBOL NAME DESCRIPTION 1 I BZl Bipolar Zero Input Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. 2 I BOl Bipolar One Input Used in conjunct ion with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. 3 I UDI Unipolar Data Input An alternate to bipolar input (B Zl, BOl), Unipolar Data Input (UDl) is used to input Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for data input, UDI must be held low.

4 I/O SD/CDS Serial Data/Command

In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern. 5 O SDO Serial Data Out The decoded serial NRZ data is tr ansmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. 6 O SRST Serial Reset In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. 7O N V M Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received. 8 O DCLK Decoder Clock The decoder clock is a 1X clock reco vered from BZl and BOl, or UDI to synchronously output received NRZ data (SDO). 9I R S T Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode, RST has the same effect on SDO, DCLK and NVM as in the converter mode. When RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received.

10 I GND Ground Ground

11 O C O Clock Output Buffered output of clock input I X. May be used as clock signal for other peripherals. 12 I I X Clock Input I X is the input for an external clock or, if the internal oscillator is used, IX and OX are used for the connection of the crystal. 13 O O X Clock Drive If the internal oscillator is used, OX and IX are used for the connection of the crystal. 14 I MS Mode Select MS must be held low for operation in the converter mode, and high for operation in the repeater mode. 15 I CTS Clear to Send In the converter mode, a high disables the encoder, forcing outputs BOO , BZO high and ECLK low. A high to low transition of CTS initiates transmission of a Command sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function of CTS is identical to that of the converter mode with the exception that a transition of CTS does not initiate a synchronization sequence. 16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop. 17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency. 18 O BZO Bipolar Zero Output BZO and its logical complement BOO are the Manchester data outputs of the encoder. The inactive state for these outputs is in the high state. 19 O BOO Bipolar One Out See pin 18. 20 I V CC VCC VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin-20) to GND (pin-10) is recommended. NOTE: (I) Input (O) Output HD-6409HD-6409

data to the MED at pin SD/CDS. Manchester “0” bits followed by a command sync pulse. synchronized with incoming data for its clocking. pattern. A data sync is a logically inverted command sync. the decoded NRZ data transmitted out of SDO. Control of the decoder outputs is provided by the RST pin. When RST is low, SDO, DCLK and NVM are forced low. external register on every high to low transition of this clock. FIGURE 1. ENCODER OPERATION

FIGURE 7. MANCHESTER ENCODER UART

8 FN2951.2 July 29, 2005 Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical) θJA θJC Maximum Junction Temperature ( Lead Tips Only for Surface Mount Packages) Die Characteristics CAUTION: Stresses above those listed in “A bsolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions NOTES: 1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Cl ock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by ±2 I X clock cycles (16X mode) or ±6 IX clock cycles (32X mode). 3. The maximum zero crossing tolerance is ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32 mode) from the nominal. SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS VIH Logical “1” Input Voltage 70% V CC -V V CC = 4.5V VIL Logical “0” Input Voltage - 20% V CC VV CC = 4.5V VIHR Logic “1” Input Voltage (Reset)V CC -0.5 - V V CC = 5.5V VILR Logic “0” Input Voltage (Reset) - GND +0.5 V V CC = 4.5V VIHC Logical “1” Input Voltage (Clock) V CC -0.5 - V V CC = 5.5V VILC Logical “0” Input Voltage (Clock) - GND +0.5 V V CC = 4.5V II Input Leakage Current (Except IX)- 1 . 0 + 1 . 0 µA VIN = VCC or GND, VCC = 5.5V II Input Leakage Current (IX)- 2 0 + 2 0 µA VIN = VCC or GND, VCC = 5.5V IO I/O Leakage Current -10 +10 µA VOUT = VCC or GND, VCC = 5.5V VOH Output HIGH Voltage (All Except OX)V CC -0.4 - V I OH = -2.0mA, VCC = 4.5V (Note 2) VOL Output LOW Voltage (All Except OX)-0 . 4V I OL = +2.0mA, VCC = 4.5V (Note 2) ICCSB Standby Power Supply Current - 100 µAV IN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current - 18.0 mA f = 16.0MHz, V IN = VCC or GND VCC = 5.5V, CL = 50pF FT Functional Test - - - (Note 1) NOTES: 1. Tested as follows: f = 16MHz, V IH = 70% VCC, VIL = 20% VCC, VOH ≥ VCC/2, and VOL ≤ VCC/2, VCC = 4.5V and 5.5V. 2. Interchanging of force and s ense conditions is permitted HD-6409HD-6409

9 FN2951.2 July 29, 2005 Capacitance TA = +25°C, Frequency = 1MHz SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 10 pF All measurem ents are referenced to device GND COUT Output Capacitance 12 pF SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS fC Clock Frequency - 16 MHz - tC Clock Period 1/f C -s e c - t1 Bipolar Pulse Width t C+10 - ns - t3 One-Zero Overlap - t C-10 ns - tCH Clock High Time 20 - ns f = 16.0MHz tCL Clock Low Time 20 - ns f = 16.0MHz tCE1 Serial Data Setup Time 120 - ns - tCE2 Serial Data Hold Time 0 - ns - tCD2 DCLK to SDO, NVM -4 0 n s - tR2 ECLK to BZO -4 0 n s - tr Output Rise Time (All except Clock) - 50 ns From 1.0V to 3.5V, C L = 50pF, Note 2 tf Output Fall Time (All except Clock) - 50 ns From 3.5V to 1.0V, C L = 50pF, Note 2 tr Clock Output Rise Time - 11 ns From 1.0V to 3.5V, C L = 20pF, Note 2 tf Clock Output Fall Time - 11 ns From 3.5V to 1.0V, C L = 20pF, Note 2 tCE3 ECLK to BZO, BOO 0.5 1.0 DBP Notes 2, 3 tCE4 CTS Low to BZO, BOO Enabled 0.5 1.5 DBP Notes 2, 3 tCE5 CTS Low to ECLK Enabled 10.5 11.5 DBP Notes 2, 3 tCE6 CTS High to ECLK Disabled - 1.0 DBP Notes 2, 3 tCE7 CTS High to BZO, BOO Disabled 1.5 2.5 DBP Notes 2, 3 tCD1 UDI to SDO, NVM 2.5 3.0 DBP Notes 2, 3 tCD3 RST Low to CDLK, SDO, NVM Low 0.5 1.5 DBP Notes 2, 3 tCD4 RST High to DCLK, Enabled 0.5 1.5 DBP Notes 2, 3 tR1 UDI to BZO, BOO 0.5 1.0 DBP Notes 2, 3 tR3 UDI to SDO, NVM 2.5 3.0 DBP Notes 2, 3 NOTES: Input rise and fall times driven at 1ns/V, Output load = 50pF. 2. Guaranteed via characteristics at in itial device design and after major process and/or design changes, not tested. 3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Cl ock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. HD-6409HD-6409