HD74AC153

HD74AC153 RENESAS | Alldatasheet

Document overview

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• PDF pages: 7

Technical content

Features

• Outputs Source/Sink 24 mA
• Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC153FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74AC153RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement E a I3a I2a I1a Za I0a GND VCC Eb I3b I2b I1b I0b Zb (Top view)

Rev.2.00, Jul.16.2004, page 2 of 6 Logic Symbol Ea Za Zb I0a I1a I2a I3a I0b I1b I2b I3b Eb Pin Names I0a to I3a Side A Data Inputs I0b to I3b Side B Data Inputs S0, S1 Common Select Inputs Ea Side A Enable Input Eb Side B Enable Input Za Side A Output Zb Side B Output Functional Description The HD74AC153 is a dual 4-input multiplexer. It can select two bits of data from up to four sources under the control of the common Select inputs (S0, S1). The two 4-input multiplexer circuits have individual active-Low Enables (Ea, Eb) which can be used to strobe the outputs independently. When the Enables (Ea, Eb) are High, the corresponding outputs (Za, Zb) are forced Low. The HD74AC153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two Select inputs. The logic equations for the outputs are shown below. Z a = Ea•(I0a•S1•S0 + I1a•S1•S0 + I2a•S1•S0 + I3a•S1•S0) Zb = Eb•(I0b•S1•S0 + I1b•S1•S0 + I2b•S1•S0 + I3b•S1•S0) Truth Table Select Inputs Input (a or b) Output S0 S1 EEEE I0 I1 I2 I3 Z X X HXXXXL L L LLXXXL L L LHXXXH H L LXLXXL HL L X H X X H L H LXXLXL L H LXXHXH H H LXXXLL HH L X X X H H H : High Voltage Level L : Low Voltage Level X : Immaterial

Rev.2.00, Jul.16.2004, page 3 of 6 Logic Diagram I0a I1a I2a I0b I1b I2b I3b EbEa I3a S1 Za Zb Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage V CC –0.5 to 7 V –20 mA V I = –0.5VDC input diode current I IK 20 mA V I = Vcc+0.5V DC input voltage V I –0.5 to Vcc+0.5 V –50 mA V O = –0.5VDC output diode current I OK 50 mA V O = Vcc+0.5V DC output voltage V O –0.5 to Vcc+0.5 V DC output source or sink current I O ±50 mA DC VCC or ground current per output pin I CC, IGND ±50 mA Storage temperature Tstg –65 to +150 °C Recommended Operating Conditions Item Symbol Ratings Unit Condition Supply voltage V CC 2 to 6 V Input and output voltage V I, VO 0 to VCC V Operating temperature Ta –40 to +85 °C VCC = 3.0V VCC = 4.5 V Input rise and fall time (except Schmitt inputs) V IN 30% to 70% VCC tr, tf 8 ns/V VCC = 5.5 V

Rev.2.00, Jul.16.2004, page 4 of 6 DC Characteristics Ta = 25°°°°C Ta = –40 to +85°°°°C Item Sym- bol Vcc (V) Unit Condition VIH VOUT = 0.1 V or VCC –0.1 V Input Voltage VIL V VOUT = 0.1 V or VCC –0.1 V VIN = VIL or VIH IOUT = –50 µA 3.0 2.58 — — 2.48 — I OH = –12 mA 4.5 3.94 — — 3.80 — I OH = –24 mA VOH VIN = VIL or VIH IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA 3.0 — — 0.32 — 0.37 I OL = 12 mA 4.5 — — 0.32 — 0.37 I OL = 24 mA Output voltage VOL V VIN = VIL or VIH IOL = 24 mA Input leakage current IIN 5.5 — — ±0.1 — ±1.0 µAV IN = VCC or GND IOLD 5 . 5 ———8 6—m A V OLD = 1.1 VDynamic output current* I OHD 5.5 — — — –75 — mA V OHD = 3.85 V Quiescent supply current I CC 5.5 — — 8.0 — 80 µAV IN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics: HD74AC153 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol V CC (V)*1 Min Typ Max Min Max Unit Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V

Rev.2.00, Jul.16.2004, page 5 of 6 Capacitance Item Symbol Typ Unit Condition Input capacitance C IN 4.5 pF V CC = 5.5 V Power dissipation capacitance C PD 65.0 pF V CC = 5.0 V

Rev.2.00, Jul.16.2004, page 6 of 6 Package Dimensions Package Code JEDEC JEITA Mass (reference value) FP-16DAV Conforms 0.24 g *Ni/Pd/Au plating *0.20 ± 0.05 *0.40 ± 0.06 0.12 0.15 M

2.20 Max

5.5 10.06

0.80 Max

10.5 Max

+ 0.20 – 0.307.80 0.70 ± 0.20 0˚ – 8˚ 0.10 ± 0.10 1.15 1.27 As of January, 2003 Unit: mm Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g *Ni/Pd/Au plating 1.27 16 9 1 8 0.15 0.25 M 1.75 Max 3.95 *0.20 ± 0.05 9.9 0˚ – 8˚

10.3 Max

+ 0.10 – 0.306.10 + 0.67 – 0.20 0.60 + 0.11 – 0.040.14 *0.40 ± 0.06 0.635 Max 1.08 As of January, 2003 Unit: mm

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