Microcontroller

HD68P01

Hitachi Semiconductor

MCU(MICROCOMPUTER UNIT)

Manufacturer: Hitachi Semiconductor

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HD68P01V07,HD68P01V07-1 HD6SP01M0 ,HD68P01M0-1 MCU (Microcomputer Unit) The HD68PO1 is an 8-bit single chip microcomputer unit (MCU) which significantly enhances the capabilities of the HDG8P01V07, HO68PO1VO7-1,HD68PO1M0, HD68PO1MO-1 HMCS6800 family of parts. It can be used in production sys a tems to allow for easy firmware changes with minimum delay or eset . it can be used to emulate the HD6801 for software development ; \\ IC includes 128 bytes of RAM, Serial Communications Interface at Neh (SCI), parallel 1/0 and a three function Programmable Timer on — \\ a> 4 chip, and 2048 bytes, 4096 bytes or 8192 bytes of EPROM on \\ eT package. It includes an upgrade HD6800 microprocessing unit \\ seer tt (MPU) while retaining upward source and object code com: \\e i t patibility. Execution times of key instructions have been im. \\ aaa proved and several new instructions have been added including yt toc.40P) an unsigned 8 by 8 multiply with 16-bit result. The HD68PO! : can function as a monolithic microcomputer or can be ex panded to a 65k byte address space. It is TTL compatible and @ PIN ARRANGEMENT (Top View) Tequires one +5 volt power supply. A summary of HD68PO! features includes HD68P01V07, HD68P01V07-1 ves fo cata © FEATURES xtra] (32) sc, © Expanded HMCS6800 Instruction Set erat 8) sc © 8x 8 Multiply Instruction NMC) OV. Veco PAP» © Serial Communications Interface (SC!) Ray onc Veco Pars: © Upward Source and Object Code Compatible with HD6800 Vee BH OA” Veco Fe © 16-bit Three-function Programmable Timer Pw Oh) OM “Oo Bmp © Applicable to All Type of EPROM ru] ont hoo PoP 4096 bytes; HN482732A bec eS Ves [21] Pa 8192 bytes; HN482764 pet om AiO Pao © 128 Bytes of RAM (64 bytes Retainable on Powerdown) Peel | OA co ea Peo © 29 Parailel 1/0 and Two Handshake Control Line Peta] O% 010 Kae © Internal Clock Generator with Divide-by-Four Output raf] Oo 0 0 Fp, © Full TTL Compatibility Palle] So, oo flew * Full Interrupt Capability Pel Oss os ew © Single-Chip or Expandable to 65k Bytes Address Space a lee © Bus compatible with HMCS6800 Family od Voz Standby = TYPE OF PRODUCTS EPROM Type No. MDOBPOTMO. HOSBPOIMO-1 HDesPo1vo7 | 1MHz | _HN482732A-30 Ves [7] 0 [aye xTAL 2] [32] Sc HDeePo1vo7-1 | 1.25MHz | HN482732A-30 eta. B] Balscs HD68P01MO HN482764-3 POT O%e Yee Flee HoesPoiMo-1 | _1.25MHz | HN482764-3 mest] SAP EO Blom es Om ee Note) EPROM is not attached to the MCU. Pi fe] OM deo Falee Pas [] OAs Ay O Felp.. ” Aw iad ra oe we Er.

1 PROGRAM DEVELOPMENT SUPPORT TOOLS reba] OM © 0 Fates

© Cross assembler software for use with IBM PCs and pee 00, oo pare compatibles ae avg Ce) [eee © Incircuit emulator for use with IBM PCs and compatibles Ps ea Oss 02 0 Fay Pas "6 [22] Par Pi Bo] [2'] Vee Standby | @HITACHI | 1066 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 COE eee ee OTT @ BLOCK DIAGRAM gate $355 BE os TFT pt dese in 21 Py Pot KN mux btt tee. ae: pat? [ c | Lee Pas Pie p> e 7 oa SC: - | scl = I Pro Pn Pu ‘Address Pi Pu an Py Pa an] ——P); Pu Hy Pia Ps en Po Data Pin Pu [ Pi: Vee Standby \\ _ On Packove_ re Ay | | 2 At Address

1 As | Output |

| EPROM a 4N482732A | wl Aul \\ (rasan) Ani ' cE! : \\ ! on! 1 0! 1 6! ' Or} i Ou!

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HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 ® ABSOLUTE MAXIMUM RATINGS Supply Voltage - ee (es i ee) v Input Voltage Vn” -0.3~+7.0 v Operating Temperature Tope 0 ~+70 _C Storage Temperature Tag -55 ~ +150 °c * With respect to Vgs (SYSTEM GND) {NOTE} Permanent LS! damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. @ ELECTRICAL CHARACTERISTICS © DC CHARACTERISTICS (Vcc =5.0V!5%, Vss = OV, Ta = 0 ~ +70°C; unless otherwise noted.) RES = V Input “High” Voltage + vy, | [eo | = | Vee v Input “Low” Voltage | All Inputs Vu jp 08 = os |v roo Fey “Vin =0~2.4V en Input Load Current SC, Mint | eo - | =. | 08 | ma EXTAL Vin = 0~ Vee -[ - 12 _tnput Leakage Current [NMI,1RQ),RES Hin! [Min =0~5.25V_ = - [| 25 HA Three State (Offset) Pio ~ Piz, Pxo ~ Par ‘| -o5~ = - io Leakage Curent [Pay <Page | ral Me SOS PAY to A Pao ~ Par Hoan = -208uA 24 | - | Output “High-Voltage [Puy ~ Per. €/SC.,8C:—] Von phoan=-145uA [2.4 | - —|¥ Other Outputs [Hono =-100ua [24 | — | ee . —— Tf Output “Low” Voltage | All Outputs Vou [loa =16ma (= [| os Tv Darlington Drive Current | Pro ~ Pi “low | Vour = 1.5V 10 | - 10.0 | mA Power Dissipation | Po - [- 1200 | mw P30 ~ Par, Pao ~ Par. SCi Vin = OV, Ta = 25°C, | — = 12.5 \\ it in ——$ F rounapacant __foumer impute | Sts nome [= as | Powerdown Vsee 40) - | 525 Vee Standby o 888 fe |} v = Operating Vss_| favs 26 |S Standby Current Powerdown Isa8 | Vsen = 4.0V = | 80 | mA “Except Mode Programming Levels: See Figure 8 | @HITACHI | 1068 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

a © AC CHARACTERISTICS BUS TIMING (Vcc = 5.0V!5%, Vss = OV, Ta = 0 ~ +70°C, unless otherwise noted.) = oe [nomen Gyele Time [7 [= [0 fos [= To Ts ‘Address Strobe Pulse width “High’’* [200 | - | - [iso | - | - [ os Address Strobe Rise Time | tas | Ls [= [sof s [= [50 [ ns Address Strobe Fall Time fs]{- | so] 5] - | 50 | ms ‘Address Strobe Delay Time* —— feo p= p- pst. fs Enable Rise Time SSS ee Enable Fall Time [ter [s [= [so [ s [= | 60 | as Enable Pulse Width “High” Time * | PWen | aso | —- | — [340 | - | - | os Enable Pulse Width “Low” Time * a50 | —_| - [350 [- | - | 1s ‘Address Strobe to Enable Delay Time” 1 taseo [eo |- | - | 30|- | - | ms ‘Address Delay Time Fig 1 [- | - | 260 | — [ — [| 260 | ns ‘Address Delay Time for Latch (f= 1.0MHz)* | tapi Fig.2 [- | - [270 [ = [ — | 260 | os Data Set-up Write Time | tosw _| fas | - | - [ms | - | - [os Data Set-up Read Time _ | sk | [eo |-|- | 7[- |=] ns Address Set-up Time for Latch” tt ns Address Hold Time for Latch [tan | 2S ns Address Hold Time rw P= =e = Access Time [Multiplexed Bus* | (taccm) | = [= [reso [== f@aor|_™ Oscillator stabilization Time tac Fig 11 [100 | — | — | 100 | - { — | ms Processor Control Set-up Time tecs Fig.12 [200 | - | - |200 | - | - [ *s * These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum (= in the highest speed operation). PERIPHERAL PORT TIMING (Vcc = 5.0V 45%, Vss = OV, Ta = 0 ~ +70°C, unless otherwise noted.) “Peripheral Data Setup Time | Port 1,2,3,4 | trosu Fig. 3 +e {— ns Peripheral Data Hold Time | Port1,2.3,4 | tron _Fig.3 | 200 - { - ns Delay Time, Enable Positive Transition | to OS3 Negative Transition ed tosor Fig. 8 ~ ft 30 Delay Time, Enable Positive Transition ry ras | a 350 | ne to OS3 Positive Transition , 0802 | Delay Time, Enable Negative| — T ~ — | | Transition to Peripheral Oata Port 1,2°,3,4 | tewo Fig. 4 - | 400 | 1s Natid Delay Time, Enable Negative . | rn _ Ee Transition to Peripheral Port 2°°, 4 1 temos Fig. 4 foe - us CMOS Data Valid | | “Input Strobe Pulse Width | tris Fig6 Pe 8 Input Data Hold Time | port Fig. 6 [ - | ns Input Data Set-up Time Port 3 [ots Fig. 6 {2} —t = ns “Except P,, **10kSt pull up register required for Port 2 @HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 1069

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Eee TIMER, SCI TIMING (Vcc = 5.0V 5%, Vss = OV, Ta = 0 ~ +70°C, unless otherwise noted.) Timer Input Pulse Width _ tewr __ 2 teyct200| ns Delay Time, Enable Positive Transition to . Fig, - Timer Out troo Fig. 7 ns SCI Input Clock Cycle seve D Teve SCI Input Clock Pulse Width — tewscK_ ~ [04 [06 | tscve MODE PROGRAMMING (Vcc = 5.0V #5%, Vsg = OV, Ta = 0 ~ +70°C, unless otherwise noted.) ite Un Mode Programming Input “Low” Voltage | _ Veeu _ Loon > | 1.7 v Mode Programming Input “High” Voltage | Veet L 40 ) = 4 - Vv Mode Programming Set-up Time tures | 2.0 = = teye Ae +s Hold Time RES Rise Time < lus wen [=f Address Strobi tas" PWasn— ov +l tas fe +h ase ol — 2av |+-——-—Pwe,, Enable { osv ter | lm tet -—— tao. ; jt an — Div Bae~Ai | BG trons (| Address Valid \\ ev tase ores | 106m —— =} few MCU Wite TW Ta 1 D,~D,.A,~A, Address ata Vale o6v oov ee |_| ‘ose Sl ‘MCU Read 22V 20V D,~D,. Ay~A, (ja |) {| Data vang !y (or 3) oBv ov — tracem! Figure 1 Expanded Multiplexed Bus Timing | @HITACHI | 1070 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy, Brisbane, CA 94005-1819 © (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 — Fd y, $ - Me 2 i aed 8 be eeeres fegetgse £25835 £322383 - z elfiele z Plpatatats * e_ {sels . ey | YE) epee ©) it sl- Sida z s[e] & sal 7 Ell i 7] 22 Heme ~ Hee 6 a gl lix sO 2 =! lee Aa 5 Em 84 Fd > _ > © ( wae é © Fi > > = | : E | é | a 5 =] ie i W @ HITACHI 1074 Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01MO0-1 = FUNCTIONAL PIN DESCRIPTIONS patible clock to the MCU’s internal clock generator. Divide-by- four circuitry is included which allows use of the inexpensive © Veg and Vgg 3.58 MHz Color Burst TV crystals. A 22 pF capacitor is requir- Vee and Veg provide power to a large portion of the MCU. _ ed from each crystal pin to ground to ensure reliable startup and ‘The power supply should provide +5 volts (5%) to Voc, and operation. Alternatively, EXTAL may be driven with an ex- Vgg should be tied to ground, Total power dissipation {includ- ternal TTL compatible clock with a duty cycle of 45% ~ 58% ing Voc Standby), will not exceed Pp milliwatts. with XTAL connected to ground. The internal oscillator is designed to interface with an AT-cut © Voc Standby quartz crystal resonator or a ceramic resonator operated in par- Voc Standby provides power to the standby portion ($80 allel resonance mode in the frequency range specified for 3.2 ~ through $BF) of the RAM and the STBY PWR and RAME bits 4 MHz. The crystal should be mounted as close as possible to of the RAM Control Register. Voltage requirements depend on _—the input pins to minimize output distortion and startup stabili- whether the MCU is in a pawerup or powerdown state, In the zation time. The MCU is compatible with most commercially powerup state, the power supply should provide +5 volts (5%) available crystals and ceramic resonators and nominal crystal and must reach Vgp volts before RES reaches 4.0 volts. During parameters are shown in Figure 15. powerdown, Vcc Standby must remain above Vspp (min) to __ sustain the standby RAM and STBY PWR bit. While in power- e RES down operation, the standby current will not exceed Ispa. This input is used to reset the MCU’s internal state and pro- It is typical to power both Vcc and Vcc Standby from the vide an orderly startup procedure, During powerup, RES must same source during normal operation. A diode must be used be held below 0.8 volts: (1) at least tec after Voc reaches 4.75 between them to prevent supplying power to Voc during volts in order to provide sufficient time for the clock generator powerdown operation. Vcc Standby should be tied to either to stabilize, and (2) until Vcc Standby reaches 4.75 volts. RES ground or Vc in Mode 3. must be held low at least three E-cycles if asserted during pow- erup operation. Veg Standby Power Line When a “High” level is detected, the MCU does the following: 1) All the higher order address lines will be forced “High”. 2) 1/0 Port 2 bits, 2, 1, and 0 are latched into programmed control bits PC2, PC1 and PCO. = 3) The last two (SFFFE, $FFFF) locations in memory will pe be used to load the program addressed by the program counter 4) The interrupt mask bit is set; must be cleared before the Figure 14 Battery Backup for Vcc Standby CPU can recognize maskable interrupts. © RAM Control Register ($14) © £ (Enable) The RAM Control Register includes two bits which can be This is an output clock used primarily for bus synchroniza- used to control RAM accesses and determine the adequacy of tion. It is TTL compatible and is the slightly skewed divide-by- the standby power source during powerdown operation. It is four result of the MCU input frequency. It will drive one intended that RAME be cleared and STBY PWR be set as part Schottky TTL load and 90 pF. and all data given in cycles is re- of a powerdown procedure. ferenced to this clock unless otherwise noted RAM Control Register © NMi (Non-Maskable Interrupt) 7 6 5 4 3 2 1 ° An NMI negative edge request an CPU interrupt sequence, orev but the current instruction will be completed before it responds Finally, a vector is fetched from SFFFC and SFFFD, trans: Bit 0~5 Not Used ferred to the Program Counter and instruction execution re- Bit 6 RAME RAM Enable. This Read/Write bit can be sumes. NMI typically requires a 3.3 k& (nominal) resistor to used to remove the entire RAM from the Vgc. There is no internal NMI pullup resistor. NMI must be intesnal memory map. RAME is set (en- held low for at least one E-cycle to be recognized under all abled) during Reset provided standby conditions. power is available on the positive edge of __ RES. If RAME is clear, any access to. a @_-TRQu (Maskable Interrupt Request 1) RAM address is external. If RAME is set IRQ, is a level-sensitive input which can be used to request and not in Mode 3, the RAM is included an interrupt sequence. The CPU will complete the current in- in the internal map. struction before it responds to the request. If the interrupt mask Bit 7STBY PWR Standby Power. This bit is a Read/Write _ bit ([-bit) in the Condition Code Register is clear, the CPU will Status bit which is cleared whenever Vcc begin an interrupt sequence. Finally, a vector is fetched from Standby decreases below Vspg (min). It SFFF8 and SFFF9, transferred to the Program Counter, and can be set only by software and is not instruction execution is resumed. affected by RES. TRO, typically requires an external 3.3 kQ (nominal) resis- tor to Voc for wire-OR application. IRQ, has no internal © XTAL and EXTAL pullup resistor These two input pins interface either a crystal or TTL com- @ HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 1075

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 © SC) and SCz2 (Strobe Control 1 and 2) SC1 and SCz in Expanded Non-Multiplexed Mode The function of SC, and SC, depends on the operating In the Expanded Non-Multiplexed Mode, both SC, and SC, mode. SC, is configured as an output in all modes except are configured as outputs. SC, functions as Input/Output Select single chip mode, whereas SC, is always an output. SC, and (TOS) and is asserted only when $0100 through $01FF is sensed SC; can drive one Schottky load and 90 pF ‘on the internal address bus. SC, is configured as Read/Write and is used to control the SC1 and SCz in Single Chip Mode direction of data bus transfers. An CPU read is enabled when In Single Chip Modes, SC, and SC, are configured as an in- Read/Write and E are high. put and output, respectively, and both function as Port 3 con- trol lines. SC, functions as IS3 and can be used to indicate that $C and SCz in Expanded Multiplexed Mode Port 3 input data is ready or output data has been accepted In the Expanded Multiplexed Modes, both SC, and SC are Three options associated with 1$3 are controlled by Port 3's configured as outputs. SC, functions as Address Strobe and can Control and Status Register and are discussed in Port 3's des- be used to demultiplex the eight least significant addresses and cription. If unused, [S3 can remain unconnected. the data bus. A latch controlled by Address Strobe captures ad- SC; is configured as OS3 and can be used to strobe output —_ dress on the negative edge, as shown in Figure 20. data or acknowledge input data. It is controlled by Output SC, is configured as Read/Write and is used to control the Strobe Select (OSS) in Port 3's Control and Status Register. The direction of data bus transfers. An CPU. read is enabled when strobe is generated by a read (OSS= 0) or write (OSS = 1) to Read/Write and E are high Port 3's Data Register. OS3 timing is shown in Figure 5 ‘Nominal Crystal Parameter Crystal | } ] 4 MHz 5 MHz Item Co 7 pF max. | 4.7 pF max. | g ame Se R, Bormax. | 308 ve. ur CRs XTAL — 2 3 CLy = CL2 = 22pF 20% Co (3.2 ~ 5 MHz) So Equivalent Circuit (Note] These are representative EXTAL AT cut parallel resonance crystal parameters C2 Cur tr dh (a) Nominal Recommended Crystal Parameters OO 475V Vee JUUU- RES bea osv ——— tae Oscillator Stabilization Time. tac {b) Oscitlator Stabitization Time (tac) Figure 18 Oscillator Characteristics @HITACHI | 1076 Hitachi America, Ltd. # Hitachi Piaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 « (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 = PORTS two lines, 153 and OS3, which can be used to control Port 3 There are four I/O ports on the MCU; three 8-bit ports and data transfers. one 5-bit port. There are two control lines associated with one Three Port 3 options are controlled by the Port 3. Control of the 8.bit ports, Each port has an associated write only Data and Status Register and available only in Single-Chip Mode: (1) Direction Register which allows each 1/0 line to be programmed Port_3 input data can be latched using [83 as a control signal, to act as an input or an output. A “1" in the corresponding (2) OS3 can be generated by either an CPU read or write to Data Direction Register bit will cause that 1/O line to be an out- Port 3's Data Register, and (3) an IRQ, interrupt can be en- put. A “0” in the corresponding Data Direction Register bit will abled by an IS3 negative edge. Port 3 latch timing is shown in cause the I/O line to be an input. There are four ports: Port |, Figure 6. Port 2, Port 3, and Port 4. Their addresses and the addresses of their Data Direction registers are given in Table 2. Port 3 Control and Status Register Table 2 Port and Data Direction Register Addresses Z 4 6 4 3 2 4 0 eat Tsd Latch = Se EBLE) 1/0 Port 1 so002 $0000 pit o~2 Not used sit O~ lot used. VO Port2 so003 sooo Bit 3 LATCH ENABLE. This bit controls the in- W/O Port 3 $0006 $0004 put latch for Port 3. If set, input data is V/O Port 4 $0007 $0008 latched by an 1S3 negative edge. The latch is transparent after a read of Port 3's Data Register. LATCH ENABLE is cleared by © P1q~P17 (Port 1) RES Port 1 is a mode independent 8-bit I/O port where each line Bit 4 OSS (Output Strobe Select). This bit deter- is an input or output as defined by its Data Direction Register. mines whether OS3 will be generated by a The TTL compatible three-state output buffers can drive one read or write of Port 3’s Data Register. Schottky TTL load and 30 pF, Darlington transistors, or CMOS When clear, the strobe is generated by a devices using external pullup resistors. It is configured as a data read; when set, it is generated by a write. input port by RES. Unused lines can remain unconnected. OSS is cleared by RES. Bit 5 Not used. __ © P29~P2e (Port 2) Bit 6 TS3 IRQ, ENABLE. When set, an IRQ, Port 2 is a mode independent 5-bit I/O port where each line interrupt will be enabled whenever IS3 is configured by its Data Direction Register. During RES, all FLAG is set; when clear, the interrupt is lines are configured as inputs. The TTL compatible three-state inhibited. This bit is cleared by RES. output buffers can drive one Schottky TTL load and 30 pF or —_—Bit7 TS3 FLAG. This read-only status bit is set CMOS devices using external pullup resistors. P29, P21 and Pa2 by an [S3 negative edge. It is cleared by a must always be connected to provide the operating mode. If read of the Port 3 Control and Status lines P,3 and Pz. are unused, they can remain unconnected. Register (with IS3 FLAG set) followed by Pro, Pai, and Pz2 provide the operating mode which is a read or write to Port 3's Data Register or latched into the Program Control Register on the positive edge by RES. of RES. The mode may be read from Port 2 Data Register as shown where PC2 is latched from pin 10. Port 3 in Expanded Non-Multiplexed Mode Port 2 also provides an interface for the Serial Communica: Port 3 is configured as a bidirectional data bus (Do~Dz) in tions Interface and Timer. Bit 1, if configured as an output, is the Expanded Non-Multiplexed Mode. The direction of data dedicated to the timer's Output Compare function and cannot transfers is controlled by Read/Write (SC;) and clocked by E be used to provide output from Port 2 Data Register. (Enable). Port 2 Data Register Port 3 in Expanded Multiplexed Mode Port 3 is configured as a time multiplexed address (Ag ~A1) z7 6 5 4 #3 #2 #41 0 and data bus (Dp~D;) in Expanded Multiplexed Mode where [rez Ject [roo [rae [ras [ozs Joa [20 | $0003 Address Strobe (AS) can be used to demultiplex the two buses. Port 3 is held in a high impedance state between valid address and data to prevent potential bus conflicts. © P39~P37 (Port 3) Port 3 can be configured as an I/O port, a bidirectional 8-bit © Pao~Pa7 (Port 4) data bus, or a multiplexed address/data bus depending on the Port 4 is configured as an 8-bit I/O port, address outputs, or operating mode. The TTL compatible three-state output buffers data inputs depending on the operating mode. Port 4 can drive can drive one Schottky TTL load and 90 pF. Unused lines can one Schottky TTL load and 90 pF and is the only port with remain unconnected. internal pullup resistors. Unused lines can remain unconnected. Port 3 in Single-Chip Mode Port 4 in Single Chip Mode Port 3 is an 8-bit I/O port in Single-Chip Mode where each In Single Chip Mode, Port 4 functions as an 8-bit I/O port line is configured by its Data Direction Register. There are also where each line is configured by its Data Direction Register. @ HITACHI Hitachi America, Ltd. © Hitachi Ptaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300 1077

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Internal pullup resistors allow the port to directly interface with up resistors are intended to pull Port 4's lines high until it is CMOS at 5 volt levels. External pullup resistors to more than —_ configured volts, however, cannot be used. Figure 18 illustrates a typical system configuration in the Expanded Non-Multiplexed Mode. The MCU interfaces directly Port 4 in Expanded Non-Multiplexed Mode with HMCS6800 family parts and can access 256 bytes of Port 4 is configured from RES as an 8-bit input port where external address space at $100 through SIFF. IOS provides an its Data Direction Register can be written to provide any or all address decode of external memory ($100-SIFF) and can of address lines, Ap to Az. Internal pullup resistors are intend- _be used similarly to an address or chip select line. ed to pull the lines high until its Data Direction Register is configured. Table 3. Summary of HD6B0O Operating Modes Port 4 in Expanded Multiplexed Mode CommontoalModes) In all Expanded Multiplexed modes except Mode 6, Port 4 Reserved Register Area functions as half of the address bus and provides Ag to Ays. In Port 1 Mode 6, the port is configured from RES as an 8-bit parallel in- Port 2 - put port where its Data Direction Register can be written to eee men intertace Provide any or all of address lines, Ay to Ars. Internal pullup sg g resistors are intended to pull the lines high until its Data Direc- 186 brs or HAM; 2048 bytes of ROM tion Register is configured where bit 0 controls Ag Port 3 is a parallel /O port with two control lines Port 4 is a parallel 1/O port © OPERATING MODES SC; és Input Strobe 3 (153) The MCU provides eight different operating modes which are _SC2 Output Strobe 3089) selectable by hardware programming and referred to as Mode 0 ——Expanded Non- Multiplexed Mode 5 through Mode 7. The operating mode controls the memory 338 oer oh crea menter of Rom map, configuration of Port 3, Port 4, SC, , SC . and the physical Port 3is on 8-bit dew ber location of interrupt vectors, Port 4 is an input port/address bus SC, is Input/Output Select (108) © Fundamental Modes —SCa is read/write (RAW) The MCU's eight modes can be grouped into three funda- Expanded Multiplexed Modes 1, 2, 3, 6 mental modes which refer to the type of bus it supports: Single Four snemory space options ASK accress space! Chip, Expanded Non-Multiplexed, and Expanded Multiplexed. (2) Internal RAM, no HOM (Mode 2) Single chip modes include 4 and 7, Expanded Non-Multiplexed (3) Internal RAM and ROM (Mode 1) is Mode 5 and the remaining five are Expanded Multiplexed port! intemal RAM, ROM with partial address bus (Mode 6) modes. Table 3 summarizes the characteristics of the operating ort Qi a multiplexed address/data bus modes. SC; is Address Strobe (AS) SC2 is Read/Write (R/W) Single Chip Modes (4, 7) “Test Modes 0 and 4 ~~ In Single-Chip Mode, the MCU’s four ports are configured as Expanded Multiplexed Test Mode 0 parallel input/output data ports, as shown in Figure 16. The sin wee at Ne ern Fanteved FM rode 4 MCU functions as a monolithic microcomputer in these two i) May be changed to Mode 5 without going through Reset modes without external address or data buses. A maximum of (2) May be used to test Ports 3 and 4 as 1/0 ports 29 1/0 lines and two Port 3 control lines are provided. In ad-—§<§ ——— dition to other peripherals, another MCU can be interfaced to Port 3 in a loosely coupled dual processor configuration, as shown in Figure 17. Expanded-Multiplexed Modes (0, 1, 2, 3, 6) In Single-Chip Test Mode (4), the RAM responds to $XX80 In the Expanded-Multiplexed Modes, the MCU has the ability through $XXFF and the ROM is removed from the internal ad- _to access a 65k bytes memory space. Port 3 functions as a time dress map. A test program must first be loaded into the RAM _multiplexed address/data bus with address valid on the negative using modes 0, 1, 2, or 6. If the MCU is Reset and then pro- _ edge of Address Strobe (AS) and the data bus valid while E is grammed into Mode 4, execution will begin at SXXFE:XXFF. high. In Modes 0 to 3, Port 4 provides address lines Ag to Ais. Mode 5 can be irreversibly entered from Mode 4 without going In Mode 6, however, Port 4 is configured during RES as data through Reset by setting bit 5 of Port 2’s Data Register. This port inputs and the Data Direction Register can be changed to mode is used primarily to test Ports 3 and 4 in the SingleChip provide any combination of address lines, Ay to Ays. Stated and Non-Multiplexed Modes. alternatively, any subset of Ag to Ars can be provided while retaining the remainder as input data lines. Internal pullup Expanded Non-Muttiplexed Mode (5) resistors are intended to pull Port 4's lines high until software A modest amount of external memory space is provided in configures the port. the Expanded Non-Multiplexed Mode while retaining signifi- Figure 19 depicts a typical configuration for the Expanded- cant on-chip resources. Port 3 functions as an 8-bit bidirectional Multiplexed Modes. Address Strobe can be used to control a data bus and Port 4 is configured as an input data port. Any transparent D-type latch to capture addresses Ap to Az, as combination of the eight least-significant address lines may be shown in Figure 20. This allows Port 3 to function as a Data Bus obtained by writing to Port 4’s Data Direction Register. Stated when E is high. alternatively, any combination of A, to A, may be provided In Mode 0, the Reset vector is external for the first two E- while retaining the remainder as input data lines. Internal pull- _cycles after the positive edge of RES and internal thereafter. In i | @ HITACHI 1078 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 « (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01MO0-1 addition, the internal and external data buses are connected and and monitor the internal data bus with the automated test there must be no memory map overlap to avoid potential bus equipment. conflicts, Mode 0 is used primarily to verify the ROM pattern Vee Vee ver TAL 5 pera ee “ora € i] NM oo — NMI a ANT lexTaL wm “Te fexran —_ T_texrat as, Vee Suny ina, Vee Standby "Veg Standby — . a Ml e Perot RES -— ‘RES. Port + Port 3 Hoserot Hoserot 81/0 Lines 81/0 Lines Port? Port

80 Port 3, 8 1/0 Lines uo

= Lines _ _ Lines 353 3} —_+8 Port 2 15 05 port ore 5.10 bine oon wis Vss 16-81 Timer 16-Bit Timer Port 4 Port 2 51/0 Lines Vss nt "Sass Figure 16 Single Chip Mode 16-Bit Timer Figure 17 Single Chip Dual Processor Configuration v ec Vee XTAC € TAL [Port 3 8 (op~0n 6 oa a 2 extaL NM exta. [OR 7 ott ae Vee Stendby in, Vec Standby fea a RES —e] woeero1 ES fe tr rr roo a LL 'HD6BPO1 Pont Pot TRG, 81/0 Lines 8 Date Lines Port 1 lag 80 Port 2 TOs Port 2 suo Port 4 $110 sant i0 Tos Sct 16Bit Timer tenn Lines Timer vss Vss. Figure 18 Expanded Non-Multiplexed Configuration Vee Vee pT spre Tre s&s “dons 8 18 Dew Bus lextar [>-AM lexTat (De~0r) Vee Standby mG, Vee Sendty fron tj Adacers Bus par ita law | aa

8 Lines

am = Address B70 as Port 2 . Port 2

5.10 Lines Blanes Ser

Serial WO Address Bus Time

16 Bit Timer a

v Figure 19 Expanded Multiplexed Configuration @HITACHI Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 1079

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 a D. G OC —— Qa, ] 74LS373 Port 3 TTT] tryorcan Address: Ay ~ Ay ___Funetion Table Address/Data | Fe Output | Enable Ta Contvat |__G . _ [TTT lo, as rm H 4 4 L H c L — L L x Q) | H x x z —— xX Data: Op ~D7 Figure 20 Typical Latch Arrangement © Programming The Mode Circuitry to provide the programming levels is dependent The operating mode is programmed by the levels asserted on _primarily on the normal system usage of the three pins. If con- P22, P21, and Pzo which are latched into PC2,PC1,and PCO of —_figured as outputs, the circuit shown in Figure 21 may be used; the program control register on the positive edge of RES. The _ctherwise, three-state buffers can be used to provide isolation operating mode may be read from Port 2 Data Register as while programming the mode. shown below, and programming levels and timing must be met as shown in Figure 8. A brief outline of the operating modes is shown in Table 4. Port 2 Data Register 2 6 5 4 3 2 1 o Goo oa co Table 4 Mode Selection Summary Pap Pat Pro Interrupt Bus a Mode 7 ceca) | ict) | iecoy | ROM | RAM | Vectors Mode Operating Mode 6 Ho] tT in MUX‘S. 6) Multiplexed/Partial Decode 5 L |. H i NMUX'S, 6) Non-Multiplexed/Partial Oecode 3 st H H E MUX(4) Multiplexed No. RAM or ROM

2 L H MUXxi4) Multiplexed /RAM _

1 L L Multiplexed/RAM & ROM

0 L L Multiplexed Test

1 — Internal (1) Internal RAM is addressed at $XX80 E — External (2) Internal ROM is disabled __ MUX — Multiplexed (3) RES vector is external for 2 cycies after RES goes high NMUX — Non-Multiplexed (4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1, 2, and 3 L — Logic “0” (5) Addresses associated with Port 3 are considered external in Modes 5 and 6 H — Logic “1” 46) Port 4 detault is user data input; address output is optional by writing to Port 4 Data Direction Register @HITACHI | 1080 Hitachi America, Ltd. * Hitachi Ptaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 » (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01MO-1 = MEMORY MAPS Table 5 Internal Register Area The MCU can provide up to 65k bytes address space depend- ing on the operating mode. The HDSSPO1 provides Bk bytes a f= dress space for EPROM, but the maps differ in EPROM types as Port 1 Data Direction Register* 00 follows. Port 2 Data Direction Register* o1 1) HN482732A (a 4k-byte EPROM) Port 1 Data Register | 02 In order to support the HD6801V0, EPROM of the Port 2 Date Register | 03 HD68P01V07/HD68P01V07-1 must be located at $FO00- Port 3 Data Direction Register* oa SFFFF. Port 4 Data Direction Register* o5** 2) HN482764 (a 8k-byte EPROM) Port 3 Data Register 06" The HD68P01M0/HD68P01M0-1 can provide up to Port 4 Data Register ovr 8k bytes address space using HN482764 instead of Timer Control and Status Register ry HN482732A. In this case, EPROM of the HD68P01M0/ Counter (High Byte) 09 HD68P01M0.-1 is located at $E000-SFFFF. Counter (Low Byte) OA ‘A memory map for each operating mode is shown in Figure _ Output Compare Register (High Byte) 0B 23. The first 32 locations of each map are reserved for the ‘Output Compare Register (Low Byte) oc MCU’s internal register area, as shown in Table 5, with excep- Input Capture Register (High Byte) 0D tions as indicated. Input Capture Register (Low Byte} OE Refer to “Precaution when emulating the HD680] Family”. Port 3 control and Status Register _ oF Rate and Mode Contro! Register 10 Transmit/Receive Control and Status Register " Receive Data Register 12 Transmit Data Register 13 RAM Control Register 14 Reserved 18-46 * External address in Modes 0, 1, 2, 3, 5, 6; cannot be accessed in Mode 5 (No 108) ‘+ External addresses in Modes 0, 1, 2, 3 +7 1 = Output, O = Input @ HITACHI 1082 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 HD68PO1 HD68PO01 Mode Mode Multiplexed Test mode Multiplexed/RAM_& EPROM | | }exterat Memory Soace | | } entemat Memory Sosce $0080 WY Y YY Y | Internat soot Z Wy, SooFF 4 | | External Memory Space External Memory Space $E000 p SE000 Y Yj Internal EPROM SFFFO 7 INOTES} INOTES) 1) Excludes the following addresses which may 1) Exeludes the following addresses which may be used externally: $04, $05, $06, $07 and SOF be used externally: $04, $05, $06, $07 and 2) Addresses SFFFE and SFFFF are considered ‘SOF. ‘external if accessed within 2 cycles alter a 2) EPROM addresses $FFFO to SFFFF are positive edge of RES and internal at all other not usable. times. 3) After 2 CPU cycles, there must be no over- tapping of internal and external memory spaces to avoid driving the data bus with more 4) This mode is the only mode which may be used to examine the interrupt vectors in EPROM using an external Reset vector. Figure 23 HOGBPO1 Memory Maps @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 » (415) 589-8300 1083

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01MO0-1 HD68P01 HD68P01 Mode Mode Multiplexed/RAM Multiplexed/No RAM or EPROM $000011) $0000'1) GY Y ister soe Yh“ e/a |_|} externa mony spac $0080 Y ‘S00FF “a External Memory Space Enteral Memory Space SFFFO seere L_____]} External Interrupt Vectors sree ae {NOTE] (NOTE) 1} Excludes the following addresses which may 1) Excludes the following addresses which may be used externally: $04, $05, $06, $07, and be used externally: $04, $05, $06, $07 and ‘SOF SOF. Figure 23 HD68P01 Memory Maps (Continued) | @ HITACHI | 1084 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 HD68P01 HO68PO1 Mode Mode Single Chip Test Non-Multiplexed/Partial Decode $0000 $0000!1) } internat Registers } internal Registers $OO1F $001F Unusabie $0080 Interna! RAM SOOFF $0100 External Memory Space SOIFF Unusable!1)(4) Unusable $€000 EPROM Sxx80 | tmernt Ran SXXFF Internat Interrupt Vectors SFFEF Internal tnterrupt Vectors [NOTES] INOTES] 1) The internal ROM is disabled. 1) Exctudes the following addresses which may 2) Mode 4 may be changed to Mode 5 without not be used externally: $04, $06, and SOF. having to assert RESET by writing a “1” into (No 108) the PCO bit of Port 2 Data Register 2) This mode may be entered without going 3) Addresses A, to A,, are treated as “don’t through RESET by using Mode 4 and sub- cares” to decode internal RAM. sequently writing a “1” into the PCO bit of 4) Internal RAM will appear at $XX80 to SXXFF Port 2 Data Register. 3) Address lines A,~A, will not contain address: es until the Data Direction Register for Port 4 has been written with "1's" in the appropriate bits. These address lines will assert "1's" until made outputs by writing the Date Direction Register Figure 23 HO68P01 Memory Maps (Continued) @ HITACHI Hitachi America, Ltd. » Hitachi Plaza « 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 1085

a HD68P01 HD68PO1 Mode Mode Multiplexed/Partial Decode Single Chip $0000'1) p 0000 or LL 8 os soe Ya) Internal Registers f | External Mensory Space Unusable $0080 WY) ‘$oog0 Internal RAM | Internat RAM soorr LL Ld SooFF a External Memory Space Unusable $E000 y $E000 Y Lp) EPROM EPROM (NOTES) 1) Excludes the following address which may be used externally: $04, $06, SOF 2) Address lines A,~A,, will not contain addresses until the Data Direction Register for Port 4 has been written with “1's” in the appropriate bits. These address lines will assert “1's” until made outputs by writing the Data Direction Register. Figure 23 HD68P01 Memory Maps (Continued) | @ HITACHI | 1086 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 589-8300 I

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 = PROGRAMMABLE TIME The Output Compare Register is set to SFFFF by RES. The Programmable Timer can be used to perform input wave- form measurements while independently generating an output © Input Capture Register ($0D: OE) waveform. Pulse widths can vary from several microseconds to The Input Capture Register is a 16-bit read-only register used many seconds, A block diagram of the Timer is shown in Figure to store the free-running counter when a “proper” input transi- 24, tion occurs as defined by IEDG. Port 2, bit 0 should be con- figured as an input, but the edge detect circuit always senses Pao © Counter ($09:0A} even when configured as an output. An input capture can occur The key timer element is a 16-bit free-running counter which _ independently of ICF: the register always contains the most cur- is incremented by E (Enable). It is cleared during RES and is rent value. Counter transfer is inhibited, however, between ac- read-only with one exception: a write to the counte: ($09) will cesses of a double byte CPU read. The input pulse width must preset it to $FFF8. This feature, intended for testing, can dis- be at least two E-cycles to ensure an input capture under all turb serial operations because the counter provides the SCI's conditions. internal bit rate clock. TOF is set whenever the counter contains all I's. © Timer Control and Status Register ($08) The Timer Control and Status Register (TCSR) is an 8-bit © Output Compare Register ($0B:0C) register of which all bits are readable while bits O~4 can be The Output Compare Register is a 16-bit Read/Write register written, The three most significant bits provide the timer’s used to control an output waveform or provide an arbitrary status and indicate if: timeout flag. It is compared with the free-running counter on + a proper level transition has been dtected, each E-cycle. When a match is found, OCF is set and OLVL is + a match has been found between the free-running counter clocked to an output level register. If Port 2, bit 1, is configured and the output compare register, and as an output, OLVL will appear at P;, and the Output Compare + the free-running counter has overflowed. _ Register and OLVL can then be changed for the next compare. Each of the three events can generate an IRQ; interrupt and The function is inhibited for one cycle after a write to itshigh _is controlled by an individual enable bit in the TCSR. byte of the Compare Resister (SOB) to ensure a valid compare [sate Regater Regater Timer wat p>) output ce) a | ie an oa register $08 ent ‘bon 5 UUY TRO, ‘ Output Compare Pulse == == 1 Output Input Level Edge Bit! Bird Port 2 Port 2 Figure 24 Block Diagram of Programmable Timer : @HITACHI | Hitachi America, Ltd. * Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 1087

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Timer Control and Status Register (TCSR) + clock: external or internal bit rate clock + Baud (or bit rate): one of 4 per E-clock frequency, or ex- 7 6 § 4 3 2 1 0 ternal bit rate (X8) input [ice [oce | r0F [eter] eocx eros] eoefouve] $0008 + wake-up feature: enabled or disabled + interrupt requests: enabled individually for transmitter and receiver BitOOLVL Output level. OLVL is clocked to the output + clock output: internal bit rate clock enabled or disabled level register by a successful output compare and to P22 will appear at P2, if Bit 1 of Port 2's Data Direc- + Port 2 (bit 3, 4): dedicated or not dedicated to serial I/O tion Register is set. It is cleared by RES. individually for transmitter and receiver. Bit 1 IEDG —_ Input Edge. IEDG is cleared by RES and controls which level transition will trigger a counter trans- © Serial Communications Registers fer to the Input Capture Register: The Serial Communications Interface includes four addres- IEDG = 0 Transfer on a negative-edge sable registers as depicted in Figure 25. It is controlled by the IEDG = | Transfer on a positive-edge. Rate and Mode Control Register and the Transmit/Receive Con- Bit2ETOI Enable Timer Overflow Interrupt. When set, an _ trol and Status Register. Data is transmitted and received utiliz- TRQ; interrupt is enabled for a timer overflow; ing a write-only Transmit Register and a read-only Receive when clear, the interrupt is inhibited. It is cleared Register. The shift registers are not accessible to software. by RES. Bit 3EOCI Enable Output Compare Interrupt. When set, an TRQ; interrupt is enabled for an output com- Bi? __ Rate end Mode Controt Regine: _Bt0 pare; when clear, the interrupt is inhibited. It is TxD] Tce: [eco] sss sso] 10 cleared by RES. vr " Bit 4EICI Enable Input Capture Interrupt. When set, an Tear Racer Convrol ane Sitar Rego TRQ, interrupt is enabled for an input capture; [sone predfond me] ne [re] re [wu ]sn when clear, the interrupt is inhibited. It is ceive Osta Repister cleared by BitS TOF Timer Overflow Flag. TOF is set when the CTT TIT TT tT) $12 counter contains SFFFF. It is cleared by reading the TCSR (with TOF set) followed by the Ponz (Not Addrensbte) counter’s high byte ($09), or by RES. | " Bit6OFC Output Compare Flag. OCF is set when the Out- put Compare Register matches the free-running counter. It is cleared by reading the TCSR (with OCF set) and then writing to the Output Com- pare Register ($0B or $0C), or by RES. Ton Bn Raw Bit 7 [CF Input Capture Flag. ICF is set to indicate a 19. Generator E proper level transition; it is cleared by reading 2 the TCSR (with ICF set) and then the Input Capture Register High Byte (SOD), or by RES. Not Adresse = SERIAL COMMUNICATIONS INTERFACE (SCI) 7 . | A full-duplex asynchronous Serial Communications Interface a (SCI) is provided with a data format and a variety of rates. The scl trancmitter and receiver are functionally independent, but [TTT TIT) $3 use the same data format and bit rate. Serial data format is Transmit Data Register standard mark/space (NRZ) and provides one start bit, eight data bits, and one stop bit. “Baud” and “bit rate” are used synonymously in the following description. Figure 25 SCI Registers © Wake-Up Feature In a typical serial loop multi-processor configuration, the Rate and Mode Control Register (RMCR) ($10) software protacol will usually identify the addresse(s) at the The Rate and Mode Control Register controls the SCI bit beginning of the message. In order to permit uninterested MCU’s _rate, format, clock source, and under certain conditions, the to ignore the remainder of the message, a wake-up feature is configuration of P,,. The register consists of four write-only included whereby all further SCI receiver flag (and interrupt) bits which are cleared by RES. The two least significant bits processing can be inhibited until its data line goes idle. An SCI control the bit rate of the internal clock and the remaining two receiver is re-enabled by an idle string of ten consecutive I's or _ bits control the format and clock source. by RES. Software must provide for the required idle string between consecutive messages and prevent it within messages. Rate and Mode Control Register (RMCR) ‘© Programmable Options 7 6 5 4 3 2 1 oo The following features of the SCI are programmable [ [=] = | « [ect [200] ss] 550] soo10 format: Standard mark/space (NRZ) @ HITACHI 1088 Hitachi America, Ltd. # Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01MO0-1 Le eee Bit !: BitO SS1: SSO Speed Select. These two bits select the and a preamble of nine consecutive 1’s is trans- Baud when using the internal clock. Four rates mitted. TE is cleared by RES. may be selected which are a function of the MCU Bit 2 TIE Transmit Interrupt Enable. When set, an IRQ; input frequency. Table 6 lists bit time and rates interrupt is enabled when TDRE is set; when for three selected MCU frequencies. clear, the interrupt is inhibited. TE is cleared by Bit 3: Bit2 | CC1:CCO Clock Control Select. These two bits RES. select the serial clock source. If CCI is set, the Bit 3 RE Receive Enable, When set, P2s’s DDR bit is DDR value for P,2 is forced to the complement cleared, cannot be changed, and will remain clear of CCO and cannot be altered until CCI is if RE is subsequently cleared. While RE is set, cleared. If CC1 is cleared after having been set the SCI receiver is enabled. RE is cleared by its DDR value is unchanged. Table 7 defines the RES. clock source, and use of P22. Bit4RIE Receiver Interrupt Enable. When set, an IRQ, If both CCI and CCO are set, an external TTL compatible interrupt is enabled when RDRF and/or ORFE is clock must be connected to P22 at eight times (8X) the desired set; when clear, the interrupt is inhibited. RIE is bit rate, but not greater than E, with a duty cycle of 50% (+ cleared by RES. 10%). If CC1:CCO = 10, the internal bit rate clock is provided at BitSTDRE Transmit Data Register Empty. TDRE is set P,, regardless of the values for TE or RE. when the Transmit Data Register is transferred to (Note) The source of SCI internal bit rate clock is the timer’s free run- the output serial shift register or by RES. It is ning counter. An CPU write to the counter can disturb serial cleared by reading the TRCSR (with TDRE set) operations. and then writing to the Transmit Data Register. Additional data will be transmitted only if TDRE Transmit/Receive Control and Status Register (TRCSR) ($11) has been cleared, The Transmit/Receive Control and Status Register controls Bit 6 ORFE Overrun Framing Error. If set, ORFE indicates the transmitter, receiver, wake-up feature, and two individual either an overrun or framing error. An overrun is interrupts and monitors the status of serial operations. All eight a new byte ready to transfer to the Receiver Data bits are readable while bits 0 to 4 are also writable. The register Register with RDRF still set. A receiver framing is initialized to $20 by RES. error has occurred when the byte boundaries of the bit stream are not synchronized to the bit Transmit/Receive Control and Status Register (TRCSR) counter, An overrun can be distinguished from a framing error by the value of RDRF: if RDRF is 76 § 4 3 2 1 0 set, then an overrun has occurred; otherwise a froneorrdrone] mie | we | vie | ve [ we | $0011 framing error has been detected. Data is not transferred to the Receive Data Register in an overrun or framing error condition. ORFE is BitOWU “Wake-up” on Idle Line. When set, WU enables cleared by reading the TRCSR (with ORFE set) the wake-up function; it is cleared by ten con- then the Receive Data Register, or by RES. secutive 1’s or by RES. WU will not set if the line Bit 7RDRF Receive Data Register Full. RDRF is set when is idle. the input serial shift register is transferred to the Bit 1 TE Transmit Enable. When set, P24 DDR bit is set, Receive Data Register. It is cleared by reading cannot be changed, and will remain set if TE is the TRCSR (with RDRF set), and then the Re- subsequently cleared. When TE is changed from ceive Data Register, or by RES. clear to set, the transmitter is connected to Pog Table 6 SCI Bit Times and Rates ___XTAL | 2.4576MHz 4.9152 MHz* ssi: sso E 614.4 kHz 1.2288 MHz ti) 0 £216 26 4s/38,400 Baud 16 us/62,500 Baud 13 ys/76,800 Baud 0 1 | &+128 | 208us/4,800 Baud 128ys/7812.5 Baud 104.2 us/9,600 Baud 1 ° & +1024 1.67ms/600 Baud 1.024ms/976.6 Baud =| 833.3 ys/1,200 Baud 1 1 E = 4096 6.67ms/150 Baud 4.096ms/244.1 Baud | _3.33 ms/300 Baud * HD68P01V07-1, HD68PO1MO-1 only Table 7 SCI Format and Clock Source Control cc: 60 Format Port 2 Bit 4 ar) = = = = = o 1 | NRZ Internal Not Used | iad bd 1 0 NRZ Internal Output® . ” tod NRZ External Input aa ha * Clock output is available regardless of values for bits RE and TE ** Bit 3 is used for serial input if RE = "1" in TRCS, bit 4 is used for serial output if TE = “1” in TRCS. | @HITACHI | Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 1089

HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1 © Intemally Generated Clcok Then the 8 data bits (beginning with bit 0) followed by the stop If the user wishes for the serial I/O to furnish a clock, the fol- bit (1), are transmitted. When the Transmitter Data Register has lowing requirements are applicable: been emptied, the TDRE flag bit is set. + the values of RE and TE are immaterial. If the MCU fails to respond to the flag within the pro- + CC1,CCO must be set to 10 per time, (TDRE is still set when the next normal transfer from + the maximum clock rate will be E+ 16. the parallel data register to the serial output register should + the clock will be at 1X the bit rate and will have a rising occur) then a 1 will be sent (instead of a 0) at “Start” bit time, edge at mid-bit. followed by more I's until more data is supplied to the data register. No 0’s will be sent while TDRE remains a 1. © Externally Generated Clock If the user wishes to provide an external clock for the serial Receive Operations 1/O, the following requirements are applicable: The receive operation is enabled by RE which configures + the CC1, CCO, field in the Rate and Mode Control Re- P,3. The receive operation is controled by the contents of the gister must be set to 11, Transmit/Receive Control and Status Register and the Rate and + the external clock must be set to 8 times (X8) the desired Mode Control Register. baud rate and The receiver bit interval is divided into 8 sub-intervals for + the maximum external clock frequency is 1.0 MHz. internal synchronization. In the NRZ Mode, the received bit stream is synchronized by the first 0 (space) encountered. © Serial Operations The approximate center of each bit time is strobed during The SCI is initialized by writing control bytes first to the the next 10 bits. If the tenth bit is not a 1 (stop bit) a framing Rate and Mode Control Register and then to the Transmit/Re- error is assumed, and ORFE is set. If the tenth bit is a 1, the ceive Control and Status Register. data is transferred to the Receive Data Register, and interrupt The Transmitter Enable (TE) and Receiver Enable (RE) bits _ flag RDRF is set. If RDRF is still set at the next tenth bit time, may be left set for dedicated operations. ORFE will be set, indicating an over-run has occurred. When the MCU responds to either flag (RDRF or ORFE) by reading ‘Transmit operations the status register followed by reading the Data Register, RDRF The transmit operation is enabled by TE in the Transmit/Re- (or ORFE) will be cieared. ceive Control and Status Register. When TE is set, the output of the transmit serial shift register is connected to P24 and the © © INSTRUCTION SET serial output by first transmitting to a ten-bit preamble of 1's. The HD68PO1 is upward source and object code compatible Following the preamble, intemal synchronization is established with the HD6800. Execution times of key instructions have and the transmitter section is ready for operation been reduced and several new instructions have been added, At this point one of two situation exist including hardware multiply. A list of new operations added to 1) if the Transmit Data Register is empty (TDRE = 1), a con the HD6800 instruction set is shown in Table 8. tinuous string of ones will be sent indicating an idle line. In addition, two new special opcodes, 4E and SE, are provid- or, ed for test purposes. These opcodes force the Program Counter 2) if a byte has been written to the Transmit Data Register to increment like a 16-bit counter, causing address lines used (TDRE = 0), it is transferred to the output serial shift reg- in the expanded modes to increment until the device is reset. ister and transmission will begin These opcodes have no mnemonics. During the transfer itself. the start bit (0) is first transmitted. Table 8 New Instructions instruction Description ABX Unsigned addition of Accumulator B 10 Index Register ADDD —_| Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator ASLD Shifts the double accumulator left {towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C-bit BRN Branch Never Loo Loads double accumulator from memory LSRD Shifts the double accumulator right {towards LSB) one bit; the MSB is cleared and the LSB is shifted into the C-bit MUL Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator PSHX Pushes the Index Register to stack PULX | Pulls the Index Register from stack STO | Stores the double accumulator to memory SUBD _| Subtracts memory from the double accumulator and leaves the difference in the double accumutator i @HITACHI | 1090 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300

ae =e ea eran HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 ‘© Programming Model © Addressing Modes A programming model for the HD68PO1 is shown in Figure The CPU provides six addressing modes which can be used 10. Accumulator A can be concatenated with accumulator B to reference memory. A summary of addressing modes for all and jointly referred to as accumulator D where A is the most instructions is presented in Table 9, 10, 11, and 12 where execu- significant byte. Any operation which modifies the double tion times are provided in E-cycles. Instruction execution times accumulator will also modify accumulator A and/or B, Other —_are summarized in Table 13. With an input frequency of 4 MHz, registers are defined as follows: E-cycles are equivalent to microseconds. A cycle-by-cycle description of bus activity for each instruction is provided in Program Counter Table 14 and a description of selected instructions is shown in ‘The program counter is a 16-bit register which always points Figure 26. to the next instruction. Immediate Addressing Stack Pointer The operand or “immediate byte(s)” is contained in the fol- ‘The stack pointer is a 16-bit register which contains the ad- lowing byte(s) of the instruction where the number of bytes dress of the next available location in a pushdown/pullup matches the size of the register. These are two or three byte (LIFO) queue. The stack resides in random access memory at a _ instructions. location defined by the programmer. Direct Addressing Index Register The least significant byte of the operand address is contained The Index Register is a 16-bit register which can be used to in the second byte of the instruction and the most significant store data or provide an address for the indexed mode of byte is assumed to be $00. Direct addressing allows the user to addressing. access $00 through $FF using two byte instructions and execu- tion time is reduced by eliminating the additional memory ac- Accumulators cess. In most applications, the 256-byte area is reserved for The CPU contains two 8-bit accumulators, A and B, which frequently referenced data. are used to store operands and results from the arithmetic logic unit (ALU). They can also be concatenated and referred to as Extended Addressing the D (double) accumulator. The second and third bytes of the instruction contain the ab- solute address of the operand, These are three byte instructions. Condition Code Registers ‘The condition code register indicates the results of an in- Indexed Addressing struction and includes the following five condition bits: Nega- The unsigned offset contained in the second byte of the in- tive (N), Zero (Z), Overflow (V), Carry/Borrow from MSB(C), __ struction is added with carry to the Index Register and used to and Half Carry from bit 3 (H). These bits are testable by the reference memory without changing the Index Register. These conditional branch instruction. Bit 4 is the interrupt mask are two byte instructions. (Lbit) and inhibits all maskable interrupts when set. The two unused bits, b6 and b7 are read as ones. Table 9 Index Register and Stack Manipulation Instructions Cond. Code Reg. lor [= [x {or |-Ts [or [-T#]or{~]s for [= Te iH iin iz {vie ‘Compare Index Reg cex acta (3fac|s|2| scjel3| || fx-mmet fefelt[s[e]e Decrement index Reg | DEX | | | joa [3 [1 [x= 1=x ofefe le fele Decrement Stack Prtr | DES | [| 3a {31 [sp—1— SP Tele . TTrerement Index Reg | _INX | oa{aty|xsr-x dete felt fel= TTrcrement Suck Pate | INS | —* io rt Bee epee letete Load index Reg Lox [3 [3] oe lee|s|2 5 MX (Mo 1 Xe 2 [elt [ale ‘Load Stack Patr Lbs BE oe [42 [ae|5|2 5 [3] m= Symon sPL [+ fe | fe[r[e Store index Reg | STX | | forlal2ler[si2ireis|3[ | | [xw=M.x.-iMs0) [e[ala[ale ‘Store Steck Pntr sts | | | [or |s[2[ar|s]2/ SPM, SP —(Metl Jo lela] [Ale index Reg Stack Patr| TXS nee | | Xa sP fele[olele Sack Pri index ee} Tx | | | J Td [iv jepv =x [ete fefete Aas mex | TTP Pe vlerx=x_ fede fetetele Push Data | PsHx 4]1 1X, = Mgp. SP -1 = SP . | | | Xt Mgp. SP - 1 SP Pull Date PULK if 1 [SP +1 SP, Mgp— Xi . |sP + 1+ SP, Mgp> Xi ‘The Condition Code Register notes are listed after Table 12 @ HITACHI : Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 1091

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Implied Addressing the branch condition is true, the Program Counter is overwritten The operand(s) are registers and no memory reference is with the sum of a signed single byte displacement in the second required. These are single byte instructions. byte of the instruction and the current Program Counter. This provides a branch range of —126 to 129 bytes from the first Relative Addressing byte of the instruction. These are two byte instructions. Relative addressing is used only for branch instructions. If Table 10 Accumulator and Memory Instructions Tmmulator anc immed | Direct | index Cond. Code Ri sara Satim | wrens [opt Felon [efor Telor{ [alan |-fe| Pommbwmen Litres ‘Add Aemiirs Het te A fe pee eee fee $ ‘Add B to x ABX Oe EE ee CCC fa with Cy tef2 [ee 212 ae |e [2 [a0 els] ‘AvMs OA ele feleet eB fc 09 eg |4 [2 [Fo B+M+C>B pete] t Add ADDA | 88 98 AB [4 |2 | 8 A+tM>A tle [tlt [tlt aops |ca[2|2/os|3|2 feels |2irala[3| | | [erma [tle islets ‘Add Double apoo |c3 F3 4 O+MM+ 1D lo [ofa [Te |e And “ANDA [84 ca A-MoA fe left (tire [anos (ca [2 [2 [oa | [2 | ea [a |2 | a [a | [e-mos fe fe fa [slate Shift Late Artietie ——s - ea {s Pe] {eee t an H ele felt lelt asia | | [58 | CCEA EERE Shift Left Db! ASLO rd [os | OCH ERERERED Shit Right, arihmatie | ASR - c Fir lept Te tee ate ASRA [| | | | [a7 fate jo fo fa ls [4 [3 asa - cs ee CU CHE SESERE: Bit Test BITA 85 |212\\95 al2 AM [ele [3 [t [ale site (cs [2/2 [os alles fa |3 | aM lo le [a[¢ [ale “Compare Ramis _ Pere A fe le[t faite Clea [orm | fit TF 00 +m [+ [+ [a {s [a [a [cima | | _ [1 [007A Je [e [ris [a [A cLAB Z - _ [1 [008 J |e [a js [ala Compe cpa 81 [2 [2/91 AL 8 A-M a lt [t[t CMP 2]2Tor{a|2 [ere]? [Ft oom Tele “Vs Comoiement [com 63 |e [2 [73 MoM le {e [fr fs COMA. aaa - Roa [t|als com ai b+8 HHS s Decimal Adj. A DAA im ne 1 | Adj binary sum to BCD [et [4 [t [ oeca | TT | | [aa [2 [i [a-teA mOOREEO DEcB B-158 lo [3 [3] |e “ExelusveOR~——~—~«Y_-«EORA | 8B 2 |2 198 a8 [4 [3 | [ [AGMA le [o[s [tale EORB |2| [a | {4 [3 | BOM>B Jefe ate ate “Increment “Tine Tf j6 [3 | MetoM CHESEEaG wea} [Pac ppt tacia etree fe im 5c BtisB CaREREO “Toad Aeminrs 36 [a6 [3 [2 | fee ~ MA Ey-EEet a toas [ce [2 |2 [oe |3 [2 [e6 | |2 [Fe [4 [3 | | [use lo |e [3 [3 [Ro . Load Double LoD cc|3]3 [oc ecjsl2[rc|s [3 | | [MM+1+0 le lols [tirfe Logical Shift, Left ist | esél2{mlel(3| || | anna t USLA | faa f2tyT lt [tt tsi | spp eee ee a) oo lols is it] ‘Shift Right, Logical sR man 74 _ ___ CaGUES ERE eet TT fae taf] eee COCHGIERERE: Pee ft pmeeas a eee + fesro | TTT TT i | Joe [3 [i] [+ [el 3 (Continued) | @HITACHI | 1092 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

Table 10 Accumulator and Memory Instructions (Continued) Gand tole Fe Stas, [uno [EE laealorTaer eters tomeomen Litre ests Muttipiy Dw | tt] tit Itt J] fsohofifaxs=o fefe[o[e [oye 2s Complement NEG PE teeta fae fee ee t overs NEGA tH a ey EEE ness [j || PET ees —— 88 OOBBEE No Operation _| Nor rtelateata taal || [for [afi trcrrsec Te fe fe fo fe fo inclusive OR [ose [ee [2 {9a | ayant | 4 BH [AtM>A___je let ie {rie oraB_ ICA [oa[s |2 [ea la | 4[3] | | fe+moe [ele lt{t|rle Push Data [psu | on [36 [3 [| A-Stack Jo fof [ojo fo ee ee | rT yt [tar Bs [1 [6 stack oooooo Pull Data PULA ce “T [32 [4 ft | Stack +A ponooo H _ _| mea 1 | Stack +8 moodon Rotate Left eo 6 i2friels; | | | CUCUERESMERES t | [ao [2 [1] le fels tele ts . ae | | [2 [9] le fo[s [els [s Rotate Right [| jo? 76 6 oe lefe isle te ts RORA + . | {as [2 [1] [elo [ele [a [s —_— RORB [| pT | tse j2 ff CHCUESESESES Subtract Acmitr ssa | | | rt ia A-B>A ~_fefe leis tlt Subwrect with Cary -|_SBCA [82 [2 |2 [92 [3 [2 | a2/4 [2 | 82 A-M-C+A OOBBEE . [secs Jez|2|2[o2|3 12 ]e2{elaira{e|st | | [e-w-eme referee lets Biore emis jer {s]2tari«|2e7 («3 | | [A>M ele lt tlale STAB for ta defer fale tr | oom SOOHEGIO stp. | | [| [pola [2] 2 {Fo aoa O>MM +1 Jefe [t [t [r[o Subtract sua |80 | 90 [3 {2 | 2/80 (4 | A-M=>A felelsi[s[t|t suse [co{2 {3 |oo's [2 [eo [«!2[r0 a tee 3 Subtract Double sued |83 |4|3| 2 {a3 [6 [2 [89 D-M:M+1>0 lefe[t{t|t lt “Transfer Amit TAB ia : [Tie [afitase ele fee irle bet Tt ste ete [> [e]e [3 fale Test, Zero or Minus TST leo [6/2/70 6 [3 M-00 [eft [tA [R [ot te A-00 : Heft [ste TTT PTET Tt 1 [8-00 OOREGG The Condition Code Register notes are listed after Table 12 @HITACHI Hitachi America, Ltd. # Hitachi Plaza « 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 1093

Table 11. Jump and Branch Instructions

00 Byte = Zero

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 (ee le le leleese ll ee Table 13 Instruction Execution Times in E-Cycles Adressing Mode ig 2 gie)/2/8 8ls Rls Ela; S/E Ele a) ABA e e . e 2 ° | INX . e e e 3 e ABX ele e fe} 3) ee: JMP eje!l3)3})e.e¢ ADC 213 !i4fai/ele | JSR le !si6!|ejeie ADD 2 3.1 4 4 . e | LDA | 2 3°, 4 4 . e ADDD 45 6 6 je . LDD | 3 [4 5 5 . . AND 2/3 |)4)4/)e/e LDS '3i4/5)5};e)e ASL elele}oj,elte| LDx 3) 4/5{s5slele ASLO eltejele 3/e usr e;e!léefe,e le ASR siete is ss USRD ele elelaje BCC ole le fel e) 3 MUL eo} e |e |e] ]e BCS ° ° . e. | . | 3 NEG e e 6 6 ° e BEQ e e . e ! e:) 3 NOP . e ° e 2 e BGE ,;e}je}jel;eie | 3 | ORA p13 pa pate te BHI etete pete 3 PsHx oe | @ | eolelajye | BHS ele le tele | 3 | PUL Je epee le yele BIT 2/3 14/4, ¢e @ lpux «|e ) ee] sie BLE elelelele 3. | ROL | 6 6jele BLO ° . ° e:,e 3° | ROR ele 6 6 |e e BLS . e e e eo | 35 PRT . ele . 10 | e@ at |e ele elo l a nis cw fe fee lb fe BMI efelelele 3 SBA |e | eo ele; 2fe«e! BNE eo} eile ee 3 | sac 2 314) 4/)e);e) BYC ° . ° ele 3 | sTD . 4 5 | 5 |e ° BVS “e | 2+ e ] oe tad STS e455 5 |e )e CBA e e. e e 2 ° | STX 3 4 5 5 e e Cc ° e e 7c. 2);,e@.) suB 3 4 ° e cui ele lei e 2!) | suBO aj} 5) 6 | 6ie|e CLR \\“,;e]6), 6 ee swt |e |e le le lide CLV efele fe 2 e | TAB ele 7 etlelzie com elejeleizie ' TBA eje | eiel2ie cPx 4 5 6|/6j jee | TPA e eje . 2 ° DES e . e . 3 . TXS . a DEX ° e ee | 3 e | WAI ° e e. e 9 e INS e e . e 3 e | @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 1095

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 = SUMMARY OF CYCLE BY CYCLE OPERATION tion. In general, instructions with the same addressing mode Table 14 provides a detailed description of the information _and_ number of cycles execute in the same manner. Exceptions present on the Address Bus, Data Bus, and the Read/Write are indicated in the table. (R/W) line during each cycle of each instruction. Note that during MCU reads of internal locations, the result- The information is useful in comparing actual with expected ant value will not appear on the external Data Bus except in results during debug to both software and hardware as the Mode 0. “High order” byte refers to the most significant byte program is executed. The information is categorized in groups _of a 16-bit value. according to addressing mode and number of cycles per instruc- Table 14 Cycle by Cycle Operation Address Mode & Cycle RW IMMEDIATE ADC EOR 2 1 Op Code Address 1 Op Code ADD LDA 2 | Op Code Address +1 1 Operand Data AND ORA BIT SBC CMP SUB \\ —_e ee LDS 3 1 Op Code Address 1 Op Code Lox 2 | Op Code Address + 1 1 Operand Data (High Order Byte} LoD 3 | Op Code Address + 2 1 Operand Data (Low Order Byte) cPx 4 1 | Op Code Address 1 Op Code suBD 2 | Op Code Address +1 1 Operand Data (High Order Byte) ADDD 3 | Op Code Address + 2 1 | Operand Data (Low Order Byte) 4 | Address Bus FFFF 1 Low Byte of Restart Vector DIRECT ADC EOR 1 Op Code Address 1 Op Code ADD LDA 2 | Op Code Address + 1 1 | Address of Operand AND ORA 3 | Address of Operand 1 Operand Data BIT SBC CMP SUB STA 3 1 | Op Code Address 1 Op Code 2 | Op Code Address +1 1 Destination Address {3 _| Destination Address | 0 _| Data from Accumulator Los 4) 4 Op Code Address 1 | Op Code Lox 2 | OpCode Address +1 1 Address of Operand LoD 3 | Address of Operand 1 Operand Data (High Order Byte) 4 — | Operand Address + 1 loa Operand Data (Low Order Byte) — a is ata {Low Order yest STS 4 1 Op Code Address 1 Op Code STX 2 | Op Code Address + 1 ,o4 Address of Operand sto 3 Address of Operand ; 0 Register Data (High Order Byte) 4 | Address of Operand +1 0 Register Data (Low Order Byte) cPx 5 1 Op Code Address Op Code SUBD 2 | Op Code Address + 1 Address of Operand i ADDD 3 | Operand Address Operand Data (High Order Byte) 4 — | Operand Address + 1 Operand Data (Low Order Byte) 5 _| Address Bus FFFF Low Byte of Restart Vector JSR Op Code Address Op Code Op Code Address + 1 Irrelevant Oata Subroutine Address First Subroutine Op Code Stack Pointer Return Address (Low Order Byte) Stack Pointer +1 Return Address (High Order Byte) : (Continued) i | @ HITACHI | 1096 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

Table 14. Cycle by Cycle Operation (Continued)

3 Op Code Address + 2 1 Address of Subroutine (Low Order Byte)

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Table 14 Cycle by Cycle Operation (Continued) Address Mode & Cycle RW Instructions Cycles | Address Bus Dine Data Bus INDEXED JMP 1 Op Code Address 1 | Op Code 2 | Op Code Address +1 1 | Offset 3_| Address Bus FFFF 1 Low Byte of Restart Vector AOC EOR Op Code Address 1 ‘Op Code ADD LDA Op Code Address + 1 1 | Offset AND ORA Address Bus FFFF 1 Low Byte of Restart Vector BIT SBC Index Register Plus Offset 1 | Operand Data CMP SUB STA Op Code Address 1 Op Code Op Code Address + 1 1 Offset Address Bus FFFF 1 Low Byte of Restart Vector Index Register Plus Offset 0 _| Operand Data Los 5 1 Op Code Address Op Code Lox 2 | Op Code Address + 1 Offset Loo 3 | Address Bus FFFF Low Byte of Restart Vector

4 Index Register Plus Offset Operand Data (High Order Byte}

5 _| Index Register Plus Offset + 1 Operand Data {Low Order Byte) sts 1 | Op Code Address 1 |Op Code sTx 2 | Op Code Address +1 1 | Offset sTD 3 Address Bus FFFF 1 Low Byte of Restart Vector

4 Index Register Plus Offset 0 Operand Data (High Order Byte)

5 | Index Register Plus Offset +1) 0 | Operand Data (Low Order Byte) ASL LSR 6 1 | Op Code Address 1 Op Code ASR NEG 2 | Op Code Address +1 1 Offset CLR ROL 3 Address Bus FFFF 1 Low Byte of Restart Vector COM ROR 4 Index Register Plus Offset 1 Current Operand Data DEC TST* 5 Address Bus FFFF 1 Low Byte of Restart Vector INC 6 Index Register Plus Offset 0 New Operand Data CPX 6 Op Code Address 1 Op Code SUBD Op Code Address + 1 1 Offset ADDD Address Bus FFFF 1 Low Byte of Restart Vector Index Register + Offset 1 | Operand Data (High Order Byte) Index Register + Offset +1 1 | Operand Data (Low Order Byte) _ Address Bus FFFF ’ | Low Byte of Restart Vector JSR i 6 1 Op Code Address 1 Op Code | 2 Op Code Address +1 1 Offset | 3 Address Bus FFFF 1 Low Byte of Restart Vector

4 Index Register + Offset 1 First Subroutine Op Code

5 Stack Pointer 0 Return Address (Low Order Byte)

6 Stack Pointer - 1 oO Return Address (High Order Byte)

In the TST instruction, the line condition of the sixth cycle does the following: R/W = “High”, AB = FFFF, DB = Low Byte of Reset Vector (Continued) @ HITACHI 1098 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

a =e HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Table 14 Cycle by Cycle Operation (Continued) Address Mode & —] Cycles | Cvcle Address Bus RAV Data Bus Instructions ¥ # Line IMPLIED ‘ABA DAA SEC 1 Op Code Address 1 Op Code ASL DEC SEI 2 | Op Code Address +1 1 Op Code of Next Instruction ASR INC SEV CBA LSR TAB CLC NEG TAP CLI NOP TBA CLR ROL TPA CLV ROR TST COM SBA _ ; _ ABX 1 Op Code Address 1 Op Code

2 Op Code Address + 1 1 Irrelevant Data

_| Address Bus FFFF 1 Low Byte of Restart Vector ASLD 1 Op Code Address 1 Op Code LSRD 2 Op Code Address +1 1 Irrelevant Data 3 __| Address Bus FFFF 1 Low Byte of Restart Vector DES Op Code Address Op Code INS Op Code Address + 1 Op Code of Next Instruction Previous Register Contents Irretevant Data INX 3 1 Op Code Address Op Code DEX 2 Op Code Address + 1 Op Code of Next Instruction

3 Address Bus FFFF Low Byte of Restart Vector

PSHA 1 Op Code Address T 1 | Op Code PSHB 2 | Op Code Address +1 {4 Op Code of Next Instruction 3._| Stack Pointer 0 _| Accumulator Data TSX 1 | Op Code Address Op Code 2 | Op Code Address + 1 Op Code of Next Instruction

3 Stack Pointer Irrelevant Data

TXS 1 Op Code Address 1 Op Code 2 | Op Code Address + t 1 Op Code of Next Instruction

3 Address Bus FFFF 1 Low Byte of Restart Vector

PULA 4 1 Op Code Address Op Code PULB 2 Op Code Address + 1 Op Code of Next Instruction

4 Stack Pointer +1 Operand Data from Stack

PSHX 1 | Op Code Address Op Code 2 ‘Op Code Address + 1 Irrelevant Data 3 | Stack Pointer Index Register (Low Order Byte)

4 Stack Pointer + 1 Index Register (High Order Byte)

PULX 1 Op Code Address Op Code

2 Op Code Address +1 Irrelevant Data

4 | Stack Pointer +1 Index Register (High Order Byte]

5 Stack Pointer +2 Index Register (Low Order Byte)

RTS 5 1 | Op Code Address ‘Op Code | 2 Op Code Address + 1 Irrelevant Data 4 | Stack Pointer + 1 Address of Next Instruction {High Order Byte) 5 | Stack Pointer +2 Address of Next Instruction (Low Order Byte) (Continued) @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 + (415) 589-8300 1099

a HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Table 14 Cycle by Cycle Operation (Continued) WAI “* 1 Op Code Address 1 Op Code 2 | Op Code Address + 1 1 | Op Code of Next Instruction 3 | Stack Pointer 0 | Return Address (Low Order Byte)

4 Stack Pointer — 1 0 Return Address (High Order Byte)

5 | Stack Pointer — 2 0 | Index Register (Low Order Byte}

6 Stack Pointer ~ 3 0 | Index Register (High Order Byte)

7 Stack Pointer — 4 0 Contents of Accumulator A

8 — | Stack Pointer — 5 0 | Contents of Accumulator B 9 Stack Pointer — 6 0 Contents of Cond. Code Register MUL io | 1 ‘Op Code Address 1 | Op Code ; 2 Op Code Address + 1 , Irrelevant Data

3 Address Bus FFFF | 1 Low Byte of Restart Vector

4 Address Bus FFFF 1 Low Byte of Restart Vector

| 5 Address Bus FFFF | 1 Low Byte of Restart Vector

6 Address Bus FFFF | 4 Low Byte of Restart Vector

7 | Address Bus FFFF | 1 | Low Byte of Restart Vector

8 Address Bus F FFF | 1 | Low Byte of Restart Vector

9 Address Bus FFFF | 1 Low Byte of Restart Vector

10 Address Bus FFFF | 1 | Low Byte of Restart Vector

RTI 10 7 ‘Op Code Address — 1 Op Code 3 | Stack Pointer 1 Irrelevant Data 4 Stack Pointer + 1 1 Contents of Cond. Code Reg. from Stack } 6 Stack Pointer + 2 1 Contents of Accumulator B | from Stack | 6 Stack Pointer +3 1 Contents of Accumulator A. | from Stack

7 Stack Pointer + 4 1 Index Register from Stack

| (High Order Byte)

8 Stack Pointer + 5 1 Index Register from Stack

(Low Order Byte)

9 Stack Pointer + 6 1 Next Instruction Address from

Stack (High Order Byte)

10 Stack Pointer + 7 1 Next Instruction Address from

‘Stack (Low Order Byte) Swi 2 [ 7 Op Code Address 1 Op Code

3 Stack Pointer oO Return Address (Low Order Byte)

7 Stack Pointer — 4 i} Contents of Accumulator A

12 Vector Address FFFB (Hex) 1 Address of Subroutine

(Low Order Byte) i ** While the MCU is in the ‘Wait’ state, its bus state will appear as 8 series of the MCU reads of an address which is seven locations i less than the original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance | state by & WAI instruction. | (Continued) @HITACHI 1100 Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 Table 14 Cycle by Cycle Operation (Continued) Address Mode & Cycle RW instruction Cycles | Address Bus Line Data Bus RELATIVE BCC BHT BNE 3 1 Op Code Address. 1 Op Code BCS BLE BPL 2 Op Code Address + 1 1 Branch Offset BEQ BLS BRA BRN 3 | Address Bus FFFF 1 Low Byte of Restart Vector BGE BLT BVC | BGT BMT BVS _ A _ oe BSR 6 1 Op Code Address 1 Op Code 2 | OpCode Address + 1 1 Branch Offset

3 Address Bus FF FF 1 Low Byte of Restart Vector

4 | Subroutine Starting Address 1 Op Code of Next Instruction

5 Stack Pointer 0 Return Address {Low Order Byte)

6 Stack Pointer —1 0 Return Address (High Order Byte}

= SUMMARY OF UNDEFINED INSTRUCTIONS OPERA- When the op codes (4E, SE) are used to execute, the MCU TION continues to increase the program counter and it will not stop The MCU has 36 undefined instructions. When these are until the Reset signal enters. These op codes are used to test the carried out, the contents of Register and Memory in MCU LSI change at random. Table 15 Op Codes Map HD6EPO1 MICROCOMPUTER INSTRUCTIONS oP ace [ACC wp | ext ACCA or SP [acca orx | CODE aj @ [iw [our [wo [ext [im foin [ino [ext o titz) 3 jets {ej7,;etotavtetetolete e000 [0 [> ——~"|sea [eral tsx NEG ; SUB [o] [oor | tesa en! ws | ome | Foo10 | (em puta en] “see [2] oon | 3 | [7 Ters [uve (+1)| com > 1 SUB0 (+2) * apop +2) [3 | aroo | 4 [7 [sec] pes | usr AND [4] 0101 | 5 |ASLDI+1) | | BCS] TXS —— _ BIT [5 | ano | 6 TAP [TAB |BNE| PSHA ROR LOA [e| 7000 | 8 | INK (+t). BVC [PULX 142) ASL { EOR [a] joor | 9 | DEXG1! [DAA __ ROL ‘ADC 9 [1010 | civ | Teec| Aex DEC ORA [A] [ion | SEV __|ABA] BMI ATI (+7) ——— ADO [e| [rior | SEC vA BLT} MUL (+7) TsT 8s JSR (+2) sen| ston ° fit | © cul | GT | wal (+6) - IMP (-3) 7) tos | toxan Te) [am | & set | [ate | swe i+9) CLR [se] sts (+t ats) [F] (NOTES) 1. Undefined Op codes are marked with [-—] 2. ( Sndicate that the number in parenthesis must be added to the cycle count for that instruction 3. The instructions shown below are all 3 bytes and are marked with “*”. Ieumadite addressing mode of SUBD. CPX. LOS, ADOD, LDD and LOX insteuctions, and undefined op codes (8F.CD, 4. The Op codes (4E, 5E) are 1 byte/= cycles instructions, and are marked with “**” ; @ HITACHI | Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 1101

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 © PRECAUTION TO USE EPROM ON THE PACKAGE 8.BIT 1 PRECAUTIONS SINGLE-CHIP MICROCOMPUTER * PRECAUTION CONCERNING COUNTER TIMER As this microcomputer takes a special packaging type with (1) Timer Output (P21) pin sockets on its surface, pay attention to the followings; After CPU reset, Py is uncertain until the value of the free (1) Do not apply higher electro-static voltage or serge voltage running counter equals the value of the output compare reg- etc. than maximum rating, or it may cause permanent ister or until the free running counter completes a software damage to the device time-out eycle (2) There are 28 pin sockets on its surface. When using 32k Q) Initialization of CF ICF should be cleared by software after initiating a reset, qt Let the index side four pins open otherwise ICF may be set if P21 is ““low” after initiating a n > When using 24 pin EPROM, match reset, do) aa miocken motor * PRECAUTION CONCERNING WRITE-ONLY REGISTER ot aay = The write-only register cannot be changed like DDR for I/O q a ae ports using Read/Modify/Write instructions. 42 °B (1) The CPU cannot read the write-only register. Procede with qo Read/Modify/Write instructions as follows: qa Bp (i) read the data of specified address; ae 2B (ii) modify the data; and qe oP (iii) write the modified data to original address. qe °B The Read/Modify/Write instructions cannot be used with the = ere write-only register like DDR. (2) Store instructions can be used for writing to the write-only Tegister. EPROM (24 pins), let the index-side four pins open. *Read/Modify/Write instructions NEG, COM, (3) When assembling this LSI into user's system products as LSR, ROR, well as the mask ROM type 8-bit single-chip microcompu- ASR. ASL ter, pay attention to the followings to keep the good ohmic ROL. DEC. contact between EPROM pins and pin sockets. » DEC, (a). When soldering on a printed circuit board, etc., keep its INC, TST condition under 250°C within 10 seconds. Over-time/ CLR temperature may cause the bonding solder of socket pins to meet and the sockets may drop. (b) Keep out detergent or coater from the pin sockets at aft-solder flux removal or board coating. The flux or coater may make pin socket contactivity worse (c) Avoid the permanent use of this LSI under the ever- vibratory place and system (d) Repeating insertion/removal of EPROMs may damage the contactivity of the pin sockets, so it is recommend- ed to assemble new ones to your system products. (4) In order to perform the normal operation at 1.25 MHz, it is recommended to use the EPROM whose access time is less than 300 ns. Ask our sales agent about anything unclear. @HITACHI 1104 Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

HD68P01V07, HD68P01V07-1, HD68P01M0, HD68P01M0-1 l§ PRECAUTION CONCERNING HD6801 SERIES SCI, TIMER STATUS FLAG Table 19 Status Flag Reset Conditions © Caution for the HD6801 Family SCI, TIMER Status Flag The flags shown in Table 19 are cleared by reading/writing (flag Status Flag Reset | Fiag Reset Condition 2 reset condition) the data register corresponding to each flag after Flag Condition 1 {Data Register) reading the status register (flag reset condition 1). (Status Register) To clear the flag correctly. use the following procedure: When each flag is ICR/Read 1. Read the status register TIMER a ‘OCR/Read 2. Test the flag TRCSR/Read TorRead 3. Read the data register When Each flag is ROR! The SCI, Timer status flag is cleared by reading a “1” for each status scl “a, Read flag and then reading the data register. SCI software routines should TRCSR/Read Faw read the received data after confirming a ‘*1” as the received status [ Tore [TT TORMWrite flag. Avoid reading dummy data after a “0” for the received status flag ° 9 TRCSR/Read 1 TRCSR/Read <<honr=1 > ROR Read ROR/Read << fons Y (a) Good Example (b) Bad Example Figure 29 Software polling of SCIL-RDAF @ TERMINAL CONDITION DURING RESET, AFTER RESET Table 20 Terminal Condition During Reset, After Reset —__CPU Mode po y iy 2 7] 3 [4 [5s J 6 J 7 pee fs f-|-t-=|=- [>= [=f = During FA i 7 a v0 T a 1 - + + « mi [obo te ee After ABLIDB ABLIDB z Ie) 1 ~ 2. - Se ew | - | = | = | 2 | ow oe 1: Input H : High Level DB: Data Bus ‘AS_: Address Strobe O — : Output L : Low Level ABL : Address Bus Low RAW : Read/Write vo InpuvOutput Z : High Impedance ABH : Address Bus High 10S : 105 Signal Upper : input Condition OSS : OSS Signal Lower : Level, Terminal Function : @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300 1105

Product Information

HD68P01 specifications and overview.

Summary

MCU(MICROCOMPUTER UNIT)

Description

MCU(MICROCOMPUTER UNIT)

Source title HD68P01 Datasheet(PDF) - Hitachi Semiconductor

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