HD6805V1

HD6805V1 HITACHI | Alldatasheet

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. . MCU (Microcomputer Unit) The HD680SV1 is the 8-bit Microcomputer Unit (MCU) 9 [ which contains a CPU, on-chip clock, ROM, RAM, I/O and HD6805V1P timer. It is designed for the user who needs an economical microcomputer with the proven capabilities of the HD6800- based instruction set The folléwing are some of the hardware and software high- | lights of the MCU @ HAROWARE FEATURES © B.Bit Architecture © 96 Bytes of RAM Ny © Memory Mapped 1/0 yt © 3848 Bytes of User ROM ayy © Internal 8-Bit Timer with 7-Bit Prescaler Q ye . © Vectored Interrupts — External and Timer h 1 © 24 1/0 Ports + 8 Input Port 1 {8 Lines LED Compatible; 7 Bits Comparator Inputs) @ On-Chip Clock Circuit @ Self-Check Mode © Master Reset (DP-40) © Low Voltage Inhibit a © Easy for System Development and Debugging © 5 Vdc Single Supply = SOFTWARE FEATURES © PIN ARRANGEMENT © Similar to HD6800 © Byte Efficient Instruction Set © Easy to Program @ True Bit Manipulation vss] O kd a) © Bit Test and Branch Instructions AES pa © Versatile Interrupt Function = Q] pa + © Powerful Indexed Addressing for Tables Vee] pa a © Full Set of Conditional Branches extac (a pa «> © Memory Usable as Registers/Flags xia Gl pa © Single Instruction Memory Examine/Change num pa a: @ 10 Powerful Addressing Modes rmen(g] pa ~ © All Addressing Modes Apply to ROM, RAM and 1/0 com pa © Compatible Instruction Set with MC6805P2 « ypesosv1 « @ pd & ® BLOCK DIAGRAM o pa & «eG Rg ® TAL extay REE NUM TNT. os [23 & o F3 a ., Ds (ia) pao se {Top View) lb Stave » I PROGRAM DEVELOPMENT SUPPORT TOOLS 8... © Cross assembler software for use with IBM PCs and P=] Ce] == compatibles [er _| Sem @ In circuit emulator for use with IBM PCs and | compatibles i | @uiTacut j Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. ® Brisbane, CA 94005-1819 « (415) 589-8300 1017

= ABSOLUTE MAXIMUM RATINGS item Unit Supply Voitage Veo" -0.3~ +7.0 Vv Input Voltage (EXCEPT TIMER) vet ~0.3~ +7.0 | Y _ Input Voltage (TIMER) _ -0.3~ +120 Vv Operating Temperature Top aL o~+70 __*e Storage Temperature Tog ~ 55 ~ +150 c * With respect to Vgg (SYSTEM GND} (NOTE) Permanent LSI damage may occur Hf maximum ratings are exceeded. Normal operation should be under recommended operating conditions, If these conditions are exceeded, it could affect reliabslity of LSI © ELECTRICAL CHARACTERISTICS © DC CHARACTERISTICS (Vcc=5.25V + 0.5V, Vss=GND, Ta=0~+70°C, unless otherwise noted.) Item Symbol | Test Condition | rnin [typ | max | Unit [aes | 40) = [Vcc] v Input “High” Voltage INT [3.0] = | vec} Vv a AnOther | Vin | 2.0) = [Vcc] v Timer Mod: v Input “High” Voltage (Timer) mer Sone. [2.0] = | Vee _ . U__| Self-Check Mode _ [9.0] — [110] v RES [Fos = Tost v INT Vv, v Input “Low” Voltage a | = | 08) |EXTAL (Crystal Mode) ee [= | o6l v Power Dissipation a Pp P= T= fr00 [mw Low Voltage Recover LVR _ | - | - |475) v Low Voltage Inhibit | = [40] - Tv [TIMER |-20 | = [20 | ua iNT Vn20.4V~V, Input Leak Current Lint he 190. ce [-s0 | — | 50 | wa XTALICrystal Mode)] [1200] — | 0 | uA © AC CHARACTERISTICS (Vcc=5.25V * 0.5V, Vss=GND, Ta=0 ~ +70°C, unless otherwise noted.) item [_symboi [Test Conaition [min [typ [max [Unie Clock Frequency ee —Syele Time - eye 1.0. ks Oscillation Frequency (External Resistor Mode) fexr | Rep=15.0k8241% = MHz nro Pep pet on ef eT cores Pe) ET - Oscattat ; C= 22pF #20%, Oscillation Start-up Time {Crystal Mode} tose | RS -600 mae 100 | ms Delay Time Reset Tane_| External Cap.=2.2ur | 100 |- | — | ms All Other [= | 10 | pF | @ HITACHI | 1018 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 « (415) 589-8300 i

@ PORT ELECTRICAL CHARACTERISTICS (Voc = 5.25V + O.5V, Vs = GND, Ta = 0 ~ +70°C, unless otherwise noted.) Port A [Ton ==t0wA [35 P= _ Non ==100u8 [2a [= | id Output “High” Voltage | Von lon = —200 vA 24 = - |v “lon = —1 mA 1s f= = tv Port C _ | low = —100 wa 24 = - vo Port A and C Llo=temA | - | - | 04 v Output “Low” Volt: v lor = 3.2mA = - o4 | ov utput "Low" Voltage | pot om fone mA ef —_| Vv _ lop=t0ma_ | = | 1.0 vi Input “High” Voltage | Port A,B,C, MH . 20 | - Vec v Input “Low” Voltage | and D* Vie 03 5 = 08 ve Vin = 0.8V 500 =] = uA Port A te et ++ : +p} Input Leak Current ie Vin = 2V 300 - - a, PortB,C, Ty coav vn, pe he Vin = 0.4V ~ Vi — 20 - 20 BA and D in oc Input “High” Voltage | Porto" Vv = |V7H+0.2 — v {Do ~ D6) 4 ° Low" Port D i Veu-o271 _ Threshold Voltage Port D(D7) Vin oO | — | 08xVce v * Port D as digital input ** Port D as analog input TTL Equiv. (Port B) TTL Equiv. (Port A and C) Vee Vec 42 3.2mMA S12kk 1,-1.6 mA $2.4k82 Test Point — Test Pont wen Vv, vy aopF S 12Ks2 ta00F Sans a (NOTE) 1. Load capacitance includes the floating capacitance of tt.e probe and the jig etc 2. All diodes are 152074@) or equivalent Figure 1 Bus Timing Test Loads ® SIGNAL DESCRIPTION The input and output signals for the MCU, shown in PIN @ TIMER ARRANGEMENT, are described in the following paragraphs. This pin allows an external input to be used to decrement © Voc and Vsg the internal timer circuitry. Refer to TIMER for additional Power is supplied to the MCU using these two pins. V¢¢- information about the timer circuitry. is +5.25V #0.5V. Vag is the ground connection. © INT . @ RES This pin provides the capability for asynchronously applying This pin allows resetting of the MCU at times other than an external interrupt to the MCU. Refer to INTERRUPTS for the automatic resetting capability already in the MCU. Refer additional information. to RESETS for additional information @ XTAL and EXTAL These pins provide connections for the on-chip clock circuit. @ NUM A crystal (AT cut, 4 MHz maximum), a resistor or an external This pin is not for user application and should be connected signal can be connected to these pins to provide a system clock _to Vss. with various stability/cost tradeoffs. Refer to INTERNAL OS- CILLATOR OPTIONS for recommendations about these inputs. @ HITACHI Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 « (415) 589-8300 1019

software control of the Data Direction Register (DDR). Refer to sters are pushed onto the stack in the order shown in Figure 3. for more details. be pushed onto the stack. Self test ROM locations can not be used for a user program. manufacturing mask for production.

3967 SFTF

4087 SFF7 a $o1F

4095 SFFF ** Read only register

Figure 2. MCU Memory Configuration

76643210 Puls r 5

• For subroutine calts, only PCH and PCL are stacked.

Figure 3. Interrupt Stacking Order Le

@ REGISTERS Interrupt (1) The CPU has five registers available to the programmer. This bit is set to mask the timer and external interrupt (INT). ‘They are shown in Figure 4 and are explained in the following _If an interrupt occurs while this bit is set it is latched and will be paragraphs. processed as soon as the interrupt bit is reset. © Accumulator (A) Negative (N) The accumulator is a general purpose 8-bit register used to Used to indicate that the result of the last arithmetic, logical hold operands and results of arithmetic calculations or data or data manipulation was negative (bit 7 in result equal to a manipulations. logical one). © Index Register (X) Zero (2) The index register is an 8-it register used for the indexed Used to indicate that the result of the last arithmetic, logical addressing mode. It contains an 8-bit address that may be added —_ or data manipulation was zero. to an offset ‘value to create an effective address. The index Carry/Borrow (C) register can also be used for limited calculations and data Used to indicate that a carry or borrow out of the arithmetic manipulations when using read/modify/write instructions. When _ogic unit (ALU) occurred during the last arithmetic operation. not required by a code sequence being executed, the index This bit is also affected during bit test and branch instructions, register can be used as a temporary storage area. shifts, and rotates. @ Program Counter (PC) The program counter is a 12-bit register that contains the # TIMER address of the next instruction to be executed. The MCU timer circuitry is shown in Figure 5. The 8-bit @ Stack Pointer (SP) counter, the Timer Data Register (TDR), is loaded under pro- ‘The stack pointer is a 12-bit register that contains the address gram control and counts down toward zero as soon as the clock of the next free location on the stack. Initially, the stack point- input is applied, When the timer reaches zero, the timer inter- er is set to location $07F and is decremented as data is being rupt request bit (bit 7) in the Timer Control Register (TCR) is pushed onto the stack and incremented as data is being pulled set. The CPU responds to this interrupt by saving the present from the stack. The six most significant bits of the stack pointer CPU state on the stack, fetching the timer interrupt vector from are permanently set to 0000011. During an MCU reset or the locations $FF8 and $FF9 and executing the interrupt routine. reset stack pointer (RSP) instruction, the stack pointer is set The timer interrupt can be masked by setting the timer inter- to location $07F, Subroutines and interrupts may be nested rupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the down to location $061 which allows the programmer to use up Condition Code Register also prevents a timer interrupt from to 15 levels of subroutine calls. being processed. © Condition Code Register (CC) The clock input to the timer can be from an external source The condition code register is a 5-bit register in which each applied to the TIMER input pin or it can be the internal $2 bit is used to indicate or flag the results of the instruction just signal. When the internal ¢2 signal is selected as the input executed, These bits can be individually tested by a program source, the node a is connected to b (see Fig. 5). In case of the and specific action taken as a result of their state, Each indi external source, the node b connects with c. When the ¢, signal vidual condition code register bit is explained in the following _is used as the source, the clock signal is input to the prescaler paragraphs. while the TIMER input is “High”. The source of the clock input Half Carry (H) is one of the options that has to be specified before manufac- Used during arithmetic operations (ADD and ADC) to ture of the MCU. A prescaler option can be applied to the clock indicate that a carry occurred between bits 3 and 4. input that extends the timing interval up to a maximum of 128 ¢ me taped [ole eee 2 TIR: Timer Interrupt Request rhe seed- ddd to TIM: Timer Interrupt Mask Timer H H Input ‘ , Pin ip---4-4-4-4-4--}-}-4 TIR TIM sees Clock a ' A 881 Counter td Tier Data Regier (TOR) Manufacturing Mask Options i | \\ vite fled Write Read | Figure § Timer Block Diagram | @HITACHI i Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300 1021

counts before decrementing the counter (TDR). The timer con- © SELF CHECK tinues to count past zero, falling through to $FF from zero and The self-check capability of the MCU provides an internal then continuing the count. Thus, the counter (TDR) can be read check to determine if the part is functional. Connect the MCU at any time by reading the TDR. This allows a program to deter-_as shown in Figure 6 and monitor the output of port C bit 3 for mine the length of time since a timer interrupt has occurred and an. oscillation of approximately 3Hz. ROM. RAM, TIMER, not disturb the counting process. Interrupts, 1/0 of Port A, B and C are checked by this capabil- The TDR is 8-bit Read/Write Register in location $008, ity. At power-up or reset, the TDR and the prescaler are initialized = RESETS with all logical ones, The MCU can be reset three ways; by initial power-up, by The Timer Interrupt Request bit (bit 7 of the TCR) is set by the external reset input (RES) and by an optional internal hardware when timer count reaches zero, and is cleared by pro- low voltage inhibit circuit, see Figure 7. All the 1/O port are gram or by hardware reset. The bit 6 of the TCR is writable by initialized to input mode (DDRs are cleared) during reset program. Both of those bits can be read by CPU. During power-up, a minimum of 100 milliseconds is needed (NOTE) If the MCU Timer is not used, the TIMER input pin _ before allowing the RES input to go “High”. must be grounded. ‘This time allows the internal crystal oscillator to stabilize. Connecting a capacitor to the RES input, as shown in Figure 8, typically provides sufficient delay.

3 J int A140

A,|39 2 |aes al 2.2uF AY | A, [| S]extac alae _| ata] HO6BO5VI 22% ____B J TIME ipesistar option! 8.| 92

7 NUM 8, [|

Vee e[ao [| S08 ey. afae | | ti Pe ey le, a [2s ear Sp) t2ic 8} 25. oi Ska 3}, Ska. 15] ¢, A——— 18} e, a tbe Veo * Pind * Reter 10 Figure 9 about crystal option Veg * Pint Figure 6 Self Check Connections ov | “Dip” inPower| RES Pin | T Vin RES | te pe : on lateral es Reset Figure 7 Power Up and RES Timing i @HITACHI 1022 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

2 The internal oscillator circuit is designed to require a mini-

MCU shown in Figure 9. Crystal specifications are given in Figure 10. A resistor selection graph is given in Figure 11. Figure 11. Typical Resistor Selection Graph

= INTERRUPTS outputs, Port A is CMOS compatible as outputs, and Port B and The CPU can be interrupted three different ways: through _C lines are CMOS compatible as inputs. Figure 14 provides some the external interrupt (INT) input pin, the internal timer inter- examples of port connections. rupt request, and a software interrupt instruction (SWI). When any interrupt occurs, processing is suspended, the present CPU © INPUT state is pushed onto the stack, the interrupt bit (1) in the Condi- Port D can be used as either 8 TTL compatible inputs or 1 tion Code Register is set, the address of the interrupt routine is threshold input and 7 analog inputs pins. Fig. 15 (2) shows the obtained from the appropriate interrupt vector address, and the construction of port D. The Port D register at location $003 interrupt routine is executed. Stacking the CPU registers, setting stores TTL compatible inputs, and those in location $007 store the I bit, and vector fetching requires 11 cycles. The Interrupt the result of comparison Do to Ds inputs with D7 threshold service routines normally end with a return from interrupt input. Port D has not only the conventional function as inputs (RTI) instruction which allows the CPU to resume processing of but also voltage-comparison function. Applying the latter, can the program prior to the interrupt. Table 1 provides a listing of easily check that 7 analog input electric potential max. exceeds the interrupts, their priority, and the vector address that contain the limit with the construction shown in Fig. 15 (b). Also, using the starting address of the appropriate interrupt routine. one output pin of MCU, after external capacity is discharged A flowchart of the interrupt processing sequence is given- at the preset state, charge the CR circuit of long enough time in Fig. 12. constant, apply the charging curve to the D7 pin. The construc- tion described above is shown in Fig. 15 (c). The compared Table 1 Interrupt Priorities result of Do to De is regularly monitored, which gives the analog input electric potential applied to Do to De pins from Interrupt Priority Vector Address _ inverted time. This method enables 7 inputs to be converted aS 7 $FFE and SFFF from analog to digital. Furthermore, combination of two func- — — RW eEED tions gives 3 level voltages from Do to Ds. Fig. 15 (d) provides Swi 2 _SFEC and $FFD the example when Vy is set to 3,5V. INT 3 SFFA and SFFB TIMER 4 $FFB and $FF9 = BIT MANIPULATION | INPUT/OUTPUT The MCU has the ability to set or clear any single random There are 24 input/output pins. All pins are programmable access memory or input/output bit (except the data direction as either inputs or outputs under software control of the cor- registers) with a single instruction (BSET, BCLR). Any bit in responding Data Direction Register (DDR). When programmed the page zero read only memory can be tested, using the BRSET as outputs, the latched output data is readable as input data, and BRCLR instructions, and the program branches as a result regardless of the logic levels at the output pin due to output of its state. This capability to work with any bit in RAM, ROM loading (see Fig. 13). When Port B is programmed for outputs or 1/O allows the user to have individual flags in RAM or to it is capable of sinking 10mA on each pin (VoL = IV max). handle single 1/O bits as control lines. The example in Figure 16 All input/output lines are TTL compatible as both inputs and illustrates the usefulness of the bit manipulation and test MOS} : ve Te : a, | mAL Load 8, R, A, i Port A Programmed as outputs), driving CMOS and TTL Load directly. Port B Programmed as outputs), driving Darlington base directly. (ad (bo) w w R a 8, 1 © : @z— : Port B H Port C 3 CMOS Inverter : 1OmA max : 8, c, Port B Programmed as outputs), driving LED(s) directly. Port C Programmed as output(s), driving CMOS loads, using external pull-up (ed resistors. (db Figure 14 Typical Port Connections @HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300 1025

instructions, Assume that bit 0 of port A is connected toa zero _vides turn-on of the TRIAC within 14 microseconds of the zero crossing detector circuit and that bit } of port A is connected to crossing. The timer could also be incorporated to provide turn- the trigger of a TRIAC which power the controlled hardware. on at some later time which would permit pulse-width modila- This program, which uses only seven ROM locations, pro- _tion of the controlled power. $003 eed Input Port Internal Bus <| OD '20~s) (Bito ~ Bité) $007 Read + $003 Read Input Port (D>) Internal Bus O (Bit 7) (a) The logic configuration of Port D 7 ° =| : Control Pulse LA ‘Analog Input 6 D, o, Cy | rot \\ Analog Input 6 ae D De D, a < Analog Input 0 Analog input 0 (b) Seven analog inputs and a reference level input of Port 0 (c} Application to A/D convertor Vin (= 3.5V) Ds 3 Levels Input 6 Ee eu | ($003) ($007) ov~osv | o fo “20V~ 3.3 1 ° 3.7V ~ Veco 1 i] 1 i

3 Levels Input 0

(a) Application to 3 levels input Figure 15 Configuration and Application of Port D | @HITACHI 1026 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-8300

© Bit Set/Clear : Refer to Figure 24. This mode of addressing applies to : instructions which can set or clear any bit on page zero. The $ lower three bits in the opcode specify the bit to be set or SELF1 BRCLA 0, PORT ASELF 1 cleared while the byte following the opcode specifies the BSET 1, PORTA address in page zero. BCLA 1,PORTA © Bit Test and Branch : Refer to Figure 25. This mode of addressing applies to : instructions which can test any bit in the first 256 locations : (S00-SFF) and branch to any location relative to the PC. The : byte to be tested is addressed by the byte following the opcode. Figure 16 Bit Manipulation Example The individual bit within that byte to be tested is addressed by the lower three bits of the opcode. The third byte is the relative = ADDRESSING MODES address to be added to the program counter if the branch condi- The CPU has ten addressing modes available for use by the tion is met. These instructions are three bytes long. The value of programmer. They are explained and illustrated briefly in the the bit tested is written to the carry bit in the condition code following paragraphs. register. © Immediate © Implied Refer to Figure 17. The immediate addressing mode accesses Refer to Figure 26. The implied mode of addressing has no constants which do not change during program execution. Such EA. All the information necessary to execute an instruction is instructions are two bytes long. The effective address (EA) is contained in the opcode. Direct operations on the accumulator the PC and the operand is fetched from the byte following the and the index register are included in this mode of addressing. opcode. In addition, control instructions such as SWI, RTI belong to this © Direct group. All implied addressing instructions are one byte long Refer to Figure 18. In direct addressing, the address of the operand is contained in the second byte of the instruction. ® INSTRUCTION SET Direct addressing allows the user to directly address the lowest The MCU has a set of 59 basic instructions. They can be 256 bytes in memory. All RAM space, 1/O registers and 128 divided into five different types: register/memory, read/modify/ bytes of ROM are located in page zero to take advantage of this write, branch, bit manipulation, and control. The following efficient memory addressing mode paragraphs briefly explain each type. Alll the instructions within © Extended a given type are presented in individual tables. Refer to Figure 19. Extended addressing is used to reference @ Register/Memory Instructions any location in memory space. The EA is the contents of the Most of these instructions use two operands. One operand is two bytes following the opcode. Extended addressing instruc- either the accumulator or the index register. The other operand tions are three bytes long. is obtained from memory using one of the addressing modes. © Relative The jump unconditional (JMP) and jump to subroutine (JSR) Refer to Figure 20. The relative addressing mode applies only _ instructions have no register operand. Refer to Table 2. to the branch instructions. In this mode the contents of the © Read/Modity/Write Instructions byte following the opcode is added to the program counter ‘These instructions read a memory location or a register, when the branch is taken. EA=(PC)+2+Rel. Rel is the contents modify or test its contents, and write the modified value back of the location following the instruction opcode with bit 7 to memory or to the register. The test for negative or zero being the sign bit. if the branch is not taken Rel=0, when a (TST) instruction is an exception to the read/modify/write branch takes place, the program goes to somewhere within the instructions since it does not perform the write. Refer to Table range of +129 bytes to -127 of the present instruction. These 3 instructions are two bytes long. @ Branch Instructions @ Indexed (No Offset) The branch instructions cause a branch from the program Refer to Figure 2!. This mode of addressing accesses the when a certain condition is met. Refer to Table 4. lowest 256 bytes of memory. These instructions are one byte © Bit Manipulation Instructions long and their EA is the contents of the index register. These instructions are used on any bit in the first 256 bytes © Indexed (8-bit Offset) of the memory. One group either sets or clears. The other group Refer to Figure 22. The EA is calculated by adding the performs the bit test and branch operations. Refer to Table 5. contents of the byte following the opcode to the contents of © Control instructions the index register. In this mode, 511 low memory locations are The control instructions control the MCU operations during accessable. These instructions occupy two bytes. program execution, Refer to Table 6. © Indexed (16-bit Offset) © Alphabetical Listing Refer to Figure 23. This addressing mode calculates the EA The complete instruction set is given in alphabetical order in by adding the contents of the two bytes following the opcode Table 7. to the index register. Thus, the entire memory space may be @ Opcode Map accessed, Instructions which use this addressing mode are three Table 8 is an opcode map for the instructions used on the bytes long. MCU. @HITACHI Hitachi America, Ltd. # Hitachi Piaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 1027

rr | ‘ '

2 Index Reg

' Co TO) PROG BRCLR 2.PORTC. PROG 2 0574 [os Ss Prog Count ee Ce ae Figure 25 Bit Test and Branch Addressing Example EA Memory Cd o_O ' ' t ' = <A = ine ah Cs] t , Stack Point — wr Goon a ce ’ ' i ' Co) ' ' ‘ ' | Figure 26 Implied Addressing Example | @HITACHI | 1032 Hitachi America, Ltd. Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

Table 2. Register/Memory Instructions with A “ OR bade ied [sf] | . Function Mnemonic | Implied (A) Implied (XI Dvect neon eurome .

Table 4 Branch Instructions a Relative Addressing Mode Code Bytes Cycles Branch Always TY a 4 Branch Never 1 a __Branch 1F Higher Es eC eS Branch IF Lower or Same {pis | __Branch IF Carry Clear BCC a 4 {Branch IF Higher or Same) ee en 4 ich wr a “(Branch IF Lower) (BLO) ee ee | 4 Branch IF Not Equal [ene] SCS 2 4 aan Ea a 4 Branch IF Half Carry Clear BHCC [2 [| 2 | 4 Branch IF Half Carry Set BHCS ee ee | 4 Branch IF Plus ~_ BPL [#3 4 _ Branch IF Minus _ BMI 4 Branch IF Interrupt Mask Bit is Clear BMC a 4 “Branch IF interrupt Mask Bit is Set ____BMS ao [| 2 | 4 Branch IF Interrupt Line is Low BIL zw | 2 ~~ ~'#/ 4 Branch IF Interrupt Line is High BIH ee ee | 4 Tabie 5 Bit Manipulation Instructions _ Addressing Modes Function Mnemonic Bit Set/Clear Bit Test and Branch i Code | Bytes | Cycles Code | Bytes | Cycles Branch IF Bit nis set BRSETn(n=0...7) | — | - | [an [3 [ 10 Set Bit BSETa (n=0....7) | 10420 f - [ - Table 6 Control Instructions Implied Function ¥ — # Code Bytes Cycles Transfer A to X TAX a 2 Transfer X to A ~ TXA fa 2 Clear Carry Bit CLC 98 1 [2 ‘ Set Interrupt Mask Bit SEI 98 1 2 Clear Interrupt Mask Bit 1 2 Software Interrupt Ee Return from Interrupt RTI fe | 7? | 9 Reset Stack Pointer Z RSP ee | 2 t | @ HITACHI! | 1034 Hitachi America, Ltd, « Hitachi Plaza « 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

Addressing Modes. Condition Code op - Mnemonic Indexed Bit | Bit | imme- |} Ex. | Re: Indexed | Indexed Implied giate | PEt | tended | lative | gin®s, | (8 Bits) | (16 Bits) S| gene Ht alnlele Abe | xf ek |x ee ee Ate TATata’ ADD | de x jx joj * 4 * x — ALP ALALA “ano | | x | x | x | x x [x le felatale cas fe | ep — fe tetayata WASRO | ie es es le le lLALAIA BCC x | | ele ° sear tO TT x “Tele e ces ff __le [ele [e fe seo ff ttf — olelete fe BHCC ff en 4+——}— fh elejejele —BHCS —j ee ee Se -—_jel|e ie BHI a T : : elele tre - BHS —_ _ ~ x i i I - ni ele ei ele BI { Lx + i eiele e BIL lx _ | eleleiele BIT x x Tl oK xe tox | ox te elelAcAle ~eL0. ne elelelele re je ee tT felefe rele BMC L Lx eleletele sme | Se Gap es eee ee - sie | ~ aM a Tobe To an oleletele ems | x i lelelelele a aE EEE "Onn en GO — BNE { _ a pre 4 i _ ejereleie BPL Te i Pox | - | clelelele “ea | [ete fe fete i [ve fete de Ts BRCLR i 4 [od | = - aos ete A Toy . | | ! A ___BRSET Se ee ee eee eee lox te leTe To] BSET i Lox elelelele ~ an a 4 feta eee it ;. = ee on ee noes : cA i x a xT eteloli te cue | i ee ee ee ne elelalala com | x x a [x x | f | ojeTa Alt ~{- j— | ee a eS Md A A cex | x x x Tx x “|e Z elelAlala DEC ~4 fx Di x L [ele [A |* __ £OR [x x |x [x x x ele ° “we Dox po x x tT ele ° “Imp [ x [x 7 ee a ee ole feleje “Jk ti<‘iti(ti‘a te ix x x | | Te lelelele aR en +2 a EDA pate pS fp mo se AA te LDX i x x i x x x x | elelalale Condition Code Symbols: coc a {to be continued) if Carey (From Bit 3 Wry Borrow y lmencpe Mae J Festand Set'st True, Cleared Otherwise N Negative (Sign it) © Not Altected 2 deo @ HITACHI Hitachi America, Ltd. » Hitachi Plaza 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 1035

Addressing Modes Condition Code | . | Indexed Bit Bit imme: Re- Indexed | Indexed use| x ee ee pT Te To TaTata usr x x {+—+-—+-+- pt Te Te To fata NEG x = a poe Te tatqata NOP x + eS ° ora | a . Rou | ee ee ee [fe fe fatata non |x 5 =a ee CUCUCSESGS a i |e [eTeTeTe aT! ae ee ee RTS i ft ° sec.) x | [| T | 1 es eee eee STA px | ° sx | —— a ee ears ° sua ex | [x | [ATATA sw | x [ ee oe eC ° tax | x | a ee ee male TT PT [sole le Condition Code Symbols: H Half Carry (From Bit 3) C Carry/Borrow

1 Interrupt Mask /\\_ Test and Set if True, Cleared Otherwise

N Negative (Sign Bit) ° Not Affected 2 2er0 3 Load CC Register From Stack @ HITACHI 1036 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 i i

a HD6805V1 AN Table 8 Opcode Map [Bit Maniputetion [Branch] _Reed/Modity rite Repister/Memory rte [we low [= [=f [oo | o | wlan] on [on peta pets pe tr ts te tstetetofete om T[eRseTo [seTo [eRa | —__ wes Cart ——] n tfercuro[ecuno| enn | = [ars] - | 1 zfensers [aseTs [en | = [ -_ | 2 5 [BRCLA2 | BcLR2 | Bcs | = BIT 5 Ww 7 saacpne | Bel [seo | ASR te = STAG 7 8 [BRSETS __ USL/ASL. [- lec | EOR 8

9 Bcurs | excs | ROL ADC 9

A BseTS | BPL OEC cu | ORA A ¢c asete | amc Inc | -_ [ase | - | IMP(=1) c ~p/eactas [ecure | ems | Ist . [ — [wor [esr] JSR(+3) . _£ = 7 - |=] LOX E F acun7 [ein] cur a ee ee {NOTE} 1. Undefined opcodes are marked with "—". 3, The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycies). Mnemonics followed by 2 "*"" require a different number of cycles as follows: ms 8 swe 1 BSR 8 3. ( ) indicate that the number in parenthesis must be added to the cycle count for that instruction. @HITACHI Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 1037