HD66781

HD66781 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 196

Technical content

Rev. 0.5, July.31.2003, page 1 of 196 Preliminary HD66781 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM REJxxxxxxx-xxxxZ Rev.0.5 July.31.2003

• Index

Rev.0.5, July.31.2003, page 2 of 196

Rev.0.5, July.31.2003, page 3 of 196

Rev.0.5, July.31.2003, page 4 of 196

Rev.0.5, July.31.2003, page 5 of 196

Rev.0.5, July.31.2003, page 6 of 196

Description

The HD66781 is a 720-channel source driver with graphics acceleration function, incorporating RAM compliant to 262,144 TFT colors and 240RGB x 320 dot graphics. In combination with the HD66783, which incorporates a power-supply integrated circuit and a gate driver on a single chip, the HD66781 can drive an a-Si TFT panel of 240 RGB x 320 dots at maximum. Also in combination with the HD667P21, which is a power-supply IC chip, the HD66781 can drive a low-temperature poly-Si TFT panel of 240 RGB x 320 dots at maximum with an incorporated gate driver. The HD66781’s high-speed RAM-write function through a high-speed interface of 8/9/16/18-bit bus enables efficient data transfer with high-speed burst RAM write function. The HD66781 is compliant to DMA transfer single address mode to keep control on bus traffic occupation when a large volume of data is transferred from external memory. The HD66781 can also handle moving picture display through an RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, and PD 17 to 0). The HD66781 incorporates RAM with the capacity of one QVGA-sized whole screen of 240 RGB x 320 x 18bits plus 96 raster-rows. In addition to OSD and α blending functions, which use this RAM area, the HD66781 also handles resizing function, which is compliant to data transfer for a large screen display. These functions make the HD66781 the best solution for the efficient and various ways of display. The combined use of HD66781 with HD66783 or HD667P21 supports the function to reduce power consumption by a liquid crystal display system. The HD66781’s RAM can display 240 RGB x 320-dot color display (max.) with low voltage operation up to 1.7 V. The HD66781 incorporates a voltage follower circuit to generate liquid crystal driving voltages and an interfacing circuit that enables through HD66781 to make instruction settings to HD66783 and HD667P21. In addition, the HD66781 supports power-saving modes such as standby mode and 8-color display mode, which allow precise power management by software. These features make this LSI the ideal solution for medium or small-sized portable battery- driven products such as digital cellular phones or small PDA with color displays, where long battery life and board size are a major concern.

Rev.0.5, July.31.2003, page 7 of 196

Features

• Drive 262,144 TFT-color 240RGB x 320 dot graphics display in combination with HD66783 (a-Si TFT panel) or HD667P21 (low-temperature poly-Si TFT panel)
• Output signals to control HD66783, which incorporates a power supply integrated circuit and a gate driver on a single chip.
• Output signals to control a low-temperature poly-Si TFT panel with an incorporated gate driver (combined use with HD667P21)
• System interface – High-speed bus interface with 8-/9-/16-/18-bit data bus – Serial Peripheral Interface (SPI)
• Interfaces for moving picture display – RGB interface with 6-/16-/18-bit data bus (VSYNC, HSYNC, DOTCLK, ENABLE, PD17-0) – VSYNC interface (System interface + VSYNC)
• High-speed burst RAM write function
• Compliant to single address mode for DMA transfer that controls data bus occupation ratio when transferring data from external SRAM
• Window address function to write data to a rectangular area of RAM specified by the window address – Interfaces for moving picture display, which write data to a rectangular RAM address area – Reduce data transfer by transferring only the data for the moving picture display area – Simultaneous display of moving picture area and still picture area that displays the contents of internal RAM – Resizing function (contraction rate: x1/2, x1/4 / magnification rate: x2, x4)
• Various functions to control color display – Simultaneous availability of 262,144 colors (settings are programmable) – Partial OSD function – α-blending function (transmission rate: 0%, 25%, 50%, 75%, 100%)
• Features for low-power architecture – Interface I/O power supply IOVcc = 1.7 ~ 3.3 V Vcc1 = 1.7 ~ 3.3 V – Logic regulator power supply Vcc = 2.5 ~ 3.3 V – Source driver liquid crystal driving voltage DDVDH-GND = 4.0 ~ 5.9 V – Power saving functions: standby mode, deep standby mode etc. – Step-up circuits to generate liquid crystal drive voltage up to 12 times (HD66783 and HD667P21) – Voltage followers for a liquid crystal drive power-supply, which fends off the direct current from bleeder-resistors
• Cst structure only (Common Vcom formula)
• 224,640-byte (240 x (320+96) x 18bits) internal RAM
• Incorporated LCD driver with 720 source outputs
• Compliant to COG

Rev.0.5, July.31.2003, page 8 of 196 Block Diagram Index register (IR) Control register (CR) External Display Interface VSYNC HSYNC DOTCLK ENABLE PD17-0 CPG Address counter Timing generating circuit System Interface 18 bit 16 bit 9 bit 8 bit SPI Graphic RAM (GRAM) 224,640 bytes Latch circuit M alternation Source line drive circuit γ control circuit BGR Circuit CS* Write data latch Read data latch S1-720 RGND IM3~1,IM0/ID V63~0 GND AGND RS WR/SCL RD* DB0/SDI DB1/SD0 DB2~17 VSYNC HSYNC DOTCLK ENABLE PD0~ RESET* OSC2 OSC1 18 18 Latch circuit Latch circuit VTEST V0P V0N V63P V63N Grayscale circuit VGS VMON Regulator Vcc VDDTEST VREFD DACK* IOVcc RESETO OSC3 TCS VDD Power-supply IC/ gate driver interface (serial) GCS* GCL GDA Internal referene voltage generation circuit VREFC1 VREFC2 VRTEST VREF TS8-0 TEST1 TEST2 PMON DDVDH VDH FLM SFTCLK1/CL1 SFTCLK2 DISPTMG M EQ DCLK BST VcomVcc1

Rev.0.5, July.31.2003, page 9 of 196 Pin Functions Signals Number of Pins I/O Connected to Functions Unused pins Pins to select an interfacing mode with MPU. IM3 IM2 IM1 IM0 MPU-Interface Mode DB Pins Colors 0 0 0 0 Setting disabled - - 0 0 0 1 Setting disabled - - 0 0 1 0 80-system 16-bit interface DB17-10, DB8-1 65,536 Note 1) 0 0 1 1 80-system 8-bit interface (Big-endian) DB17-10 65,536 Note 2) 0 1 0 * Serial peripheral interface (SPI) DB1-0 65,536 - 0 1 1 0 Setting disabled - - 0 1 1 1 80-system 8-bit interface (Little-endian) DB17-10 65,536 Note 2) 1 0 0 0 Setting disabled - - 1 0 0 1 Setting disabled - - 1 0 1 0 80-system 18-bit interface DB17-10 262,144 1 0 1 1 80-system 9-bit interface DB17-9 262,144 1 1 * * Setting disabled - - IM3~1, IM0/ID

4 I GND or

Note 1) 262,144 colors available (max.) in 2-transfer mode. Note 2) 262,144 colors available (max.) in 3-transfer mode. CS* 1 I MPU Select the HD66781. Low: the HD66781 is selected and is accessible High: the HD66781 is not selected and is inaccessible IOVcc RS 1 I MPU Select the register. Low: Index/status registers High: Control registers IOVcc WR*/SCL 1 I MPU Write strobe signal in the 80-system bus interface Write data at the “Low” level. In the Serial Peripheral Interface, a synchronizing clock signal. RD* 1 I MPU Read-strobe signal in the 80-system bus interface Read data at the “Low” level. IOVcc DACK* 1 I MPU Select the HD66781 in the DMA transfer single address mode. Low: Select the HD66781 (Accessible) High: Not Select the HD66781 (Inaccessible) Vcc1 DB0/SDI 1 I/O MPU 18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Serial data input pin (SDI) in the Serial Peripheral Interface mode to input data on the rising edge of SCL signal. IOVcc

Rev.0.5, July.31.2003, page 10 of 196 Signals Number of Pins I/O Connected to Functions Unused pins DB1/SDO 1 I/O MPU 18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Serial data output pin (SDO) in the Serial Peripheral Interface mode to output data on the falling edge of SCL signal. IOVcc DB2~DB17 16 I/O MPU 18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 IOVcc RESET* 1 I MPU or external R-C circuit Reset pin. Initialize the LSI at the “Low” level. A power-on reset required after turning on the power. - RESETO1 RESETO2

2 O HD66783 or

Output the same polarity level as RESET*. Control both HD66781 and HD66783 or HD66781 and HD667P21 by connecting to HD66783 or HD667P21. Open OSC1 OSC2

2 I or

O Oscillation resistor Connect an external resistor for R-C oscillation. ENABLE 1 I MPU or LCDC Data enable signal in the RGB interface mode. Low: Select (accessible) High: Not select (inaccessible) ENABLE signal inverts the polarity according to the setting of EPL resister. Set ENABLE inactive while it is not used and its level is fixed or the polarity is set with registers. GND/ IOVcc VSYNC 1 I MPU or LCDC Frame synchronizing signal. This signal is active low. The polarity of VSYNC is inverted by setting VSPL register. Set VSYNC inactive while it is not used and its level is fixed or the polarity is set with registers. GND/ IOVcc HSYNC 1 I MPU or LCDC Line synchronizing signal. This signal is active low. The polarity of HSYNC is inverted by setting HSPL register. Set HSYNC inactive while it is not used and its level is fixed or the polarity is set with registers. GND/ IOVcc DOTCLK 1 I MPU or LCDC Dot clock signal. The timing of data input is determined at the rising edge. This signal is active low. The polarity of DOTCLK is inverted by setting DPL register. Set DOTCLK inactive while it is not used and its level is fixed or the polarity is set with registers. GND/ IOVcc PD0~PD17 18 I MPU or LCDC 18-bit bus for RGB data. 6-bit bus: PD17-PD12 16-bit bus: PD17-PD13 and PD11-PD1 18-bit bus: PD17-PD0 GND/ IOVcc

Rev.0.5, July.31.2003, page 11 of 196 Signals Number of Pins I/O Connected to Functions Unused pins BST 1 O MPU or LCDC Output a pulse that indicates the start of blank (front porch). When writing data in synchronization with display scan, serve as a trigger signal. Amplitude: Vcc1 and GND. Open S1~S720 720 O Liquid Crystal Output a voltage applied to liquid crystal. The correspondence between the RAM write address and source output signal is changeable with SS bit. When SS=0, data in the RAM address “h00000” are output from S1-3. When SS=1, data in the RAM address “h00000” are output from S718-720. and S3, S6, S9, ... display blue (B) (SS = 0). Open FLM1 FLM2 Output a frame head pulse. Open CL11/ SFTCLK11 CL12/ SFTCLK12 Output a different signal according to the LTPS register setting. LTPS=0: Output a pulse of one line cycle. Connect to CL1 pin of HD66783. LTPS=1: Gate shift clock for LTPS. Output a pulse of 2-line cycles. Open SFTCLK21 SFTCLK22 2 O HD667P21 Output a different signal a ccording to the LTPS register setting. LTPS=0: Output is GND. No connection with HD66783 is required. LTPS=1: Gate shift clock for LTPS. Output a pulse of 2-line cycles. Open DISPTMG1 DISPTMG2 Gate off signal during partial display. Low: Voff output High: Normal output For an LTPS LCD panel, a control signal for the gate driver incorporated therein. Open Output alternating pulse. Open EQ1 EQ2 Make Vcom output Hi-z in Vcom transition timing during Vcom alternating drive. Low: Output VcomH or VcomL from Vcom High: Make Vcom output Hi-z Open DCCLK1 DCCLK2 Output step-up clocks. Open GCL1 GCL2 Clock signal for making a serial transfer of values set in registers to gate driver/power supply IC. Output data from the falling edge of the clock. Open GDA1 GDA2 Data signal for making a serial transfer of values set in registers to gate driver/power supply IC. Open GCS1* GCS2* Select the HD66781. Low: Select the HD66781 (Serial transfer) High: Not select the HD66781 (Serial transfer not available) Open

Rev.0.5, July.31.2003, page 12 of 196 Signals Number of Pins I/O Connected to Functions Unused pins GND 1 Power supply Ground for the logic side. GND = 0V When assembled on COG, connect to GND on the FPC to avoid effects from the noise. AGND 1 Power supply Ground for the I/O side and analogue circuits other than logic circuits and the internal GRAM, which operate with VDD voltage. AGND = 0V When assembled on COG, connect to GND on the FPC to avoid effects from the noise. RGND 1 Power supply Ground for the internal RAM. RGND = 0V. When assembled on COG, connect to GND on the FPC to avoid effects from the noise. IOVcc 1 Power supply Supply with the power supply voltage for interface pins. IOVcc = 1.7~3.3V. IOVcc ≤ Vcc1 ≤ Vcc Vcc 1 I Power supply Power supply for internal logic regulator. Connect to an external power supply of Vcc = 2.5~3.3V. IOVcc ≤ Vcc1 ≤ Vcc Vcc1 1 I Power supply Power supply voltage for a deep standby control circuit and the I/O side. IOVcc ≤ Vcc1 ≤ Vcc VREF 1 O Power supply Reference voltage output for internal logic regulator. Leave open. Open VDD 1 I/O Stabilizing Capacitor Power supply output for an internal logic. Do not connect to other than stabilizing capacitors. - DDVDH 1 I HD66783 or HD667P21 Supply with a liquid crystal drive voltage through HD66783 or HD667P21. DDVDH = +4.0V~+5.9V VDH 1 I HD66783 or HD667P21 A reference level for a grayscale voltage generation circuit. Can be supplied through HD66783 or HD667P21. - VGS 1 I GND or External Resistor A reference level for a grayscale voltage generation circuit. Connect to an external variable resistor to make a level adjustment for each panel. Vcom 1 I HD66783 or HD667P21 Signal for equalization. Short-circuit all liquid crystal output (S1~S720) to Vcom level (Hi-z) while EQ = High. Leave open when Vcom < 0V. Open TEST1 TEST2 2 I GND Test pins. Must be fixed to the GND level. - TSC 1 I GND Test pin. Must be fixed to the GND level. - OSC3 1 O Open Test pin. Leave open. Open TS8-0 9 O Open Test pins. Leave open. Open VTEST 1 O Open Test pin. Leave open. Open VRTEST 1 O Open Test pin. Leave open. Open VREFC1 VREFC2 2 I GND Test pins. Must be fixed to GND level. -

Rev.0.5, July.31.2003, page 13 of 196 Signals Number of Pins I/O Connected to Functions Unused pins VDDTEST 1 I GND Test pin. Mu st be fixed to GND level. - VREFD 1 O Open Test pin. Leave open. Open PMON 1 O Open Test pin. Leave open. Open VMON 1 O Open Test pin. Leave open. Open V0P V63P 2 I or O Open Test pins. Leave open. - V0N V63N 2 I or O Open Test pins. Leave open. - TIN1 1 I GND Test pin. Must be fixed to GND level. - TOUT1-3 3 O Open Test pins. Leave open. Open TVcc1 TVcc2 2 I GND Test pins. Must be fixed to GND level. - DUMMY14 DUMMY15 2 - - Dummy pads. DUMMY 14 and DUMMY 15 are short-circuited within the LSI. Available for measuring COG contact resistor. Open DUMMY 1~13, 16~30 28 - Open Dummy pads. Must be left open. Open IOVccDUM 1~3 3 O Input pins Output an internal IOVc c level. When neighboring input pins are fixed to IOVcc, short-circuit them. Open Vcc1DUM1 Vcc1DUM2 2 O Input pins Output an internal Vcc1 level. When neighboring input pins are fixed to Vcc1, short-circuit them. Open AGNDDUM 1-4 4 O Input pins Output an internal AGND level. When neighboring input pins are fixed to AGND, short-circuit them. Open TESTO1 TESTO2 2 O Open Test pins. Leave open. -

Rev.0.5, July.31.2003, page 14 of 196 HD66781 power-supply specification Item Voltage range Specification IOVcc Interface voltage 1 +1.7V~+3.3V Power supply for signals interfacing with MPU or LCDC. Supply through the system. Power supply for CS*, RS, WR*/SCL, RD*, DB17-2, DB1/SDO, DB0/SDI, VSYNC, HSYNC, ENABLE, PD17-0. Connect on the FPC when using at the same electric potential with Vcc1. Vcc1 Interface voltage 2 +1.7V~+3.3V Power supply for signals interfacing with a gate driver/power supply IC and a deep standby mode control circuit that halts the logic regulator. Supply with the same electric potential with Vcc of HD66783 or HD667P21 though the system. Power supply for FLM1, FLM2, CL11/SFTCLK11, CL12/SFTCLK12, SFTCLK21, SFTCLK22, M1, M2, EQ1, EQ2, DCCLK1, DCCLK2, GCL1, GCL2, GDA1, GDA2, GCS1*, GCS2*, RESET*, RESETO1, RESETO2, DACK*, BST, M3-1, IM0/ID. Connect on the FPC when using at the same potential with IOVcc. Vcc Power supply for the logic regulator +2.5V~+3.3V Supply through the system. Connect on the FPC when using at the same electric potential with Vci of HD66783 or HD667P21. VDD Power supply for the Internal logic Generated from the internal logic regulator. Supply through the system is not required. GND - 0V GND for the internal logic circuit. Connect to GND on the FPC. RGND - 0V GND for the internal GRAM. Connect to GND on the FPC. Input Voltage AGND - 0V GND for the I/O side and analogue circuits other than logic circuits and the internal GRAM, which operate with VDD voltage. Connect to GND on the FPC. LCD drive voltage DDVDH - +4.5V~+5.9V Connect to DDVDH of HD66783 or HD667P21. VDH - +3.0V~ (DDVDH-0.5)V Connect to VREG1OUT of HD66783 or HD667P21. Source driver grayscale reference voltage VGS - - Connect to GND or variable resistor. LCD drive output S1~ S720 V0~V63 grayscale level - -

(4-a) DUMMY30 DUMMY29 S76 S77 DUMMY28 DUMMY27 (4-d) (3-a)     DUMMY1  i1-aj  DUMMY26 TESTO1   DUMMY25 FLM1   S78 SFTCLK21   S79 œChip SizeF16.94mm~2.99mm CL11/SFTCLK11  œChip ThicknessF400mm(typ.) M1  œPAD Coordinate : PAD center EQ1  DISPTMG1  œCoordinate Origin : Chip Center GDA1  GCS1*  œAu Bump Size : GCL1  (1) 54mm~106mm DCCLK1  NO.1~NO.200 RESETO1  DUMMY2  RESET*  (2)26mm~90mm BST  NO.201~NO.281,NO.853~NO.933 DUMMY3  DB17  DB16  (3)90mm~26mm DB15  NO.282~NO.852 DB14  DB13  DB12  DB11  DB10  DB9  IOVccDUM1  DB8  DB7  DB6  œAu Bump pitch : See PAD coordinate DB5  œAu Bump height : 15mm(typ.) DB4  DB3  œ"No.X" in the Figure corresponds to the PAD No. in the PAD Coordinate Table. DB2  DB1/SDO  œAlignment Mark DB0/SDI  (1) Arranged Coordinate : 2 places IOVccDUM2  Cell NameFMARK_COGTGT RD*  (1-a) Coordinate (X,Y) = (-8199.6, 1324.3) WR*/SCL  (1-b) Coordinate (X,Y) = (8199.6, 1324.3) RS  CS*  DUMMY4  DACK*  Vcc1DUM1  VSYNC  HSYNC  DOTCLK  ENABLE  PD17  PD16  PD15  PD14  PD13  (2) Arrangement Coordinate PD12  (2-a) Coordinate (X,Y) = (-8339.6, 1364.6) PD11  Cell NameFMARK_EN_A PD10  PD9  PD8  PD7  PD6  PD5  PD4  PD3  (2-b) Coordinate (X,Y) = (8339.6, 1364.6) PD2  Cell NameFMARK_EN_B PD1  PD0  IOVcc  IOVcc  IOVcc  IOVcc  Vcc1  Vcc1  (3) Arrangement Coordinate Vcc1  (3-a) Coordinate (X,Y) = (-8339.6, 1274.3) Vcc1  Cell NameFMARK_L_A Vcc  Vcc  Vcc  Vcc  Vcc  Vcc  Vcc  Vcc  Vcc  VDD  VDD  VDD  VDD  VDD  VDD  VDD  VDD  (3-b) Coordinate (X,Y) = (8339.6, 1274.3) VDD  Cell NameFMARK_L_B VDD  VDD  VDD  VDD  VDD  VDD  GND  GND  GND  GND  RGND  RGND  RGND  RGND  (4) Arrangement Coordinate : 4 places RGND  Cell NameFZBASFLONGSCALELCD RGND  (4-a) Coordinate (X,Y) = (-8339.6, -1197.9) RGND  (4-b) Coordinate (X,Y) = (8339.6, -1197.9) RGND  (4-c) Coordinate (X,Y) = (8339.6, 1197.9) RGND  (4-c) Coordinate (X,Y) = (-8339.6, 1197.9) AGND  AGND  (5) Arrangement Coordinate : 1 place AGND  (5-a) Coordinate (X,Y) = (8339.6, -1276.1) AGND  Cell NameFZBSHORTSCALE_L0106 AGND  AGND  AGND  DDVDH  DDVDH  DDVDH  DDVDH  DDVDH  DDVDH  DDVDH  V0P  V0N  V63P  V63N  VGS  VDH  PMON  VMON  VTEST  Vcom  Vcom  DUMMY5  VREFD  VRTEST  VREF  DUMMY6  VREFC1  VREFC2  VDDTEST  DUMMY7  TSC  AGNDDUM1  DUMMY8  OSC1  DUMMY9  DUMMY10  OSC2  DUMMY11  Vcc1DUM2  OSC3  IOVccDUM3  IM0/ID  IM1  IM2  IM3  AGNDDUM2  TEST1  TEST2  TS8  TS7  TS6  TS5  TS4  TS3  TS2  TS1  TS0  RESETO2  DCCLK2  GCL2  GCS2*  GDA2  DISPTMG2  EQ2  M2  CL12/SFTCLK12  SFTCLK22  FLM2  AGNDDUM3  TIN1  TOUT1  TOUT2  TOUT3  AGNDDUM4  TVcc1  TVcc2  DUMMY12  DUMMY13  DUMMY14   S642 DUMMY15   S643 DUMMY16   DUMMY24 TESTO2   DUMMY23 DUMMY17  i1-bj  DUMMY22     (5-a) (4-b) DUMMY18 DUMMY19 S720 S719 S645 S644 DUMMY20 DUMMY21 (4-c) (3-b) HD667B81 Laced Output Top View 50m‚ 50mm20 10 25 25 10 10 25 25 10 70mm 70mm 10 25 25 10 10 25 25 10 5 5 80mm 70mm 80mm 70mm 30 40 30 30 40 30 100m‚ 100m‚ NO.1 NO.933 NO.2 NO.201 NO.281 NO.852 NO.853 NO.199 NO.200 NO.282 NO.203 NO.279 NO.285 NO.850 NO.855NO.931 Chip BUMP Top View Short-circuit TypeCode : HD667B81 Arrangement

Rev.0.5, July.31.2003, page 16 of 196 Pad Coordinate Unit : µ m pad No pad name X Y pad No pad name X Y pad No pad name X Y pad No pad name X Y 1364.6

Rev.0.5, July.31.2003, page 17 of 196 pad No pad name X Y pad No pad name X Y pad No pad name X Y pad No pad name X Y XY Cross Alignment Mark L-type (Positive) L-type (Negative) Circle (Positive) Circle (Negative)

Rev.0.5, July.31.2003, page 18 of 196 Bump Arrangement Unit : um S=5724um2I/O pins (No1 ~ 200) 2626 30 135 45 28 28 Unit : um S=2340um2 106 Min.80 S1~S720

1 DUMMY17 1 DUMMY22

1 TESTO2 1 DUMMY23

1 DUMMY16 1 S643

1 DUMMY15 1 S642

1 DUMMY14

1 DUMMY13

1 DUMMY12

1 TVcc2

1 TVcc1

1 AGNDDUM4

1 TOUT3

1 TOUT2

1 TOUT1

1 TIN1

1 AGNDDUM3

1 FLM2

1 SFTCLK22

1 CL12/SFTCLK12

1 EQ2

1 DISPTMG2

1 GDA2

1 GCS2*

1 GCL2

1 DCCLK2

1 RESETO2

1 TS0

1 TS1

1 TS2

1 TS3

1 TS4

1 TS5

1 TS6

1 TS7

1 TS8

1 TEST2

1 TEST1

1 AGNDDUM2

1 IM3

1 IM2

1 IM1

1 IM0/ID

1 IOVccDUM3

1 OSC3

1 Vcc1DUM2

1 DUMMY11

1 OSC2

1 DUMMY10

1 DUMMY9

1 OSC1

1 DUMMY8

1 AGNDDUM1

1 TSC

1 DUMMY7

1 VDDTEST

1 VREFC2

1 VREFC1

1 DUMMY6

1 VREF

1 VRTEST

1 VREFD

1 DUMMY5

1 Vcom

1 VTEST

1 VMON

1 PMON

1 VDH

1 VGS

1 V63N

1 V63P

1 V0N

1 V0P

1 DDVDH

1 AGND

1 RGND

1 GND

1 VDD

1 Vcc

1.7~3.3V 1 Vcc1

1 Vcc1

1 IOVcc

1.7~3.3V 1 IOVcc

1 Vcc1DUM1

DACK* 1 DACK*

1 DUMMY4

CS* 1 CS* RS 1 RS WR*/SCL 1 WR*/SCL RD* 1 RD*

1 IOVccDUM2

1 IOVccDUM1

1 DUMMY3

RESET* 1 RESET*

1 DUMMY2

1 RESETO1

1 DCCLK1

1 GCL1

1 GCS1*

1 GDA1

1 DISPTMG1

1 EQ1

1 CL11/SFTCLK11

1 SFTCLK21 1 S79

1 FLM1 1 S78

1 TESTO1 1 DUMMY25

1 DUMMY1 1 DUMMY26

1111111111111111111111111111DMY1 VCOMR2 RESET* DCCLK DMY2 GCL DMY3 GCS* DMY4 GDA DMY5 DISPTMG DMY6 EQ DMY7 M GNDDMY1 GON DMY8 MODE GNDDMY2 TOS VCCDMY1 CL1 DMY9 FLM DMY10 DMY11

1 DMY36

1 DMY35 1 DMY12

1 VREG1OUT 1 DMY13

1 GND 1 G1

1 GND 1 G2

1 GND 1 G3

1 GND 1 G4

1 DMY34 1 G5

1 DMY33 1 G6

1 C22+

1 C22-

1 C21+

1 C21-

1 C12+

1 C12-

1 C11+

1 C11-

1 DMY32

1 VGH

1 DMY31

1 VCOMH2

1 VCIOUT

1 VCOML2

1 VCL

1 VGL

1 VCI

2.5~3.3V 1 VCILVL

1 TMP

1 TMN

1 VCOM2

1 DMY30

1 DMY29

1 DMY28

1 DMY27

1 DMY26

1 DMY25

1 TESTA12

1 TESTA2

1 TESTA42

1 DMY24

1 DMY23

1 DMY22

1 TG328

1 G328 1

1 G327 1

1 G326 1

1 G284 1 G229

1 G283 1 DMY14

1 DMY21 1 DMY15

1 DMY20

(Bottom View) Example of connecting HD66781 and HD66783 Gate electrode HD667B83 (Bottom View) IOVcc Connect on the FPC. Laced Output Arrangement Connect on the FPC. Vcc1(781)=Vcc(783) GND Vcc(781)=Vci(783) Laced Output Arrangement Connect on the FPC. Connect on the FPC. Short-circuit DMY22 and DMY23 within LSI Short-circuit TG328 and G328 within LSI Short-circuit DUMMY14 and DUMMY15 Within LSI Glass Chip Bottom View (Non Bump View) 10ohm 10ohm 5ohm 20ohm 5ohm 10ohm 20ohm 20ohm 1uF/3V/B 1uF/6V/B > 200kΩ 1uF/10V/B 1uF/10V/B 1uF/6V/B 1uF/6V/B 1uF/10V/B VF<0.4V/20mA at 25Ž, VR†30V 1uF/25V/B 1uF/25V/B 1uF/6V/B 1uF/6V/B 1uF/6V/B 1uF/6V/B 15ohm 30ohm 30ohm 30ohm 30ohm 30ohm 30ohm 20ohm 20ohm 10ohm 30ohm 30ohm 15ohm 15ohm 30ohm 10ohm 15ohm 30ohm 20ohm 50ohm Note: This is an example of connecting HD66781 and HD66783 when these drivers are used as a set. The bottom views show an example of pin arrangements. See the pad cooridnation of each product for more accurate and detailed reference to the number of pads and the coordination. The validity of this connection example is not confirmed. It is necessary to throughly check the operation and the display quality before use. To opposing electrodes on the panel(Vcom) IOVcc = 1.7V~3.3V (HD66781) Vcc1 = 1.7~3.3V (HD66781) Vcc = 2.5~3.3V (HD66781) VCC = 1.7~3.3V (HD667P21) VCI = 2.5~3.3V (HD667P21) Supply a same potential to Vcc1 of HD66781 and VCC of HD66783. Make sure that IOVcc Vcc1 Vcc (HD66781). Source Electrode 80-system 18-bit interface VF<0.4V/20mA at 25Ž, VR†30V Gate electrode

1.7~3.3V 1 Vcc1 1.7~3.3V 1 IOVcc DACK* 1 DACK* CS* 1 CS* RS 1 RS WR*/SCL 1 WR*/SCL RD* 1 RD* RESET* 1 RESET* DMY4 1 111111111111111111111 1 DMY7 DMY5 SIN7 RESET* DCCLK GCL GCS* GDA SIN4 EQ GNDDNY1 SIN5 M VCCDMY1 GNDDMY2 SIN3 SIN2 SIN1 CLA CLB CLC DMY6

1 DMY3 DMY8 1

1 Vci DMY 9 1

1 Vci DMY1 0 1

1 Vci DMY11 1

1 Vci DMY1 2 1

2.5\`3.3V 1 Vci GNDDMY 3 1

1 VCC GNDDMY4 1

1 VCC GNDDMY5 1

1 GND TEST M 1

1 GND TEST L 1

1 GND TESTG 1

1 GND VCCDMY 2 1

1 GND VCCDMY 3 1

1 GND VTES T 1

1 VciOUT SOUT8 1

1 Vci1

1 VCOMR

1 VREG1

1 VREG1OUT

1 VLOUT1

1 DDVDH 1

1 VLOUT2 1

1 VGH 1

1 VCOMH 1

1 VCOML 1

1 VCL 1

1 VLOUT4 1

1 VLOUT3 1

1 VGL 1

1 C11+ Vcom 1

1 C11+ CLCO 1

1 C12- CLBO 1

1 C12- CLAO 1

1 C12- SOUT7 1

1 C12+ SOUT6 1

1 C12+ SOUT5 1

1 C12+ SOUT4 1

1 C21- SOUT3 1

1 C21- SOUT2 1

1 C21+ SOUT1 1

1 C22- DMY30 1

1 C22- DMY31 1

1 C22+ DMY3 2 1

1 C22+ DMY3 3 1

1 DMY2 DMY34 1

DMY‚P 1 1111111111111111111111 1 DMY35 DMY46 Vcom Vcom TDCA TDCB TESTR TESTA6 TESTA5 TESTA4 TESTA3 TESTA2 TESTA1 DMY45 DMY44 DMY43 DMY42 DMY41 DMY40 DMY39 DMY38 DMY37 DMY36 Poly-Si TFT HD66781 (Bottom View) To opposing electrodes on the panel(Vcom Source Electrode Gate Circuit IOVcc = 1.7V~3.3V (HD66781) Vcc1 = 1.7~3.3V (HD66781) Vcc = 2.5~3.3V (HD66781) VCC = 1.7~3.3V (HD667P21) VCI = 2.5~3.3V (HD667P21) Supply a same potential to Vcc1 of HD66781 and VCC of HD667P21. Make sure that IOVcc Vcc1 Vcc (HD66781). HD667P21 (Bottom View) IOVcc Connect on the FCP. 80-system 18-bit interface Connect on the FPC. Vcc1(781)=VCC(7P21) GND Vcc(781)=Vci(7P21) Laced Output Connect on the FCP. Short-circuit DUMMY14 and DUMMY15 within LSI Glass Chip Bottom View (Non Bump View) Fix to GND To opposing electrodes on the panel(Vcom) 10ohm > 200kW 1uF/10V/B 1uF/10V/B 1uF/6V/B 1uF/10V/B 1uF/25V/B 1uF/6V/B 1uF/6V/B 1uF/6V/B 1uF/6V/B 1uF/3V/B VF<0.4V/20mA at 25Ž, VR†30V 10ohm 5ohm 20ohm 5ohm 10ohm 20ohm 20ohm 5ohm 10ohm 5ohm 10ohm 40ohm 10ohm 40ohm 50ohm 20ohm 20ohm 40ohm 20ohm 30~50ohm 10ohm 10ohm 20ohm 20ohm 40ohm 40ohm 40ohm 40ohm 1uF/25V/B 1uF/6V/B 1uF/6V/B 1uF/25V/B 1uF/25V/B VF<0.4V/20mA at 25Ž, VR†30V VF<0.4V/20mA at 25Ž, VR†30V Example of connecting HD66781 and HD667P21

Rev.0.5, July.31.2003, page 21 of 196 Block Function (1) System interface The HD66781 has 2 kinds of high-speed system interfaces: 80-system 18-/16-/9-/8-bit bus interfaces and Serial Peripheral Interface (SPI) ports. The 8-bit bus interface is compliant to both big and little endian data outputs from the microcomputer. The interface mode is selected with the IM3-0 pins. The HD66781 incorporates 16-bit index register (IR), write-data register (WDR), and 16-bit read-data register (RDR). The IR stores index information from the control register and GRAM. The WDR temporarily stores data to write into the control register and GRAM, and the RDR temporarily stores data read from GRAM. Data written into GRAM from MPU is first written into the WDR and then automatically written to GRAM by internal operation. Since data are read through the RDR from GRAM, the data that are read out first are invalid and the ensuing data are read out normally. The execution time for the instructions other than oscillation start is 0-clock cycle, which enables writing instructions consecutively. Table 1 Register Selection (8/9/16/18 parallel interface) 80-system bus WR* RD* RS Operation 0 1 0 Write index to IR. 1 0 0 Read internal status 0 1 1 Write to control r egisters/GRAM through WDR 1 0 1 Read from GRAM through RDR Table 2 Register Selection (SPI) Start byte RW RS Operation 0 0 Write index to IR. 1 0 Read internal status 0 0 Write to control regi sters/GRAM through WDR 1 1 Read from GRAM through RDR

Rev.0.5, July.31.2003, page 22 of 196 The HD66781 incorporates DMA single address mode interface to keep control on the bus occupation ratio when transferring a large volume of data. The DMA controller supporting a single address mode controls the DACK pin of HD66781 to recognize out-enable signal (OE) for SRAM as a write strobe signal. The HD66781 enables data transfer with less bus cycle by using a same bus cycle for a readout operation from an external SRAM and a write operation to HD66781. See “DMA transfer single address mode” (p.131) for details on controlling the execution of transfer and conditions in using this mode. (2) External Display Interface (RGB I/F, VSYNC I/F) The HD66781 incorporates RGB and VSYNC interfaces as an external interface for displaying moving pictures. When the RGB-I/F is selected, the operation is synchronized with externally supplied signals, VSYN C, HSYNC, and DOTCLK. The display data (PD17-0) are written in accordance with the data enable signal (ENABLE). Accordingly, the display on the screen does not flicker when RAM data are being updated internally. When the VSYNC-I/F is selected, the operation is synchronized with internal clocks except frame synchronization, which is synchronized with VSYNC signal. The display data is written to GRAM through a system interface. In this case, there are constraints on the speed and methods of updating RAM data when the VSYNC I/F is selected. For details, see the “External Display Interface” section (p.139). The switch from and to the system interface is made through instructions. An optimum interface can be selected for the kind of display (still and/or moving pictures). The display data are all written to GRAM through the RGB-I/F. This enables transmission of data only when the display on the screen is being updated, and thereby reduces the data transmission as well as consumption of power when a moving picture is displayed. (3) Address Counter (AC) The address counter (AC) assigns the address to GRAM. When a set-address instruction is written to the IR, the address information is sent from the IR to the AC. After writing data into GRAM, the AC is automatically incremented or decremented by 1, while after data are read form GRAM, the AC is not updated. Window address function enables data write only in the rectangular area of GRAM specified by the window address. (4) Graphic RAM (GRAM) GRAM is a graphics RAM that stores 224,640-byte bit-pattern data, where one pixel is expressed by 18 bits. Maximum 240 RGB x 320 can be displayed by using both main/sub panels. Besides data of 240 RGB x 320 lines for a base image, it can store OSD data of 240 RGB x 96 lines. The allocation of the numbers of lines for a base image and an OSD image is changeable. (5) Grayscale Voltage Generation Circuit The grayscale voltage generation circuit generates an LCD drive voltage according to the grayscale level set in the γ-correction register. Simultaneously 262,144 colors are available for display.

Rev.0.5, July.31.2003, page 23 of 196 (6) Timing generator Timing generator generates a timing signal for the operation of internal circuits such as GRAM. The timing for display operation such as RAM read and the internal operation timing such as access from MPU are generated in a way to avoid mutual interfere. Also the signals interfacing with gate driver/power supply IC (M, FLM, CL1/SFTCLK1, SFTCLK2, EQ, DCCLK, and DISPTMG) are generated. (7) Oscillation Circuit (OSC) The HD66781 generates R-C oscillation simply by placing an external oscillation-resistor between the OSC1 and OSC2 pins. The oscillation frequency is changeable with the value of external resistor. Adjust oscillation frequency in accordance to an operation voltage, display size, and frame frequency. During the standby mode, the R-C oscillation is halted to reduce power consumption. For details, see “Oscillation Circuit” (p.173). (8) Liquid Crystal Display Driver Circuit The LCD driver circuit consists of a 720-output source driver (S1 ~ S720). Display pattern data are latched when 720-bit data arrive. The latched data controls the source driver and generates drive waveforms. The shift direction of 720-bit output from source driver is changeable with SS bit. Select an appropriate shift direction for the assembly. (9) Gate driver/power supply IC interfacing circuit Gate driver/power supply IC interfacing circuit is a serial interface circuit to interface with the HD66783 and the HD667P21. When making settings for instructions to the HD66783 or the HD667P21 though the HD66781, values set in the register of HD66781 are transferred through this serial interface circuit. The transfer starts by making a serial transfer ENABLE setting. Both transfer of instruction to the HD66783/HD667P21 and read out from the HD66781 are impossible during standby mode. For details, see “Gate Driver/Power Supply IC interface control” (p.70). (10) Internal Logic Power Supply Regulator Internal logic power supply regulator generates power supply VDD for the internal logic.

Rev.0.5, July.31.2003, page 24 of 196 GRAM Address MAP Relation between GRAM addresses and Screen positions (SS=0, BGR=0) Table 3 S10 S11 S12䊶䊶䊶䊶䊶 S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 S720 GS=0 GS=1 䊶䊶䊶䊶䊶 G1 G328 䊶䊶䊶䊶䊶 G2 G327 䊶䊶䊶䊶䊶 G3 G326 䊶䊶䊶䊶䊶 G4 G325 䊶䊶䊶䊶䊶 G5 G324 䊶䊶䊶䊶䊶 G6 G323 䊶䊶䊶䊶䊶 G7 G322 䊶䊶䊶䊶䊶 G8 G321 䊶䊶䊶䊶䊶 G9 G320 䊶䊶䊶䊶䊶 G10 G319 䊶䊶䊶䊶䊶 G11 G318 䊶䊶䊶䊶䊶 G12 G317 䊶䊶䊶䊶䊶 G13 G316 䊶䊶䊶䊶䊶 G14 G315 䊶䊶䊶䊶䊶 G15 G314 䊶䊶䊶䊶䊶 G16 G313 䊶䊶䊶䊶䊶 G17 G312 䊶䊶䊶䊶䊶 G18 G311 䊶䊶䊶䊶䊶 G19 G310 䊶䊶䊶䊶䊶 G20 G309 䊶䊶䊶䊶䊶 䋺䋺 䋺䋺 G301 G28 䊶䊶䊶䊶䊶 G302 G27 䊶䊶䊶䊶䊶 G303 G26 䊶䊶䊶䊶䊶 G304 G25 䊶䊶䊶䊶䊶 G305 G24 䊶䊶䊶䊶䊶 G306 G23 䊶䊶䊶䊶䊶 G307 G22 䊶䊶䊶䊶䊶 G308 G21 䊶䊶䊶䊶䊶 G309 G20 䊶䊶䊶䊶䊶 G310 G19 䊶䊶䊶䊶䊶 G311 G18 䊶䊶䊶䊶䊶 G312 G17 䊶䊶䊶䊶䊶 G313 G16 䊶䊶䊶䊶䊶 G314 G15 䊶䊶䊶䊶䊶 G315 G14 䊶䊶䊶䊶䊶 G316 G13 䊶䊶䊶䊶䊶 G317 G12 䊶䊶䊶䊶䊶 G318 G11 䊶䊶䊶䊶䊶 G319 G10 䊶䊶䊶䊶䊶 G320 G9 䊶䊶䊶䊶䊶 h13FEC h13FED h13FEE h13FEFh13F00 h13F01 h13F02 h13F03 h13EEC h13EED h13EEE h13EEFh13E00 h13E01 h13E02 h13E03 h13DEC h13DED h13DEE h13DEFh13D00 h13D01 h13D02 h13D03 h13CEC h13CED h13CEE h13CEFh13C00 h13C01 h13C02 h13C03 PD17-0 PD17-0 PD17-0 S/ G pins PD17-0 PD17-0 PD17-0 PD17-0 h00000 h00001 h00002 h00003 h000EC h000ED h000EE h000EF PD17-0 h00100 h00101 h00102 h00103 h001EC h001ED h001EE h001EF h00200 h00201 h00202 h00203 h002EC h002ED h002EE h002EF h00300 h00301 h00302 h00303 h003EC h003ED h003EE h003EF h00400 h00401 h00402 h00403 h004EC h004ED h004EE h004EF h00500 h00501 h00502 h00503 h005EC h005ED h005EE h005EF h00600 h00601 h00602 h00603 h006EC h006ED h006EE h006EF h00700 h00701 h00702 h00703 h007EC h007ED h007EE h007EF h00800 h00801 h00802 h00803 h008EC h008ED h008EE h008EF h00900 h00901 h00902 h00903 h009EC h009ED h009EE h009EF h00A00 h00A01 h00A02 h00A03 h00AEC h00AED h00AEE h00AEF h00B00 h00B01 h00B02 h00B03 h00BEC h00BED h00BEE h00BEF h00C00 h00C01 h00C02 h00C03 h00CEC h00CED h00CEE h00CEF h00D00 h00D01 h00D02 h00D03 h00DEC h00DED h00DEE h00DEF h00E00 h00E01 h00E02 h00E03 h00EEC h00EED h00EEE h00EEF h00F00 h00F01 h00F02 h00F03 h00FEC h00FED h00FEE h00FEF h01000 h01001 h01002 h01003 h010EC h010ED h010EE h010EF h01100 h01101 h01102 h01103 h011EC h011ED h011EE h011EF h01200 h01201 h01202 h01203 h012EC h012ED h012EE h012EF h01300 h01301 h01302 h01303 h013EC h013ED h013EE h013EF 䋺䋺䋺䋺 䋺䋺䋺䋺 h12C00 h12C01 h12C02 h12C03 h12CEC h12CED h12CEE h12CEF h12D00 h12D01 h12D02 h12D03 h12DEC h12DED h12DEE h12DEF h12E00 h12E01 h12E02 h12E03 h12EEC h12EED h12EEE h12EEF h12F00 h12F01 h12F02 h12F03 h12FEC h12FED h12FEE h12FEF h13000 h13001 h13002 h13003 h130EC h130ED h130EE h130EF h13100 h13101 h13102 h13103 h131EC h131ED h131EE h131EF h13200 h13201 h13202 h13203 h132EC h132ED h132EE h132EF h13300 h13301 h13302 h13303 h133EC h133ED h133EE h133EF h13400 h13401 h13402 h13403 h134EC h134ED h134EE h134EF h13500 h13501 h13502 h13503 h135EC h135ED h135EE h135EF h13600 h13601 h13602 h13603 h136EC h136ED h136EE h136EF h13700 h13701 h13702 h13703 h137EC h137ED h137EE h137EF h13800 h13801 h13802 h13803 h138EC h138ED h138EE h138EF h13900 h13901 h13902 h13903 h139EC h139ED h139EE h139EF h13A00 h13A01 h13A02 h13A03 h13AEC h13AED h13AEE h13AEF h13B00 h13B01 h13B02 h13B03 h13BEC h13BED h13BEE h13BE F

Rev.0.5, July.31.2003, page 25 of 196 Relation between GRAM data and Display data (SS=0, BGR=0) The following figure illustrates the relationship between data on GRAM and display data through each interface. 80 system 18-bit interface (1 transmission/pixel) GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 G3 G2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) 80 system 16-bit interface (1 transmission/pixel) RGB Assignment Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80 system 16-bit interface (2 transmissions/pixel) 1 GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 2nd transmission1st transmission 80 system 16-bit interface (2 transmissions/pixel) 2 GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 1st transmission 2nd transmission 80-system 18/16-bit interface (SS = 0, BGR = 0)

Rev.0.5, July.31.2003, page 26 of 196 1st transmission 2nd tr ansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) 80 system 8- bit interface / (3 transmissions/pixel) 1 2nd transmission 3rd tr ansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) 80 system 8-bit interface (big endian) / SPI (2 transmissions/pixel) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 1st transmission 2nd tr ansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) 80 system 9-bit interface (2 transmissions/pixel) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 2nd transmission 1st transmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) 80 system 8-bit interface (little endian) / (2 transmissions/pixel) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80 system 8- bit interface / (3 transmissions/pixel) 2 1st transmission 2nd transmission 3rd tr ansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(3n+1) S(3n+2) S(3n+3 ) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display Note 3: Upper 2-bit data of each transmission are not used. 11 10 11 10 1st transmission 80-system 9/8-bit interface (SS = 0, BGR = 0)

Rev.0.5, July.31.2003, page 27 of 196 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 S(3n+1) S(3n+2) S(3n+3 ) PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 S(3n+1) S(3n+2) S(3n+3 ) PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 S(3n+1) S(3n+2) S(3n+3 ) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 1st transmission 2nd transmission 3rd transmission GRAM data RGB Assignment Output pin GRAM data RGB Assignment Output pin GRAM data RGB Assignment Output pin 6-bit RGB interface (3 transmissions/pixel) 16-bit RGB interface (1 transmission/pixel) 18 bit RGB interface (1 transmission/pixel) RGB interface (SS = 0, BGR = 0)

Rev.0.5, July.31.2003, page 28 of 196 Relation between GRAM address and Screen position (SS=1, BGR=1) Table 4 S10 S11 S12䊶䊶䊶䊶䊶 S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 S720 GS=0 GS=1 䊶䊶䊶䊶䊶 G1 G328 䊶䊶䊶䊶䊶 G2 䌇327 䊶䊶䊶䊶䊶 G3 䌇326 䊶䊶䊶䊶䊶 G4 䌇325 䊶䊶䊶䊶䊶 G5 䌇324 䊶䊶䊶䊶䊶 G6 䌇323 䊶䊶䊶䊶䊶 G7 䌇322 䊶䊶䊶䊶䊶 G8 䌇321 䊶䊶䊶䊶䊶 G9 䌇320 䊶䊶䊶䊶䊶 G10 䌇319 䊶䊶䊶䊶䊶 G11 䌇318 䊶䊶䊶䊶䊶 G12 䌇317 䊶䊶䊶䊶䊶 G13 䌇316 䊶䊶䊶䊶䊶 G14 䌇315 䊶䊶䊶䊶䊶 G15 䌇314 䊶䊶䊶䊶䊶 G16 䌇313 䊶䊶䊶䊶䊶 G17 䌇312 䊶䊶䊶䊶䊶 G18 䌇311 䊶䊶䊶䊶䊶 G19 䌇310 䊶䊶䊶䊶䊶 G20 䌇309 䊶䊶䊶䊶䊶 䋺䋺 䋺䋺 G301 G28 䊶䊶䊶䊶䊶 G302 G27 䊶䊶䊶䊶䊶 G303 G26 䊶䊶䊶䊶䊶 G304 G25 䊶䊶䊶䊶䊶 G305 G24 䊶䊶䊶䊶䊶 G306 G23 䊶䊶䊶䊶䊶 G307 G22 䊶䊶䊶䊶䊶 G308 G21 䊶䊶䊶䊶䊶 G309 G20 䊶䊶䊶䊶䊶 G310 G19 䊶䊶䊶䊶䊶 G311 G18 䊶䊶䊶䊶䊶 G312 G17 䊶䊶䊶䊶䊶 G313 G16 䊶䊶䊶䊶䊶 G314 G15 䊶䊶䊶䊶䊶 G315 G14 䊶䊶䊶䊶䊶 G316 G13 䊶䊶䊶䊶䊶 G317 G12 䊶䊶䊶䊶䊶 G318 G11 䊶䊶䊶䊶䊶 G319 G10 䊶䊶䊶䊶䊶 G320 G9 䊶䊶䊶䊶䊶 h13F03 h13F02 h13F01 h13F00h13FEF h13FEE h13FED h13FEC h13E03 h13E02 h13E01 h13E00h13EEF h13EEE h13EED h13EEC h13D03 h13D02 h13D01 h13D00h13DEF h13DEE h13DED h13DEC h13C03 h13C02 h13C01 h13C00h13CEF h13CEE h13CED h13CEC PD17-0 PD17-0 PD17-0 S/ G pins PD17-0 PD17-0 PD17-0 PD17-0 h000EF h000EE h000ED h000EC h00003 h00002 h00001 h00000 PD17-0 h001EF h001EE h001ED h001EC h00103 h00102 h00101 h00100 h002EF h002EE h002ED h002EC h00203 h00202 h00201 h00200 h003EF h003EE h003ED h003EC h00303 h00302 h00301 h00300 h004EF h004EE h004ED h004EC h00403 h00402 h00401 h00400 h005EF h005EE h005ED h005EC h00503 h00502 h00501 h00500 h006EF h006EE h006ED h006EC h00603 h00602 h00601 h00600 h007EF h007EE h007ED h007EC h00703 h00702 h00701 h00700 h008EF h008EE h008ED h008EC h00803 h00802 h00801 h00800 h009EF h009EE h009ED h009EC h00903 h00902 h00901 h00900 h00AEF h00AEE h00AED h00AEC h00A03 h00A02 h00A01 h00A00 h00BEF h00BEE h00BED h00BEC h00B03 h00B02 h00B01 h00B00 h00CEF h00CEE h00CED h00CEC h00C03 h00C02 h00C01 h00C00 h00DEF h00DEE h00DED h00DEC h00D03 h00D02 h00D01 h00D00 h00EEF h00EEE h00EED h00EEC h00E03 h00E02 h00E01 h00E00 h00FEF h00FEE h00FED h00FEC h00F03 h00F02 h00F01 h00F00 h010EF h010EE h010ED h010EC h01003 h01002 h01001 h01000 h011EF h011EE h011ED h011EC h01103 h01102 h01101 h01100 h012EF h012EE h012ED h012EC h01203 h01202 h01201 h01200 h013EF h013EE h013ED h013EC h01303 h01302 h01301 h01300 䋺䋺䋺䋺 䋺䋺䋺䋺 h12CEF h12CEE h12CED h12CEC h12C03 h12C02 h12C01 h12C00 h12DEF h12DEE h12DED h12DEC h12D03 h12D02 h12D01 h12D00 h12EEF h12EEE h12EED h12EEC h12E03 h12E02 h12E01 h12E00 h12FEF h12FEE h12FED h12FEC h12F03 h12F02 h12F01 h12F00 h130EF h130EE h130ED h130EC h13003 h13002 h13001 h13000 h131EF h131EE h131ED h131EC h13103 h13102 h13101 h13100 h132EF h132EE h132ED h132EC h13203 h13202 h13201 h13200 h133EF h133EE h133ED h133EC h13303 h13302 h13301 h13300 h134EF h134EE h134ED h134EC h13403 h13402 h13401 h13400 h135EF h135EE h135ED h135EC h13503 h13502 h13501 h13500 h136EF h136EE h136ED h136EC h13603 h13602 h13601 h13600 h137EF h137EE h137ED h137EC h13703 h13702 h13701 h13700 h138EF h138EE h138ED h138EC h13803 h13802 h13801 h13800 h139EF h139EE h139ED h139EC h13903 h13902 h13901 h13900 h13AEF h13AEE h13AED h13AEC h13A03 h13A02 h13A01 h13A00 h13BEF h13BEE h13BED h13BEC h13B03 h13B02 h13B01 h13B00

Rev.0.5, July.31.2003, page 29 of 196 Relation between GRAM data and Display data (SS=1, BGR=1) 80 system 18- bit interface (1 transmission/pixel) GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(720- 3n) S(719- 3n) S( 718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 G3 G2 B1 B 0 Output pin 80 system 16-bit interface (1 transmission/pixel) RGB Assignment Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80 system 16 bit interface (2 transmissions/pixel) 1 GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(720- 3n) S(719- 3n) S( 718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 1st transmission 2nd transmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(720- 3n) S(719- 3n) S( 718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 16 bit interface (2 transmissions/pixel) 2 1st transmission 2nd transmission 2 1 80-system18/16-bit interface (SS = 1, BGR = 1)

Rev.0.5, July.31.2003, page 30 of 196 1st transmission 2nd tr ansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(720- 3n) 80 system 8-bit interface / (3 transmissions/pixel) 2 1st transmission 2nd transmission 3rd t ransmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin 80 system 8-bit interface (big endian) / SPI (2 transmissions/pixel) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display Note 3 : Upper 2-bit data of each transmission are not used. 1st transmission 2nd tr ansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin 80 system 9-bit interface (2 transmissions/pixel) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 8- bit interface / (3 transmissions/pixel) 1 2nd transmission 3rd transmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 11 10 11 10 1st transmission 2nd transmission 1st tansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Output pin S(720- 3n) 80 system 8-bit interface (little endian) / (2 transmissions/pixel) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80-system 9/8-bit interface (SS = 1, BGR = 1)

Rev.0.5, July.31.2003, page 31 of 196 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 S(720 - 3n) S(719 - 3n) S (718 - 3n) PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 1st transmission 2nd transmission 3rd transmission GRAM data RGB Assignment Output pin GRAM data RGB Assignment Output pin GRAM data RGB Assignment Output pin 6-bit RGB interface (3 transmissions/pixel) 16-bit RGB interface (1 transmission/pixel) 18 bit RGB interface (1 transmission/pixel) RGB interface (SS = 1, BGR = 1)

Rev.0.5, July.31.2003, page 32 of 196 Instruction Outline The HD66781 adapts an 18-bit bus architecture that enables high-speed interfacing with high-performance microcomputers. The HD66781 starts internal processing of 18/16/9/8/-bit data sent from external after storing control information in the instruction register (IR) and data register (DR). Since the internal operation of HD66781 is determined by signals sent from the microcomputer, register selection signal (RS), read/write signal (R/W), and internal 16-bit data bus signals (DB15 to DB0) are called instructions. GRAM is accessed through internal 18-bit data bus. The HD66781 has ten categories of instruction. 1. Specify index 2. Read status 3. Control display 4. Power management control 5. Graphics data processing 6. Set internal GRAM address 7. Transfer data to and from internal GRAM 8. Make an internal γ-adjustment 9. Control a panel 10. Control OSD display Normally, the instruction to write data on GRAM is used the most often. The address of internal GRAM is updated automatically after data are written to the internal GRAM. With window address function, this reduces the amount of data transmission to minimum and thereby lightens the load on the program processed by the microcomputer. Since instructions are executed in 0 cycle, it is possible to write instructions consecutively.

Rev.0.5, July.31.2003, page 33 of 196 Instruction data format As the following figure shows, the assignment to the 16 instruction bits (IB15-0) varies according to the interface in use. An instruction must adopt the data format for each interface. DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Instruction bit (IB) IB IB IB IB IB IB IB IB 8 IB IB IB IB IB IB IB IB 80 system 16-bit interface DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB 1st transmission DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB 1st transmission 2nd transmission DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB 80 system 18-bit interface Instruction bit (IB) Instruction bit (IB) Instruction bit (IB) 80 system 9-bit interface 80 system 8-bit interface (big endian) / SPI (2 transmisions) 2nd transmission 2nd transmission 1st transmission DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB Instruction bit (IB) 80 system 8-bit interface (little endian) / (2 transmisions) 80-system interface instruction data format

Rev.0.5, July.31.2003, page 34 of 196 Basic Operation modes The basic operation modes of HD66781 and transitions between the modes are illustrated as follows. A transition between the modes must be made according to the instruction setting flow. OSD display Reset state Display OFF Standby mode Oscillation Start Sleep mode Internal clock display VSYNC interface RGB interface (1) RGB interface (2) Initialization Display ON flow (Power ON flow) Display OFF flow (Power OFF flow) VSYNC i/F flow 2 (DM=10, RM=0) VSYNC i/F flow 1 (DM=00, RM=0) RGB i/F (1) flow 1 (DM=01, RM=1) RGB i/F (1) flow 2 (DM=00, RM=0 RGB i/F (2) flow 1 (DM=01, RM=0) RGB i/F(2) flow 2 (DM=01, RM=1) moving picture display System i/F access while displaying moving picturemoving picture display Base image display STB = 1 Standby set OSC =1 Stand-by releaseSTB=0(at SLP=1) STB = 0 Standby release Sleep release Slee p set 262k-color mode 8-color mode Reset STB=1 Partial Display BASEE =0 =1BASEE=1 OSDE=1 BASEE=1 BASEE =1 BASEE =0 BASEE=1 Panel control Display color control 262k 8 color flow8 262k color flow Partial display flow 2 Partial display flow 1 Deep standby release flow Deep standby mode DSTB = 1 Deep standby set Low power consumption display mode Low power consumption display mode 262k 262k Low power consumption display mode OSDE OSDE OSDE OSDE OSDE Base image display OSD image display (partial display) Basic operation modes

Rev.0.5, July.31.2003, page 35 of 196 Instructions The following are detail explanations of instructions with illustrations of instruction bits (IB15-0) assigned to each interface. Index/Status/Display control instruction Index (IR) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 * * * * * ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 The index instruction specifies the control register and the RAM control indexes that are accessed (R000h to R508h). The register number is set in binary from “000_0000_0000” to “101_0000_1000”. Do not access to the registers and bits to which the index and the instruction bit are not assigned. Status read (SR) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 0 0 0 0 0 0 0 0 L8 L7 L6 L5 L4 L3 L2 L1 L0 SR read the internal status of HD66781. L[8:0]: Indicate the position of the raster-row driving liquid crystal. Start Oscillation (R000h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 The start oscillation instruction restarts the oscillator in a halt state during the standby mode. After executing this instruction, wait at least 10ms for stabilizing oscillation before issuing a next instruction. For details, see “ Standby/Sleep mode” (p190.). The device code “0781”H is read out when this register is forced to read out.

Rev.0.5, July.31.2003, page 36 of 196 Driver Output Control (R001h) LTPS: Select the type of a panel. The output waveforms from SFTCLK1, 2 vary according to the setting of the panel. When LTPS = 0, a-Si TFT panel waveforms are output. When LTPS = 1, low temperature poly-Si TFT panel waveforms are output. See SFTCLK waveforms (p.67) for detail. Make a setting for this register when D[1:0] = 2’h0. SS: Select the correspondence between RAM write address and source driver output. SS = “0”: data written in H’00000 is output from S1. SS = “1”: data written in H’00000 is output from S720. For details, see “GRAM Address Map”. By making settings for both SS and RGB bits, the assignment of RGB dots to the S1 ~ S720 pins is determined. When SS = 0 and BGR = 0, R, G, B are assigned interchangeably in this order from S1 to S720. When SS = 1 and BGR =1, R, G, B are assigned interchangeably in this order from S720 to S1. Changes in the SS and BGR settings require RAM data rewrite. LCD Driving Wave Control (R002h) NW[5:0]: Specify “n”, the number of raster-rows from 1 to 64, to alternate every n+1 raster-rows when C- pattern waveform is generated (B/C = 1). EOR: When EOR = 1, alternations occur by applying EOR (exclusive OR) operation to an odd/even frame select signal and an n-raster-row inversion signal while a C-pattern waveform is generated (B/C =1). This instruction is used when liquid crystal alternate drive is not available due to a combination of numbers of LCD raster-rows and the value of “n”. For details, see “n-raster-row inversion Alternate drive”(p.174). B/C: When B/C =0, field alternating waveforms are generated. Alternation occurs every frame to drive liquid crystal. When B/C=1, alternation occurs every n raster-rows. For details, see the “n-raster-row Inversion alternating Drive” section. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 00LT PS 0 SS 0 0 0 0 0 0 0 0 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 B/C 0 0 EOR 0 0 NW5 FLD1 FLD0 NW4 NW3 NW2 NW1 NW0

Rev.0.5, July.31.2003, page 37 of 196 FLD[1:0]: Specify the number of fields for n-field interlaced drive. For details, see the “Interlaced Drive”(p.175) section. Table 5 FLD [1:0] Numbers of fields 2’h0 Setting disabled 2’h1 1 field (= 1 frame) 2’h2 Setting disabled 2’h3 3 fields Note 1) This instruction is not available with the external display interface. In the external display interface mode, make sure FLD[1:0] = 2’h1. The following functions are not available during interlaced drive (FLD =2’h3). Table 6 Unavailable functions when FLD = 2’h3 External display interface OSD function ( αblending) Scroll function Resizing function (vertical direction magnification) Entry Mode 1 (R003h) This instruction is for writing data from the microcomputer to the internal GRAM of HD66781. ODF: Set the format to write OSD data to the internal RAM. When ODF =0, assign transmission rate bits (α channel) to the LSB of RGB data. When ODF = 1, assign transmission rate bit (α channel) to the MSB. OSD bit must be “1” when writing OSD data. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 TRI DFM 0 0 0 0 0 0 0 OSD ODFBGR HWM I/D1 I/D0 AM

Rev.0.5, July.31.2003, page 38 of 196 Table 7 BGR = 0 OSD ODF D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 * R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 0 R5 R4 R3 R2 R1 α2 G5 G4 G3 G2 G1 α1 B5 B4 B3 B2 B1 α0 1 1 α2 α1 α0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Table 8 BGR =1 OSD ODF D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 * B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 R0 1 0 B5 B4 B3 B2 B1 α0 G5 G4 G3 G2 G1 α1 R5 R4 R3 R2 R1 α2 1 1 α0 α1 α2 B4 B3 B2 B1 B0 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0 Table 9 α2 α1 α0 Transmission rate Display screen 0 0 0 0% Base picture display 0 0 1 - Setting disabled 0 1 0 25% Base picture (75%) + OSD image (25%) display 0 1 1 75% Base picture (25%) + OSD image (75%) display 1 0 0 50% Base picture (50%) + OSD image (50%) display 1 0 1 - Setting disabled 1 1 0 100% OSD image display 1 1 1 - Setting disabled OSD: Set RAM write data as OSD data. Set OSD =1, when writing OSD data. By setting OSD to 1, OSD data are written to the internal RAM according to the format set by ODF. OSD =0: Write normal picture data (18-bit RGB) to RAM OSD =1: Write OSD image data (18-bit (α+RGB)) to RAM AM: Set the automatic updating method of address counter after data are written to GRAM. AM =0, the address counter is updated in horizontal direction. AM =1, the address counter is updated in vertical direction. When a window-address range is specified, data are written in the window-address range specified within the GRAM in accordance with I/D1-0 and AM setting. I/D[1:0]: I/D sets automatic increment (+1) and automatic decrement (-1) of address counter (AC) after data are written to GRAM. When I/D=0, the address counter is incremented or decremented in horizontal direction (lower address: AD7-0). When I/D =1, the address counter is incremented or decremented in vertical direction (upper address: AD16-8). The AM bit specifies the address transition direction when data are being written to GRAM.

Rev.0.5, July.31.2003, page 39 of 196 HWM: When HWM =1, data are written to GRAM in high speed with low power consumption. In power saving high-speed write mode, the data in the horizontal line of rectangular area specified by the window address are stored in the line buffer and one-line data are written to GRAM at once. This minimizes the number of RAM access required to write data and thereby reduces power consumption. When HWM =1, the data write in horizontal direction must be executed by line of the specified window- address range. If data write is terminated in the middle of the line, data in that line are not correctly written to GRAM. Note 1) Insertion of dummy write is not required in high-speed write mode. Note 2) Data in the buffer will be erased if RAM write is terminated in the middle of a line and other instruction set is executed. Note 3) In the high-speed write mode, wait at least 2 write cycles (tcycw) of the normal write mode after RAM write before making a transition from RAM write to index write. BGR: Change the order of (R), (G), (B) dots to (B), (G), (R) when the dots are assigned to the 18-bit write data. BGR=0, the dot order (R), (G), (B) is not changed when 18-bit data are written to GRAM. BGR =1, the dot order changes from (R), (G), (B) to (B), (G), (R) when 18-bit data are written to GRAM. The assignment of α bit of OSD data is also changed. DFM: Set the data format for 3-RAM-write 18-bit data transfers in 80-system 8-bit interface (big-endian) mode when IM3-0 = GND/GND/ Vcc1/Vcc1 in conjunction with TRI. DFM =0, RGB 18-bit data are written to GRAM by byte-boundary 3 transfers. DFM =1, RGB 18-bit data are written to GRAM by 3 x 6-bit transfer. Set the data format for 2-RAM-write 18-bit data transfers in 80-system 16-bit interface mode when IM3-0 = GND/GND/Vcc1/GND in conjunction with TRI. DFM =0, RGB 18-bit data are written to GRAM in the MSB format by 2 transfers. DFM =1, RGB 18-bit data are written to GRAM in the LSB format by 2 transfers. DFM must be set to 0, when not using 8- or16-bit interface. TRI: Make the 3-RAM-write transfers available in 80-system 8-bit interface (big-endian) when IM3-0 = GND/GND/Vcc1/Vcc1. TRI =0, 16-bit RAM data are transferred in 2 transfers. TRI =1, 18-bit RAM data are transferred in 3 transfers. Make the 2-RAM-write transfers available in 80-system 16-bit interface (big-endian) when IM3-0 = GND/GND/Vcc1/GND. TRI =0, 16-bit RAM data are transferred in one transfer. TRI =1, 18-bit RAM data are transferred in 2 transfers. TRI must be set to 0, when not using 8- or 16-bit interface. During RAM read, set TRI = 0.

Rev.0.5, July.31.2003, page 40 of 196 GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Assignment 1st transmission 2nd tr ansmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1st transmission 3rd transmission RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 80 system 8-bit interface (3 transmissions/pixel) 262,144 colors transmission2nd GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1st transmission 3rd transmission RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 80 system 8-bit interface (3 transmissions/pixel) 262,144 colors transmission2nd 80 system 8-bit interface(big endian) (2 trannsmissions/pixel) 65,536 colors TRI DFM 0 * 0 * 1 0 8-bit interface RAM write transmission formula IM3-0 = (GND, GND, Vcc1, Vcc1) IM3-0 = (GND, GND, Vcc1, Vcc1) IM3-0 = (GND, GND, Vcc1, Vcc1) 1 1 GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Assignment 2nd transmission 1st tr ansmission 80 system 8-bit interface (little endian) (2 trannsmissions/pixel) 65,536 colors IM3-0 = (GND, Vcc1, Vcc1, Vcc1) 8-bit interface: RAM write transmission Note 1) Instruction setting is transferred by 2 x 8-bit transmissions regardless of TRI and DFM settings.

Rev.0.5, July.31.2003, page 41 of 196 GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Assignment 1st transmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 2nd transmission RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 80 system 16 -bit interface (2 transmissions/pixel) 262,144 colors transmission1st 80 system 16 -bit interface (2 transmissions/pixel) 262,144 colors 80 system 16-bit interface (1 trannsmission/pixel) 65,536 colors TRI DFM 0 * 1 0 1 1 16-bit interface RAM write transmission formula GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1st transmission RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B 0 transmission2nd 17 16 16-bit interface: RAM write transmission Note 1) Instruction setting is transferred by 1 x 16-bit transmission regardless of TRI and DFM settings. I/D1-0 = “00” Horizontal: Decrement Vertical: Decrement I/D1-0 = “01” Horizontal: Increment Vertical: Decrement I/D1-0 = “10” Horizontal: Decrement Vertical: Increment I/D1-0 = “11” Horizontal: Increment Vertical: Increment Direction Setting AM = “0” Horizontal AM = “1” Vertical 17’00000 17’h19FEF 17’00000 17’h19FEF 17’00000 17’h19FEF 17’00000 17’h19FEF 17’00000 17’h19FEF 17’00000 17’h19FEF 17’00000 17’h19FEF 17’00000 17’h19FEF Address direction setting Note 1) When a window-address range is specified, write operation is executed only within the specified window-address range of GRAM.

Rev.0.5, July.31.2003, page 42 of 196 Resizing Control 1/2 (R004/R005h) RSR[1:0]: Set the contraction scale which is applied during RAM write. When the resizing scale is set, data are written to RAM according to this bit scale in horizontal and vertical directions. See the “Resizing Function” (p.105) section for details. RCH[1:0]: RCH specifies the number of surplus pixels in the horizontal direction, which are made after resizing a picture. By specifying the number of surplus pixels, it is possible to disregard the surplus pixels when data are transferred. This instruction is only available with resizing function. Set RCH = 2’h0 when resizing function is not used (RSR = 2’h0). RCV[1:0]: RCV specifies the number of surplus pixels in the vertical direction, which are made after resizing a picture. By specifying the number of surplus pixels, it is possible to disregard the surplus pixels when data are transferred. This instruction is only available with resizing function. Set RCV = 2’h0 when resizing function is not used (RSR = 2’h0). RSEH: Set the magnifying scale in the horizontal direction of a picture. When the magnifying scale is set, data are written to RAM according to the bit scale in horizontal direction. See “Resizing Function” for details. RSEV[7:0]: Set magnifying scale in the vertical direction of a picture. When the magnifying scale is set, the data in the internal RAM are magnified when displayed. Note 1) When using picture magnification function, the picture re sizing scale register (contraction) must be RSR1-0 = 2’h0. Note 2) When using picture contraction function, the picture resizing scale (magnification) must be set RSEV7-0 = 8’h00, RSEH = 0. Note 3) Base picture scrolling function and vertical-direction display magnification function cannot be used simultaneously. Settings for resizing scales Table 10 Resizing scale ratio setting (RSR) RSR[1:0] Resizing scale 2’h0 No resizing (x 1) 2’h1 x 1/2 2’h2 Setting disabled 2’h3 x 1/4 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 RCV 0 00 0 RSR1 RSR00 RCV RCH1 RCH0 0 W 1 RSE RSE RSE RSE RSE RSE V0 00 0 0 RSEHRSE RSE V1 0 0 0

Rev.0.5, July.31.2003, page 43 of 196 Table 11 Setting for the number of surplus pixel in the horizontal/vertical direction (RCV, RCH) RCH [1:0] / RCV [1:0] Number of pixel surplus in horizontal/vertical direction 2’h0 0 pixel 2’h1 1 pixel 2’h2 2 pixels 2’h3 3 pixels Note 1) 1 pixel = 1RGB Table 12 magnification in horizontal direction (RSEH) RSEH Magnification 2’h0 No resizing (x1) 2’h1 2 times (x2) Table 13 BASE picture magnification in the vertical direction (RSEV) RSEV [1:0] Magnification 2’h0 No resizing (x1) 2’h1 2 times (x2) 2’h2 Setting disabled 2’h3 Setting disabled Table 14 OSD image 1 magnification in the vertical direction (RSEV) RSEV [3:2] Magnification 2’h0 No resizing (x1) 2’h1 2 times (x2) 2’h2 4 times (x4) 2’h3 Setting disabled Table 15 OSD image 2 magnification in the vertical direction (RSEV) RSEV [5:4] Magnification 2’h0 No resizing (x1) 2’h1 2 times (x2) 2’h2 4 times (x4) 2’h3 Setting disabled

Rev.0.5, July.31.2003, page 44 of 196 Table 16 OSD image 3 magnification in the vertical direction (RSEV) RSEV [7:6] Magnification 2’h0 No resizing (x1) 2’h1 2 times (x2) 2’h2 4 times (x4) 2’h3 Setting disabled Display Control 1 (R007h) D[1:0]: The graphics display is shown when D[1] = 1, and turned off when D[1] = 0. When setting D[1] = 0, the data are retained in GRAM. This means the graphics display is instantly shown when setting D[1] to 1. When D[1] is 0 (i.e. the display is not shown) all source outputs are set to the GND level. This reduces the charged/discharged current on LCD, which is generated during liquid crystal alternate drive. When D= 2’b01, the display operation is being executed inside the HD66781 even while the external display is turned off. When D = 2’b00, both internal and external display operations are halted. In combination with GON and DTE bits, D1-0 bits control ON/OFF of display. For details, see the “Instruction Setting”(p.185) section. Table 17 D[1:0] Source output HD66781 internal operation Gate control signal/Power supply IC, LCD panel control signal (FLM, CL1/SFTCLK1, 2, DCCLK, EQ) 2’h0 GND Halt Halt 2’h1 GND Continue Continue 2’h2 Non-lit display Continue Continue 2’h3 Display Continue Continue Note 1) Data from the microcomputer can be written to GRAM irrespective of D bit setting. Note 2) D = 2’h00 during the standby mode. In this case, the register setting of D bit is not changed. Note 3) A picture displayed when D = 2’b11 is specified by the BASEE setting. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 OSD OSD E1 0OSD E0 0 BASE E 0000 0 DTE 0 0 D1 D0

Rev.0.5, July.31.2003, page 45 of 196 DTE: Control the DISPTMG output. Table 18 DTE DISPTMG

0 GND

1 Vcc1/GND

BASEE: Set display enable of a base image. The D-bit setting takes precedence over the BASEE-bit setting. Table 19 D[1:0] BASEE Source Output (S1~S720) 2’h0 * GND 2’h1 * GND 2’h2 * Non-lit level

0 Non-lit display

2’h3

1 Display BASE image

Note 1) The source output at the “non-lit display” level is determined according to the PTS bit setting. Note 2) Gate lines are scanned in the manner determined by the PTS bit setting during the non-lit display. OSDE0: Display enable bit for OSD image 1. OSDE1: Display enable bit for OSD image 2. OSDE2: Display enable bit for OSD image 3. OSDE0/OSDE1/OSDE2 = 0, the HD66781 does not display OSD images. Only base images are displayed. OSDE0/OSDE1/OSDE2 = 1, the HD66781 displays OSD images according to the α channel bits in the pixel data of the OSD image. When OSDE =1, while a base image is not displayed (BASEE =0), an OSD is displayed with 100% transmission rate.

Rev.0.5, July.31.2003, page 46 of 196 Display Control 2 (R008h) FP [3:0]: Set the number of lines for a front porch (a blank period made before the end of display). BP [3:0]: Set the number of lines for a back porch (a blank period made after the beginning of display). In the external display interface mode, a back porch (BP) period starts at the falling edge of VSYNC and display operation starts after the back porch period. A front porch (FP) period starts after the numbers of raster-rows set with NL bit are driven for display. After the front porch period, a blank period continues until the next VSYNC input. Table 20 FP [3:0] BP [3:0] Number of Front porch line Number of Back porch line 4’h0 Setting disabled 4’h1 Setting disabled 4’h2 2 lines 4’h3 3 lines 4’h4 4 lines 4’h5 5 lines 4’h6 6 lines 4’h7 7 lines 4’h8 8 lines 4’h9 9 lines 4’hA 10 lines 4’hB 11 lines 4’hC 12 lines 4’hD 13 lines 4’hE 14 lines 4’hF Setting disabled Set BP, FP, and MP within the range indicated below. Table 21 FLD = 2’h1 BP ≥ 2 lines FP ≥ 2 lines FP+BP ≤ 16 lines Internal clock operation FLD = 2’h3 BP = 3 lines FP = 5 lines RGB interface BP ≥ 2 lines FP ≥ 2 lines FP+BP ≤ 16 lines VSYNC interface BP ≥ 2 lines FP ≥ 2 lines FP+BP = 16 lines R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 FP1 0 0 FP0 00 0FP3 FP2 0 BP3 BP2 BP1 BP0 Back porch Front porch Display Area Note: The output timing to the LCD panel is delayed by 2 lines in relation to the input-synchronizing signal VSYNC

Rev.0.5, July.31.2003, page 47 of 196 Display Control 3 (R009h) ISC [3:0]: Specify the cycle to scan gate lines, when PTG bits set the scan mode in the non-display area to the interval scan mode. The scan cycle is always odd number of frames, and polarity inversion is applied each timing when gate lines are scanned. Table 22 ISC [3:0] Scan cycle When (fFLM) = 60Hz 4’h0 Setting disabled - 4’h1 3 frames 50ms 4’h2 5 frames 84ms 4’h3 7 frames 117ms 4’h4 9 frames 150ms 4’h5 11 frames 184ms 4’h6 13 frames 217ms 4’h7 15 frames 251ms 4’h8 17 frames 284ns 4’h9 19 frames 317ms 4’hA 21 frames 351ms 4’hB 23 frames 384ms 4’hC 25 frames 418ms 4’hD 27 frames 451ms 4’hE 29 frames 484ms 4’hF 31 frames 518ms PTG [1:0]: Set the DISPTMG output to determine the gate bus line scan mode in non-display area. The setting is applied to all no-display areas and front/back porch periods of the entire panel. Table 23 PTG[1:0] DISPTMG output Gate output in non- display area Source output in non- display area 2’h0 Normal drive Normal scan PT setting 2’h1 GND VGL (fixed) PT setting 2’h2 Interval drive Interval scan PT setting 2’h3 Setting disabled - - Note 1) Set alternating drive to frame cycle when using interval scan. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 PTS1 0 0 PTS0 00 P T G 10 PTS2 PTG0 ISC3 ISC2 ISC1 ISC0

Rev.0.5, July.31.2003, page 48 of 196 PTS [2:0]: Determine the kind of source outputs in the no-display area, which is applied to the front/back porch periods and non-display area of partial display. When PTS [2] =1, the grayscale voltage generating amplifiers are halted except those for the V0 and V63 levels during no-display area drive period to reduce power consumption. Table 24 Non-display source output Non-display area Non-display area PTS[2:0] Positive polarity Negative polarity Operation of grayscale amplifier Step up clock frequency 3’h0 V63 V0 V0 to V63 DC0, DC1 setting 3’h1 Setting disabled Setting disabled - DC0, DC1 setting 3’h2 GND GND V0 to V63 DC0, DC1 setting 3’h3 Hi-Z Hi-Z V0 to V63 DC0, DC1 setting 3’h4 V63 V0 V0, V63 DC0, DC1 setting x 1/2 3’h5 Setting disabled Setting disabled - - 3’h6 GND GND V0, V63 DC0, DC1 setting x 1/2 3’h7 Hi-z Hi-z V0, V63 DC0, DC1 setting x 1/2 Note 1) Gate outputs in non-display area are controlled by the off-scan mode (PTG). Note 2) Grayscale amplifier operation halt and slowdown of step-up clocks are applied to the non-display area. Note 3) When DC[4:3]=2’h3, the frequency of step-up clocks in the non-display area are not slowed down half even if PTS[2:0] is set to 4, 6 or 7.

Rev.0.5, July.31.2003, page 49 of 196 Display Control 4 (R00Bh) FRCON: Make a setting for the FRC mode. Control on and off of the FRC mode. D16B: When FRCON=1, the FRC mode sets in. When COL[1:0]=2’h1 and the low-power display mode, where only 32 operational amplifiers are used, the FRC mode enables display with abundant colors. For details, see “low-power display mode”(p.169). Set D16B to 1 when using a 16-bit interface (one-transfer 16-bit interface, 2-transfer 8-bit interface, 16-bit SPI, RGB interfaces). Table 25 Interface mode FRCON D16B Colors 0 * 262,144 18-bit, 16-bit x2, 9-bit x2, 8-bit x3, RGB 18-bit, 6-bit x3 1 0 250,047 0 * 65,536 16-bit x1, 8-bit x2, SPI 1 1 64,512 Note 1) When the FRC mode is on, do not switch the interface mode settings (M, TRI, D16B registers) Note 2) When the FRC mode is on, 18-bit format data and 16-bit format data are not displayed simultaneously. COL[1:0]: When COL=2’h1, 32 grayscale operational amplifiers are halted. When making a setting, it must follow the setting sequence in the “Low Power Consumption Display Mode” section. When COL = 2’h2, 8-color mode sets in. When making a setting, it must follow the setting sequence in the “8-Color Display Mode” section. All operational amplifiers except V0 and V63 levels are halted for low power consumption display. Table 26 Available colors for display COL[1:0] Amplifiers in operation FRCON = 0 FRCON = 1 2’h0 64 262,144 colors/65,536 colors - 2’h1 32 32,768 colors 250,047 colors/64,512 colors 2’h2 2 8 colors - 2’h3 Setting disabled Setting disabled Setting disabled Note 1) When COL[1:0] =2’h1 and FRCON = 0, do not write data that correspond to the grayscale levels the amplifiers of which are halted. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 FRC ON D16 B 00 0 0 00 00 0 0 0 0 COL COL

Rev.0.5, July.31.2003, page 50 of 196 Table 27 grayscale level amplifiers in operation (when REV=0) COL[1:0] COL[1:0] amplifier 2’h0 2’h1 2’h2 GRAM data RGB amplifier 2’h0 2’h1 2’h2 GRAM data RGB V0 * * * 6’h00 6’h3F V32 * 6’h20 6’h1F V1 * 6’h01 6’h3E V33 * * 6’h21 6’h1E V2 * * 6’h02 6’h3D V34 * 6’h22 6’h1D V3 * 6’h03 6’h3C V35 * * 6’h23 6’h1C V4 * * 6’h04 6’h3B V36 * 6’h24 6’h1B V5 * 6’h05 6’h3A V37 * * 6’h25 6’h1A V6 * * 6’h06 6’h39 V38 * 6’h26 6’h19 V7 * 6’h07 6’h38 V39 * * 6’h27 6’h18 V8 * * 6’h08 6’h37 V40 * 6’h28 6’h17 V9 * 6’h09 6’h36 V41 * * 6’h29 6’h16 V10 * * 6’h0A 6’h35 V42 * 6’h2A 6’h15 V11 * 6’h0B 6’h34 V43 * * 6’h2B 6’h14 V12 * * 6’h0C 6’h33 V44 * 6’h2C 6’h13 V13 * 6’h0D 6’h32 V45 * * 6’h2D 6’h12 V14 * * 6’h0E 6’h31 V46 * 6’h2E 6’h11 V15 * 6’h0F 6’h30 V47 * * 6’h2F 6’h10 V16 * * 6’h10 6’h2F V48 * 6’h30 6’h0F V17 * 6’h11 6’h2E V49 * * 6’h31 6’h0E V18 * * 6’h12 6’h2D V50 * 6’h32 6’h0D V19 * 6’h13 6’h2C V51 * * 6’h33 6’h0C V20 * * 6’h14 6’h2B V52 * 6’h34 6’h0B V21 * 6’h15 6’h2A V53 * * 6’h35 6’h0A V22 * * 6’h16 6’h29 V54 * 6’h36 6’h09 V23 * 6’h17 6’h28 V55 * * 6’h37 6’h08 V24 * * 6’h18 6’h27 V56 * 6’h38 6’h07 V25 * 6’h19 6’h26 V57 * * 6’h39 6’h06 V26 * * 6’h1A 6’h25 V58 * 6’h3A 6’h05 V27 * 6’h1B 6’h24 V59 * * 6’h3B 6’h04 V28 * * 6’h1C 6’h23 V60 * 6’h3C 6’h03 V29 * 6’h1D 6’h22 V61 * * 6’h3D 6’h02 V30 * * 6’h1E 6’h21 V62 * 6’h3E 6’h01 V31 * 6’h1F 6’h20 V63 * * * 6’h3F 6’h00 *: amplifier in operation

Rev.0.5, July.31.2003, page 51 of 196 External Display interface Control 1 (R00Ch) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 RM 0 0 DM [1] DM [0] 0 0 RIM [1] RIM [0] RIM[1:0] Make settings for the RGB interface mode when the RGB interface is selected with DM and RM bits. The setting must be made before the display through an external display interface. Do not make changes to the setting during display. Table 28 RIM[1:0] RGB interface mode Colors 2’h0 18-bit RGB interface (1 transmission/pixel) 262,144 2’h1 16-bit RGB interface (1 transmission/pixel) 65,536 2’h2 6-bit RGB interface (3 transmission/pixel) 262,144 2’h3 Setting disabled - Note 1) The instruction register setting is made only through a system interface. Note 2) Data transfer and DOTCLK input must be by the RGB unit when a 6-bit RGB interface is selected. DM[1:0]: Set a display operation mode. An interface for display operation is selected by the DM setting. DM allows switching between the internal clock operation mode and the external display interface mode. Do not try to switch between the external interface modes (RGB-I/F and VSYNC-I/F). Table 29 DM[1:0] Display operation interface 2’h0 Internal clock operation 2’h1 RGB interface 2’h2 VSYNC interface 2’h3 Setting disabled- RM: Set a RAM access interface. RAM access is made only through the interface specified by the RM setting. Set RM to 1 when writing display data through the RGB interface. This setting is valid irrespective of the display operation mode. Changes in display data can be made by setting RM to 0, which enables RAM data overwrite through a system interface, even while the screens are displayed through the RGB interface mode. Table 30 RM Display operation interface

0 Internal clock operation/VSYNC interface

1 RGB interface

Rev.0.5, July.31.2003, page 52 of 196 As the following table shows, an optimum interface is selected for the kind of display by the external display interface control setting. Write display data during moving picture display (through RGB and VSYNC interfaces) in the high-speed write mode (HWM=1), which enables high-speed RAM access with low power consumption. Table 31 Kind of Display Operation mode RAM access setting (RM) Display operation mode (DM) still picture internal clock operation only system interface (RM = 0) internal clock operation (DM = 2’h0) moving picture RGB interface (1) RGB interface (RM = 1) RGB interface (DM = 2’h1) Write over still picture area during moving picture display RGB interface (2) system interface (RM = 0) RGB interface (DM = 2’h1) moving picture VSYNC interface system interface (RM = 0) VSYNC interface (DM = 2’h2) Note 1) The instruction register settings are made only through a system interface. Note 2) No switching between the RGB and VSYNC interfaces is made. Note 3) No change in the settings of RGB interface mode (RIM) is made during the RGB interface operation. Note 4) See “External Display Interface” for reference to the transition flows between the modes. Note 5) Use the RGB and VSYNC interfaces in the high-speed write mode (HWM =1). Internal clock mode: All display operations are controlled by signals generated by the internal clock in internal clock operation mode. All inputs through the external display interface are invalid. The internal RAM is accessible only through a system interface. RGB interface mode (1): Display operation is controlled by the frame synchronizing clock (VSYNC), line synchronizing signal (VSYNC), and dot clock (DOTCLK) in the RGB interface mode. These signals must be supplied throughout the display operation in this mode. All display data are stored in the internal RAM, transmitted through DB17-0 bits by pixel. The combination with the window address function enables simultaneous display of both moving picture areas and the internal RAM area. The data are transmitted only when the screen is being updated, thereby reducing the overall data transmission to minimum. The periods of the front (FP) and back (BP) porches and the display period (NL) are automatically generated in the HD66782 by counting the clock of line synchronizing signal (HSYNC) in accordance to the frame synchronizing signal (VSYNC). Transmit pixel data through DB17-0 bits in accordance with the aforementioned setting. RGB interface mode (2): When RGB-I/F is selected, RAM data are changeable through the system interface. This write operation must be performed while display data are not being transmitted through the RGB-I/F (ENABLE = High). When reverting from the system interface mode to the data transmission through the RGB interface, make a new setting for the address set and index (R202h) after changing the aforementioned settings.

Rev.0.5, July.31.2003, page 53 of 196 VSYNC interface mode: The internal display operation is synchronized with the frame-synchronizing signal (VSYNC) in the VSYNC interface mode. By writing data to RAM at a fixed speed on the falling edge of VSYNC, it enables moving pictures display with a system interface. In this case, there are some constraints in the RAM write speed and methods. For details, see “External Display Interface” (p.139). In the VSYNC-I/F mode, only VSYNC input is valid. Other input signals for the external display interface are invalid. The front porch (FP), back porch (BP) periods and display period (NL) are automatically generated in accordance to the frame synchronizing signal (VSYNC) according to the register setting of HD66781.

Rev.0.5, July.31.2003, page 54 of 196 Frame Cycle Control (R00Dh) RTNI[4:0]: Set IH (line) period. DIVI[1:0]: Set the division ratio of clocks for internal operations (DIV1-0). The internal operations are executed by the clocks, the frequency of which is divided according to the DIV1-0 setting. When changing the number of raster-rows to drive, adjust the frame frequency too. For details, see “Frame Frequency Adjustment Function”(p.178). Table 32 RTNI[3:0] clocks per line DIVI[1:0] division ratio internal operation clock frequency 5’h00 Setting disabled 2’h0 1/1 fosc / 1 : : 2’h1 1/2 fosc / 2 5’h0F Setting disabled 2’h2 1/4 fosc / 4 5’h10 16 clocks 2’h3 1/8 fosc / 8 5’h11 17 clocks 5’h12 18 clocks 5’h13 19 clocks 5’h14 20 clocks Note 1) fosc : R-C oscillation frequency 5’h15 21 clocks 5’h16 22 clocks 5’h17 23 clocks 5’h18 24 clocks 5’h19 25 clocks 5’h1A 26 clocks 5’h1B 27 clocks 5’h1C 28 clocks 5’h1D 29 clocks 5’h1E 30 clocks 5’h1F 31 clocks Formula for frame frequency fosc frame frequency = Number of clock per line x division ratio x (Line +FP+BP) [Hz] fosc : R-C oscillation frequency Line : Number of drive raster-rows (NL bit) division ration : DIVI bit clocks per line : RTNI bit R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 RTNI RTNI RTNI 0 0 0 0 0 0 DIVI1 DIVI0 RTNI RTNI

Rev.0.5, July.31.2003, page 55 of 196 External Display Interface Control 2 (R00Eh) RTNE[6:0]: Specify the number of clocks for internal operation per 1H (line). Set the value of the number of DOTCLK input in 1H period, divided by the division ratio. DIVE[1:0]: Set the internal division ratio of DOTCLK (DIVE). The internal operation is executed according to the clocks divided by the division ratio set by DIVE. Table 33 RTNE[6:0] Clocks per line DIVE[1:0] Division Internal operation clock frequency 7’h00 Setting disabled 2’h0 Setting disabled : : 2’h1 1/4 fdotclk / 4 7’h0F Setting disabled 2’h2 1/8 fdotclk / 8 7’h10 16 clocks 2’h3 1/16 fdotclk / 16 7’h11 17 clocks fdotclk: DOTCLK frequency 7’h12 18 clocks : : 7’h7D 125 clocks 7’h7E 126 clocks 7’h7F 127 clocks External Display Interface Control 3 (R00Fh) DPL: Specify the polarities of signals on DOTCLK pin. DPL=0: Input data on a rising edge of DOTCLK. DPL=1: Input data on a falling edge of DOTCLK. EPL: Specify the polarities of signals on ENABLE pin. EDL = 0 Data are written to PD17 to PD 0 when ENABLE = 0. No data are written when ENABLE = 1. EDL = 1 Data are written to PD17 to PD 0 when ENABLE = 1. No data are written when ENABLE = 0. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 DIVE 100 0 DIVE 0 0 RTNE RTNE RTNE RTNE RTNE RTNE RTNE R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 0 0 00 0 0 0 0 0 VSPL HSPL 0 EPL DPL

Rev.0.5, July.31.2003, page 56 of 196 HSPL: Specify the polarities of signals on HSYNC pin. HSPL=0: Low active. HSPL=1: High active. VSPL: Specify the polarities of signals on VSYNC pin. VSPL=0: Low active. VSPL=1: High active. Gate Driver/LTPS LCD Panel Interface Control 1 (R010h) FTI[2:0]: FTI bits specify the rising position of FLM during display operation with internal clocks (DM = 2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the rising position of FLM is at a reference point. FWI[4:0]: FWI bits specifies the width of “High” of FLM during display operation with internal clocks (DM = 2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the width of “High” of FLM is 1H. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 34 FTI[2:0] FLM Rising position FWI[4:0] FLM “High” width 2’h0 0 clock 5’h00 0 clock 2’h1 1 clock 5’h01 1 clock 2’h2 2 clocks 5’h02 2 clocks 2’h3 3 clocks 5’h03 3 clocks : : 5’h1D 29 clocks 5’h1E 30 clocks 5’h1F 31 clocks Note 1) The clocks in the tables are measured from the reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 FWI FWI FWI FWI 4 0 FWI 0 00 0 0 0 FTI2 FTI1 FTI0

Rev.0.5, July.31.2003, page 57 of 196 Gate Driver/LTPS LCD Panel Interface Control 2 (R011h) STI[1:0]: STI bits specifies the rising position of SFTCLK1/2 during display operation with internal clocks (DM = 2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the rising position of CL1 is 8 clocks away from a reference point. SWI[4:0]: SWI bits specifies the width of “High” of SFTCLK1/2 during display operation with internal clocks (DM = 2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 35 STI[1:0] CL1/SFTCLK1, 2 Rising position SWI[4:0] CL1/SFTCLK1, 2 “High” width 2’h0 0 clock 5’h00 0 clock 2’h1 1 clock 5’h01 1 clock 2’h2 2 clocks 5’h02 2 clocks 2’h3 3 clocks 5’h03 3 clocks : : 5’h1D 29 clocks 5’h1E 30 clocks 5’h1F 31 clocks Note 1) The clocks in the tables are measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 SWI SWI SWI SWI 4 0 SWI 0 00 0 00 0 S T I 1 S T I 0

Rev.0.5, July.31.2003, page 58 of 196 Gate Driver/LTPS LCD Panel Interface Control 3 (R012h) SDTI[1:0]: Specify the delay from a reference point of the source output during display operation with internal clocks (DM = 2’h0 or 2’h2). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 36 SDTI[1:0] Source output delay 2’h0 1 clock 2’h1 2 clocks 2’h2 3 clocks 2’h3 4 clocks Note 1) The clocks in the tables are measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 0 0 00 0 0 0 0 0 00 0 SDTI SDTI

Rev.0.5, July.31.2003, page 59 of 196 Gate Driver/LTPS LCD Panel Interface Control 4 (R013h) DPTI[1:0]: Specify the rising position of DISPTMG during display operation with internal clocks (DM = 2’h0 or 2’h2). DPWI[4:0]: DPWI bits specifies the width of “High” of DISPTMG during display operation with internal clocks (DM = 2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 37 DPTI[1:0] DISPTMG Rising position DPWI[4:0] DISPTMG “High” width 2’h0 0 clock 5’h00 0 clock 2’h1 1 clock 5’h01 1 clock 2’h2 2 clocks 5’h02 2 clocks 2’h3 3 clocks 5’h03 3 clocks : : 5’h1D 29 clocks 5’h1E 30 clocks 5’h1F 31 clocks Note 1) The clocks in the tables are measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Note 2) The gate non-overlap period can be set to 0 when DPTI = “2’h0” and DPWI is set to the number of clocks more than that of the 1H period. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 DPW DPW DPW DPW I4 0 DPW I0 00 0 00 0 DPTI DPTI

Rev.0.5, July.31.2003, page 60 of 196 Gate Driver/LTPS LCD Panel Interface Control 5 (R015h) EQWI[1:0]: Specify the width of “High” of EQ during display operation with internal clocks (DM = 2’h0 or 2’h2). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Also see “Equalizing Function” for details on equalization. Table 38 EQWI[1:0] EQ “High” width 2’h0 0 clock 2’h1 1 clock 2’h2 2 clocks 2’h3 3 clocks Note 1) The clocks in the tables are measured from the source output alternating point. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 0 EQW I1 00 0 EQW I0 00 0 0 0 0 0 0

Rev.0.5, July.31.2003, page 61 of 196 Gate Driver/LTPS LCD Panel Interface Control 6 (R016h) FTE[2:0]: FTE bits specifies the rising position of FLM during display operation with DOTCLK (DM = 2’h1) when LTPS = 1. The setting of this register setting is invalid when LTPS = 0. In this case, the rising position of FLM is at a reference point. FWE[5:0]: FWE bits specifies the width of “High” of FLM during display operation with DOTCLK (DM = 2’h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the width of “High” of FLM is 1H. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 39 FTE[2:0] FLM Rising position FWE[5:0] FLM “High” width 3’h0 0 clock 6’h00 0 clock 3’h1 1 clock 6’h01 1 clock 3’h2 2 clocks 6’h02 2 clocks 3’h3 3 clocks 6’h03 3 clocks 3’h4 4 clocks : : 3’h5 5 clocks 6’h3D 61 clocks 3’h6 6 clocks 6’h3E 62 clocks 3’h7 7 clocks 6’h3F 63 clocks Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 FWE FWE FWE FWE FWE 4 0 FWE 0 00 0 00 FTE2 FTE1 FTE0

Rev.0.5, July.31.2003, page 62 of 196 Gate Driver/LTPS LCD Panel Interface Control 7 (R017h) STE[2:0]: STE bits specifies the rising position of SFTCLK1/2 during display operation with DOTCLK (DM = 2’h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the rising position of CL1 is 8 clocks away from a reference point. SWE[5:0]: SWE bits specifies the width of “High” of SFTCLK1/2 during display operation with DOTCLK (DM = 2’h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 40 STE[2:0] CL1/SFTCLK1,2 Rising positi on SWE[5:0] CL1/SFTCLK1,2 “High” width 3’h0 0 clock 6’h00 0 clock 3’h1 1 clock 6’h01 1 clock 3’h2 2 clocks 6’h02 2 clocks 3’h3 3 clocks 6’h03 3 clocks 3’h4 4 clocks : : 3’h5 5 clocks 6’h3D 61 clocks 3’h6 6 clocks 6’h3E 62 clocks 3’h7 7 clocks 6’h3F 63 clocks Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 SWE SWE SWE SWE SWE 4 0 SWE 0 00 0 0 0 STE2 STE1 STE0

Rev.0.5, July.31.2003, page 63 of 196 Gate Driver/LTPS LCD Panel Interface Control 8 (R018h) SDTE[2:0]: Specify the delay from a reference point of the source output during display operation with DOTCLK (DM = 2’h1). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 41 SDTE[2:0] Source output delay 3’h0 1 clock 3’h1 2 clocks 3’h2 3 clocks 3’h3 4 clocks 3’h4 5 clocks 3’h5 6 clocks 3’h6 7 clocks 3’h7 Setting disabled Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 0 0 00 0 0 0 0 0 0 0 SDTE SDTE SDTE

Rev.0.5, July.31.2003, page 64 of 196 Gate Driver/LTPS LCD Panel Interface Control 9 (R019h) DPTE[2:0]: Specify the rising position of DISPTMG during display operation with DOTCLK (DM = 2’h1). DPWE[5:0]: DPWE specifies the width of “High” of DISPTMG during display operation with DOTCLK (DM = 2’h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 42 DPTE[2:0] DISPTMG Rising position DPWE[5:0] DISPTMG “High” width 3’h0 0 clock 6’h00 0 clock 3’h1 1 clock 6’h01 1 clock 3’h2 2 clocks 6’h02 2 clocks 3’h3 3 clocks 6’h03 3 clocks 3’h4 4 clocks : : 3’h5 5 clocks 6’h3D 61 clocks 3’h6 6 clocks 6’h3E 62 clocks 3’h7 7 clocks 6’h3F 63 clocks Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Note 2) The gate non-overlap period can be set to 0 when DPTI = “2’h0” and DPWI is set to the number of clocks more than that of the 1H period. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 DPW DPW DPW DPW DPW E4 0 DPW E0 00 0 0 0 DPTE DPTE DPTE

Rev.0.5, July.31.2003, page 65 of 196 Gate Driver/LTPS LCD Panel Interface Control 10 (R01Bh) EQWE[2:0]: Specify the width of “High” of EQ DISPTMG during display operation with DOTCLK (DM = 2’h1). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Also see “Equalizing Function” for details on equalization. Table 43 EQWE[2:0] EQ “High” width 3’h0 0 clock 3’h1 1 clock 3’h2 2 clocks 3’h3 3 clocks 3’h4 4 clocks 3’h5 5 clocks 3’h6 6 clocks 3’h7 7 clocks Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from the source output change. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 00 0 EQW EQW E20 0 EQW E0 00 0 0 0 0 0 0

Rev.0.5, July.31.2003, page 66 of 196 1H period DPT DISPTMG Source output delay (SDT) Sn Equalization period (EQW) EQ M (Vcom) 1H period FLM CL1 8 clocks gate non-overlap period Note: The figure shows waveforms for 1-line inversion AC drive. Reference point Output waveforms of a-Si TFT panel (LTPS = 0)

Rev.0.5, July.31.2003, page 67 of 196 DPT DISPTMG Sn EQ M (Vcom) SFTCLK1 FLM SFTCLK2 ST SW ST SW FT FW 1H period Source output delay (SDT) Equalization period (EWQ) Note: The figure shows waveforms for 1-line inversion AC drive. Reference point 1H period Output waveforms of low-temperature poly-Si TFT panel (LTPS = 1)

Rev.0.5, July.31.2003, page 68 of 196 Power control 1 (R100h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 DC DC 3 0 0 0 SAP SAP SAP 0 0 AP AP AP 0 0 DS TB SLP STB STB: When STB = 1, the HD66781 enters into the standby mode. In the standby mode, display operation is completely halted, and all internal operations including the internal R-C oscillator and reception of external clock pulse, are halted. Only instructions to release from the standby mode (STB = 0) and to start oscillation are accepted during the standby mode. In the standby mode, a serial transfer to the gate driver/power supply IC cannot be made and it requires retransfer after release from the standby mode. Also in the standby mode, any change in the GRAM data or instruction setting cannot be made, but GRAM data are retained. SLP: When SLP = 1, the HD66781 enters into the sleep mode. In the sleep mode, internal display operation is halted except the R-C oscillator to reduce current consumption. No change is made to the GRAM data or instructions during the sleep mode, and the GRAM data and the instructions are retained. DSTB: When DSTB = 1, the HD66781 enters into the deep standby mode, where the power supply for the internal logic is turned off to save more power than the standby mode. The GRAM data and the instruction setting are destroyed in the deep standby mode and it requires resetting after release from the deep standby mode. Also in the deep standby mode, a serial transfer to the gate driver cannot be made and it requires a retransfer after the release from the deep standby mode. AP[2:0]: Adjust the amount of constant current in the operational amplifier in the liquid crystal drive power supply. When the amount of constant current is set large, the liquid crystal drive capacity will be enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set AP[2:0] = “3’h0” to halt the operation of operational amplifier and step-up circuits to reduce the current consumption. Also if AP[2:0] is set to other than 0, the clock for the step-up circuit DCCLK is output. SAP[2:0]: Adjust the amount of constant current in the operational amplifier of source driver. When the amount of constant current is set large, the liquid crystal drive capacity is enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set SAP[2:0] = “3’h0” to halt the operation of operational amplifier and step-up circuits to reduce the current consumption. DC[4:3]: Select the frequency of clocks for the step-up circuit (DCCLK). If the DCCLK frequency is set high, display quality is enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration.

Rev.0.5, July.31.2003, page 69 of 196 Note: The AP[2:0] in the above description is the instruction bits for gate driver/power supply IC. The instruction setting in the AP[2:0] must be transferred to the gate driver/power supply IC before an instruction is executed. For details, see “Gate driver/power supply IC Serial Transfer”. Table 44 SAP setting DC setting SAP[2:0] Current in the operational amplifier DC[4:3] DCCLK frequency 3’h0 operation halt : op-amp, step-up circuit 2’h0 Fosc / 4 3’h1 op-amp constant current flow rate : 0.65 2’h1 fosc / 8 3’h2 op-amp constant current flow rate : 0.80 2’h2 fosc / 16 3’h3 op-amp constant current flow rate : 1.00 2’h3 fosc / 32 3’h4 op-amp constant current flow rate : 1.35 3’h5 op-amp constant current flow rate : 1.60 3’h6 Setting disabled 3’h7 Setting disabled Note 1) The amount of current in the above table is shown as a ratio against that of SAP[2:0] = 3’h3 as 1.

Rev.0.5, July.31.2003, page 70 of 196 Gate Driver/ Power Supply IC Interface Control 1 (R110h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 TE 0 0 0 0 0 IDX IDX IDX R 1 0 0 0 0 0 0 0 TE 0 0 0 0 0 IDX IDX IDX Gate Driver/ Power Supply IC Interface Control 2 (R111h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 TB TB TB TB TB TB TB TB TB TB TB TB TB IDX[2:0]: The index register of the instruction, which is transferred to the gate driver/power supply IC. The instruction that corresponds to the index as determined by the IDX[2:0] setting is transferred to the gate driver or power supply IC through a serial interface for the gate/power supply IC. The following figures illustrates the bit array with which instructions are transferred. The upper 3 bits in the figures corresponds to the IDX[2:0] bits. The instructions of the indexes determined by the IDX[2:0]settings as below are transferred to the gate driver/power supply IC. When any change will be made to the instruction setting to the gate driver/power supply IC, the setting must be made first in the R111h register of HD 66781 before making a setting for IDX[2:0]. The transfer start (TE = 1) starts transferring the instructions, which is then followed by the execution. TE: The ENABLE for the serial transfer to the gate driver/power supply IC. TE=0 enables a serial transfer. TE=1 starts a transfer to the gate driver/power supply IC. When the transfer is completed, TE=0 is returned. A serial transfer takes 18 clocks at maximum (with reference to internal clocks). Do not make any changes to the instructions that are being transferred. Other instructions can be executable even during the instruction transfer. Note 1) The transfer of the NL[5:0], AP[2:0], FLD[1:0] settings to the gate driver/power supply IC must be made right after the instruction setting of HD66781. Make a same setting to the HD66781 and HD66783/HD667P21 with regard to NL, AP, FLD registers. Otherwise, a proper operation is not guaranteed. Note 2) As in the following figures, the bits to which no register is assigned must be overwritten with “0” or “1”.

Rev.0.5, July.31.2003, page 71 of 196 IDX2 IDX1 IDX0 TB12 TB11 TB10 TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 0 0 0 0 GON VCO MG BT[2] BT[1] BT[0] DC0 [2] DC0 [1] DC0 [0] AP [2] AP [1] AP [0] 0 0 0 1 0 DK 1 EQM 0 PON VRH [3] VRH [2] VRH [1] VRH [0] VC [2] VC [1] VC [0] 0 1 0 DC1 [2] DC1 [1] DC1 [0] VDV [4] VDV [3] VDV [2] VDV [1] VDV [0] VCM [4] VCM [3] VCM [2] VCM [1] VCM [0] 0 1 1 Setting disabled 1 0 0 Setting disabled 1 0 1 Setting disabled 1 1 0 GS NL [5] NL [4] NL [3] NL [2] NL [1] NL [0] SC N [5] SC N [4] SC N [3] SC N [2] SC N [1] SC N [0] 1 1 1 0 0 0 0 0 0 0 0 0 0 0 NL [1] NL [0] IDX2 IDX1 IDX0 TB12 TB11 TB10 TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 0 0 0 0 GON VCO MG BT[2] BT[1] BT[0] DC [2] DC [1] DC [0] AP [2] AP [1] AP [0] 0 0 0 1 0 0 0 0 0 PON VRH [3] VRH [2] VRH [1] VRH [0] VC [2] VC [1] VC [0] 0 0 1 0 1 0 DK [1] DK [0] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 VDV [4] VDV [3] VDV [2] VDV [1] VDV [0] VCM [4] VCM [3] VCM [2] VCM [1] VCM [0] 0 1 1 Setting disabled 1 0 0 Setting disabled 1 0 1 Setting disabled 1 1 0 Setting disabled 1 1 1 0 0 VGL [4] VGL [3] VGL [2] VGL [1] VGL [0] 0 VGH [4] VGH [3] VGH [2] VGH [1] VGH [0] HD66783 Instructions HD667P21 Instructions HD66783 / HD667P21 instructions Set data to transfer Write to R111h Index HD66781's registers No (transfer in procession) TE=”0” Yes (transfer allowed) Power-supply side index (IDX2-0) TE=”1” (start transfer) Set Index R110h Read instructions Specify IDX[2:0] that includes changed instruction bits in accordance to the instruction list of power-supply/gate drivers (HD66783) or power-supply IC(HD667P21). Serial transfer sequence: gate driver/power supply IC interface

Rev.0.5, July.31.2003, page 72 of 196 Setting examples 1. Set DC1[2:0], VDV[4:0], VCM of HD66783 to 3’h2, 5’h2, 5’h3 respectively. (1) Instruction set: R111h (2) Data write: 16’h0843 (DC1[2:0]=3’h2, VDV[4:0]=5’h2, VCM[4:0]=5’h3) (3) Instruction set: R110h (4) Data read: (make sure TE=0) (5) Data write: 16’h0102 (TE=1, IDX[2:0]=3’h2) 2. Set NL of HD66781 and HD66783 to 6’h20 (NL, AP, FLD are the registers that require a setting in both HD66781 and HD66783). (1) Instruction set: R400h (2) Data write: 16’h0020 (3) Instruction set: R111h (4) Data write: 16’h0800 (GS=0, NL[5:0]=6’h20, SCN[5:0]=6’h00) (5) Instruction set: R110h (6) Data read: (make sure TE=0) (7) Data write: 16’h0102 (TE=1, IDX[2:0]=3’h6) Note 1) Make a same setting to the HD66781 and HD66783 at one time. (1) and (2) are the setting for the HD66781. (3)~(7) are the setting for the HD66783.

Rev.0.5, July.31.2003, page 73 of 196 Common registers for HD66783 and HD667P21 BT[2:0]: Change the output scale of step-up circuits. Adjust the step-up scale according to the voltage in use. To set power consumption lower, it is necessary to set the step-up scale smaller. For details, see the datasheets of HD66783 and HD667P21. VCOMG: Make settings for the output level of VcomL. VCOMG = 0 The low-side output of Vcom is fixed to GND and the instruction (VDV) setting becomes invalid. Outputs from VcomL and VCL are halted. For this reason, the VCOMG setting is related to the power-supply startup sequence. Make a VCOMG setting by following the power-supply setting sequence. VCOMG = 1 The low-side output of Vcom becomes VcomL. The output voltage of VcomL is set by instruction (VDV) setting. VCOMG = 1 is valid when PON = 1. VC[2:0]: Adjust the reference voltages of VREG1OUT, VREG2OUT, and Vci1 voltages according to Vci as the reference voltage. For details, see the datasheets of HD66783 and HD667P21. VRH[3:0]: Set the amplifying scale of VREG1OUT with the values set in VC bits (REGP) as an input. For details, see the datasheets of HD66783 and HD667P21. VCM[4:0]: Make a setting for VcomH (the “High” of Vcom). VcomH can be amplified to VREG1OUT x 0.41 ~ 1.00. When VCM = 5’h01, VcomH is not adjusted by the internal volume adjustment but by an external resistor from VcomR. For details on whether to generate the VcomH level with internal electronic volume or an external resistor, see the datasheets of HD66783 and HD667P21. VDV[4:0]: Set the Vcom alternating amplitude. The setting is invalid without Vcom alternating drive. For details, see the datasheets of HD66783 and HD667P21. Registers of HD66783 AP[2:0]: Adjust the amount of constant current in the operational amplifier in the liquid crystal drive power supply. When the amount of constant current is set large, the liquid crystal drive capacity is enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set AP[2:0] = “3’h0” to halt the operation of operational amplifiers and step-up circuits to reduce the current consumption. To set AP[2:0] otherwise, it starts step-up circuits to output VGH. For details, see the datasheets of HD66783. DC0[2:0]: Select the operation frequency of step-up circuit 1. If the step-up operation frequency is set high, display quality will be enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration. For details, see the datasheets of HD66783. GON: When GON=0, the output level of G1~G320 pins of HD66783 becomes VGH and the Vcom level becomes GND.

Rev.0.5, July.31.2003, page 74 of 196 PON: Set start/halt of VGL, VCL operations. Set PON according to the power supply start sequence. PON=0: Halt PON=1: Start EQM: Select the operation mode of Vcom2 output. Set EQM = 0. DK: Control the start-up of DDVDH. See “Instruction Setting Flow” (p.185) for details on the setting. VCM[4:0]: Make a setting for VcomH (the High voltage of Vcom). VcomH can be amplified to the level VREG1OUT x 0.40 ~ 0.98. When VCM[4:0] = 5’h0F, internal volume is halted and VcomH is adjusted by an external resistor from VcomR. See the datasheet of HD66783 whether to generate VcomH level with internal electronic volume or an external resistor. DC1[2:0]: Select the operation frequency of step-up circuit 2. If the step-up operation frequency is set high, display quality will be enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration. See the datasheet of HD66783 for details. SCN[5:0]: Set the start position of scanning gate bus line. For details, see the datasheets of HD66783. NL[5:0]: Set the number of liquid crystal drive raster-rows. The number of raster-rows can be set to 8 multiples. The value should be set equal to or more than to drive the number of raster-rows required for the panel size. Note: Set SCN[5:0] and NL[5:0] to satisfy the following equation: (Output start position) + (Number of drive raster-rows) – 1 ≤ 320 (raster-rows) GS: Set the scan direction of gate bus lines. The direction is changeable according to the gate driver’s position on the assembly. For details, see the datasheets of HD66783. FLD[1:0]: Set the number of valid lines to drive n-line interlacing. For details, see the datasheets of HD66783. Registers of HD667P21 AP[2:0]: Adjust the amount of constant current in the operational amplifier in the liquid crystal drive power supply. When the amount of constant current is set large, the liquid crystal drive capacity will be enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set AP[2:0] = “3’h0” to halt the operation of operational amplifier and step-up circuits to reduce the current consumption. If AP[2:0] is set otherwise, it starts step-up circuit to output VLOUT1, VLOUT2. For details, see the datasheets of HD667P21. DC[2:0]: Select the operation frequency of step-up circuit 1. If the step-up operation frequency is set high, display quality will be enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration. For details, see the datasheets of HD66783. GON: When GON=0, the Vcom level becomes GND.

Rev.0.5, July.31.2003, page 75 of 196 PON: Set start/halt of VLOUT3 operation. Set PON according to the power supply start sequence. PON=0: Halt PON=1: Start VCM[4:0]: Make a setting for VcomH (the High voltage of Vcom). VcomH can be amplified to the level VREG1OUT x 0.41 ~ 1.00. When VCM[4:0] = 5’h1F, internal volume is halted and VcomH is adjusted by an external resistor from VcomR. See the datasheet of HD667P21 whether to generate VcomH level with internal electronic volume or an external resistor. VGH[4:0]: Set the VGH regulator output level. The setting can be made from 2.82 to 4.06 times of REGP voltage. VGL[4:0]: Set the VGL regulator output level. The setting can be made from –1.60 to –2.84 times of REGP voltage.

Rev.0.5, July.31.2003, page 76 of 196 RAM Address set in horizontal/vertical directions (R200h/R201h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 0 AD [7] AD [6] AD [5] AD [4] AD [3] AD [2] AD [1] AD [0] W 1 0 0 0 0 0 0 0 AD [16] AD [15] AD [14] AD [13] AD [12] AD [11] AD [10] AD [9] AD [8] Note : Top R200h, Bottom R201h AD[16:0]: Initialize GRAM address at AC (Address Counter). The address counter is automatically updated in accordance with AM, I/D settings after data are written to GRAM. Data can be written consecutively without making a new address setting. The address counter is not automatically updated when data are read out from GRAM. Table 45 GRAM address range AD[16:0] GRAM Setting 17’h00000 – 17’h000EF Bitmap data for G1 17’h00100 – 17’h001EF Bitmap data for G2 17’h00200 – 17’h002EF Bitmap data for G3 17’h00300 – 17’h003EF Bitmap data for G4 17’h00400 – 17’h004EF Bitmap data for G5 : : 17’h13F00 – 17’h13CEF Bitmap data for G317 17’h13F00 – 17’h13DEF Bitmap data for G318 17’h13F00 – 17’h13EEF Bitmap data for G319 17’h13F00 – 17’h13FEF Bitmap data for G320 Note 1) An address set is made every frame within the GRAM address range set by AD[16:0] at the falling edge of VSYNC when RGB interface (RM=1) is selected. Note 2) An address set is made when instructions are executed in the internal clock operation or the VSYNC interface mode (RM = 0). Note 3) Register values are loaded in both horizontal/vertical address counters when a setting is made for either one of the R200h/R201h registers.

Rev.0.5, July.31.2003, page 77 of 196 Write Data to GRAM (R202h) R/W RS W 1 The DB[17:0] pins are assigned to RAM write data (WD[17:0]) differently according to an interface. RGB interface The DB[17:0] pins are assigned to RAM write data (WD[17:0]) differently according to an interface . WD[17:0]: All data are expanded into 18 bits internally before being written to GRAM. The way of expanding data into 18 bits is different according to the interface. The grayscale level is selected according to the GRAM data. The address is automatically updated according to the setting with the AM and I/D bits after data are written to GRAM. During the standby mode, no access is allowed to GRAM. When the 8 or 16 bit interface modes are selected, the data in the MSB of R and B pixels are also written to the LSB of R and B pixels respectively to expand the 8/16- bit data into the 18-bit data internally. During the RGB interface mode, when writing data to RAM through a system interface, make sure to avoid conflicts between writing through the RGB interface and writing through system interface. When the 18-bit RGB interface is selected, the18-bit data in PD17-0 bits are written, and 262,144 colors are available. When the 16-bit RGB interface is selected, the data in the MSB of R and B pixels are also written to the LSB of R and B pixels respectively, and 65,536 colors are available. The upper 3 bits of OSD image data are used as a transmission-rate bit (α channel). Table 46 BGR = 0 OSD ODF D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 * R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 0 R5 R4 R3 R2 R1 α2 G5 G4 G3 G2 G1 α1 B5 B4 B3 B2 B1 α0 1 1 α2 α1 α0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Table 47 BGR =1 OSD ODF D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 * B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 R0 1 0 B5 B4 B3 B2 B1 α0 G5 G4 G3 G2 G1 α1 R5 R4 R3 R2 R1 α2 1 1 α0 α1 α2 B4 B3 B2 B1 B0 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0

Rev.0.5, July.31.2003, page 78 of 196 Table 48 α channel α2 α1 α0 transmission rate displayed picture 0 0 0 0% Base image display 0 0 1 Setting disabled 0 1 0 25% Base image 75%+OSD 25% 0 1 1 75% Base image 25%+OSD 75% 1 0 0 50% Base image 50%+OSD 50% 1 0 1 Setting disabled 1 1 0 100% OSD image display 1 1 1 Setting disabled input pins DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM write data WD [17 ] WD [16 ] WD [15 ] WD [14 ] WD [13 ] WD [12 ] WD [11 ] WD [10 ] WD [9 ] WD [8 ] WD [7 ] WD [6 ] WD [5 ] WD [4 ] WD [3 ] WD [2 ] WD [1 ] WD [0 ] RGB pixel assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF = 0 R5 R4 R3 R2 R1 G 5 G 4 G 3 G 2 G 1 B 5 B 4 B 3 B 2 B 1 α0 OSD data ODF = 1 α2 α1 α0 R5 R4 R3 R2 R1 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 18-bit interface (Base image:262,144 colors, OSD image: 32,768 colors) 9 0 α1α2 RAM data write in 18-bit interface (Base image 262,144 colors/OSD image 8,192 colors)

Rev.0.5, July.31.2003, page 79 of 196 Base image data format Input pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB picture Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R5 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B5 0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0]

210 R5 R4 R3 R2 R5 G5 G4 G3 G2 G1 B5 B4 B3 B2 B5

OSD image data format 1 (ODF = 0) Input pin GRAM Write data RGB picture Assignment Input pin GRAM Write data RGB picture Assignment OSD image data format 1 (ODF = 1) α α α αα α 16-bit interface 1 transmission TRI = 0, DFM = * (Base image: 65, 536 colors/OSD image: 8,192 colors) RAM data write in 16-bit interface (Base image 65,536 colors/OSD image 32,768 colors)

Rev.0.5, July.31.2003, page 80 of 196 input pins DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM write data WD [17 ] WD [16 ] WD [15 ] WD [14 ] WD [13 ] WD [12 ] WD [11 ] WD [10 ] WD [9 ] WD [8 ] WD [7 ] WD [6 ] WD [5 ] WD [4 ] WD [3 ] WD [2 ] WD [1 ] WD [0 ] RGB pixel assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF = 0 R5 R4 R3 R2 R1 α2 G5 G4 G3 G2 G1 α1 B5 B4 B3 B2 B1 α0 OSD data ODF = 1 α2 α1 α0 R5 R4 R3 R2 R1 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 16-bit interface 2 transmissions TRI = 1, DFM = 0 (Base image:262,144 colors, OSD image: 32,768 colors) 17 16 1st transmission 2nd transmission input pins DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM write data WD [17 ] WD [16 ] WD [15 ] WD [14 ] WD [13 ] WD [12 ] WD [11 ] WD [10 ] WD [9 ] WD [8 ] WD [7 ] WD [6 ] WD [5 ] WD [4 ] WD [3 ] WD [2 ] WD [1 ] WD [0 ] RGB pixel assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF = 0 R5 R4 R3 R2 R1 α2 G5 G4 G3 G2 G1 α1 B5 B4 B3 B2 B1 α0 OSD data ODF = 1 α2 α1 α0 R5 R4 R3 R2 R1 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 16-bit interface 2 transmissions TRI = 1, DFM = 1 (Base image:262,144 colors, OSD image: 32,768 colors) 2 1 2nd transmission1st transmission RAM data write in 16-bit interface (Base image 262,144 colors/OSD image 32,768 colors) 1st transmission (Upper) 2nd transmission (Lower) Input pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB picture Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1α α α αα α 9-bit interface (Base image 262,144 colors/OSD image 32,786 colors) RAM data write in 9-bit interface (Base image 262,144 colors /OSD image 32,768 colors)

Rev.0.5, July.31.2003, page 81 of 196 DB DB DB DB DB DB DB DB 10 DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 α2 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 DB DB DB DB DB DB DB DB 10 DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] α2 α1 α0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 α1 α0 1st transmission (Upper) 2nd transmission (Lower) Input pin GRAM Write data OSD data ODF = 0 1st transmission (Upper) 2nd transmission (Lower) Input pin GRAM Write data OSD data ODF = 0 OSD image data format (ODF = 1) OSD image data format (ODF = 0) DB DB DB DB DB DB DB DB 10 DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1st transmission (Upper) 2nd transmission (Lower) Input pin GRAM Write data RGB pixel Assignment 8-bit interface, 2 transmissions TRI = 0, DFM = * (Big endian) (Base image 65,536 colors/ OSD 8,192 colors) Base image data format RAM data write in 8-bit interface, big endian (Base image/OSD image)

Rev.0.5, July.31.2003, page 82 of 196 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 R5 R4 R3 R2 R1 α 2 G5 G4 G3 G2 G1 α 1 B5 B4 B3 B2 B1 α 0 α 2 α 1 α 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1st transmission 2nd transmission Input pin GRAM Write data OSD data ODF = 0 3rd transmission OSD data ODF = 1 RGB pixel assignment DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 R5 R4 R3 R2 R1 α 2 G5 G4 G3 G2 G1 α 1 B5 B4 B3 B2 B1 α 0 α 2 α 1 α 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1st transmission 2nd transmission Input pin GRAM Write data OSD data ODF = 0 3rd transmission OSD data ODF = 1 RGB pixel assignment 11 10 11 10 8-bit interface, 3 transmissions TRI = 1, DFM = 0 (Base image 262,144 colors/ OSD 32,768 colors) 8-bit interface, 3 transmissions TRI = 1, DFM = 1 (Base image 262,144 colors/ OSD 32,768 colors) RAM data write in 8-bit interface, 3 transmissions (Base image/OSD image)

Rev.0.5, July.31.2003, page 83 of 196 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 α2 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] α2 α1 α0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 α1 α0 transmission (Upper) 1st transmission (Lower) Input pin GRAM Write data OSD data ODF = 0 transmission (Upper) 1st transmission (Lower) Input pin GRAM Write data OSD data ODF = 0 OSD image data format (ODF = 1) OSD image data format (ODF = 0) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 transmission (Upper) 1st transmission (Lower) Input pin GRAM Write data RGB pixel Assignment 8-bit interface, 2 transmissions TRI = 0, DFM = * (Little endian) (Base image 65,536 colors/ OSD 8,192 colors) Base image data format 2nd 2nd 2nd RAM data write in 8-bit interface, little endian (Base image/OSD image)

Rev.0.5, July.31.2003, page 84 of 196 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 R5 R4 R3 R2 R1 α 2 G5 G4 G3 G2 G1 α 1 B5 B4 B3 B2 B1 α 0 α 2 α 1 α 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 Input pin GRAM Write data OSD data ODF = 0 OSD data ODF = 1 RGB pixel assignment RGB 18-bit interface (Base image 262,144 colors, OSD image 32,768 colors) Note : RAM write through RGB interface requires index register settings. RGB 18-bit interface (Base/OSD image display) Base image data format Input pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] RGB picture Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD image data format 1 (ODF = 0) Input pin GRAM Write data Input pin GRAM Write data OSD image data format 1 (ODF = 1) RGB 16-bit interface (Base image: 65, 536 colors/OSD image: 8,192 colors) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] R5 R4 R3 R2 R1 α2 G 5G 4G 3G 2G 1 α1B 5B 4B 3B 2B 1 α0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] R5 R4 R3 R2 R1α2 G5 G4 G3 G2 G1α1 B5 B4 B3 B2 B1α0 DB OSD data ODF = 0 OSD data ODF = 0 RGB 16-bit interface (Base/OSD image display)

Rev.0.5, July.31.2003, page 85 of 196 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 R5 R4 R3 R2 R1 α 2 G5 G4 G3 G2 G1 α 1 B5 B4 B3 B2 B1 α 0 α 2 α 1 α 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1st transmission 2nd transmission Input pin GRAM Write data OSD data ODF = 0 3rd transmission OSD data ODF = 1 RGB pixel assignment RGB 6-bit interface, 3 transmissions (Base image 266,144 colors/ OSD 32,768 colors) RGB 6-bit interface (Base/OSD image) Table 49 GRAM data and LCD output level (REV = 0) Selected grayscale level Selected grayscale level GRAM data RGB Positive Negative GRAM data RGB Positive Negative 6’h00 V0 V63 6’h20 V32 V31 6’h01 V1 V62 6’h21 V33 V30 6’h02 V2 V61 6’h22 V34 V29 6’h03 V3 V60 6’h23 V35 V28 6’h04 V4 V59 6’h24 V36 V27 6’h05 V5 V58 6’h25 V37 V26 6’h06 V6 V57 6’h26 V38 V25 6’h07 V7 V56 6’h27 V39 V24 6’h08 V8 V55 6’h28 V40 V23 6’h09 V9 V54 6’h29 V41 V22 6’h0A V10 V53 6’h2A V42 V21 6’h0B V11 V52 6’h2B V43 V20 6’h0C V12 V51 6’h2C V44 V19 6’h0D V13 V50 6’h2D V45 V18 6’h0E V14 V49 6’h2E V46 V17 6’h0F V15 V48 6’h2F V47 V16 6’h10 V16 V47 6’h30 V48 V15 6’h11 V17 V46 6’h31 V49 V14 6’h12 V18 V45 6’h32 V50 V13 6’h13 V19 V44 6’h33 V51 V12 6’h14 V20 V43 6’h34 V52 V11 6’h15 V21 V42 6’h35 V53 V10 6’h16 V22 V41 6’h36 V54 V9 6’h17 V23 V40 6’h37 V55 V8 6’h18 V24 V39 6’h38 V56 V7 6’h19 V25 V38 6’h39 V57 V6 6’h1A V26 V37 6’h3A V58 V5 6’h1B V27 V36 6’h3B V59 V4 6’h1C V28 V35 6’h3C V60 V3 6’h1D V29 V34 6’h3D V61 V2 6’h1E V30 V33 6’h3E V62 V1 6’h1F V31 V32 6’h3F V63 V0

Rev.0.5, July.31.2003, page 86 of 196 RAM Access through RGB-I/F and System I/F The HD66781 writes all display data to the internal RAM even in the RGB-I/F mode. Through the RGB- I/F mode, only the data for the moving picture area as well as for the frames to update screens can be transmitted. By writing data in the high-speed write mode (HWM = 1) and with the window address function, the HD66781 achieves high-speed access to RAM with low power consumption while displaying moving pictures. In the frames other than the moving picture screen update, the display data in the area other than the moving picture area can be updated through a system interface. RAM access is also possible through the system interface even in the RGB-I/F mode. In the RGB interface mode, data are written to RAM in synchronization with the DOTCLK input during ENABLE = “Low”. When writing data in the RGB-I/F mode through the system interface, it is necessary to set ENABLE “High” to stop writing through the RGB interface. After accessing RAM through the system interface, wait an enough time for the write/read bus cycle before starting RAM access through the RGB interface. In dex R22 Index R202 Address Set Data update in the area other than moving picture area Address Set RM= 1 Index R202 Updating moving pict ur e area Note 1) An address set is made every falling edge of VSYNC in the RGB interface mode. Note 2) An address set and an index set (R202h) must be made before RAM access through the RGB interface. No te 3) Write data in the high-speed write mode (HWM = 1) in the RGB interface mode. Moving picture are a 6/26/25 00: 00:0000 Moving picture are a 6/26/25 00: 00:0000 Note 1) Updat ing still picture area Updating moving picture area Screen update Screen update Updating still picture area while displaying a moving picture

Rev.0.5, July.31.2003, page 87 of 196 Read Data from GRAM (R202h) R/W RS R 1 RAM read data (RD[17:0]) are assigned differently to the DB[17:0] pins according to an interface . RD[17:0]: Read 18-bit data from GRAM. The RAM read data (RD[17:0]) are assigned differently to the DB[17:0] pins according to an interface. When data are read out from GRAM to the microcomputer, the first-word data read immediately after the GRAM address set are latched in the internal read-data latch, and the data in the data bus (DB17–0) are nullified. The data are read as valid data from the second word. When the 8-/16-bit interfaces are selected, the GRAM data in the LSBs of R and B pixels are not read out. When reading out OSD data, it takes the data format when ODF = 0. This function is not available in the RGB interface mode. Set TRI = 0 while data read is executed. 18-bit interface GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 16-bit interface GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB DB DB DB DB DB DB DB 10 DB DB DB DB DB DB DB DB Read data from GRAM: 18/16-bit interface

Rev.0.5, July.31.2003, page 88 of 196 9-bit interface (2 transmissions) GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB First transmission Second transmission 8-bit interface (2 transmissions(Big endian)/3 transmissions) GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB First transmission second transmission 8-bit interface (2 transmissions(Little endian)/3 transmissions) GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB First transmissionsecond transmission Read data from GRAM: 9/8-bit interface I/D,AM bit Setting HSA,HEA VSA, VEA Address set : N set First word Dummy read (void data) GRAM – read data latch Second word Read (data at address N) read data latch - DB17-0 Address set : Mset First word Dummy read (void data) GRAM – read data latch Second word Read (data at address N) read data latch - DB17-0 Read out data to microcomputer GRAM read sequence

Rev.0.5, July.31.2003, page 89 of 196 RAM Write Data Mask 1/2 (R203h/R204h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 WM [11] WM [10] WM [9] WM [8] WM [7] WM [6] 0 0 WM [5] WM [4] WM [3] WM [2] WM [1] WM [0] W 1 0 0 0 0 0 0 0 0 0 0 WM [17] WM [16] WM [15] WM [14] WM [13] WM [12] Note 1) Top R203, bottom R204 WM[17:0]: Write-mask data by bit when the data are written to GRAM. For example, if WM17 = 1, the WM17 write-mask the MSB of the data to write to GRAM so that the data in the MSB is not written to GRAM. The rest of WM16 ~ 0 bits also write-mask the data in the corresponding bits of GRAM write data as well when they are set to 1. The WM17-0 bits write-mask the 18-bit data to write to GRAM. Note 1) This function is not available in the RGB-I/F mode. Note 2) OSD image data are written to RAM in the ODF = 0 format. The write-mask setting for OSD images must be made for the ODF = 0 format. Write mask WM [17] WM [16] WM [15] WM [14] WM [13] WM [12] WM [11] WM [10] WM [9] WM [8] WM [7] WM [6] WM [5] WM [4] WM [3] WM [2] WM [1] WM [0] GRAM Write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0α αα RAM write data mask

Rev.0.5, July.31.2003, page 90 of 196 Window Address Control Instructions Window horizontal RAM address Start/End (R210h/ R211h) Window vertical RAM address Start/End (R212h/R213h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 5 0 W 1 00000000 HSA [7] HSA [6] HSA [5] HSA [4] HSA [3] HSA [2] HSA [1] HSA [0] R 5 1 W 1 00000000 HEA [7] HEA [6] HEA [5] HEA [4] HEA [3] HEA [2] HEA [1] HEA [0] R 5 2 W 1 0000000 VSA [8] VSA [7] VSA [6] VSA [5] VSA [4] VSA [3] VSA [2] VSA [1] VSA [0] R 5 3 W 1 0000000 VEA [8] VEA [7] VEA [6] VEA [5] VEA [4] VEA [3] VEA [2] VEA [1] VEA [0] HSA[7:0] Specify the start position of a window-address range in the horizontal direction by address. HEA[7:0] Specify the end position of a window-address range in the horizontal direction by address. Data are written to a rectangular area within GRAM from the address specified by HSA to the address specified by HEA. The setting of the address is required before writing data to RAM. Make sure the address is set to satisfy 8’h00≤ HSA< HEA ≤ 8’hEF and 8’h4≤ HEA - HSA. VSA[7:0] Specify the start position of a window-address range in the vertical direction to access to RAM. VEA[7:0] Specify the end position of a window-address range in the vertical direction to access to RAM. Data are written to a rectangular area within GRAM from the address specified by VSA to the address specified by VEA. The setting of addresses is required before writing data to RAM. Make sure the addresses are set to satisfy 9’h000≤ VSA< VEA ≤ 9’h19F. 17’h000-00 17’h19F-EF HSA HEA VSA VEA Window Address area Window-address range 8'h00 ҇ HSA< HEA ҇ 8'hEF, 8'h04҇ HEA - HSA, 9'h00҇VSA < VEA ҇ 9'h19F GRAM address map and window-address range Note 1) Set a window-address range within the GRAM address map. Note 2) In the high-speed write mode, data are written to GRAM by one horizontal line. Write data to GRAM by horizontal line unit. Note 3) Make an address set within the window address area. In the high-speed write mode, make an address set from the first line of the window address area.

Rev.0.5, July.31.2003, page 91 of 196 γ Control (R300h ~ R309h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R300 W 1 00000 PK P1[2] 00000 PK P0[2] PK P0[1] W 1 00000 PK P3[2] 00000 PK P2[2] PK P2[1] W 1 00000 PK P5[2] PK P5[1] PK P5[0] 00000 PK P4[2] PK P4[1] PK P4[0] W 1 00000 PR P1[2] PR P1[1] PR P1[0] 00000 PR P0[2] PR P0[1] PR P0[0] W 1 00000 PK N1[2] PK N1[1] PK N1[0] 00000 PK P0[2] PK P0[1] PK P0[0] W 1 00000 PK N3[2] PK N3[1] PK N3[0] 00000 PK N2[2] PK N2[1] PK N2[0] W 1 00000 PK N5[2] PK N5[1] PK N5[0] 00000 PK N4[2] PK N4[1] PK N4[0] W 1 00000 PR N1[2] 00000 PR N0[2] PR N0[1] PR N0[0] W1 0 0 0 VR P1[4] VR P1[3] VR P1[2] VR P1[1] VR P1[0] 0000 VR P0[3] VR P0[2] VR P0[1] VR P0[0] W1 0 0 0 VR N1[4] VR N1[3] VR N1[2] VR N1[1] VR N1[0] 0000 VR N0[3] VR N0[2] VR N0[1] VR N0[0] PK P1[1] PK P1[0] PR N1[1] PR N1[0] PK P3[1] PK P3[0] PK P0[0] PK P2[0] R301 R302 R303 R304 R305 R306 R307 R308 R309 PKP5-0[2:0]: γ fine adjustment registers for positive polarity PRP1-0[2:0]: γ gradient adjustment registers for positive polarity VRP(N)0[3:0]: amplitude adjustment resistor for positive polarity PKN5-0[2:0]: γ fine adjustment registers for negative polarity PRN1-0[2:0]: γ gradient adjustment registers for negative polarity VRP(N)1[4:0]: amplitude average adjustment resistor for negative polarity

Rev.0.5, July.31.2003, page 92 of 196 Base image display control instructions Number of Line (R400h) Base image display position (R401h) Base picture RAM Address (R402h) Base picture RAM Address (R403h) Vertical scroll Control (R404h) Base image expansion area/start line address (R405h) Base image expansion area/end line address (R406h) R /W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R400 W1 NL1 [5] NL1 [4] NL1 [3] NL1 [2] NL1 [1] NL1 [0] R401 W 1 00000000000000 VLE REV R402 W 1 0000000 BSA [8] BSA [7] BSA [6] BSA [5] BSA [4] BSA [3] BSA [2] BSA [1] BSA [0] R403 W 1 0000000 BEA BEA BEA BEA BEA BEA BEA BEA BEA R405 W 1 0000000 VL [8] VL [7] VL [6] VL [5] VL [4] VL [3] VL [2] VL [1] VL [0] R406 0000000000 ESA [8] ESA [7] ESA [6] ESA [5] ESA [4] ESA [3] ESA [2] ESA [1] ESA [0] EEA EEA EEA EEA EEA EEA EEA EEA EEA 0000000 0000000 R404 Base image control instructions NL0[5:0]: Set the number of liquid crystal drive raster-rows. The number of raster-rows can be set to 8 multiples. The GRAM address mapping is made irrespective of the value set for the number of raster-rows to drive liquid crystal. The value should be set equal to or more than to drive the number of raster-rows required for the panel size. REV: When REV = 1, a reverse display is shown within the display area. The grayscale level inversion enables to use same data to display on both normally white and normally black panels. The REV setting is effective for both OSD and base image areas. The source outputs during front and back porches and a blank period during partial display mode depend on the setting of PTS bits. Table 50 Source output level in display area REV0 GRAM data Positive polarity Negative polarity 18’h00000 V63 V0 : : : 0 18’h3FFFF V0 V63 18’h00000 V0 V63 : : : 1 18’h3FFFF V63 V0 Note 1) The source outputs during front and back porches and a blank period during partial display mode depend on the setting of PTS bits.

Rev.0.5, July.31.2003, page 93 of 196 VLE: When VLE = 1, settings for the vertical scroll display is made valid. The start line is displayed according to the VL[8:0] setting. The raster-rows that display a base image are scrolled by the number of lines set by VL bits. OSD area is not affected by the base-picture scrolling. This function is not available while external display interface is selected. While external display interface is selected, make sure that VLE= 0. Table 51 VLE Base image

0 Fixed display

1 Scrolling display

Note 1) Scroll function is not available during the interlaced drive (FLD = 2’h3) BSA[8:0]/BEA[8:0]: Set the start line address (BSA) and the end line address (BEA) of the base image display RAM area. Display RAM data from the one set at BSA bits from the first line. Make sure that base image display RAM area (BSA/BEA) is equal to or more than the number of raster-rows driving a panel (= NL ≤ BSA – BEA). In case of BSA – BEA ≤ NL, outside the base image area becomes non-lit display. VL[8:0] Set the number of raster-rows that are scrolled for a base image. The numbers of raster-rows set by VL bits are scrolled within the base image. ESA[8:0]/EEA[8:0] Set the start line address (ESA) and the end line address (EEA) of the area which is magnified in the base image display RAM area. A base image in the area specified with ESA and EEA is magnified on display. Make sure that BSA ≤ ESA ≤ EEA ≤ BEA. A magnified base image is not available with the scrolling function. Table 52 Liquid crystal drive raster-rows NL[5:0] Number of raster-rows NL[5:0] Number of raster-rows 6’h00 Setting disabled 6’h14 168 6’h01 16 6’h15 176 6’h02 24 6’h16 184 6’h03 32 6’h17 192 6’h04 40 6’h18 200 6’h05 48 6’h19 208 6’h06 56 6’h1A 216 6’h07 64 6’h1B 224 6’h08 72 6’h1C 232 6’h09 80 6’h1D 240 6’h0A 88 6’h1E 248 6’h0B 96 6’h1F 256 6’h0C 104 6’h20 264 6’h0D 112 6’h21 272 6’h0E 120 6’h22 280 6’h0F 128 6’h23 288 6’h10 136 6’h24 296 6’h11 144 6’h25 304 6’h12 152 6’h26 312 6’h13 160 6’h27 320

Rev.0.5, July.31.2003, page 94 of 196 OSD control instructions OSD image 1 display position (R500h) OSD image 1 RAM Address /Start line Address (R501h) OSD image 1 RAM Address /End line Address (R502h) OSD image 2 display position (R503h) OSD image 2 RAM Address/Start line Address (R504h) OSD image 2 RAM Address/End line Address (R505h) OSD image 3 display position (R506h) OSD image 3 RAM Address/Start line Address (R507h) OSD image 3 RAM Address/End line Address (R508h) R /W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R500 W 1 0000000 ODP 0 [8] ODP 0 [7] ODP 0 [6] ODP 0 [5] ODP 0 [4] ODP 0 [3] ODP 0 [2] ODP 0 [1] ODP 0 [0] R501 W 1 0000000 OSA 0 [8] OSA 0 [7] OSA 0 [6] OSA 0 [5] OSA 0 [4] OSA 0 [3] OSA 0 [2] OSA 0 [1] OSA 0 [0] R502 W 1 0000000 OEA 0 [8] OEA 0 [7] OEA 0 [6] OEA 0 [5] OEA 0 [4] OEA 0 [3] OEA 0 [2] OEA 0 [1] OEA 0 [0] R503 W 1 0000000 ODP 1 [8] ODP 1 [7] ODP 1 [6] ODP 1 [5] ODP 1 [4] ODP 1 [3] ODP 1 [2] ODP 1 [1] ODP 1 [0] R504 W 1 0000000 OSA 1 [8] OSA 1 [7] OSA 1 [6] OSA 1 [5] OSA 1 [4] OSA 1 [3] OSA 1 [2] OSA 1 [1] OSA 1 [0] R505 W 1 0000000 OEA 1 [8] OEA 1 [7] OEA 1 [6] OEA 1 [5] OEA 1 [4] OEA 1 [3] OEA 1 [2] OEA 1 [1] OEA 1 [0] R506 W 1 0000000 ODP 2 [8] ODP 2 [7] ODP 2 [6] ODP 2 [5] ODP 2 [4] ODP 2 [3] ODP 2 [2] ODP 2 [1] ODP 2 [0] R507 W 1 0000000 OSA 2 [8] OSA 2 [7] OSA 2 [6] OSA 2 [5] OSA 2 [4] OSA 2 [3] OSA 2 [2] OSA 2 [1] OSA 2 [0] R508 W 1 0000000 OEA 2 [8] OEA 2 [7] OEA 2 [6] OEA 2 [5] OEA 2 [4] OEA 2 [3] OEA 2 [2] OEA 2 [1] OEA 2 [0] ODP0[8:0]: ODP0 : Set the display position of OSD image 1. ODP1[8:0]: ODP1 : Set the display position of OSD image 2. ODP2[8:0]: ODP2 : Set the display position of OSD image 3. The display areas for OSD images 1, 2, 3 should not overlap one another. Set each area as follows. Display area of OSD image 1: ODP0, ODP0+(OEA0 – OSA0) Display area of OSD image 2: ODP1, ODP1+(OEA1 – OSA1) Display area of OSD image 3: ODP2, ODP2+(OEA2 – OSA2) Make sure that display area of OSD image 1 < Display area of OSD image 2 < Display area of OSD image 3. If ODP0 is set “9’h000”, OSD image 1 is displayed from the start line of the base image on the first panel. The OSD is not available during interlaced drive (FLD = 2’h3). OSA0[8:0] OEA0[8:0]: OSA0, OEA0 : Set the start line address and end line address for display RAM area of the OSD image 1.

Rev.0.5, July.31.2003, page 95 of 196 OSA1[8:0] OEA1[8:0]: OSA1, OEA1 : Set the start line address and end line address for display RAM area of the OSD image 2. OSA2[8:0] OEA2[8:0]: OSA2, OEA2 : Set the start line address and end line address for display RAM area of the OSD image 3.

Rev.0.5, July.31.2003, page 96 of 196 Instruction list Index Command IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 - Index 䋭 Index *** I D 1 0 I D 9 I D 8 I D 7 I D 6 I D 5 I D 4 I D 3 I D 2 I D 2 1 I D 0 SR Status Read 䋭 Status Read 0 0 0 0 0 0 0 L8 L7 L6 L5 L4 L3 L2 L1 L0 D e v i c e C o d e R e a d 0000011110000001 001h Driver Output Control 0 0 0 LTPS (0) 000 SS (0) 00000000 002h Liquid Crystal Drive Alternating Control 0000 FLD[1] (0) FLD[0] (1) B/C (0) EOR (0) 00 NW[5] (0) NW[4] (0) NW[3] (0) NW[2] (0) NW[1] (0) NW[0] (0) 003h Entry Mode TRI (0) DFM (0) 0 BGR (0) 00 HWM (0) 000 ID[1] (1) ID[0] (1) AM (0) 0 OSD (0) ODF (0) 004h Resizing Control (1) 0 0 0 0 0 0 RCV[1] (0) RCV[0] (0) 00 RCH[1] (0) RCH[0] (0) 00 RSR[1] (0) RSR[0] (0) 005h Resizing Control (2) RSEV[7] (0) RSEV[6] (0) RSEV[5] (0) RSEV[4] (0) RSEV[3] (0) RSEV[2] (0) RSEV[1] (0) RSEV[0] (0) 0000000 RSEH (0) 006h Setting Disabled 007h Display Control (1) 0 OSDE[2] (0) OSDE[1] (0) OSDE[0] (0) 000 BASEE (0) 000 DTE (0) 00 D[1] (0) D[0] (0) 008h Display Control (2) 0 0 0 0 FP[3] (1) FP[2] (0) FP[1] (0) FP[0] (0) 0000 BP[3] (1) BP[2] (0) BP[1] (0) BP[0] (0) 009h Display Control (3) 0 0 0 0 0 PTS[2] (0) PTS[1] (0) PTS[0] (0) 00 PTG[1] (0) PTG[0] (0) ISC[3] (0) ISC[2] (0) ISC[1] (0) ISC[0] (0) 00Ah Settin g Disabled 00Bh Display Control (4) 0 FRCON (0) D16B (0) 00000000000 COL[1] (0) COL[0] (0) 00Ch External Display Interface Control (1) 0000000 RM (0) 00 DM[1] (0) DM[0] (0) 00 RIM[1] (0) RIM[0] (0) 00Dh Frame Cycle Adjustment Contr o 000000 DIVI[1] (0) DIVI[0] (0) 000 RTNI[4] (1) RTNI[3] (0) RTNI[2] (0) RTNI[1] (0) RTNI[0] (0) 00Eh External Display Interface Control (2) 000000 DIVE[1] (1) DIVE[0] (0) 0 RTNE[6] (0) RTNE[5] (0) RTNE[4] (1) RTNE[3] (1) RTNE[2] (1) RTNE[1] (1) RTNE[0] (0) 00Fh External Display Interface Control (3) 00000000000 VSPL (0) HSPL (0) 0 EPL (0) DPL (0) 010h Gate Driver/LTPS Liquid Crystal Panel Interface Control (1) 000 FWI[4] (0) FWI[3] (0) FWI[2] (0) FWI[1] (0) FWI[0] (0) 000000 FTI[1] (0) FTI[0] (0) 011h Gate Driver/LTPS Liquid Crystal Panel Interface Control (2) 000 SWI[4] (0) SWI[3] (0) SWI[2] (0) SWI[1] (0) SWI[0] (0) 000000 STI[1] (0) STI[0] (0) 012h Gate Driver/LTPS Liquid Crystal Panel Interface Control (3) 00000000000000 SDTI[1] (0) SDTI[0] (0) 013h Gate Driver/LTPS Liquid Crystal Panel Interface Control (4) 000 DPWI[4] (0) DPWI[3] (0) DPWI[2] (0) DPWI[1] (0) DPWI[0] (0) 000000 DPTI[1] (0) DPTI[0] (0) 014h Setting Disabled 015h Gate Driver/LTPS Liquid Crystal Panel Interface Control (5) 000000 EQWI[1] (0) EQWI[0] (0) 00000000 016h Gate Driver/LTPS Liquid Crystal Panel Interface Control (6) 00 FWE[5] (0) FWE[4] (0) FWE[3] (0) FWE[2] (0) FWE[1] (0) FWE[0] (0) 00000 FTE[2] (0) FTE[1] (0) FTE[0] (0) 017h Gate Driver/LTPS Liquid Crystal Panel Interface Control (7) 00 SWE[5] (0) SWE[4] (0) SWE[3] (0) SWE[2] (0) SWE[1] (0) SWE[0] (0) 00000 STE[2] (0) STE[1] (0) STE[0] (0) 018h Gate Driver/LTPS Liquid Crystal Panel Interface Control (8) 0000000000000 SDTE[2] (0) SDTE[1] (0) SDTE[0] (0) 019h Gate Driver/LTPS Liquid Crystal Panel Interface Control (9) 00 DPWE[5] (0) DPWE[4] (0) DPWE[3] (0) DPWE[2] (0) DPWE[1] (0) DPWE[0] (0) 00000 DPTE[2] (0) DPTE[1] (0) DPTE[0] (0) 01Ah Setting Disabled 01Bh Gate Driver/LTPS Liquid Crystal Panel Interface Control (10) 00000 EQWE[2] (0) EQWE[1] (0) EQWE[0] (0) 00000000 01Ch-0FFh Settin g Disabled 1 Power Control System 100h Power Control (1) DC[4] (0) DC[3] (0) 000 SAP[2] (0) SAP[1] (0) SAP[0] (0) 0 AP[2] (0) AP[1] (0) AP[0] (0) 0 DSTB (0) SLP (0) STB (0) 102h-10Fh Settin g Disabled (Gate Driver / Power Supply IC Interface) 110h Gate Driver / Power Supply IC I/F Control (1) 0000000 TE (0) 00000 IDX[2] (0) IDX[1] (0) IDX[0] (0) 111h Gate Driver / Power Supply IC I/F Control (2) 000 TB[12] (0) TB[11] (0) TB[10] (0) TB[9] (0) TB[8] (0) TB[7] (0) TB[6] (0) TB[5] (0) TB[4] (0) TB[3] (0) TB[2] (0) TB[1] (0) TB[0] (0) 112h-1FFh Setting Disabled 2 RAM Access System 200h RAM Address Set (1) 0 0 0 0 0000 AD[7] (0) AD[6] (0) AD[5] (0) AD[4] (0) AD[3] (0) AD[2] (0) AD[1] (0) AD[0] (0) 201h RAM Address Set (2) 0 0 0 0 0 0 0 AD[16] (0) AD[15] (0) AD[14] (0) AD[13] (0) AD[12] (0) AD[11] (0) AD[10] (0) AD[9] (0) AD[8] (0) 202h RAM Data Write / Read 203h RAM Write Data Mask (1) 0 0 WM[11] (0) WM[10] (0) WM[9] (0) WM[8] (0) WM[7] (0) WM[6] (0) 00 WM[5] (0) WM[4] (0) WM[3] (0) WM[2] (0) WM[1] (0) WM[0] (0) 204h RAM Write Data Mask (2) 0 0 0 0 000000 WM[17] (0) WM[16] (0) WM[15] (0) WM[14] (0) WM[13] (0) WM[12] (0) 205h-20Fh Setting Disabled Window Address 210h Horizontal RAM Address Poseition (1) 00000000 HSA[7] (0) HSA[6] (0) HSA[5] (0) HSA[4] (0) HSA[3] (0) HSA[2] (0) HSA[1] (0) HSA[0] (0) Control System 211h Horizontal RAM Address Poseition (2) 00000000 HEA[7] (1) HEA[6] (1) HEA[5] (1) HEA[4] (0) HEA[3] (1) HEA[2] (1) HEA[1] (1) HEA[0] (1) 212h Vertical RAM Address Poseition (1) 0000000 VSA[8] (0) VSA[7] (0) VSA[6] (0) VSA[5] (0) VSA[4] (0) VSA[3] (0) VSA[2] (0) VSA[1] (0) VSA[0] (0) 213h Vertical RAM Address Poseition (2) 0000000 VEA[8] (1) VEA[7] (0) VEA[6] (0) VEA[5] (1) VEA[4] (1) VEA[3] (1) VEA[2] (1) VEA[1] (1) VEA[0] (1) 214h-2FFh Setting Disabled 3 Control 300h Control (1) 00000 PKP1[2] (0) PKP1[1] (0) PKP1[0] (0) 00000 PKP0[2] (0) PKP0[1] (0) PKP0[0] (0) 301h Control (2) 00000 PKP3[2] (0) PKP3[1] (0) PKP3[0] (0) 00000 PKP2[2] (0) PKP2[1] (0) PKP2[0] (0) 302h Control (3) 00000 PKP5[2] (0) PKP5[1] (0) PKP5[0] (0) 00000 PKP4[2] (0) PKP4[1] (0) PKP4[0] (0) 303h Control (4) 00000 PRP1[2] (0) PRP1[1] (0) PRP1[0] (0) 00000 PRP0[2] (0) PRP0[1] (0) PRP0[0] (0) 304h Control (5) 000 VRP1[4] (0) VRP1[3] (0) VRP1[2] (0) VRP1[1] (0) VRP1[0] (0) 0000 VRP0[3] (0) VRP0[2] (0) VRP0[1] (0) VRP0[0] (0) 305h Control (6) 00000 PKN1[2] (0) PKN1[1] (0) PKN1[0] (0) 00000 PKN0[2] (0) PKN0[1] (0) PKN0[0] (0) 306h Control (7) 00000 PKN3[2] (0) PKN3[1] (0) PKN3[0] (0) 00000 PKN2[2] (0) PKN2[1] (0) PKN2[0] (0) 307h Control (8) 00000 PKN5[2] (0) PKN5[1] (0) PKN5[0] (0) 00000 PKN4[2] (0) PKN4[1] (0) PKN4[0] (0) 308h Control (9) 00000 PRN1[2] (0) PRN1[1] (0) PRN1[0] (0) 00000 PRN0[2] (0) PRN0[1] (0) PRN0[0] (0) 309h Control (10) 000 VRN1[4] (0) VRN1[3] (0) VRN1[2] (0) VRN1[1] (0) VRN1[0] (0) 0000 VRN0[3] (0) VRN0[2] (0) VRN0[1] (0) VRN0[0] (0) 30Ah-3FFh Setting Disabled 4 Coordinate Control System 400䌨 L i n e N u m b e r C o n t r o l0000000000 NL[5] (1) NL[4] (0) NL[3] (0) NL[2] (1) NL[1] (1) NL[0] (1) 401h Screen Control 0 0 0 0 0000000000 VLE (0) REV (0) 402h Base Picture RAM Area (Start Line) 0000000 BSA[8] (0) BSA[7] (0) BSA[6] (0) BSA[5] (0) BSA[4] (0) BSA[3] (0) BSA[2] (0) BSA[1] (0) BSA[0] (0) 403h Base Picture RAM Area (End Line) 0000000 BEA[8] (1) BEA[7] (0) BEA[6] (0) BEA[5] (1) BEA[4] (1) BEA[3] (1) BEA[2] (1) BEA[䋱] (1) BEA[0] (1) 404h Vertical Scroll Control 0 0 0 0 0 0 0 VL[8] (0) VL[7] (0) VL[6] (0) VL[5] (0) VL[4] (0) VL[3] (0) VL[2] (0) VL[1] (0) VL[0] (0) 405h Base Picture 1RAM Magnified Area (Start Line) 0000000 ESA[8] (0) ESA[7] (0) ESA[6] (0) ESA[5] (0) ESA[4] (0) ESA[3] (0) ESA[2] (0) ESA[䋱] (0) ESA[0] (0) 406h Base Picture 2RAM Magnified Area (End Line) 0000000 EEA[8] (0) EEA[7] (0) EEA[6] (0) EEA[5] (0) EEA[4] (0) EEA[3] (0) EEA[2] (0) EEA[䋱] (0) EEA[0] (0) 407h-4FFh Setting Disabled 5 OSD Control 500h OSD Picture 1 Display Position 0 0 0 0 0 0 0 ODP0[8] (0) ODP0[7] (0) ODP0[6] (0) ODP0[5] (0) ODP0[4] (0) ODP0[3] (0) ODP0[2] (0) ODP0[1] (0) ODP0[0] (0) 501h OSD Picture䋱 RAM Area 䋨Start Line䋩 0000000 OSA0[8] (0) OSA0[7] (0) OSA0[6] (0) OSA0[5] (0) OSA0[4] (0) OSA0[3] (0) OSA0[2] (0) OSA0[1] (0) OSA0[0] (0) 502h OSD Picture 1 RAM Area 䋨End Line䋩 0000000 OEA0[8] (0) OEA0[7] (0) OEA0[6] (0) OEA0[5] (0) OEA0[4] (0) OEA0[3] (0) OEA0[2] (0) OEA0[1] (0) OEA0[0] (0) 503h OSD Picture 2 Display Position 0000000 ODP1[8] (0) ODP1[7] (0) ODP1[6] (0) ODP1[5] (0) ODP1[4] (0) ODP1[3] (0) ODP1[2] (0) ODP1[1] (0) ODP1[0] (0) 504h OSD Picture 2 RAM Area 䋨Start Line䋩 0000000 OSA1[8] (0) OSA1[7] (0) OSA1[6] (0) OSA1[5] (0) OSA1[4] (0) OSA1[3] (0) OSA1[2] (0) OSA1[1] (0) OSA1[0] (0) 505h OSD Picture 2 RAM Area 䋨End Line䋩 0000000 OEA1[8] (0) OEA1[7] (0) OEA1[6] (0) OEA1[5] (0) OEA1[4] (0) OEA1[3] (0) OEA1[2] (0) OEA1[1] (0) OEA1[0] (0) 506h OSD Picture 3 Display Position 0000000 ODP2[8] (0) ODP2[7] (0) ODP2[6] (0) ODP2[5] (0) ODP2[4] (0) ODP2[3] (0) ODP2[2] (0) ODP2[1] (0) ODP2[0] (0) 507h OSD Picture 3 RAM Area 䋨Start Line䋩 0000000 OSA2[8] (0) OSA2[7] (0) OSA2[6] (0) OSA2[5] (0) OSA2[4] (0) OSA2[3] (0) OSA2[2] (0) OSA2[1] (0) OSA2[0] (0) 508h OSD Picture 3 RAM Area 䋨End Line䋩 0000000 OEA2[8] (0) OEA2[7] (0) OEA2[6] (0) OEA2[5] (0) OEA2[4] (0) OEA2[3] (0) OEA2[2] (0) OEA2[1] (0) OEA2[0] (0) 509h-5FFh Setting Disabled 6** 600h-6FFh Setting Disabled Note 1) Numerals in parentheses in instruction bit cells are initial value. 䇯 Note 2) Do not try to access to the index where setting is disabled. RAM Write Data 䋨WD17-0䋩or RAM䇭Read Data (RD17-0) 䇭Bit assignment will change according to the selected interface. NoteMain Category Sub Category Upper Code Lower Code 000h Upper bits of Index γ

Rev.0.5, July.31.2003, page 97 of 196 HD66783 Instruction Table IDX[2] IDX[1] IDX[0] TB[12] TB[11] TB[10] TB[9] TB[8] TB[7] TB[6] TB[5] TB[4] TB[3] TB[2] TB[1] TB[0]

0000 GON VCOMG BT[2] BT[1] BT[0] DC0[2] DC0[1] DC0[0] AP[2] AP[1] AP[0] 0

0010 DK 1 EQM 0 PON VRH[3] VRH[2] VRH[1] VRH[0] VC[2] VC[1] VC[0]

010 DC1[2] DC1[1] DC1[0] VDV[4] VDV[3] VDV[2] VDV[1] VDV[0] VCM[4] VCM[3] VCM[2] VCM[1] VCM[0]

110 GS NL[5] NL[4] NL[3] NL[2] NL[1] NL[0] SCN[5] SCN[4] SCN[3] SCN[2] SCN[1] SCN[0]

111 00000000000 F L D [ 1 ] F L D [ 0 ] HD667P21 Instruction Table IDX[2] IDX[1] IDX[0] TB[12] TB[11] TB[10] TB[9] TB[8] TB[7] TB[6] TB[5] TB[4] TB[3] TB[2] TB[1] TB[0]

0000 GON VCOMG BT[2] BT[1] BT[0] DC[2] DC[1] DC[0] AP[2] AP[1] AP[0] 0

00100000 PON VRH[3] VRH[2] VRH[1] VRH[0] VC[2] VC[1] VC[0]

001010 DK[1] DK[0] 00000000

010000 VDV[4] VDV[3] VDV[2] VDV[1] VDV[0] VCM[4] VCM[3] VCM[2] VCM[1] VCM[0]

11100 VGL[4] VGL[3] VGL[2] VGL[1] VGL[0] 0 VGH[4] VGH[3] VGH[2] VGH[1] VGH[0]

AP and NL require a same and separate setting for each HD66781 and the register to transfer (Different Setting Disabled). 1. Setting for AP register of 781 2䋮Setting for AP register of 783/7P21 (R111h,TB[3]-[1]) 3䋮Serial Transfer to 783/7P21 (IDX000) 䋱䋮Setting for NL register of 781 2䋮Setting for NL register of 783 (R111h TB[11]-[6]) 3䋮Serial Transfer to 783 (IDX110) 䋱䋮Setting for FLD register of 781 2䋮Setting for FLD register of 783 (R111h TB[1]-[0]) 3䋮Serial Transfer to 783 (IDX111) Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled

Rev.0.5, July.31.2003, page 98 of 196 Reset Function The HD66781 is internally initialized by RESET input. During the reset period, internal settings are initialized. No access to instructions or GRAM data from the MPU is accepted during the reset period. The gate driver and the power supply are also automatically initialized when RESET input enters into the HD66781. The RESET period must be secured for at least 1 ms. In case of resetting by turning on the power supply (power-on reset), wait until the R-C oscillation frequency becomes stable after power is supplied (10 ms). During this period, do not access GRAM or make any initial instruction setting. Instruction Set Initialization See the parenthetic number in each bit in the instruction list for the initial value. RAM Data Initialization The RAM data are not automatically initialized by RESET input and must be initialized by software during the display-off period (D1–0 = 00). Output Pin Initialization 1. LCD driver output pins (source outputs) : Output GND level (All pins) 2. Vcom : Halt (Output GND) 3. Gate driver control signal : Halt (Output GND) (FLM1, FLM2, CL11/SFTCLK11, CL12/SFTCLK12, SFTCLK21, SFTCLK22, M1, M2, DISPTMG1, DISPTMG2, EQ1, EQ2, DCCLK1, DCCLK2) 4. Gate driver serial interface : Halt GCS, GCL, GDA (Vcc1 output) 5. Oscillator output pin : Oscillate 6. Synchronizing signal (BST) : Output GND 7. RESET signal output : Same polarity with the RESET* input

Rev.0.5, July.31.2003, page 99 of 196 RAM Address and Display Position on the Panel The HD66781 incorporates a memory for 240RGB x 416-line display, and enables to drive QVGA-size panel (240RGB x 320 lines). Unused display memory is available for a partial OSD area. These features realize various ways of display with a single chip. The HD66781 allows independent settings for the display panel and the drive position, where the RAM area of each image is specified in relation to the display panel that is assigned to gate pins to fit into the assembly. Accordingly, in designing a panel, it is not necessary to take the assembly position into account. The HD66781 allows realizes various ways of display with the following settings: 1. Specify the RAM area of a base image (BSA, BEA) 2. Specify the RAM area of an OSD image (OSAx, OEAx) 3. Specify the display position of the OSD image (step 2) on the panel (ODPx). 4. Specify the gate pins for driving the panel displaying a base image (SCN, NL) and the scan order (GS). 5. Execute display ENABLE (BASEE, OSDE0/1/2) for each image after turning on display. A base image is a display that is set to be a basic display on each panel. An OSD image is a picture that is set to display on the base image. The panel-drive settings are made with gate scan starting position (SCN), the number of raster-rows to drive (NL), and scan direction (GS). The gate scan direction can be set differently for each panel to fit into the assembly. To change the display position horizontally, the setting of SS bit is required during RAM write. Table 53 Display ENABLE Numbers of lines RAM area (Base image 1) BASEE NL (BSA, BEA) Note 1) The base image is displayed from the start line of each panel. Note 2) Make sure that base image RAM area is NL ≤ BEA – BSA. Table 54 Display ENABLE Display position RAM area OSD image 1 OSDE0 ODP0 (OSA0, OEA0) OSD image 2 OSDE1 ODP1 (OSA1, OEA1) OSD image 3 OSDE2 ODP2 (OSA2, OEA2)

Rev.0.5, July.31.2003, page 100 of 196 BSA BEA SCN NL+SCN Base image (HSA,HEA) (VSA,VEA) Window Address ODP0 OSD image 1 ODP1 OSD image n+1 n+m LCD OSA0 OEA0 OEA1 OSA1 OSD image OSA2 OEA2 ODP2 GS Gate pins Panel position Base image RAM address OSD image RAM address RAM write Address RAM Address, display position and drive position Notes to the setting of panel control registers The HD66781 has some constrains in setting the coordinate with regard to the display data, position, and OSD. Screen settings The following equation must be observed in making a setting for the screen. NL ≤ 320 lines 0 ≤ SCN < SCN+NL ≤ 320 lines Base image display Base image is displayed from the first line of each panel. Base image display start position: SCN = BSA Set the base image RAM area (BSA, BEA) equal to or more than the number of lines (NL) required driving a panel. NL ≤ BEA – BSA OSD image display Set the OSD image RAM area (OSAx, OEAx) not to overlap one another. Set the OSD positions not to overlap one another. 0 ≤ ODP0 ≤ ODP0+ n x (OEA0 – OSA0+1) - 1< ODP1 ≤ ODP1+ n x (OEA1 – OSA1+1) - 1< ODP2 ≤ ODP2+ n x (OEA2 – OSA2+1) - 1≤ NL n: OSD image magnification scale The OSD images are displayed 100% when base image is turned off (BASEE = 0). The arrangement of α channels is also changed when changing RGB order to BGR. The OSD data are read out in the format when ODF is set to 0. During interlaced drive (FLD = 2’h3), OSD and α blending functions are not available.

Rev.0.5, July.31.2003, page 101 of 196 Following figure shows the relationship among RAM address, display position, and panel drive. G317 SCN LCD panel physical line address 0(1line) 1(2lines) 2(3lines) NL Display panel 9’h000 RAM line address BSA n-1 ( n line) BEA ODP0 OSD image 1 display area ODP1 OSD image 2 display area Base image RAM area OSD image RAM area OSA0 OEA0 OSA1 OEA1 OSD image RAM area OSA2 OEA2 OSD image RAM area ODP2 OSD image 3 display area 9’h19F G1G2 G4G5 G318 G319 G320 GS Note: This figure shows the definition of address in relation to a display. The address for writing RAM data is defined by the window address. Display RAM address and panel display position

Rev.0.5, July.31.2003, page 102 of 196 OSD and α blending functions The HD66781 incorporates OSD and α blending functions. The OSD image data has 3 α bits to select transmission rates among 0, 25, 50, 75, 100%. The HD66781 not only handles 32,678-color OSD at maximum but also enables picture display data as OSD, in addition to usual single color text display. The HD66781 realizes various ways of display with a single-chip configuration. The HD66781 eliminates the processing of OSD and α blending from the microcomputer. Just transmitting OSD image data including α bits into the LCD driver as usual enables OSD and α blending display. OSD and α blending processing The HD66781 writes data to RAM as an OSD image according to the setting of OSD bit. An image read out as OSD according to the OSD image display setting is displayed after being processed according to the transmission rate set by α bits. OSD and α blending settings can be made by pixels (RGB). Table 55 α2 α1 α0 Transmission rate Picture processing (Display data) Picture processing (Display data) 0 0 0 0% Base image display Base image x 1.0 + OSD image x 0 0 0 1 - Setting disabled - 0 1 0 25% Base image (75%) + OSD image (25%) display 25% transmission 0 1 1 75% Base image (25%) + OSD image (75%) display 75% transmission 1 0 0 50% Base image (50%) + OSD image (50%) display Base image x 0.5 + OSD image x 0.5 1 0 1 - Setting disabled - 1 1 0 100% OSD image display Base image x 0 + OSD image x 1.0 1 1 1 - Setting disabled - Note 1) The OSD image is displayed 100% when base image is turned off (BASEE = 0).

Rev.0.5, July.31.2003, page 103 of 196 OSD and α blending processing The following is an example of display with OSD and α blending functions with the HD66781. In the following example, the unused RAM area, which is not used for base image display, is used for OSD and α blending RAM area. First panel base image ar ea First OSD image ar ea Second OSD i mage area Thir d OSD image area HD66781 first panel display 100%OSD display ico n 50%OSD display (Base color: yellow) 100% OSD display (letters) 100 % OSD display(icon) HD66781 RAM data Display with OSD and α blending OSD image data format OSD image data format (α bit arrangement) is changeable with ODF bits. Select an appropriate format for the system to process. When writing an OSD image to RAM, set OSD to 1 beforehand. Specify the RAM write area by the window address. OSD image data format ODF D D D D D D D D

10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 R5 R4 R3 R2 R1 ƒ¿2 G5 G4 G3 G2 G1 ƒ¿1 B5 B4 B3 B2 B1 ƒ¿0

1 ƒ¿2 ƒ¿1 ƒ¿0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Normal data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD image display setting To make a setting for OSD image display, 1. Specify OSD RAM area (OSA, OEA) 2. Specify OSD position 3. Set OSD ENABLE (OSDE)

Rev.0.5, July.31.2003, page 104 of 196 BSA BEA SCN NL+SCN Base image (HSA,HEA) (VSA,VEA) Window Address ODP0 OSD image 1 ODP1 OSD image n+1 n+m LCD OSA0 OEA0 OEA1 OSA1 OSD image OSA2 OEA2 ODP2 GS Gate pins Panel position Base image RAM address OSD image RAM address RAM write Address RAM Address, display position, drive position Whenever making an OSD image setting, the following must be observed. 1. Set the OSD RAM area with OSAx, OEAx not to overlap one another. 2. Set the OSD position so that an OSD image does not overlap one another. 0 ≤ ODP0 ≤ ODP0+n x (OEA0 – OSA0+1) –1 < ODP1 ≤ ODP1+ n x (OEA1 – OSA1+1) –1 < ODP2 ≤ ODP2+ n x (OEA2 – OSA2+1) –1 ≤ NL “n” is a magnification scale of an OSD image. 3. An OSD image is displayed 100% when the base image is turned off (BASEE = 0). 4. During the interlaced drive (FLD = 2’h3), the OSD and α blending functions are not available. OSD Setting(OSD,ODF) Address Set RAM data write OSD data write flow

Rev.0.5, July.31.2003, page 105 of 196 Resizing function The HD66781 incorporates resizing function (contraction: x 1/2, x 1/4, magnification: x2) available when writing picture data. Contraction The HD66781 enables to write resized image data to RAM by simply transmitting original image data to the window address as usual with the setting of RSR bit that specifies the contraction rate. This means the HD66781 allows the system simply to transmit data as usual even if resizing is required, and therefore makes resized images easily available on cameras, sub panels, or as a thumbnail display of a picture. The HD66781 performs contraction resizing simply by selecting pixels. The resized image may seem distorted from the original image. Check the resized image before use. 0123456 0123 Transmitted image data RAM data 1/2 resizing Resizing: contraction 240 320 transmitted data for RAM write Main Panel Display HD66781 RAM data 160 RAM Write RSZ=2’h1 Resizing transmission, display example Table 56 Resized image size Original image size (X x Y) 640x480(VGA) 320x240 160x120 352x268 (CIF) 176x144 88x72 320x240 (QVGA) 160x120 80x60 176x144 (QCIF) 88x72 44x36 120x160 60x80 30x40 132x176 66x88 33x44

Rev.0.5, July.31.2003, page 106 of 196 Resizing setting The HD66781 selects resizing (contraction) rate according to the setting of RSR bit. Specify the RAM window-address range to fit into the resized picture. If resizing creates surplus pixels according to the result of calculation using the following formulas, set them in RCV, RCH registers before writing data to RAM. Original image data size X Y Rx Ry (X0,Y0) (X0+Rx-1,Y0+Ry-1) RAM write data (1/N resizing) HD66781 GRAM Address Formulas for calculating the number of surplus pixels The number of surplus pixels in horizontal direction L = X mod N The number of surplus pixels in vertical direction M = Y mod N Resized picture size in horizontal direction Rx = (X-L)/N Resized picture size in vertical direction Ry = (Y-M)/N Resizing Setting, surplus pixel calculation Table 57 Original image (before resizing) HD66781 settings number of data in horizontal direction X Resizing setting RSR N-1 number of data in vertical direction Y number of data in horizontal direction RCV L resizing ratio 1/N number of data in vertical direction RCH M RAM writing start address AD (X0, Y0) HSA X0 HEA X0+Rx - 1 VSA Y0 RAM window address VEA Y0+Ry - 1 Original image data 240 x 320 X=240 Y=320 Rx=120 Ry=160 (0,0) (119,159) RAM write data (1/2 resizing) 120 x 160 HD66781 GRAM address Resizing setting example (1/2 size)

Rev.0.5, July.31.2003, page 107 of 196 Table 58 Original image (before resizing) HD66781 settings number of data in horizontal direction X 240 Resizing setting RSR 2’h1 number of data in vertical direction Y 320 number of data in horizontal direction RCV 2’h0 resizing ratio 1/N 1/2 number of data in vertical direction RCH 2’h0 RAM writing start address AD 17’h00000 HSA 8’h00 HEA 8’h77 VSA 8’h00 RAM window address VEA 8’h9F Instructions for Resizing Table 59 Resizing ratio RSR[1:0] ratio 2h’0 No resizing (x 1) 2h’1 1/2 resizing (x 1/2) 2h’2 setting disabled 2h’3 1/4 resizing (x 1/4) Table 60 Surplus pixels vertical direction horizontal direction RCV[1:0] surplus pixels RCH[1:0] surplus pixels 2h’0 0 2h’0 0 2h’1 1 pixel 2h’1 1 pixel 2h’2 2 pixels 2h’2 2 pixels 2h’3 3 pixels 2h’3 3 pixels 1 pixel = 1 RGB 1 pixel = 1 RGB

Rev.0.5, July.31.2003, page 108 of 196 Notes to the resizing function 1. Make settings for resizing instructions (RSR, RCV, and RCH) before writing data to RAM. 2. Write data to RAM from the start position of the window address by line when using resizing function. 3. Fit the window-address range into the size of the resized picture. 4. Make an address set before writing data to RAM when using resizing function. 5. Settings for RCH, RCV are only required when using resizing function. Otherwise (RSR = 2’h0), set RCH = RCV = 2’h0. Resizing setting (RSR , RCH,RCV) Window address setting (HSA , H SE, VSA, VEA) Address set RAM data wr it e Note: The window-address range must be fit into the size of a resized image RAM Writing flow when using resizing

Rev.0.5, July.31.2003, page 109 of 196 Magnification The HD66781 enables to write resized image data to RAM by simply transmitting original image data to the window address as usual with the settings of RESH/RESEV[7:0] bits that specify the magnification rate each for the base and OSD images. The magnification rate is specified each for the base and OSD images. Also, only a part of RAM area of a base image can be magnified on display in the vertical direction. This means the HD66781 allows the system simply to transmit an original data as usual even when displaying a magnified image on a large screen, and therefore enables to reduce the data transmission required for a large screen display. The display magnification in the vertical direction should be specified by line. Base image: The image specified by ESA[8:0] and EEA[8:0] on RAM is magnified on display by the scale set by the RSEV[1:0] setting. OSD image: The image specified by OSAx[8:0] and OEAx[8:0] on RAM is magnified on display in the manner set by the RSEV[7:2] setting. When magnifying in the horizontal direction, the window-address settings (HSA[0], HEA[0]), RAM address set (AD[0]), and horizontal incremental direction of the counter (I/D[0]) as follows. Table 61 Registers Register setting HSA[0] 1’b0 HEA[0] 1’b1 1’b0 when I/D[0]=0 AD[0] 1’b1 when I/D[0]=1 The HD66781 performs magnification resizing simply by inserting pixels. The resized image is an extended original image in both horizontal and vertical direction. Check the resized image before use. 0 1 2 3 4 5 6 7 0 1 2 3 0 (0,0) 1 (1,0) 2 (2,0) 3 (3,0) data of an image to transfer RAM data Horizontal direction x2 resizing RSEH=1 Display on the panel vertical direction x2 resizing RSEV=1 (0,0) (0,0) (1,0) (1,0) (1,0) (1,0) (2,0) (2,0) (2,0) (2,0) (3,0) (3,0) (3,0) (3,0) (0,0) (0,0) (1,0) (1,0) (2,0) (2,0) (3,0) (3,0) (0,1) (0,2) (0,3) (1,1) (1,2) (1,3) (2,1) (2,2) (2,3) (3,1) (3,2) (3,3) (0,1) (0,1) (1,1) (1,1) (1,1) (1,1) (2,1) (2,1) (2,1) (2,1) (3,1) (3,1) (3,1) (3,1) (0,1) (0,1) (1,1) (1,1) (2,1) (2,1) (3,1) (3,1) (0,2) (0,2) (1,2) (1,2) (2,2) (2,2) (3,2) (3,2) (0,3) (0,3) (1,3) (1,3) (2,3) (2,3) (3,3) (3,3) Resizing: magnification

Rev.0.5, July.31.2003, page 110 of 196 The following figure illustrates the relationship of RAM address, display position and panel driving position when a base image is magnified in the vertical direction. RESV[1:0] = 2’h1 NL 9’h000 BSA BEA 9’h19F 0(1line) 2(3lines) 1(2lines) 0(1line) n-1 ESA EEA (ESA - BSA) (ESA - (ESA - BSA +1) Base image RAM magnified area EEA + 1 (EEA - BSA + 1) (EEA - BSA) (EEA - BSA – 1) (EEA - BSA – 1) (ESA - BSA +1) (EEA - BSA) BSA) LCD panel physical line address Display panel RAM line address Base image RAM area Base image RAM magnified display area Note 1) BSA҇ ESA҇ EEA҇ BEA Note 2) The RAM area of a base image outside the NL range is not displayed on a panel.

Rev.0.5, July.31.2003, page 111 of 196 RSEV[3:2] = 2’h1, RSEV[5:4] = 2’h0, RSEV[7:6] = 2’h0 9’h000 BSA 9’h19F 0(1line) 2(3lines) 1(2lines) 0(1line) n-1 ODP0 ODP1 OSD image 1 RAM area OSA0 OEA0 OSA1 OEA1 OSA2 OEA2 ODP2 OSD image 1 display area OSD image 2 display area OSD image 3 display area BEA (OEA0 - OSA0 +1) 㬍 2 lines OSD image 1 magnified display area 0㻡 ODP0 㻡ODP0 +n 㬍(OEA0-OSA0+1) - 1 䋼 ODP1㻡ODP1 +n 㬍(OEA1-OSA1+1) - 1 䋼 ODP2㻡ODP2 +n 㬍(OEA2-OSA2+1) - 1 㻡NL n: magnification scale of OSD display Note: The OSD display positions must be designated not to overlap one another. OSD image 2 RAM area OSD image 3 RAM area

Rev.0.5, July.31.2003, page 112 of 196 Interface specification The HD66781 incorporates a system interface to make settings for instructions and an external display interface to display moving pictures. The HD66781 allows selecting an optimum interface for display (moving or still picture, or both) to transmit data efficiently. The external display interface includes RGB interface and VSYNC interface, which enable flicker-free screen update. In the RGB-I/F mode, the display operation is performed in synchronization with the signals (VSYNC, HSYNC, and DOTCLK). The display data are written according to the values of the data enable signal (ENABLE), and PD17-0 bits in synchronization with the VSYNC, HSYNC, and DOTCLK signals. The display data are written to GRAM to reduce the data transmission to minimum, i.e. only when the displays are being changed. With the window address function, only the RAM area used for moving picture display is overwritten, and therefore the simultaneous display of moving picture area, which is overwritten, and the RAM data in the area other than the moving picture area, which is not overwritten, is possible. In the RGB and VSYNC interface modes, write data to GRAM in the high speed write mode (HWM = 1) during displaying moving pictures to access to GRAM in high speed with low power consumption. In the VSYNC interface mode, the frame synchronization signal (VSYNC) synchronizes internal display operations. By writing data in synchronization with the falling edge of VSYNC at a fixed speed to GRAM through a system interface, moving pictures are displayed with the system interface in use. In this case, there are some constraints in the speed and method to write data to RAM. The HD66781 handles the following 4 operational modes according to the type of display. All settings are made through the external display interface. Transition between the modes must be done according to the transitional flow charts. Table 62 Operation Mode RAM Access Setting (RM) Display Operation Mode (DM1-0) Internal operating clock only (Displaying still picture) System interface (RM = 0) Internal operating clock (DM1-0 = 00) RGB interface (1) (Displaying moving picture) RGB interface (RM = 1) RGB interface (DM1-0 = 01) RGB interface (2) (Rewriting still picture while displaying moving pictures) System interface (RM = 0) RGB interface (DM1-0 = 01) VSYNC interface (Displaying moving pictures) System interface (RM = 0) VSYNC interface (DM1-0 = 10) Note 1) Instructions are set only through a system interface. Note 2) RGB-I/F and VSYNC-I/F are not used simultaneously. Note 3) Do not make a change to the RGB-I/F mode (RIM-0) while the RGB I/F is operating. Note 4) When making transitions between the interfaces, see the “External Display Interface” (p.139) for the transition flow chart Note 5) RGB-I/F and VSYNC-I/F modes should be used with the high-speed write mode (HWM = 1).

Rev.0.5, July.31.2003, page 113 of 196 System System interface RGB interface CS* RS WR* (RD*) DB17-0 ENABLE VSYNC HSYNC DOTCLK PD17- HD66781 18/16/9/8 18/16/6 HD66781 Interface

Rev.0.5, July.31.2003, page 114 of 196 System Interface The setting with IM3/2/1/0 pins allows selecting among the following system interfaces. The system interface enables instruction settings and RAM access. Table 63 IM bits settings and system interface IM3 IM2 IM1 IM0 Interfacing mode with MPU DB Pin Colors 0 0 0 0 Setting disabled 0 0 0 1 Setting disabled 0 0 1 0 80-system 16-bit interface DB17 to 10 and 8 to 1 65,536 (262,144) Note 2) 0 0 1 1 80-system 8-bit interface (Big endian) DB17 to 10 65,536 (262,144) Note 2) 0 1 0 * Serial Peripheral interface (SPI) DB1 to 0 65,536 0 1 1 0 Setting disabled 0 1 1 1 80-system 8-bit interface (Little endian) DB17 to 10 65,536 (262,144) Note 2) 1 0 0 0 Setting disabled 1 0 0 1 Setting disabled 1 0 1 0 80-system 18-bit interface DB17 to 0 262,144 1 0 1 1 80-system 9-bit interface DB17 to 9 262,144 1 1 * * Setting disabled Note 1) 262,144 colors in 16-bit data bus 2-transmission mode. Note 2) 262,144 colors in 8-bit data bus 3-transmission mode.

Rev.0.5, July.31.2003, page 115 of 196 80-system 18-bit interface 80-system 18-bit parallel data transmission is selected by setting IM3/2/1/0 pins to Vcc1/GND/Vcc1/GND levels. CSn* HWR (RD*) D31-0 MPU CS* RS WR* (RD*) DB17-0 HD66781 Example of Interface with the 18-bit Microcomputer input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Instruction IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB Instruction code input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1 pixel RAM data write α αα α α α In 18-bit interface mode, Normal display: 262,144 colors OSD display: 32,768 colors Instruction 18-bit interface data format (Instruction / RAM write data)

Rev.0.5, July.31.2003, page 116 of 196 80-system 16-bit interface 80-system 16-bit parallel data transmission is selected by setting IM3/2/1/0 pins to GND/GND/Vcc1/GND levels. CSn* HWR (RD*) D15-0 MPU CS* RS WR* (RD*) DB17-10,8-1 HD66781 16-bit microcomputer and interface (example) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Instruction IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB Instruction code RAM data write Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1pixel 65,536 Color with 16-bit system interface input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 1pixel 8,192 Color with 16-bit system interface input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 Color with 16-bit system interface α α α α α α Instruction 16-bit interface data format (Instruction / RAM write data)

Rev.0.5, July.31.2003, page 117 of 196 80 system 16 bit interface (2 transmissions: TRI = 1, DFM = 0) GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assignment WD [17] 1st transmission 2nd transmission GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 80 system 16 bit interface (2 transmissions: TRI =1, DFM = 1) 1st transmission 2nd transmission 2 1 WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1 pixel α αα α α α Note: Normal display in 262,144 colors, OSD display in 32,768 colors in16-bit system interface, 2-transmission mode. RGB Assignment WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1 pixel α αα α α α Note: Normal display in 262,144 colors, OSD display in 32,768 colors in16-bit system interface, 2-transmission mode. 16-bit interface data format (RAM write data in 2-transmission mode)

Rev.0.5, July.31.2003, page 118 of 196 Data transmission synchronization in 16-bit bus interface mode The HD66781 supports the data transmission synchronization function, which resets the counter that counts the number of data transmission of upper 2 bits and lower 16 bits or upper 16 bits and lower 2 bits in the 16-bit data bus interface 2-transmission mode. When a discrepancy occurs in the data transmission of the upper/lower bits due to effects from noise and so on, the “000” H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. DB17~10 DB8~1 Upper Lower “000”H “000”H “000” H “000”H Upper Lower Upper WR RD RS (16-bit transmission synchronization) Data Transmission Synchronization

Rev.0.5, July.31.2003, page 119 of 196 80-system 9-bit interface The 80-system 9-bit parallel data transmission through DB17-9 pins is selected by setting IM3/2/1/0 pins to Vcc1/GND/Vcc1/Vcc1 levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits (the LSB is not used) and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 9 bits, and the upper bits are transmitted first. The DB8-0 pins, that are not used, must be fixed to either IOVcc level. When writing the index register, the upper byte (8 bits) must be written. CSn* HWR (RD*) D15-0 H8/2245 CS* RS WR* (RD*) DB17-9 HD66781

9 DB8-0

Example of Interface with the 9-bit Microcomputer Instruction First transmission (Upper) Second tr ansmission (Lower) input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB instruction IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB instruction code RAM data write First transmission (Upper) Second t ransmission (Lower) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pi xel with 9-bit system interface Normal display : 262,144 colors OSD : 32,768 colors α α αα αα 9-bit interface data format

Rev.0.5, July.31.2003, page 120 of 196 Data transmission synchronization in 9-bit bus interface mode The HD66781 supports the data transmission synchronization function, which resets the upper/lower counters that count the number of data transmission of upper/lower 9 bits in the 9-bit bus interface mode. When a discrepancy occurs in the data transmission of the upper/lower 9 bits due to effects from noise and so on, the “000” H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper 9-bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. DB17~9 Upper Lower “000”H “000”H “000” H “000”H Upper Lower Upper WR RD RS (9- bit transmission synchronization) 9-bit Transfer Synchronization

Rev.0.5, July.31.2003, page 121 of 196 80-system 8-bit interface (Big endian) The 80-system 8-bit parallel data transmission is selected by setting IM3/2/1/0 pins to GND/GND/Vcc1/Vcc1 levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 8 bits, and the upper bits are transmitted first. The data to write to RAM are expanded into 18 bits internally. The DB9-0 pins, that are not used, must be fixed to either IOVcc level. When writing the index register, the upper byte (8 bits) must be written. CSn* HWR (RD*) D15-0 H8/2245 CS* RS WR* (RD*) DB17-10 HD66781

8 DB9-0

Example of Interface with the 8-bit Microcomputer

Rev.0.5, July.31.2003, page 122 of 196 Instruction First transmission (Upper) Second transmission (Lower ) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Instruction IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB instruction code RAM data write (2 transmission mode :TRI=0) First transmission (Upper) Second transmission (Lower ) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM data write R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5 1pixel 65,536 colors with 8-bit system interface First transmission (Upper) Second transmission (Lower) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with 8-bit system interface First transmission (Upper) Second transmission (Lower) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with 8-bit system interface α1α2 α0 α2 α1 α0 8-bit interface data format, RAM data write (2-transmission mode)

Rev.0.5, July.31.2003, page 123 of 196 RAM data write(3 transmission mode : TRI =1, DFM =0) first transmission second transmission third t ransmission input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM data write R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1 pixel with 8-bit system interface Normal display : 262,144 colors OSD : 32,786 colors RAM data write (3 transmission mode :TRI =1, DFM =1) first transmission second transmission third transmission input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM data write R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1 pixel with 8-bit system interface Normal display : 262,144 colors OSD : 32,768 colors α αα ααα α ααα αα 8-bit interface data format, RAM data write (3-transmission mode)

Rev.0.5, July.31.2003, page 124 of 196 Data transmission synchronization in 8-bit bus interface mode The HD66781 supports the data transmission synchronization function, which resets the upper/lower counters that count the number of data transmission of upper/lower 8 bits in the 8-bit bus interface mode. When a discrepancy occurs in the data transmission of the upper/lower 8 bits due to effects from noise and so on, the “00” H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper 8-bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. DB17~10 Upper Lower “00”H “00”H “00”H “00”H Upper Lower Upper WR RD RS (8-bit transfer synchronization) 8-bit data transmission synchronization

Rev.0.5, July.31.2003, page 125 of 196 Serial Peripheral interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting IM3/2/1 pins to GND/Vcc1/GND levels respectively. The SPI is available through the chip select line (CS), serial transfer clock line (SCL), serial data input (SDI), and serial data output (SDO). In the SPI mode, the IM0/ID pin functions as ID pin. In the SPI mode, the DB17-2 pins, which are not used, must be fixed at either IOVcc level. The HD66781 recognizes the start of data transfer at the falling edge of CS input to initiate the transfer of start byte. It recognizes the end of data transfer at the rising edge of CS input. The HD66781 is selected when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device identification code assigned to the HD66781 are compared and both 6-bit data correspond. When selected, the HD66781 starts taking in the subsequent data string. The setting for the least significant bit of the identification code is made with the ID pin. The five upper bits of the identification code must be 01110. Two different chip addresses must be assigned to the HD66781 because the seventh bit of the start byte is assigned to a register select bit (RS). When RS = 0, index register write or status read is executed. When RS = 1, instruction write or RAM read/write is executed. The eighth bit of the start byte is to specify read or write (R/W bit). The data are received when the R/W bit is 0, and are transmitted when the R/W bit is 1. In the SPI mode, the data are written to GRAM after two-byte data transmission. The data are expanded into 18 bits by adding one bit (the same data as the MSB of RB) to the LSB of RB data. After receiving the start byte, the HD66781 starts to transmit or receive data by byte. The data transmission adopts a format by which the MSB is first transmitted. All HD66781 instructions consist of 16 bits and they are executed internally after two bytes are transmitted with the MSB first (DB15 to 0). The data to write to RAM are expanded into 18-bit data. After the start byte is received, the first byte is always fetched as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction. The 4-byte data that are read from RAM right after the start byte are made invalid. The HD66781 reads as valid data from the 5th-byte data. Start Byte Format Transmitted bits S 1 2 3 4 5 6 7 8 Start byte format Transmission start Device ID code RS R/W 0 1 1 1 0 ID Note 1) ID bit is selected with the IM0/ID pin. Table 64 RS R/W Function 0 0 Set index register 0 1 Read status 1 0 Write instruction or RAM data 1 1 Read instruction or RAM data

Rev.0.5, July.31.2003, page 126 of 196 instruction First transmission (upper) Second t ransmission (lower) input D D D D D D First transmission (upper) Second tr ansmission (lower) input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5 1pi xel 65,536 colors with serial interface First t ransmission (upper) Second tr ansmission (lower) input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with serial interface First transmission (upper) Second transmission (lower) input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with serial interface α2 α1 α0 α2 α1 α0 Data format for Serial Peripheral Interface

Rev.0.5, July.31.2003, page 127 of 196 LSB “0” “1” “1” “1” “0” ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Device ID code RS RW MSB Start bite Index register set, instruction set, RAM data write Transmission start Transmission end CS input SCL input SDI input D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Status read, instruction read, RAM data re ad SDO output CS input SCL input SDI input Start bite Instruction(1) Upper 8 bits Instruction(1) Lower 8 bits Instruction(2) Upper 8 bits Instruction(2) Lower 8 bits Instruction (1) execution time Start End CS input SCL input RAM read Lower 8 bits SDI input Start bite RS=1 R/W=1 Start SDO output dummy read dummy read dummy read dummy read dummy read RAM read Upper 8 bits End The first bite right after start bite is always upper 8 bits The 5 bites right after start bite are dummy read, and invalid data are read out to RAM. Normal RAM data read starts from the 6th byte. (a) Clock synchronization serial transmission (Basic) (b) Clock synchronization serial transmission (consecutive) (c) RAM read-out transmission The 1 bite right after Start bite is dummy, and invalid data are read out to RAM. Normal RAM data read starts from the 2nd byte. (d) status read, instruction read CS input SCL input SDI input Start byte RS = 0 R/W = 1 Start SDO output dummy read Status Read Upper 8 bits Status Read Lower 8 bits End Serial Peripheral Interface: data transfer

Rev.0.5, July.31.2003, page 128 of 196 80-system 8-bit interface (Little endian) The 80-system 8-bit parallel data transmission is selected by setting IM3/2/1/0 pins to GND/Vcc1/Vcc1/Vcc1 levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 8 bits, and the upper bits are transmitted first. The data to write to RAM are expanded into 18 bits internally. The DB9-0 pins, that are not used, must be fixed to either IOVcc level. When writing into the index register, the upper byte (8 bits) must be written. CSn* HWR (RD*) D15-0 H8/2245 CS* RS WR* (RD*) DB17-10 HD66781 Example of Interface with the 8-bit Microcomputer

Rev.0.5, July.31.2003, page 129 of 196 Instruction transmission (Upper) ransmission (Lower ) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Instruction IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB instruction code RAM data write (2 transmission mode :TRI=0) transmission (Upper) ransmission (Lower ) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB GRAM data write R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1pixel 65,536 colors with 8-bit system interface transmission (Upper) ransmission (Lower) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with 8-bit system interface transmission (Upper) First t ransmission (Lower) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OSD data ODF=0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with 8-bit system interface α1α2 α0 α2 α1 α0 First t First t First tSecond Second Second Second 8-bit interface data format, RAM data write (2-transmission mode)

Rev.0.5, July.31.2003, page 130 of 196 Data transmission synchronization in 8-bit bus interface mode The HD66781 supports the data transmission synchronization function, which resets the upper/lower counters that count the number of data transmission of upper/lower 8 bits in the 8-bit bus interface mode. When a discrepancy occurs in the data transmission of the upper/lower 8 bits due to effects from noise and so on, the “00” H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper 8-bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. DB17~10 Upper Lower “00”H “00”H “00”H “00”H Upper Lower Upper WR RD RS (8-bit transfer synchronization) 8-bit data transmission synchronization

Rev.0.5, July.31.2003, page 131 of 196 DMA transfer Single Address mode When connecting a microcomputer or an application processor, which are compliant to DMA transfer single address mode, with the HD66781, and SRAM or pseudo SRAM, the HD66781 allows using same bus cycle for data read from memory and data write to the HD66781. This reduces transfer time and controls bus occupation ratio when transferring a large volume of data from external memory to a LCD driver. 1. Pin functions in DMA single address mode DACK: In DMA single address mode, it has the same function as CS in normal operation mode. RD: Recognize write strobe (WR) internally when DACK is at the low level (active). WR: Fix to High. CS: Fix to High. RS: Recognize a high level (data transfer) inside the HD66781 under any condition when DACK is at the low level (active). CSn* A21-0 WR RD* D15-0 SH7300 CS* RS WR* RD* DB15-0 HD66781 CS* WE* D15-0 OE* DACK* SRAM AD21-0 DREQ Port CSm* DACK* Interfacing with microcomputer and SRAM

Rev.0.5, July.31.2003, page 132 of 196 2. Transfer procedure in DMA single address mode HWM=1,AM=0,I/D Set Window address set (HSA,HEA,VSA,VEA) (R202h) Words for transfer Source address Transfer mode set Data transfer Normal operation Normal operation Settings for HD66781 Settings for DMAC Detect DREQ signal Release DREQ Setting for DMAC Transferred word counter=0 Note 1) Set to level acceptance an output from an assigned control port, DREQ judgement DREQ (Transfer request signal) output Note 1) Start transfer End of transfer Address set Index register set

Rev.0.5, July.31.2003, page 133 of 196 3. Notes to the DMA single address mode 1. DACK*pin and CS*pin cannot be made at a low level (active) simultaneously. 2. Once starting a transfer in the DMA single address mode, no command access to the HD66781 will be allowed until the end of the transfer. 3. The DMA single adders mode must be used with the window address function to make sure the number of data transfer in the DMA mode and the numbers of data in the specified window address area correspond. . 4. After transferring in the DMA mode, wait at least for RAM write execution time (bus cycle time in the normal write mode, tcycw) before issuing a next instruction. 5. It is not possible to make a transfer form the HD66781 to external memory in the DMA single address mode. 6. The DMA single address mode is compatible with the normal cycle still mode and the burst mode. CPU DMAC DREQ CPU CPU CPU DMAC CPU DMAC DMAC R / W DMAC DREQ Data transfer in DMA single address mode (burst mode) CPU CPU CPU DMAC DMAC DMAC CPU CPUDMAC DMAC R / W R / W R / W R / W R / W R / W R / W R / W R / W DMAC DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC CPUDMAC DMAC Read Read Write Write Write Read Bus cycle Bus cycle Reference: Data transfer in DMA dual address mode (burst mode) Data transfer in DMA single address mode (cycle still mode)

Rev.0.5, July.31.2003, page 134 of 196 VSYNC Interface The HD66781 incorporates a VSYNC-I/F, which enables moving picture display with a system interface and the frame synchronization signal (VSYNC) only. This interface enables the display of moving pictures with minimum modification to the conventional system. LCDC/MPU VSYNC CS* RS WR* DB17-10,8-1 HD66781 VSYNC interface The VSYNC-I/F is selected by setting DM1-0 = 10 and RM = 0. In the VSYNC I/F mode, the internal display operations are synchronized with VSYNC. By writing data to RAM through the system interface in a speed that is higher for more than a fixed speed than the internal display operation speed, it enables moving picture display through a system interface and flicker-free screen update. Display operations are executed by the internal clock generated by the internal oscillator and the VSYNC input. All display data are stored in RAM. Therefore, it only requires transfer of the data that is written over to update the screen, thereby minimizing the numbers of data transfers while displaying moving picture. The use of high-speed write mode (HWM = 1) with VSYNC interface enables RAM access in high speed with low power consumption. VSYNC System interface RAM data Write Display execution with internal clock Moving picture data transmission through VSYNC interface Note 1) Data must be written to RAM in the high-speed write mode (HWM = 1) in VSYNC interface mode.

Rev.0.5, July.31.2003, page 135 of 196 The VSYNC-I/F has limits on the minimum speed for RAM write through the system interface and the frequency of the internal clock. It requires RAM write speed more than the calculated result from the following formula. Internal clock frequency (fosc) [Hz] = Frame frequency × (Display raster-row (NL) + Front porch (FP) +Back porch (BP)) × 16 clocks × Fluctuation RAM writing speed (min.) [Hz] > 320× Display lines (NL)/{[(Back porch (BP)+Display lines (NL) – margin) x 16 clocks] /fosc} When RAM write does not start immediately after the falling edge of VSYNC, the period from the falling edge of VSYNC to the start of RAM write must also be taken into consideration. An example of calculations for the internal clock frequency and RAM write speed in the VSYNC interface mode is as follows.

• Calculation Example: moving picture display in VSYNC I/F
• Panel size 240 RGB × 320 raster-rows (NL0 = 6’27)
• Total number of raster-rows(NL) 320 raster-rows
• Back, Front porches 14, 2, raster-rows (BP = 4’hE, FP = 4’h2)
• Frame frequency 60Hz Internal clock frequency (fosc) Hz = 60 Hz × (320 + 2 + 14) raster-rows × 16 clocks × 1.1 / 0.9 = 394 [kHz] When calculating an internal clock frequency, possible causes of fluctuations must also be taken into consideration. The allowance for this fluctuation is ± 10 % from the center value, and the range of the frequency must be within the VSYNC cycle. As the causes of fluctuations, the above example takes the variation in the LSI fabrication and the room temperature into account. Other possible causes of fluctuations, such as variation in the external resistors or the voltage change are not considered in the above calculation. It is necessary to make a setting with enough margins to include the allowances for these factors. Minimum RAM writing speed [Hz] > 240 × 320 / {((14 + 320 - 2) raster-rows × 16 clocks) / 394 kHz} = 5.70 [MHz] In this case, RAM write is performed on the input of VSYNC. When the data for one frame are written to RAM completely, there must be 2 raster-rows or more of a margin before the display raster-rows. According to the above calculation results, writing data to RAM on the input of VSYNC at the speed of 5.7 MHz or more, the data for the entire screen on RAM are overwritten before the display operation starts. Accordingly, the flicker due to moving picture update can be avoided even if displaying a moving picture.

Rev.0.5, July.31.2003, page 136 of 196 BP=14H [lines] 320 RAM write (10MHz)76,800 times Display operation R-C oscillation 㫧10% RAM write 5.70MHz VSYNC 7.68 13.5 16.67 (60Hz) [ms] 13.4 FP=2H Back porch (14 lines) Panel Moving picture Display (320 lines) Blank period VSYNC RAM write Display operation Front porch (2 lines) line processing Minimum RAM write speed and internal clock frequency in VSYNC interface

Rev.0.5, July.31.2003, page 137 of 196 Notes to the VSYNC interface 1. The aforementioned example of calculation is just a result of calculation. In the actual settings, causes for the fluctuations such as internal oscillators and so on should be taken into consideration. It is necessary to make a setting for RAM write speed with enough margins. 2. The aforementioned example of calculation is the value in case of writing over the entire screen. Limiting the area for the moving picture display will create more margins for the RAM write speed. BP=14H 320 VSYNC 13.4 16.67 (60Hz) [ms] 11.8 FP=2H 㩿㪉㪇㩷㫃㫀㫅㪼㫊㪀 300 㩿㪉㪇㩷㫃㫀㫅㪼㫊㪀 [lines] Display operation R-C oscillation 㫧10% RAM write 5.70MHz Back porch (14 lines) Panel Moving picture Display (280 lines) RAM write Display operation Front porch (2 lines) Blank period line processing Condition on using VSYNC interface 3. A front porch period continues after the completion of 1 frame display and until the next input of VSYNC. 4. The transition between the internal clock operation mode (DM1-0 = 00) and the VSYNC interface mode becomes effective after displaying one frame made during instruction setting. 5. In the VSYNC interface mode, the partial display, vertical scroll, and interlaced drive functions are not available. 6. In the VSYNC interface mode, set AM to 0 to transmit display data in the aforementioned method. 7. In the VSYNC interface mode, write display data to RAM in the high speed write mode (HWM = 1)

Rev.0.5, July.31.2003, page 138 of 196 HWM = 1, AM = 0 Address Setting VSYNC interface mode setting (DM1-0=10, RM=0) VSYNC interface Writing RAM data Index resister setting (R202)h Wait more than 1 frame VSYNC interface operation Internal clock mode setting (DM1-0 = 00, RM=0) Wait more than 1 frame Internal clock operation Internal clock operation VSYNC interface operation Display operation in synchronization with the internal clocks The settings in DM1-0, RM become valid after displaying one frame. Display operation in synchronization with the internal clocks Display operation in synchronization with VSYNC Note: VSYNC signal must be supplied for at least one frame when switching to the internal clock operation. Display operation in synchronization with VSYNC Internal clock mode setting (DM1-0 = 00, RM=0) Wait more than 1 frame Internal clock operation From Internal clock operation to VSYNC interface mode From VSYNC interface mode to Internal clock operation The settings in DM1-0, RM become valid after displaying one frame. Note: VSYNC signal must be supplied before setting DM1-0, RM when switching to the VSYNC I/F mode. Transition between VSYNC and Internal clock operation modes

Rev.0.5, July.31.2003, page 139 of 196 External Display Interface The following interfaces are available as an external display interface (RGB interface). The interface is selected by setting RIM1-0 bits. The RGB interface allows RAM access. Table 65 RIM1 RIM0 RGB Interface PD Pin 0 0 18-bit RGB interface PD17-0 0 1 16-bit RGB interface PD17-13, 11-1 1 0 6-bit RGB interface PD17-12 1 1 Setting disabled - Note 1) It is not possible to use multiple interfaces at the same time. Through the RGB-I/F, the display operation is in synchronization with VSYNC, HSYNC, and DOTCLK. The RGB interface enables data transmission in high speed with low power consumption by only overwriting the area that is needed to update in the high-speed write mode in combination with window address function. Front and back porches must be set before and after the display period. HSYNC DOTCLK ENABLE(H) PD17-0 VSYNC Moving picture display area Back porch period (BP) Display period (NL) Front porch period (FP) ENABLE(V) Note 1) The front porch period continues until the next input of VSYNC signal. Note 2) The DOTCLK signal must be supplied consecutively. VSYNC: Frame synchronization signal Back porch period (BP): 14H ≥BP≥2H HSYNC: Line synchronization signal Front porch period (FP): 14H ≥FP≥2H DOTCLK: DOT clock FP + BP = 16H ENABLE: Data enable signal Display Period NL ≤320H PD17-0: RGB(6:6:6)display data The numbers of raster-rows for 1 frame FP+NL+BP

Rev.0.5, July.31.2003, page 140 of 196 In the RGB interface mode, VYSNC, HSYNC and DOTCLK must be supplied more than to achieve the resolution on the liquid crystal panels. Polarities of VSYNC, HSYNC, ENABLE, DOTCLK signals The polarities of VSYNC, HSYNC, ENABLE, DOTCLK signals are changeable by instruction settings (DPL, EPL, HSPL, and VSPL) to conform to the system. RGB interface timing Timing chart of signals in 16/18-bit RGB interface mode 1 frame Back porch period Front porch period VSYNC HSYNC DOTCLK ENABLE PD17-0 VSYNC HSYNC DOTCLK ENABLE PD17-0 HLW҈1CLK 1 clock DTST ҈1CLK Valid data 1H or more Note 1) VLW: VSYNC “Low” period HLW: HSYNC “Low” period DTST: Setup time for data transfer Note 2) Write data in the high speed write mode (HWM = 1) in the RGB I/F mode.

Rev.0.5, July.31.2003, page 141 of 196 Timing chart of signals in 6-bit RGB interface mode HSYNC DOTCLK ENABLE PD17-0 VSYNC Back porch period Front porch period 1 frame 1H or more HLW ҈ 3CLK DOTCLK 1CLK DTST ҈1CLK VSYNC HSYNC ENABLE PD17-0 R G B R G B R G B R G B R G B R G B R G B Valid data Note 1) VLW: VSYNC “Low” period HLW: HSYNC “Low” period DTST: Setup time for data transfer Note 2) Write data in the high speed write mode (HWM = 1) in the RGB I/F mode. Note 3) VSYNC, HSYNC, EVABLE, DOTCLK, and PD17-0 must be transmitted by 3 clocks.

Rev.0.5, July.31.2003, page 142 of 196 Moving picture display in RGB Interface The HD66781 incorporates the RGB interface to display moving pictures and RAM to store display data, which provides the following merits in displaying moving pictures.

• The window address function enables the transfer of only data for the moving picture area.
• The high-speed write modes enables high-speed access to RAM with low power consumption
• Only transfer data that are written over the moving picture area.
• Reduced transmission contributes to the reduction of power consumption of the entire system.
• In combination with the system interface, the still picture area, such as an icon, can be updated while displaying moving pictures. RAM access through the system interface in RGB-I/F mode RAM is accessible through the system interface in the RGB-I/F mode. In the RGB interface mode, data are being written to RAM in synchronization with the DOTCLK input while the ENABLE is “Low”. When writing data to RAM through the system interface, it is necessary to set ENABLE to “High” to stop data write through the RGB-I/F. Setting RM = 0 allows RAM access through the system interface. When reverting to the RGB interface mode, wait a write/read bus cycle. Then, set RM = 1 and the index to R202h to start RAM access though the RGB-I/F. When RAM write through the RGB and system interfaces conflicts, it is not guaranteed that the data are properly written to RAM. The following is an example of moving picture display through the RGB-I/F and updating still picture area through the system interface. In dex R202 Index R202 Address Set Data update in the area other than moving picture area Address Set RM= 1 Index R202 Moving picture area Update Note 1) An address set is made every falling edge of VSYNC in the RGB interface mode. Note 2) An address set and an index set (R202h) must be made before RAM access through the RGB interface. No te 3) Write data in the high-speed write mode (HWM = 1) in the RGB interface mode. Moving picture are a 6/26/25 00: 00:0000 Moving picture are a 6/26/25 00: 00:0000 Moving picture area Update Screen update Screen update VSYNC ENABLE DOTCLK PD17-0 System interface Note 4) When transferring to a system interface mode, wait at least 1 write cycle (tcycw) after writing through the RGB interface. Note 4)Note 4) Still picture area update Updating still picture area during moving picture display

Rev.0.5, July.31.2003, page 143 of 196 6-bit RGB interface The 6-bit RGB interface is selected by setting RIM1-0 bits to 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through 6-bit RGB data bus (PD17-12) according to the data enable signal (ENABLE). Unused pins (PD11 to 0) must be fixed to either IOVcc or GND level. The instructions are set only through the system interface. LCDC/MPULCDC/MPULCDC/MPULCDC/MPU VSYNC HDHDHDHD 66781 HSYNC DOTCLK ENABLE PD17-12 First transmission Second transmission Third tr ansmission input PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD GRAM Write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1 pixel 262,144 colors with 6-bit interfacs α αα α α α PD11-0 Example of 6-Bit RGB Interface and data format

Rev.0.5, July.31.2003, page 144 of 196 Transfer synchronization function for a 6-bit bus interface The HD66781 incorporates a transmission counter to count the first, second, third data transmissions in 6- bit RBG interface mode. The transmission counter is always reset to the first transmission on the falling edge of the VSYNC. When a discrepancy occurs in the transmission of first, second and third data, the counter is reset to the first data transmission at the start of each frame (the falling edge of VSYNC) and the data transmission restarts in the correct order from the next frame. In case of displaying moving pictures, which requires consecutive data transfer, this function minimizes the effect from the discrepancy in the data transmission and facilitates to return to the normal display. VSYNC ENABLE DOTCLK PD17-0 Transfer synchronization 2nd Transmission 1st Trans- mission 2nd Trans- mission 3rd Trans- mission 1st Trans- mission 2nd Trans- mission 3rd Trans- mission 6-bit Transfer Synchronization

Rev.0.5, July.31.2003, page 145 of 196 16-bit RGB interface The 16-bit RGB interface is selected by setting RIM1-0 bits to 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through16-bit RGB data bus (PD17-13, 11-1) according to the data enable signal (ENABLE). The instructions are set only through the system interface. LCDC/MPU VSYNC HD66781 HSYNC DOTCLK ENABLE PD17-13,11-1 PD12,0 input PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 pixel 65,536 colors with 16-bit interface input PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD GRAM wr e data R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 pixel 8,192 colors with 16-bit interface input PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD GRAM write data 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 pixel 8,192 colors with 16-bit interface α α αα α α Example of 16-Bit RGB Interface and data format

Rev.0.5, July.31.2003, page 146 of 196 18-bit RGB interface The 18-bit RGB interface is selected by setting RIM1-0 bits to 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through 18-bit RGB data bus (PD17-0) according to the data enable signal (ENABLE). The instructions are set only through the system interface. LCDC/MPU VSYNC HD66781 HSYNC DOTCLK ENABLE PD17-0 input PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 262,144 colors with 18-bit RGB interface α α αα αα Example of 18-Bit RGB Interface and data format

Rev.0.5, July.31.2003, page 147 of 196 Notes to the external display interface 1. While an external display interface is selected, the following functions are not available. Table 66 Function External Display Interf ace Internal Display Operation Partial display Not available Available Scroll function Not available Available Interlaced drive Not available Available 2. The VSYNC, HSYNC, and DOTCLK signals must be supplied through the display operation through the RGB-I/F. 3. When making settings for gate driver/LTPS panel controlling signal in the RGB-I/F modes, the reference clock is DOTCLK, not the internal operation clocks. 4. In the 6-bit RGB-I/F mode, the RGB (pixels) data are transmitted by three clocks. 5. In the 6-bit RGB-I/F mode, the interface signals, VSYNC, HSYNC, DOTCL, ENABLE, and PD17-0, should be set by RGB (pixels) unit in convenience for the transmitting RGB pixels. 6. The transitions between the internal operation mode and external display interface should be made according to the mode switching sequence below. 7. In the RGB-I/F mode, the front porch period continues after displaying one frame data until the next VSYNC signal input. 8. In the RGB-I/F mode, the data must be written in the high-speed write mode (HWM = 1). 9. In the RGB-I/F mode, the address is set every frame on the falling edge of VSYNC. HWM = 1, AM = 0 Set Address RGB I/F Setting (DM1-0=01, RM=1) RGB I/F Write RAM data Index resister setting (R202h) Wait more than 1 frame Internal clock operation to RGB I/F (1) Internal clock mode setting (DM1-0 = 00, RM=0) Wait more than 1 frame Internal clock operation RGB I/F (1) to Internal clock operation Internal clock operation RGB I/F operation Display operation in synchronization with the internal clock Display operation in synchronization with VSYNC, HSYNC, DOTCLK Display operation in synchronization with the internal clock Display operation in synchronization with VSYNC, HSYNC, DOTCLK From From The settings in DM1-0, RM become valid after displaying one frame. Note: RGB interface signals must be supplied for at least one frame when switching to the internal clock operation. Note: RGB interface signals must be supplied before setting DM1-0, RM when switching to the RGB I/F mode. The settings in DM1-0, RM become valid after displaying one frame. RGB interface operation

Rev.0.5, July.31.2003, page 148 of 196 Display Synchroniaing Data Transfer The HD66781 outputs BST signal that indicates the start of vertical retrace line period for flicker-free screen update. The BST signal is used as trigger to start internal GRAM write so that data transfer is synchronized with display scan. LCDC/MPU BST CS* RS WR* DB17-10,8-1 HD66781 Display synchronizing data transfer: Interface example By writing data to RAM through the system interface in a speed that is higher for more than a fixed speed than the internal display operation speed, it enables moving picture display through an conventional interface and flicker-free screen update. All display data are stored in RAM. Therefore, it only requires transfer of the data that is written over to update the screen, thereby minimizing the numbers of data transfers while displaying moving picture. The use of high-speed write mode (HWM = 1) with VSYNC interface enables RAM access in high speed with low power consumption. BST System interface RAM data Write Display execution with internal clock Moving picture data transmission through VSYNC interface Note 1) Data must be written to RAM in the high-speed write mode (HWM = 1) in VSYNC interface mode.

Rev.0.5, July.31.2003, page 149 of 196 The display synchronizing data transfer mode has limits on the minimum speed for RAM write through the system interface and the frequency of the internal clock. It requires RAM write speed more than the calculated result from the following formula. Internal clock frequency (fosc) [Hz] = Frame frequency × (Display raster-row (NL) + Front porch (FP) +Back porch (BP)) × 16 clocks × Fluctuation RAM writing speed (min.) [Hz] > 320× Display lines (NL)/{[(Front porch (FP)+Back porch (BP)+Display lines (NL) – margin) x 16 clocks] /fosc} When RAM write does not start immediately after the rising edge of BST, the period from the rising edge of BST to the start of RAM write must also be taken into consideration. An example of calculations for the internal clock frequency and RAM write speed in the display synchronizing data transfer mode is as follows.

• Calculation Example: moving picture display in VSYNC I/F
• Panel size 240 RGB × 320 raster-rows (NL0 = 6’27)
• Total number of raster-rows(NL) 320 raster-rows
• Back, Front porches 14, 2, raster-rows (BP = 4’hE, FP = 4’h2)
• Frame frequency 60Hz Internal clock frequency (fosc) Hz = 60 Hz × (320 + 2 + 14) raster-rows × 16 clocks × 1.1 / 0.9 = 394 [kHz] When calculating an internal clock frequency, possible causes of fluctuations must also be taken into consideration. The allowance for this fluctuation is ± 10 % from the center value, and the range of the frequency must be within the BST signal cycle. As the causes of fluctuations, the above example takes the variation in the LSI fabrication and the room temperature into account. Other possible causes of fluctuations, such as variation in the external resistors or the voltage change are not considered in the above calculation. It is necessary to make a setting with enough margins to include the allowances for these factors. Minimum RAM writing speed [Hz] > 240 × 320 / {((2+14 + 320 - 2) raster-rows × 16 clocks) / 394 kHz} = 5.66 [MHz] In this case, RAM write is performed on the rising edge of BST. When the data for one frame are written to RAM completely, there must be 2 raster-rows or more of a margin before the display raster-rows. According to the above calculation results, writing data to RAM on the rising of BST at the speed of 5.66 MHz or more, the data for the entire screen on RAM are overwritten before the display operation starts. Accordingly, the flicker due to moving picture update can be avoided even if displaying a moving picture.

Rev.0.5, July.31.2003, page 150 of 196 FP+BP=16H [lines] 320 RAM write (10MHz)76,800 times Display operation R-C oscillation 㫧10% RAM write 5.66MHz 7.68 13.5 16.67 (60Hz) [ms] 13.4 Panel Moving picture Display (320 lines) RAM write Display operation Front porch (2 lines) Back porch (14 lines) Back porch (14 lines) Front porch (2 lines) BST BST line processing Minimum RAM write speed and internal clock frequency in VSYNC interface Notes to the display synchronizing GRAM data transfer mode 1. The aforementioned example of calculation is just a result of calculation. In the actual settings, causes for the fluctuations such as internal oscillators and so on should be taken into consideration. It is necessary to make a setting for RAM write speed with enough margins. 2. In the display synchronizing GRAM data transfer mode, write display data to RAM in the high speed write mode (HWM = 1)

Rev.0.5, July.31.2003, page 151 of 196 Timing interfacing with LCD panel signals The relationship between RGB I/F signals and LCD panel signals during internal operation is as follows. Timing interfacing with liquid crystal panel signals in RGB interface mode HSYNC DOTCLK ENABLE PD17-0 VSYNC Back porch period Front porch period 1 frame 123456 3 2 0 319318317316315 123 4 320319318317 FLM CL1 Gn G320 S1~720 DPT SDT Gn+1 nn-1 n+ 2n+1 M (VCOM) (EQ) EQ 5DOTCLK 5DOTCLK (BST) Note 1) This figure is the example when DIVE[1:0] = 2’h2

Rev.0.5, July.31.2003, page 152 of 196 Timing interfacing with liquid crystal panel signals in internal clock operation mode 123 4 320319318317 (CL1) Gn G320 S1~720 DPT SDT Gn+1 nn-1 n+ 2n+1 M (VCOM) (EQ) EQ 1H Front porch period + Back porch period 1 frame (BST)

Rev.0.5, July.31.2003, page 153 of 196 High-Speed Burst RAM Write Function The HD66781 incorporates high-speed burst RAM-write function, which writes data to RAM about half the time required for the normal RAM write. This function is especially useful for applications, which require high-speed display data rewrite, such as colored moving picture display and so on. In the high-speed RAM-write mode (HWM=1), data to write to RAM is temporarily stored to the internal register of HD66781 and then written to RAM by horizontal line in the area specified by the window address. Since the data stored in the register are written to RAM at once, it is possible to write next data to the internal register while data are being written from the internal register to RAM. This reduces the frequency of RAM access to minimum and enables consecutive high-speed access to the internal RAM with low power consumption, which is required for moving picture display. Latch circuit 18 x n Address counter AC Microcomputer Register 1 Register 2 Register n 18’h0-0000 18’h0-0001 18’h0-0003 GRAM High-speed consecutive access to RAM, operational flow CS input WR input DB17-0 input index (R202) RAM data (n) index (R202) RAM data (1) - (n) RAM data (2n+1) - (3n) RAM data (n+1) - (2n) RAM write execution time RAM write execution ti me RAM write execution time x 2 Note 18’h00000 – 18’h0000n 18’h00200 – 18’h0020n 18’h00100 – 18’h0010n RAM write data (18 x n bits) RAM address (AC17-0) High-speed consecutive access to RAM (HWM = “1”) Note 1) When making a transition from the high-speed RAM write to the index write, wait at least 2 bus cycle time (tcycw) in the normal write mode after RAM write before executing next instructions.

Rev.0.5, July.31.2003, page 154 of 196 CS in put WR in put DB17-0 in put index R202 RAM data (1) - (n) RAM data (n+1) – (2n ) RAM wri te execution time RAM wri te data (18 x n bit s) RAM ad dress (AC16-0) RAM data upper (1) RAM data lower (1) RAM data upper (n) RAM data lower (n) RAM data upper (1) RAM data lower (1) RAM data upper (n) RAM data lower (n) RAM wri te execution time 18’h00000 – 18’h0000n 18’h00100 – 18’h0010n 12 3 45 6 7 8 High-speed consecutive access to RAM (9-bit interface) Note 1) The high-speed RAM write mode (HWM=1) writes data to RAM by n words. In the 9-bit interface mode, data are written to RAM 2xn times per line. Notes to the high-speed RAM write mode 1. RAM write is executed by line. If write operation is terminated before it reaches the end of horizontal line of the window-address area, it is not guaranteed that data are properly written on that line. 2. The index register for the RAM data write (202H), if selected, executes the first data write operation. This setting does not allow RAM data read. HWM must be set to 0 during RAM read. 3. The high-speed RAM write mode is not compatible with the normal RAM write mode. Whenever switching to the other mode, it is necessary to set the address before starting RAM write. Table 67 Normal RAM Write (HWM=0) High-Speed RAM Write (HWM=1) BGR function Available Available Write mask function Available Available RAM address set Set by words Set by words RAM read Set by words Not available RAM write Set by words Set by lines Window address Set by words (minimum range: 1 word x 1 line) Set by words (minimum range: 8 word x 1 line) External display interface Available Available AM AM = 1/0 AM = 0

Rev.0.5, July.31.2003, page 155 of 196 High-Speed RAM Write with Window Address Function Specifying a window-address range (minimum range: 8 words x 1 word) enables consecutive high-speed RAM data write in an arbitrary rectangular area on RAM. In the high-speed write mode, data must be written to RAM by horizontal lines. If RAM write is terminated in the middle of the line, there is no guarantee that data are properly written on that line. The following figure illustrates an example of high-speed RAM write in the window-address range on RAM. By setting the window address specifying bits (HSA = 8’h10, HEA = 8’h2F, VSA = 9’h020, VEA = 9’h05F), data are written consecutively in high speed in the window-address range specified by these bits. 00000h 10F83h 18’h02012 18’h05BA7 Window address-range GRAM addr ess map Window addr ess-range setting HA S = 8’h10, HE A = 8’h2F VSA = 9’h020, VEA = 9’h05F AM = 0, I D0 = 1 Wi ndow addr ess-r ange set t ing HAS = 8’h12, HEA = 8'hA8 VSA = 9’h020, VEA = 9'h05F High-speed RAM w rite mode setting HW M = 1 Address set AD = 18’h02010* RAM w rite x 150 x 60 times * Note: Make an address set within the window address Write in the horizontal direction (overwritten area)

Rev.0.5, July.31.2003, page 156 of 196 Window Address Function The window address function writes data consecutively to the on-chip GRAM within the rectangular window-address range specified by the horizontal address registers (start: HSA7-0, end: HEA 7-0) and the vertical address registers (start: VSA7-0, end: VEA7-0). The address transition direction is determined by AM bit (either increment or decrement). This allows writing data, including picture data, consecutively without taking the data wrap position into consideration. The window-address range must be specified within the GRAM address area. An address set must be made within the window-address range. [Conditions on setting window-address range] (horizontal direction) 8’h00 ≤ HSA ≤ HEA ≤ 8’hEF (vertical direction) 9’h000 ≤ VSA ≤ VEA ≤ 9’h19F [Conditions on making an address set within the window-address range] (RAM address) HSA ≤ AD7-0 ≤ HEA VSA ≤ AD16-8 ≤ VEA 18’h05F2F 18’h0202F 18’h0212F Window address area 18’h00000 18’h000EF 18’h19F00 18’h19FEF 18’h02110 18’h05F10 18’h02010 GRAM address map Window address range setting HSA= 8’h10, HEA = 8’h2F I/D = 2’h3(increment) VSA = 9’h020,VEA = 9’h05F AM = 1’h0(Horizontal write) Address transition direction in specified window-address range

Rev.0.5, July.31.2003, page 157 of 196 γ-Correction Function The HD66781 incorporates γ-correction function to simultaneously display 262,144 colors, by which 8- level grayscale is determined by the gradient-adjustment and fine-adjustment registers. The HD66781 incorporates gradient-adjustment and fine-adjustment registers for both positive and negative polarities and allows selecting either positive or negative polarity according to the characteristics of a liquid crystal panel. LCD 648 Gray-scale amp 64 gray-scale control <R> LCD driver R 64 gray-scale control <G> LCD driver G 64 gray-scale control <B> LCD driver B V63 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 666 Display data GRAM MSB L SB + polar register - polar register PKP0[2:0] PKN0[2:0] PKP1[2:0] PKN1[2:0] PKP2[2:0] PKN2[2:0] PKP3[2:0] PKN3[2:0] PKP4[2:0] PKN4[2:0] PKP5[2:0] PKN5[2:0] PRP0[2:0] PRN0[2:0] PRP1[2:0] PRN1[2:0] VRP0[3:0] VRN0[3:0] VRP1[4:0] VRN1[4:0] LCD Grayscale control

Rev.0.5, July.31.2003, page 158 of 196 Grayscale Amplifier Configuration The following figure illustrates the configuration of grayscale amplifier. The eight-level grayscales (VIN0-7) are determined by the gradient adjustment and fine adjustment registers. The 8 levels are then divided by the ladder resistors placed between each level into 64 levels (V0-63). Increment adjustment Fine adjustment(6 x 3 bits) Amplitude adjustment 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector Ladder resistor Gray-scale ope-amp PRP/N0,PRP/N1 VRP/N0 3 3 3 3 3 3 3 3 5 PKP/N0 PKP/N1 PKP/N2 PKP/N3 PKP/N4 PKP/N5 VINP0 /VINN0 VINP1 /VINN1 VINP2 /VINN2 VINP3 /VINN3 VINP4 /VINN4 VINP5 /VINN5 VINP6 /VINN6 VINP7 /VINN7 V20 V21 V43 V44 V55 V56 V62 V63 V57 VDH VGS VRP/N1 Grayscale amplifier

Rev.0.5, July.31.2003, page 159 of 196 KVN9 RN8 KVN10 RN9 KVN11 RN10 KVN12 RN11 KVN13 RN12 KVN14 RN13 KVN15 RN14 KVN16 PKN1[2:0] 8 to 1 SEL VINN2 KVN17 RN16 KVN18 RN17 KVN19 RN18 KVN20 RN19 KVN21 RN20 KVN22 RN21 KVN23 RN22 KVN24 PKN2[2:0] 8 to 1 SEL VINN3 KVN25 RN24 KVN26 RN25 KVN27 RN26 KVN28 RN27 KVN29 RN28 KVN30 RN29 KVN31 RN30 KVN32 PKN3[2:0] 8 to 1 SEL VINN4 KVN33 RN32 KVN34 RN33 KVN35 RN34 KVN36 RN35 KVN37 RN36 KVN38 RN37 KVN39 RN38 KVN40 PKN4[2:0] 8 to 1 SEL VINN5 KVN41 RN39 KVN42 RN40 KVN43 RN41 KVN44 RN42 KVN45 RN43 KVN46 RN44 KVN47 RN45 KVN48 PKN5[2:0] 8 to 1 SEL VINN6 KVN1 RN1 KVN2 RN2 KVN3 RN3 KVN4 RN4 KVN5 RN5 KVN6 RN6 KVN7 RN7 KVN8 PKN0[2:0] 8 to 1 SEL VINN1 PRN0[2:0] VRHN 0~28R PRN1[2:0] VRLN 0~28R 5R RN15 16R RN23 5R RP 31 5R RN0 VINN0 5R RN46 VRN[4:0] VRN1 0~31R 8R RN47 KVP0 VINN7KVN49 KVP9 RP8 KVP10 RP9 KVP11 RP10 KVP12 RP11 KVP13 RP12 KVP14 RP13 KVP15 RP14 KVP16 PKP1 [2:0 ] 8 to 1 SEL VINP2 KVP17 RP16 KVP18 RP17 KVP19 RP18 KVP20 RP19 KVP21 RP20 KVP22 RP21 KVP23 RP22 KVP24 PKP2 [2:0 ] 8 to 1 SEL VINP3 KVP25 RP24 KVP26 RP25 KVP27 RP26 KVP28 RP27 KVP29 RP28 KVP30 RP29 KVP31 RP30 KVP32 PKP3 [2:0 ] 8 to 1 SEL VINP4 KVP33 RP32 KVP34 RP33 KVP35 RP34 KVP36 RP35 KVP37 RP36 KVP38 RP37 KVP39 RP38 KVP40 PKP4 [2:0 ] 8 to 1 SEL VINP5 KVP41 RP39 KVP42 RP40 KVP43 RP41 KVP44 RP42 KVP45 RP43 KVP46 RP44 KVP47 RP45 KVP48 PKP5 [2:0 ] 8 to 1 SEL VINP6 KVP1 RP1 KVP2 RP2 KVP3 RP3 KVP4 RP4 KVP5 RP5 KVP6 RP6 KVP7 RP7 KVP8 PKP0 [2:0 ] 8 to 1 SEL VINP1 PRP0[2:0] VRHP 0~28R PRP1[2:0] VRLP 0~28R 5R RP 15 16R RP 23 5R RP 31 5R RP 0 VINP0 5R RP 46 VRP[4:0] VRP1 0~31R 8R RP 47 KVP0 VINP7 KVP49 VRP0 0 ~15R VGS VDH VRN0 1 ~ 15R VRP0[3:0] VRN0[3:0] Ladder Resistors and 8 to 1 Selectors

Rev.0.5, July.31.2003, page 160 of 196 γ-Correction Registers The γ-adjustment register is a group of registers to set an appropriate grayscale voltage for the γ- characteristics of a liquid crystal panel. The register group is categorized into the ones adjusting gradient, amplitude, and reference value and fine-tuning in relation to grayscale number and grayscale voltage characteristics. Each register group can make an independent setting for the positive/negative polarity. The reference value and RGB are common to both polarities. Gray-scale voltage Gray-scale number Gradient adjustment Gray-scale voltage Gray-scale number Fine adjustment Gray-scale voltage Gray-scale number Amplitude adjustment Gradient, Amplitude, Fine Adjustments 1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient around the middle of the grayscale number and voltage characteristics without changing a dynamic range. To adjust a gradient, the values of the variable resistors (VRHP (N)/VRLP (N)) in the ladder resistor block for grayscale voltage generation are controlled. The registers incorporate separate registers for positive and negative polarities to be compatible with asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. To adjust the amplitude, the values of the variable resistors (VRP(N)1/0) in the upper and lower parts of the ladder resistor block for grayscale voltage generation are adjusted. Same with the gradient registers, the amplitude adjustment registers also incorporate separate registers for positive and negative polarities. 3. Fine adjustment registers The fine adjustment register is to fine-adjust the grayscale voltage level. To fine-adjust the grayscale voltage level, 8-to-1 selectors control each level of 8-level reference voltages generated from the ladder registers. Same with the other registers, the fine adjustment registers also incorporate separate registers for positive and negative polarities.

Rev.0.5, July.31.2003, page 161 of 196 Table 68 List of output signals Register Groups Positive Polarity Negative Polarity PRP0 [2:0] PRN0 [2:0] Vari able resistor VRHP (N) Gradient adjustment PRP1 [2:0] PRN1 [2:0] Vari able resistor VRLP (N) VRP0 [3:0] VRN0 [3:0] Vari able resistor VRP (N) 0 Amplitude adjustment VRP1 [4:0] VRN1 [4:0] Vari able resistor VRP (N) 1 PKP0 [2:0] PKN0 [2:0] 8-to-1 selector (voltage level of grayscale 1) PKP1 [2:0] PKN1 [2:0] 8-to-1 selector (voltage level of grayscale 8) PKP2 [2:0] PKN2 [2:0] 8-to-1 selector (voltage level of grayscale 20) PKP3 [2:0] PKN3 [2:0] 8-to-1 selector (voltage level of grayscale 43) PKP4 [2:0] PKN4 [2:0] 8-to-1 selector (voltage level of grayscale 55) Fine adjustment PKP5 [2:0] PKN5 [2:0] 8-to-1 selector (voltage level of grayscale 62)

Rev.0.5, July.31.2003, page 162 of 196 Ladder resistors and 8 to 1 selector Block configuration The block configuration of page 159 consists of two ladder resistors including variable resistors, and 8 to 1 selectors, which select the voltage generated by the ladder resistors, to output the reference voltage for the grayscale voltage. The γ−correction registers control the variable resistors and the 8 to 1 selectors. Pins that are connected to a variable resistor are also provided to compensate the variation among the panels. Variable resistors There are three kinds of variable resistors for the gradient adjustment (VRHP(N)/VRLP(N)), the amplitude adjustment (VRP(N)), and the reference adjustment (VDR). The resistance is determined by the gradient adjustment and amplitude adjustment registers as is shown below. Table 69 Gradient adjustment Amplitude adjustment Reference adjustment Register PRP(N)0/1[2:0] Resistance VRHP(N) VRLP(N) Register VRP(N)0[3:0] Resistance VRP(N)0 Register VRP(N)1[4:0] Resistance VRP(N)1 000 0R 0000 0R 00000 0R 001 4R 0001 1R 00001 1R 010 8R 0010 2R 00010 2R 011 12R 100 16R 101 20R 1101 13R 11101 29R 110 24R 1110 14R 11110 30R 111 28R 1111 15R 11111 31R 8 to 1 selector The 8-to-1 selectors select a voltage level generated by the ladder resistors according to the fine adjustment registers, and output as a reference voltage of either one of the following VIN1 ~ VIN 6. The relationship between the fine adjustment register and the selected voltage is as follows Table 70 Contents of Register Selected Voltage PKP(N) 0/1 [2:0] VINP(N)1 VINP(N)2 VINP(N)3 VINP(N)4 VINP(N)5 VINP(N)6

000 KVP(N)1 KVP(N)9 KVP(N)1 7 KVP(N)25 KVP(N)33 KVP(N)41

001 KVP(N)2 KVP(N)10 KVP(N)1 8 KVP(N)26 KVP(N)34 KVP(N)42

010 KVP(N)3 KVP(N)11 KVP(N)1 9 KVP(N)27 KVP(N)35 KVP(N)43

011 KVP(N)4 KVP(N)12 KVP(N)2 0 KVP(N)28 KVP(N)36 KVP(N)44

100 KVP(N)5 KVP(N)13 KVP(N)2 1 KVP(N)29 KVP(N)37 KVP(N)45

101 KVP(N)6 KVP(N)14 KVP(N)2 2 KVP(N)30 KVP(N)38 KVP(N)46

110 KVP(N)7 KVP(N)15 KVP(N)2 3 KVP(N)31 KVP(N)39 KVP(N)47

111 KVP(N)8 KVP(N)16 KVP(N)2 4 KVP(N)32 KVP(N)40 KVP(N)48

Rev.0.5, July.31.2003, page 163 of 196 The gray scale levels (V0-V63) are calculated according to the following formulas. Formulas for calculating voltage (Positive polarity) (1) Pins Formula Fine-adjustment registers Reference voltage KVP0 VDH- ƒ¢V*VxP0/SUMRP | VINP0 KVP1 VDH- ƒ¢V*(VxRP0+5R)/SUMRP PKP0[2:0]=”000” KVP2 VDH- ƒ¢V*(VxRP0+9R)/SUMRP PKP0[2:0]=”001” KVP3 VDH- ƒ¢V*(VxRP0+13R)/SUMRP PKP0[2:0]=”010” KVP4 VDH- ƒ¢V*(VxRP0+17R)/SUMRP PKP0[2:0]=”011” KVP5 VDH- ƒ¢V*(VxRP0+21R)/SUMRP PKP0[2:0]=”100” KVP6 VDH- ƒ¢V*(VxRP0+25R)/SUMRP PKP0[2:0]=”101” KVP7 VDH- ƒ¢V*(VxRP0+29R)/SUMRP PKP0[2:0]=”110” KVP8 VDH- ƒ¢V*(VxRP0+33R)/SUMRP PKP0[2:0]=”111” VINP1 KVP9 VDH- ƒ¢V*iVxRP0+33R+VRHPj/SUMRP PKP1[2:0]=”000” KVP10 VDH- ƒ¢V*iVxRP0+34R+VRHPj/SUMRP PKP1[2:0]=”001” KVP11 VDH- ƒ¢V*iVxRP0+35R+VRHPj/SUMRP PKP1[2:0]=”010” KVP12 VDH- ƒ¢V*iVxRP0+36R+VRHPj/SUMRP PKP1[2:0]=”011” KVP13 VDH- ƒ¢V*iVxRP0+37R+VRHPj/SUMRP PKP1[2:0]=”100” KVP14 VDH- ƒ¢V*iVxRP0+38R+VRHPj/SUMRP PKP1[2:0]=”101” KVP15 VDH- ƒ¢V*iVxRP0+39R+VRHPj/SUMRP PKP1[2:0]=”110” KVP16 VDH- ƒ¢V*iVxRP0+40R+VRHPj/SUMRP PKP1[2:0]=”111” VINP2 KVP17 VDH- ƒ¢V*iVxRP0+45R+VRHPj/SUMRP PKP2[2:0]=”000” KVP18 VDH- ƒ¢V*iVxRP0+46R+VRHPj/SUMRP PKP2[2:0]=”001” KVP19 VDH- ƒ¢V*iVxRP0+47R+VRHPj/SUMRP PKP2[2:0]=”010” KVP20 VDH- ƒ¢V*iVxRP0+48R+VRHPj/SUMRP PKP2[2:0]=”011” KVP21 VDH- ƒ¢V*iVxRP0+49R+VRHPj/SUMRP PKP2[2:0]=”100” KVP22 VDH- ƒ¢V*iVxRP0+50R+VRHPj/SUMRP PKP2[2:0]=”101” KVP23 VDH- ƒ¢V*iVxRP0+51R+VRHPj/SUMRP PKP2[2:0]=”110” KVP24 VDH- ƒ¢V*iVxRP0+52R+VRHPj/SUMRP PKP2[2:0]=”111” VINP3 KVP25 VDH- ƒ¢V*iVxRP0+68R+VRHPj/SUMRP PKP3[2:0]=”000” KVP26 VDH- ƒ¢V*iVxRP0+69R+VRHPj/SUMRP PKP3[2:0]=”001” KVP27 VDH- ƒ¢V*iVxRP0+70R+VRHPj/SUMRP PKP3[2:0]=”010” KVP28 VDH- ƒ¢V*iVxRP0+71R+VRHPj/SUMRP PKP3[2:0]=”011” KVP29 VDH- ƒ¢V*iVxRP0+72R+VRHPj/SUMRP PKP3[2:0]=”100” KVP30 VDH- ƒ¢V*iVxRP0+73R+VRHPj/SUMRP PKP3[2:0]=”101” KVP31 VDH- ƒ¢V*iVxRP0+74R+VRHPj/SUMRP PKP3[2:0]=”110” KVP32 VDH- ƒ¢V*iVxRP0+75R+VRHPj/SUMRP PKP3[2:0]=”111” VINP4 KVP33 VDH- ƒ¢V*iVxRP0+80R+VRHPj/SUMRP PKP4[2:0]=”000” KVP34 VDH- ƒ¢V*iVxRP0+81R+VRHPj/SUMRP PKP4[2:0]=”001” KVP35 VDH- ƒ¢V*iVxRP0+82R+VRHPj/SUMRP PKP4[2:0]=”010” KVP36 VDH- ƒ¢V*iVxRP0+83R+VRHPj/SUMRP PKP4[2:0]=”011” KVP37 VDH- ƒ¢V*iVxRP0+84R+VRHPj/SUMRP PKP4[2:0]=”100” KVP38 VDH- ƒ¢V*iVxRP0+85R+VRHPj/SUMRP PKP4[2:0]=”101” KVP39 VDH- ƒ¢V*iVxRP0+86R+VRHPj/SUMRP PKP4[2:0]=”110” KVP40 VDH- ƒ¢V*iVxRP0+87R+VRHPj/SUMRP PKP4[2:0]=”111” VINP5 KVP41 VDH- ƒ¢V*iVxRP0+87R+VRHP+VRLPj/SUMRP PKP4[2:0]=”000” KVP42 VDH- ƒ¢V*iVxRP0+91R+VRHP+VRLPj/SUMRP PKP5[2:0]=”001” KVP43 VDH- ƒ¢V*iVxRP0+95R+VRHP+VRLPj/SUMRP PKP5[2:0]=”010” KVP44 VDH- ƒ¢V*iVxRP0+99R+VRHP+VRLPj/SUMRP PKP5[2:0]=”011” KVP45 VDH- ƒ¢V*iVxRP0+103R+VRHP+VRLPj/SUMRP PKP5[2:0]=”100” KVP46 VDH- ƒ¢V*iVxRP0+107R+VRHP+VRLPj/SUMRP PKP5[2:0]=”101” KVP47 VDH- ƒ¢V*iVxRP0+111R+VRHP+VRLPj/SUMRP PKP5[2:0]=”110” KVP48 VDH- ƒ¢V*iVxRP0+115R+VRHP+VRLPj/SUMRP PKP5[2:0]=”111” VINP6 KVP49 VDH- ƒ¢V*iVxRP0+120R+VRHP+VRLPj/SUMRP | VINP7 Note 1) Sum of ladder resistors with positive polarities = 128R+VRHP+VRLP+VRP0+VRP1 Note 2) Sum of ladder resistors with negative polarities = 128R+VRHN+VRLN+VRN0+VRN1 Note 3) ∆V :Electric potential difference between VDH and VGS

Rev.0.5, July.31.2003, page 164 of 196 Formulas for calculating voltage (Positive polarity) (2) Grayscale voltage Formula Grayscale voltage Formula V0 VINP0 V32 V43+(V20-V43)*(11/23) V1 VINP1 V33 V43+(V20-V43)*(10/23) V8 VINP2 V40 V43+(V20-V43)*(3/23) V11 V20+(V8-V20)*(18/24) V43 VINP4 V20 VINP3 V52 V55+(V43-V55)*(6/24) V23 V43+(V20-V43)*(20/23) V55 VINP5 V30 V43+(V20-V43)*(13/23) V62 VINP6 V31 V43+(V20-V43)*(12/23) V63 VINP7 Note 1) Make sure DDVDH – V0 > 0.5V, DDVDH – V4 > 1.1V, V55-GND > 1.1V

Rev.0.5, July.31.2003, page 165 of 196 Formulas for calculating voltage (Negative polarity) (1) Pins Formula Fine-adjustment registers Reference voltage KVN0 VDH- ƒ¢V*VxRN0/SUMRN | VINN0 KVN1 VDH- ƒ¢V*(VxRN0+5R)/SUMRN PKN0[2:0]=”000” KVN2 VDH- ƒ¢V*(VxRN0+9R)/SUMRN PKN0[2:0]=”001” KVN3 VDH- ƒ¢V*(VxRN0+13R)/SUMRN PKN0[2:0]=”010” KVN4 VDH- ƒ¢V*(VxRN0+17R)/SUMRN PKN0[2:0]=”011” KVN5 VDH- ƒ¢V*(VxRN0+21R)/SUMRN PKN0[2:0]=”100” KVN6 VDH- ƒ¢V*(VxRN0+25R)/SUMRN PKN0[2:0]=”101” KVN7 VDH- ƒ¢V*(VxRN0+29R)/SUMRN PKN0[2:0]=”110” KVN8 VDH- ƒ¢V*(VxRN0+33R)/SUMRN PKN0[2:0]=”111” VINN1 KVN9 VDH- ƒ¢V*iVxRN0+33R+VRHNj/SUMRN PKN1[2:0]=”000” KVN10 VDH- ƒ¢V*iVxRN0+34R+VRHNj/SUMRN PKN1[2:0]=”001” KVN11 VDH- ƒ¢V*iVxRN0+35R+VRHNj/SUMRN PKN1[2:0]=”010” KVN12 VDH- ƒ¢V*iVxRN0+36R+VRHNj/SUMRN PKN1[2:0]=”011” KVN13 VDH- ƒ¢V*iVxRN0+37R+VRHNj/SUMRN PKN1[2:0]=”100” KVN14 VDH- ƒ¢V*iVxRN0+38R+VRHNj/SUMRN PKN1[2:0]=”101” KVN15 VDH- ƒ¢V*iVxRN0+39R+VRHNj/SUMRN PKN1[2:0]=”110” KVN16 VDH- ƒ¢V*iVxRN0+40R+VRHNj/SUMRN PKN1[2:0]=”111” VINN2 KVN17 VDH- ƒ¢V*iVxRN0+45R+VRHNj/SUMRN PKN2[2:0]=”000” KVN18 VDH- ƒ¢V*iVxRN0+46R+VRHNj/SUMRN PKN2[2:0]=”001” KVN19 VDH- ƒ¢V*iVxRN0+47R+VRHNj/SUMRN PKN2[2:0]=”010” KVN20 VDH- ƒ¢V*iVxRN0+48R+VRHNj/SUMRN PKN2[2:0]=”011” KVN21 VDH- ƒ¢V*iVxRN0+49R+VRHNj/SUMRN PKN2[2:0]=”100” KVN22 VDH- ƒ¢V*iVxRN0+50R+VRHNj/SUMRN PKN2[2:0]=”101” KVN23 VDH- ƒ¢V*iVxRN0+51R+VRHNj/SUMRN PKN2[2:0]=”110” KVN24 VDH- ƒ¢V*iVxRN0+52R+VRHNj/SUMRN PKN2[2:0]=”111” VINN3 KVN25 VDH- ƒ¢V*iVxRN0+68R+VRHNj/SUMRN PKN3[2:0]=”000” KVN26 VDH- ƒ¢V*iVxRN0+69R+VRHNj/SUMRN PKN3[2:0]=”001” KVN27 VDH- ƒ¢V*iVxRN0+70R+VRHNj/SUMRN PKN3[2:0]=”010” KVN28 VDH- ƒ¢V*iVxRN0+71R+VRHNj/SUMRN PKN3[2:0]=”011” KVN29 VDH- ƒ¢V*iVxRN0+72R+VRHNj/SUMRN PKN3[2:0]=”100” KVN30 VDH- ƒ¢V*iVxRN0+73R+VRHNj/SUMRN PKN3[2:0]=”101” KVN31 VDH- ƒ¢V*iVxRN0+74R+VRHNj/SUMRN PKN3[2:0]=”110” KVN32 VDH- ƒ¢V*iVxRN0+75R+VRHNj/SUMRN PKN3[2:0]=”111” VINN4 KVN33 VDH- ƒ¢V*iVxRN0+80R+VRHNj/SUMRN PKN4[2:0]=”000” KVN34 VDH- ƒ¢V*iVxRN0+81R+VRHNj/SUMRN PKN4[2:0]=”001” KVN35 VDH- ƒ¢V*iVxRN0+82R+VRHNj/SUMRN PKN4[2:0]=”010” KVN36 VDH- ƒ¢V*iVxRN0+83R+VRHNj/SUMRN PKN4[2:0]=”011” KVN37 VDH- ƒ¢V*iVxRN0+84R+VRHNj/SUMRN PKN4[2:0]=”100” KVN38 VDH- ƒ¢V*iVxRN0+85R+VRHNj/SUMRN PKN4[2:0]=”101” KVN39 VDH- ƒ¢V*iVxRN0+86R+VRHNj/SUMRN PKN4[2:0]=”110” KVN40 VDH- ƒ¢V*iVxRN0+87R+VRHNj/SUMRN PKN4[2:0]=”111” VINN5 KVN41 VDH- ƒ¢V*iVxRN0+87R+VRHN+VRLNj/SUMRN PKN4[2:0]=”000” KVN42 VDH- ƒ¢V*iVxRN0+91R+VRHN+VRLNj/SUMRN PKN5[2:0]=”001” KVN43 VDH- ƒ¢V*iVxRN0+95R+VRHN+VRLNj/SUMRN PKN5[2:0]=”010” KVN44 VDH- ƒ¢V*iVxRN0+99R+VRHN+VRLNj/SUMRN PKN5[2:0]=”011” KVN45 VDH- ƒ¢V*iVxRN0+103R+VRHN+VRLNj/SUMRN PKN5[2:0]=”100” KVN46 VDH- ƒ¢V*iVxRN0+107R+VRHN+VRLNj/SUMRN PKN5[2:0]=”101” KVN47 VDH- ƒ¢V*iVxRN0+111R+VRHN+VRLNj/SUMRN PKN5[2:0]=”110” KVN48 VDH- ƒ¢V*iVxRN0+115R+VRHN+VRLNj/SUMRN PKN5[2:0]=”111” VINN6 KVN49 VDH- ƒ¢V*iVxRN0+120R+VRHN+VRLNj/SUMRN | VINN7 Note 1) Sum of ladder resistors with positive polarities = 128R+VRHP+VRLP+VRP0+VRP1 Note 2) Sum of ladder resistors with negative polarities = 128R+VRHN+VRLN+VRN0+VRN1 Note 3) ∆V :Electric potential difference between VDH and VGS

Rev.0.5, July.31.2003, page 166 of 196 Formulas for calculating voltage (Negative polarity) (2) Grayscale voltage Formula Grayscale voltage Formula V0 VINN0 V32 V43+(V20-V43)*(11/23) V1 VINN1 V33 V43+(V20-V43)*(10/23) V8 VINN2 V40 V43+(V20-V43)*(3/23) V11 V20+(V8-V20)*(18/24) V43 VINN4 V20 VINN3 V52 V55+(V43-V55)*(6/24) V23 V43+(V20-V43)*(20/23) V55 VINN5 V30 V43+(V20-V43)*(13/23) V62 VINN6 V31 V43+(V20-V43)*(12/23) V63 VINN7 Note 1) Make sure DDVDH – V0 > 0.5V, DDVDH – V4 > 1.1V, V55-GND > 1.1V

Rev.0.5, July.31.2003, page 167 of 196 Relationship between RAM data and output level (REV =0) The relationship between the RAM data and the source output level is as follows. Negative polarity Positive polarity Output level V63 000000 111111 RAM data (Common characteristics to RGB) RAM data and the output voltage (REV = 0) Positive polarity Negative polarity Sn Vcom Source output and Vcom

Rev.0.5, July.31.2003, page 168 of 196 Relationship between RAM data and output level (REV =1) The relationship between the RAM data and the source output level is as follows. Negative polarity Positive polarity Output level V63 0000 111111 RAM data (Common characteristics to RGB) RAM data and the output voltage (REV = 1) Positive polarity Negative polarity Sn Vcom Source output and Vcom

Rev.0.5, July.31.2003, page 169 of 196 Low Power Consumption Display Mode Setting COL[1:0] to 2’h1 halts 32 amplifiers among V0 ~ V63 grayscale amplifiers to display with low power consumption. In combination with the FRC mode setting, it is possible to realize display with low power consumption in abundant colors. To make a setting for the low power consumption display, set in accordance to the following table according to the interface in use. The setting must be made in accordance to the setting sequence for low power consumption display mode. Using this mode with short screen refreshing cycle may affect the quality of display. Consider the trade-off between the display quality and power-saving effects before use. Table 71 Interface mode FRCON D16B Available colors 0 * 262,144 18 bit, 16 bit x2, 9 bit x2, 8 bit x3, RGB18bit, 6 bit x3 1 0 250,047 0 * 65,536 16bit x1, 8 bit x2, SPI 1 1 64,512 Note 1) When the FRC mode is on, do not switch the interface mode settings (M, TRI, D16B registers) Note 2) When the FRC mode is on, 18-bit format data and 16-bit format data are not displayed simultaneously. Table 72 Available colors for display COL[1:0] Amplifiers in operation FRCON = 0 FRCON = 1 2’h0 64 262,144 colors/65,536 colors - 2’h1 32 32,768 colors 250,047 colors/64,512 colors 2’h2 2 8 colors - 2’h3 Setting disabled Setting disabled Setting disabled Note 1) When COL[1:0] =2’h1 and FRCON = 0, do not write data that correspond to the grayscale levels for which the amplifiers are halted.

Rev.0.5, July.31.2003, page 170 of 196 Table 73 grayscale level amplifiers in operation COL[1:0] COL[1:0] amplifier 2’h0 2’h1 2’h2 GRAM data RGB amplifier 2’h0 2’h1 2’h2 GRAM data RGB V0 * * * 6’h00 6’h3F V32 * 6’h20 6’h1F V1 * 6’h01 6’h3E V33 * * 6’h21 6’h1E V2 * * 6’h02 6’h3D V34 * 6’h22 6’h1D V3 * 6’h03 6’h3C V35 * * 6’h23 6’h1C V4 * * 6’h04 6’h3B V36 * 6’h24 6’h1B V5 * 6’h05 6’h3A V37 * * 6’h25 6’h1A V6 * * 6’h06 6’h39 V38 * 6’h26 6’h19 V7 * 6’h07 6’h38 V39 * * 6’h27 6’h18 V8 * * 6’h08 6’h37 V40 * 6’h28 6’h17 V9 * 6’h09 6’h36 V41 * * 6’h29 6’h16 V10 * * 6’h0A 6’h35 V42 * 6’h2A 6’h15 V11 * 6’h0B 6’h34 V43 * * 6’h2B 6’h14 V12 * * 6’h0C 6’h33 V44 * 6’h2C 6’h13 V13 * 6’h0D 6’h32 V45 * * 6’h2D 6’h12 V14 * * 6’h0E 6’h31 V46 * 6’h2E 6’h11 V15 * 6’h0F 6’h30 V47 * * 6’h2F 6’h10 V16 * * 6’h10 6’h2F V48 * 6’h30 6’h0F V17 * 6’h11 6’h2E V49 * * 6’h31 6’h0E V18 * * 6’h12 6’h2D V50 * 6’h32 6’h0D V19 * 6’h13 6’h2C V51 * * 6’h33 6’h0C V20 * * 6’h14 6’h2B V52 * 6’h34 6’h0B V21 * 6’h15 6’h2A V53 * * 6’h35 6’h0A V22 * * 6’h16 6’h29 V54 * 6’h36 6’h09 V23 * 6’h17 6’h28 V55 * * 6’h37 6’h08 V24 * * 6’h18 6’h27 V56 * 6’h38 6’h07 V25 * 6’h19 6’h26 V57 * * 6’h39 6’h06 V26 * * 6’h1A 6’h25 V58 * 6’h3A 6’h05 V27 * 6’h1B 6’h24 V59 * * 6’h3B 6’h04 V28 * * 6’h1C 6’h23 V60 * 6’h3C 6’h03 V29 * 6’h1D 6’h22 V61 * * 6’h3D 6’h02 V30 * * 6’h1E 6’h21 V62 * 6’h3E 6’h01 V31 * 6’h1F 6’h20 V63 * * * 6’h3F 6’h00 *: amplifier in operation

Rev.0.5, July.31.2003, page 171 of 196 The following table shows the relationship between GRAM data and liquid crystal grayscale level. Table 74 GRAM data and LCD grayscale level (REV = 0) in FRC mode Selected grayscale level Selected grayscale level GRAM data RGB positive negative GRAM data RGB positive negative 6’h00 V0 V63 6’h20 (V30+V33)/2 (V30+V33)/2 6’h01 (V0+V2)/2 (V61+V63)/2 6’h21 V33 V30 6’h02 V2 V61 6’h22 (V33+V35)/2 (V28+V30)/2 6’h03 (V2+V4)/2 (V59+V61)/2 6’h23 V35 V28 6’h04 V4 V59 6’h24 (V35+V37)/2 (V26+V28)/2 6’h05 (V4+V6)/2 (V57+V59)/2 6’h25 V37 V26 6’h06 V6 V57 6’h26 (V37+V39)/2 (V24+V26)/2 6’h07 (V6+V8)/2 (V55+V57)/2 6’h27 V39 V24 6’h08 V8 V55 6’h28 (V39+V41)/2 (V22+V24)/2 6’h09 (V8+V10)/2 (V53+V55)/2 6’h29 V41 V22 6’h0A V10 V53 6’h2A (V41+V43)/2 (V20+V22)/2 6’h0B (V10+V12)/2 (V51+V53)/2 6’h2B V43 V20 6’h0C V12 V51 6’h2C (V43+V45)/2 (V18+V20)/2 6’h0D (V12+V14)/2 (V49+V51)/2 6’h2D V45 V18 6’h0E V14 V49 6’h2E (V45+V47)/2 (V16+V18)/2 6’h0F (V14+V16)/2 (V47+V49)/2 6’h2F V47 V16 6’h10 V16 V47 6’h30 (V47+V49)/2 (V14+V16)/2 6’h11 (V16+V18)/2 (V45+V47)/2 6’h31 V49 V14 6’h12 V18 V45 6’h32 (V49+V51)/2 (V12+V14)/2 6’h13 (V18+V20)/2 (V43+V45)/2 6’h33 V51 V12 6’h14 V20 V43 6’h34 (V51+V53)/2 (V10+V12)/2 6’h15 (V20+V22)/2 (V41+V43)/2 6’h35 V53 V10 6’h16 V22 V41 6’h36 (V53+V55)/2 (V8+V10)/2 6’h17 (V22+V24)/2 (V39+V41)/2 6’h37 V55 V8 6’h18 V24 V39 6’h38 (V55+V57)/2 (V6+V8)/2 6’h19 (V24+V26)/2 (V37+V39)/2 6’h39 V57 V6 6’h1A V26 V37 6’h3A (V57+V59)/2 (V4+V6)/2 6’h1B (V26+V28)/2 (V35+V37)/2 6’h3B V59 V4 6’h1C V28 V35 6’h3C (V59+V61)/2 (V2+V4)/2 6’h1D (V28+V30)/2 (V33+V35)/2 6’h3D V61 V2 6’h1E V30 V33 6’h3E (V61+V63)/2 (V0+V2)/2 6’h1F (V30+V33)/2 (V30+V33)/2 6’h3F V63 V0 Note 1) This table shows effective grayscale levels by FRC grayscale.

Rev.0.5, July.31.2003, page 172 of 196 8-color Display Mode The HD66781 incorporates an 8-color display mode. The available grayscale levels are V0 and V63, and the voltages for the other levels (V1-V62) are halted to reduce power consumption. The γ-fine-adjustment registers, PKP0-PKP5 and PKN0-PKN5 are not available in the 8-color display mode. Since the power supplies for the levels V1-V62 are halted in the 8-color mode, data are converted to automatically select V0/V63 levels: the MSB of each R, G, B, pixel of GRAM data is allocated to the lower 5 bits of R, G, B of display data. The HD 66781 enables to switch between 8-color and normal display modes without rewriting GRAM data only with the COL setting. LCD Gray-scale amp 2 gray- scale control <R> LCD driver R 2 gray- scale control <G> LCD driver G 2 gray- scale control <B> LCD driver B V63 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 666 Display data GRAM MSB L SB + polar register - polar register PKP0[2:0] PKN0[2:0] PKP1[2:0] PKN1[2:0] PKP2[2:0] PKN2[2:0] PKP3[2:0] PKN3[2:0] PKP4[2:0] PKN4[2:0] PKP5[2:0] PKN5[2:0] PRP0[2:0] PRN0[2:0] PRP1[2:0] PRN1[2:0] VRP0[3:0] VRN0[3:0] VRP1[4:0] VRN1[4:0] LCD G5R5 R5 R5 R5 R5 R5 G5 G5 G5 G5 G5 B 5 B 5 B 5 B 5 B 5 B5 COL[1:0]=h'2

Rev.0.5, July.31.2003, page 173 of 196 Oscillation Circuit The HD66781 generates oscillation by an internal R-C oscillator with an external oscillation resistor placed between the OSC1 and OSC2 pins. The oscillation frequency varies depending on the value of external resistor, the distance of wiring, and the operational power supply voltage. For example, the oscillation frequency becomes low when increasing the value of Rf resistor, or lowering the power supply voltage. See the “Notes to Electric Characteristics” section for the relationship between the Rf resistor value and the oscillation frequency. Rf OSC1 OSC2 HD66781 External Resistor Oscillation Mode Note 1) Place the Rf resistor as close to the OSC1, OSC2 pins as possible. Note 2) Make sure not to arrange other wiring close to or beneath OSC1-OSC2 wiring to avoid effects from coupling

Rev.0.5, July.31.2003, page 174 of 196 n-raster-row Inversion alternating Drive The HD66781, in addition to LCD inversion alternating drive by frame, supports n-raster-row inversion alternating drive where alternation occurs by n raster-rows, where n takes a number from 1 to 64. The n- raster-row inversion alternating drive enables to overcome the problems related to display quality. In determining n (the value set by the NW bit +1), the number of raster-rows by which alternation occurs, check the display quality on the actual liquid crystal panel. Setting a small number of raster-rows will raise the alternating frequency of the liquid crystal and increase the charge/discharge current on the liquid crystal cells. 1 frame1 f r a m e Back porch Front porch Front porchBack porch 1234 3 2 1 3 2 2 336 1 2 3 4 321 Frame alternating drive -320 raster-rows N-raster-row alternating drive -320 raster-row drive -3 raster-row inversion -EOR = 1 336322 n-raster-row alternating drive Note 1) Make sure to set EOR = 1 to avoid direct bias on liquid crystal during n-raster-row alternating drive.

Rev.0.5, July.31.2003, page 175 of 196 Interlaced Drive The HD66781 supports interlaced drive, which divides one frame into n fields and then drives to prevent flickers. To determine the number of fields (n: value set by the FLD bits), check the display quality on the actual liquid crystal panel. The following table shows the gate selection for each number of fields, 1 to 3. The figure illustrates the output waveforms of the 3-field interlaced drive. Table 75 GA=0, SM=0, GS0=0, GS1=0 GA=1, SM=0, GS0=0, GS1=1 FLD1-0 2’h1 2’h3 FLD1-0 2’h1 2’h3 Field Gate - 1 2 3 Field Gate - 1 2 3 G1 O O G328 O O G2 O O G327 O O G3 O O G326 O O G4 O O G325 O O G5 O O G324 O O G6 O O G323 O O G7 O O G322 O O G8 O O G321 O O G9 O O G320 O O G317 O O G12 O O G318 O O G11 O O G319 O O G10 O O G320 O O G9 O O Note 1) Interlaced drive is not available in RGB interface mode. Note 2) Middle porch must be set to BP = 3 (3 lines) for interlaced drive. Note 3) OSD (α blending), scrolling, and resizing functions are not available with interlaced drive.

Rev.0.5, July.31.2003, page 176 of 196 G3n+1 G3n+2 G3n+3 Polarity Field 1 Fiel d 2 Fiel d 3 Fiel d 1 Blank period 1 frame Alternation 3-field interlaced drive: gate output timing

Rev.0.5, July.31.2003, page 177 of 196 Alternating Timing The following figure illustrates the alternating timing of each alternating drive formula. In case of frame inversion alternating drive, alternation occurs at the completion of one frame, followed by a blank that lasts for 16H periods. In case of interlaced drive, alternation occurs at the completion of one field, followed by a blank. The total period of the blanks in one frame adds up to 16H period. In case of n-raster-row, a blank lasting 16H period is inserted after all screens are drawn. During interlaced drive, make the numbers of back, front porches more than the numbers of fields. Frame 1 Back porch Front porch Field 1 Field 2 Field 3 Blank period 1 period 2 Front porch Back porch n-raster-rows One frame period Frame inversion Alternating drive 3-field interlaced drive n-raster-row inversion Alternating drive Alternating timing Blank period = front porch + back porch One frame period One frame period Blank Blank period 3 Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows Blank period = front porch + back porch Alternating timing

Rev.0.5, July.31.2003, page 178 of 196 Frame-Frequency Adjustment Function The HD66781 incorporates frame frequency adjustment function. The frame frequency during the liquid crystal drive is adjusted by the instruction setting (DIVI, RTNI) while keeping the oscillation frequency fixed. By setting the oscillation frequency high in advance, it becomes possible to switch the frame frequency in accordance to the kind of displayed picture (i.e. moving/still picture). When displaying a still picture, set the frame frequency low to save power consumption, while setting the frame frequency high when displaying a moving picture which requires high-speed screen switching. Relationship between Liquid Crystal Drive Duty and Frame Frequency The relationship between the liquid crystal drive duty and the frame frequency is calculated by the following formula. The frame frequency is adjusted by the instruction setting with the 1-H period adjustment bit (RTNI bit) and the operation clock division bit (DIVI bit). (Formula for the frame frequency) fosc Frame frequency = [Hz] Clock cycles per raster-row × division ratio × (Line+BP+ FP) fosc : R-C oscillation frequency Clock cycles per raster-row : RTNI bits Division ratio : DIVI bit Line : number of drive raster-rows (NL) Front Porch : FP bits Back Porch : BP bits Calculation Example The maximum frame frequency = 60 Hz Number of drive raster-row : 320 1-H period : 16 clock cycles (RTNI[4:0] = 2’h10) Operation clock division ratio : 1 division fosc = 60 Hz × 16 clocks × 1 division × (320+2+14) lines = 323 (kHz) In this case, the R-C oscillation frequency becomes 323 kHz. Adjust the value of external resistor for R-C oscillator to set the frequency 323kHz.

Rev.0.5, July.31.2003, page 179 of 196 Partial Display Function The HD66781 enables arbitrary settings for on-display picture RAM area and the display position on the screen with the use of OSD. When the display of base image is turned off (BASEE=0), OSD is displayed 100%. By making settings for OSD RAM area (OSA, OEA) and OSD position (ODP), the HD66781 allows displaying an arbitrary set of data. Other than OSD area becomes no-display area to reduce power consumption. The partial display area using OSD can be made up to 3 areas. In combination with 8-color mode and off-scan settings (PTS, PTG, ISC), more power-saving display will be obtained. Make an appropriate setting taking power-saving effect and display quality into consideration. G41 G59 Non-display area Number of driving raster-row : NL0 =6’h07 (64 raster-rows) Base picture display ENABLE : BASEE = 0 First OSD picture display RAM area : (OSA0, OEA0) = (8’h000, 8’h013) First OSD picture display position : ODP0=8’h028 First OSD picture display ENABLE : OSDE=1 Non-display area First OSD image : 19 raster-rows Partial Display Note 1) See the “RAM Address and Display Position on the Panel” for more details on the relationship between the display area and the setting of RAM area.

Rev.0.5, July.31.2003, page 180 of 196 Power-saving drive settings The HD66781 incorporates various settings for lower power consumption display. The low power consumption and the quality of display are in trade-off, and the power-saving effect may vary depending on the characteristics of a panel. Make an appropriate setting among the settings listed below taking the trade- off into consideration. 1. 8-color display mode (COL) When this mode is selected (COL [1:0] = 2’h2), voltage generation for grayscale levels other than V0 and V63 levels is halted. In this mode, only 8 colors are available for display for saving power. 2. Low power consumption display mode (COL, FRC) Setting COL[1:0] to 2’h1 halts 32 amplifiers among V0 ~ V63 grayscale amplifiers to display with low power consumption. In combination with the FRC mode setting, it is possible to realize display with low power consumption in abundant colors. In this mode, 250,047 colors are available with 18-bit, 16-bit x2, 9-bit x2, 8-bit x3 (RGB 6 bits each) interfaces and 64,512 colors are available with 16-bit x1, 8-bit x2 interfaces and SPI (R, B: 5 bits, G: 6 bits). Using this mode with short screen refreshing cycle may affect the quality of display. Consider the trade-off between the display quality and power-saving effects before use. See the “Low power consumption display mode” (p.169) for details. 3. Partial display (OSD) The partial display is made with OSD and base image display off setting (BASEE = 0). Display operation is limited to the partial display area to save power. Power saving effects will increase as the number of partial display lines decreases. Also, see “Partial Display Function”(p.139) for details. 4. Non-lit drive setting The non-lit drive setting is available for partial display and allows specifying the kind of source outputs in the non-lit drive area with PTS bits. Also, in the non-lit drive area, grayscale generation amplifier is halted and step-up clock cycle is slowed down to half. PTG bits can specify the scan mode of gate bus lines in the non-lit drive area. In the interval gate scan mode, gate bus lines are scanned by the frame cycle specified by ISC bits to hold power consumption required for scanning gate bus lines to minimum. The longer scan cycle may affect the quality of display. Make an appropriate setting by taking trade-off between power-saving effects and display quality.

Rev.0.5, July.31.2003, page 181 of 196 Table 76 Source outputs in non-display area Source output in non-display area PTS[2:0] Positive polarity Negative polarity Non-display area Grayscale amp operation Non-display area Step-up clock frequency 3’h0 V63 V0 V0 to V63 DC0,DC1Setting 3’h1 Setting disabled Setting disabled - - 3’h2 GND GND V0 to V63 DC0,DC1Setting 3’h3 Hi-Z Hi-Z V0 to V63 DC0,DC1Setting 3’h4 V63 V0 V0,V63 DC0,DC1Setting x1/2 3’h5 Setting disabled Setting disabled - - 3’h6 GND GND V0,V63 DC0,DC1Setting x1/2 3’h7 Hi-Z Hi-Z V0,V63 DC0,DC1Setting x1/2 Note 1) Gate outputs in non-lit drive area can be controlled by off-scan mode (with PTG bits). Note 2) The operation halt of grayscale amplifier and the slowdown of step-up clock frequency are valid only to the non-display area. Note 3) When DC[4:3]=2’h3, the frequency of step-up clocks in the non-display area are not slowed down half even if PTS[2:0] is set to 4, 6 or 7. Table 77 Gate outputs in non-display area PTG[1:0] DISPTMG output Gate output in non- display area Source output in non- display area 2’h0 Normal drive Normal scan PTS setting 2’h1 GND DISPTMG (Fixed) PTS setting 2’h2 Internal drive Interval scan PTS setting 2’h3 Setting disabled - - Note 1) When the interval scan is executed, make setting for the frame alternating drive. Table 78 Interval gate scan frequency ISC[3:0] Scan frequency When (fFLM) = 60Hz 4’h0 Setting disabled – 4’h1 3 frames 50ms 4’h2 5 frames 84ms 4’h3 7 frames 117ms 4’h4 9 frames 150ms 4’h5 11 frames 184ms 4’h6 13 frames 217ms 4’h7 15 frames 251ms 4’h8 17 frames 284ms 4’h9 19 frames 317ms 4’hA 21 frames 351ms 4’hB 23 frames 384ms 4’hC 25 frames 418ms 4’hD 27 frames 451ms 4’hE 29 frames 484ms 4’hF 31 frames 518ms

Rev.0.5, July.31.2003, page 182 of 196 5. Frame frequency setting Frame frequency adjusting functions (with DIVI, RTNI bits) allows changing liquid crystal alternating frequency through instructions. Frame frequency can be reduced to achieve low power consumption while display method with low power consumption such as partial display mode is employed. See “Frame Frequency Adjustment Function”(p.178) section for details. Generally, the lower frame frequency and the quality of display are in trade-off. The power-saving effects and the quality of display also vary depending on the characteristics of a panel. Check the quality of display on the panel before use. 6. Liquid crystal alternating drive The HD66781 allows selecting among frame alternating drive, 3-field interlace drive, and line inversion alternating drive through instructions (B/C, EOR, NW, and FLD). Select an appropriate alternating drive method for the kind of display. See the “Alternating Timing”(p.177) section for details. Generally, the lower frame frequency and the quality of display are in trade-off. The power-saving effects and the quality of display also vary depending on the characteristics of a panel. Check the quality of display on the panel before use.

Rev.0.5, July.31.2003, page 183 of 196 Equalization function The HD66781 incorporates source-Vcom equalization function, which short-circuits source outputs S1- S720 and Vcom at alternating points to equalize the electric potential of source capacities and Vcom capacities during “High” period of EQ signal. By driving source and Vcom from the equalized electric potential, the electric charges accumulated in the source and Vcom capacities are reallocated, and power consumption is reduced. EQ EQ EQ EQ EQ S1 S720 VCOM + + S1 S720 + + EQ EQ EQ EQ VCOM EQ HD66781 HD66781 HD66783/HD667P21 HD66781/HD667P21 VCOM VCOM Normal Display Equalization Note 1) Equalization function is only available when Vcom Low level ≥ 0V Note 2) Power-saving effects depend on display data.

Rev.0.5, July.31.2003, page 184 of 196 Specifications of external element of HD66781 The specifications of external element connected to power supply circuit of HD66781 are as follows. Table 79 Capacitor Capacitor capacitance Recommended capacitor voltage Connection pin 1µF Characteristics B 3V VDD

Rev.0.5, July.31.2003, page 185 of 196 Instruction Setting The following flowcharts show the sequences with respect to power on/off of the combined use of HD66781 and HD66783 or HD667P21, display on/off, standby set/release, and sleep set/release. Whenever turning on or off the power supply and so on, it must be done in accordance to the following procedures. A serial interface is used to make instruction settings to the HD66783 and HD667P21, where a serial transfer is always required. The serial transfer must be made in accordance to the serial transfer sequence and right after the instructions are set. Timing of the instruction setting is necessary to take into consideration the delay of 16-cycle internal clocks (OSC) from the start of serial transfer from the HD66781 through TE and IDX2-0 before each of the following mode settings becomes effective on the HD66783 and HD667P21.

Rev.0.5, July.31.2003, page 186 of 196 Power-supply/display ON (LPTS = 0: a-Si TFT panel, with HD66783) Power supply ON (Vcc, IOVcc, Vcc1, Vci) Power ON reset Display ON flow 1ms or more Display control register settings NL, GS, SCN settings serial transfer other settings Power supply ON Sequence Instructions before power supply startup The power-suppy must be turned on in the order of IOVcc, Vcc1(781), Vcc(783), Vcc(781), Vci or all power-supplies must be turned on simultaneously. Instructions for starting up power supply(1) Instructions for starting Power supply(2) Instructions for other mode settings Display ON D1-0 = 2'h1 Display ON (1) GON="1" serial transfer Display ON (2) D1-0 = 2'h3 Display ON (3) DTE ="1" Display ON (4) Display ON VDD startup oscillation start Power-supply control register setting (HD66783) VC, VRH, (PON = 0) settings serial transfer VCM, VDV, DC1=3'h0 settings serial transfer DK = 1 setting serial transfer sPower-supply operation start settings (HD66781) AP setting (HD66783) AP, DC0, BT (VCOMG = 0, GON = 0) settings serial transfer DC1 settings serial transfer PON = 1 setting see Note 2) serial transfer Power-supply operation start setting VCOMG = 1 serial transfer DK = 0 setting serial transfer Serial transfer GRAM write 100ms or more 70ms or more 30ms or more VGH, VGL start up DDVDH, VCL start up Instructions before power supply startup SAP setting (HD6678) 2 frames or more 2 frames or more Display each image by setting BASEE and OSDE to 1 (Display ENABLE). Note 1) Do not set GON = 1 while D - 2'h0. Note 2) AP[2:0] setting must be compleged before or simultaneously with setting PON = 1. While PON = 1, no change to the AP[2:0] setting will be accepted except AP[2:0] = 3'h0 while the power supply is turned off.

Rev.0.5, July.31.2003, page 187 of 196 Power-supply/display OFF (LPTS = 0: a-Si TFT panel, with HD66783) EQW =0 D1-0 = "2'h2" Display OFF (1) Power supply OFF SequenceDisplay OFF DTE = 0 Display OFF (2) GON = 0 Serial transfer Display OFF (3) D1-0="2'h0" Display OFF (4) Note 1) Do not set GON = 1 when D=2'h0 Note 2) Set PON = 0 after transferring the AP[2:0] = 3'h0 setting to HD66783 when the power-supply is turned off. Power supply OFF (Vcc, Vci, IOVcc,Vcc1) Instructions for setting power supply OFF Power-supply off setting bits (HD66781) SAP = 3'h0, AP = 3'h0 (HD66783) VCOMG =0, AP = 3'h0 serial transfer PON =0 see Note 2) serial transfer The power-suppy must be turned on in the order of Vcc(781), Vci, IOVcc, Vcc1, Vcc(783) or all power-supplies must be turned on simultaneously. 2 frames or more required only when equalization function is in use.

Rev.0.5, July.31.2003, page 188 of 196 Power-supply/display ON (LPTS = 1: LTPS TFT panel, with HD667P21) Power supply ON (Vcc, IOVcc, Vcc1, Vci) Power ON reset Display ON flow 1ms or more Power supply ON Sequence Instructions before power supply startup The power-suppy must be turned on in the order of IOVcc, Vcc1(781), Vcc(7P21), Vcc(781), Vci or all power-supplies must be turned on simultaneously. Instructions for starting up power supply(1) Instructions for starting Power supply(2) Display ON D1-0 = 2'h1 Display ON (1) GON="1" serial transfer Display ON (2) D1-0 = 2'h3 Display ON (3) DTE ="1" Display ON (4) Display ON VDD startup oscillation start Power-supply control register settings (HD667P21) VC, VRH, (PON = 0) settings serial transfer VCM, VDVsettings serial transfer VGH, VGL settings serial transfer DK[1:0] = 2'h1 setting serial transfer Power-supply operation start setting (HD66781) AP setting (HD667P21) AP, DC, BT settings (VCOMG = 0, GON = 0) setting serial transfer PON = 1 setting serial transfer Power-supply operation start setting (HD667P21) DK = 2'h0 setting see Note 2) serial transfer Serial transfer GRAM write 20ms or more 30ms or more VLOUT2, VLOUT3 start up VLOUT1 start up Instructions before power supply startup SAP setting (HD6678) 2 frames or more 2 frames or more Display each image by setting BASEE and OSDE to 1 (Display ENABLE). Note 1) Do not set GON = 1 while D - 2'h0. Note 2) Start up VLOUT1 after waiting VLOUT2 to start up completely so that it is always VLOUT 2>VLOUT1. When using 4-time stepped-up VLOUT2, first start up VLOUT2 to step up 5 times, and then resetting VLOUT2 to step up 4 times after starting up VLOUT1. Instructions for starting Power supply(3) Power-supply operation start setting VCOMG = 1 serial transfer Instructions for other mode settings 60ms or more VLOUT4 start up step-up circuits stabilizing time Gate driver/LTPS LCD panel control signal register settings LPTS = 1 FW, FT settings SW, ST settings DPW, DPT settings SDT setting

Rev.0.5, July.31.2003, page 189 of 196 Power-supply/display OFF (LPTS = 1: LPTS TFT panel, with HD667P21) EQW =0 D1-0 = "2'h2" Display OFF (1) Power supply OFF SequenceDisplay OFF DTE = 0 Display OFF (2) GON = 0 Serial transfer Display OFF (3) D1-0="2'h0" Display OFF (4) Note: Do not set GON = 1 whenever D=2'h0 Power supply OFF (Vcc, Vci, IOVcc,Vcc1) Instructions for setting power supply OFF Power-supply off setting bits (HD66781) SAP = 3'h0, AP = 3'h0 (HD667P21) VCOMG =0, AP = 3'h0 serial transfer PON =0 serial transfer The power-suppy must be turned on in the order of Vcc(781), Vci, IOVcc, Vcc1, Vcc(7P21) or all power-supplies must be turned on simultaneously. 2 frames or more required only when equalization function is in use. 2 frames or more

Rev.0.5, July.31.2003, page 190 of 196 Standby/Sleep mode Standby Set Sleep release Oscillation start Standby release (STB="0") Power supply ON sequence Display ON sequence Sleep release (SLP="0") Display ON sequence Sleep set (SLP="1") Display OFF sequence Sleep set Display OFF sequence SleepStandby Standby release Standby set (STB="1") Power-supply OFF sequence 1ms or more Power-supply OFF sequence wait 1 clock see Note Note: The clock refers to internal clock OSC1. Power supply ON sequence

Rev.0.5, July.31.2003, page 191 of 196 Deep standby mode 䋨DSTB=”1”䋩 CS=”Low” (1) CS=”Low " x 6 CS=”Low” (2) CS=”Low” (3) CS=”Low” (4) CS=”Low” (5) CS=”Low” (6) VDD startup oscillation stabilization period Display OFF flow Set Deep standbyPower-supply OFF flow Set Deep standby Deep standby mode 1ms or more internal initialization Power-supply setting Display ON flow Release Deep standby input Note 1) See AC characteristics of each interface mode in "Electrical Characteristics" with regard to Low width (PWLW), High width (PWHW) and cycle (tCYCW) periods. Note 2) Leave at least 1ms between 2nd and 3rd inputs of CS="Low". Deep standby mode

Rev.0.5, July.31.2003, page 192 of 196 Low power consumption display mode COL=2'h1 262,144-color mode display 1frame at max. Low power consumption display mode 262,144 color mode to Low power consumption display mode FRCON=1 (D16B = 1) COL=2'h0 262,144-color mode display 1frame at max. Low power consumption display mode FRCON=0 Low power consumption display mode to 262,144 color mode 8-color mode CL=2'h2 262,144-color mode display 1frame at max. 8-color mode display 262,144 color mode to 8-color mode CL=2'h0 262,144-color mode display 8-color mode display 1frame at max. 8-color mode to 262,144 color mode

Rev.0.5, July.31.2003, page 193 of 196 Partial display mode Full-screen display OSD display setting OSA,OEA,ODP Base image display OFF BASEE=0 OSD display ON OSDE=1 Non-display area drive settings: PTS, PTG, ISC 8-color mode setting: Partial display ON Base image display ON BASEE=1 OSD display OFF OSDE=0 Full-screen display As required COL = 2'h2

Rev.0.5, July.31.2003, page 194 of 196 Absolute Maximum Values Item Symbol Unit Value Notes Power supply voltage (1) IOVcc, Vcc1 V -0.3 ~ + 4.6 1, 2, 5 Power supply voltage (2) Vcc - GND V -0.3 ~ + 4.6 1, 3, 5 Power supply voltage (3) DDVDH - GND V -0.3 ~ + 6.5 1, 4 Input voltage Vt V -0.3 ~ Vcc + 0.3 1 Operating temperature Topr °C -40 ~ + 85 1, 6 Note 1) The LSI may be permanently damaged if it is used under the condition exceeding the above absolute maximum values. It is also recommended to use the LSI within the limit of its electric characteristics during normal operation. Exceeding the conditions may lead to malfunction of LSI and affect its credibility. Note 2) IOVcc(High) ≥ GND(Low), Vcc1(High) ≥ GND(Low) must be observed. Note 3) Vcc(High) ≥ GND(Low) must be observed. Note 4) DDVDH(High) ≥ GND(Low) must be observed. Note 5) Vcc(High) ≥ IOVcc(Low), Vcc(High) ≥ Vcc1(Low) must be observed. Note 6) The DC and AC characteristics of chip and wafer products are guaranteed at 85 °C. Note 7) The electric potential of this LSI’s substrate is GND. The electrical connection of the other side of the chip must be at the electric potential of an insulated state or GND. The electrical and operational characteristics of the LSI will not be guaranteed otherwise.

Rev.0.5, July.31.2003, page 195 of 196 Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0

Rev.0.5, July.31.2003, page 196 of 196 Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.5 2003, July 31 First issue