Microcontroller

HD65901

Hitachi Semiconductor

MCU(MICROCOMPUTER UNIT)

Manufacturer: Hitachi Semiconductor

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Technical content

MCU (Microcomputer Unit) HDD65901 is a CMOS 8-bit microcomputer, with integrated CPU, BLOCK DIAGRAM 2k-bytes of EEPROM, 3k-bytes of ROM, 128 bytes of RAM, and one Input/Output line on a single chip. Vs —— RES FEATURES | ‘@ CMOS EEPROM Process | f © &-bit CPU —, —27 Instructions R= CI =o v0 —Five Addressing Modes: ee ae Immediate, Register Direct, Register Indirect, Relative, Implied Register —Internal Registers: by Program Counter (PC), General Purpose Register (Ro-Ris) = [| (-FerRon Condition Code Register (CCR: N, Z, and C flags) KK ‘@ Memory ] —3k-byte ROM —128 byte RAM —2k-byte EEPROM —EEPROM is located in internal memory address space —Byte write/erase —Page write/erase —Single 5V Power Supply © General Purpose /0 One W/O Line © Data Security —ROM Data Security —EEPROM Data Security ‘© Operating Range f = 3to 10 MHz (Voc = 5V + 10%) © Available in die form for smart card applications. | PROGRAM DEVELOPOMENT SUPPORT TOOLS @ Cross assembler and simulator software for use with IBM PC or compatibles © Hardware evaluation board @HITACHI Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 (415) 589-8300 1181

Section 1. Overview This MCU is a CMOS 8-bit microcomputer, integrating a CPU, 2k bytes of EEPROM, 3k bytes of ROM, 128 bytes of RAM, and one 1/0 line on a single chip.

1.1 Features

.» CMOS EEPROM Process . EEPROM 2k-byte EEPROM + Sit CPU EEPROM is located in internal 27 instructions memory address space Five addressing modes; Byte erase/write Immediate, Register direct, Fage erase/write Register indirect, Relative, Single 5V power supply Implied register Internal Re te : hihi . General purpose I/O Program Counter (PC), . Ol General Purpose Register (RO-R15) ne 1/0 line Condition Code Register . (CCR: N, 2, and C flags) + Data Security | Memory ROM data security 3k-byte ROM EEPROM data security 128-byte RAM . Operating range £ = 3 to 5 MHz (Vcc = SV + 10%) 1.2. Block Diagram Voc ——- cre -——- cLK vss —= -— ms RAM, —_ CK i ; ; 3 3 rom 2 3(— >) eeprom Ty Kk : Figure 1-1 Block Diagram | @ HITACHI | 1182 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 i I

1.3 Pad Arrangement

1/o2|0 | cLK2 a a . a . s s e . a a QO} RES a a s s a a a a . a Vss2|qa O}vec2 T/oljo OJcLkl . s s a (Top view) Note: (1) For each VCC, VSS and CLK, one of the pins or each should be connected. For I/O, one of the pins but not the both should be connected. (2) Pins other than the ones specified above should be open. (3) The substrate of each die should be connected to Vcc or floated. Figure 1-2 Pad Arrangement

1.4 Pin Description

Pin symbol Input/Output Pin Name and Function a Power Vee Power supply: Connected to Power. Supply (SV£10%) —Supphy OE GND Vss Ground: Tied to ground. (0V) a Clock CLK Input Clock: External clock is input. a _ Reset. RES Input Reset: When asserted LOW, initializes the MCU*. a Port 1/o Input/Output I/O port: l-bit I/O line. Can be softwarely programmed as input or output. a * MCU: Microcomputer Unit | @ HITACHI Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 * (415) 589-8300 1183

Section 2. CPU Architecture

2.1 CPU Architecture

This section explains the CPU architecture.

2.1.1 CPU registers

The CPU contains sixteen 8-bit General Purpose Registers (RO-R15), a 3-bit Condition Code Register (CCR) and a 16-bit Program Counter (PC). The CPU register configuration is shown in Figure 2-1. bit 15 oO Program Counter 7 07 oO aS <5 a General Purpose po Rk? Register a <C <n R14 (SP) Condition Code Register (CCR) 210 {wl zTc] Figure 2-1 CPU Registers

2.1.2 Addressing mode

The CPU has five addressing modes as follows. Register direct: The operand is located in one of the 8-bit or 16-bit General Purpose Registers specified by the register field in the op-code. 8-bit register : RO - R15 16-bit register pair: R1RO - RI5R14 When selecting a 16-bit register pair in ADDD and SUBD, the odd-numbered register should be selected by the register field. For example, when selecting R1RO, Rl should be selected by the register field. Register indirect: The effective address is located in one of the 8-bit or | 16-bit General Purpose Register. @ HITACHI 1184 Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

When selecting an odd-numbered register Ri (i=l, 3, -----, 15), an effective address is contained in the 16-bit register pair RiRi-1. byte of the effective address is contained in the 8-bit register Ri and the upper byte of that becomes 0. Therefore, the effective address ranges from $0000 to SOOFF. In this case, register Ri+l can be used as a data register. Memory upper lower When selecting an odd- [ei [Ro | R: Ri-1} R: SEE numbered register Ri > Operand Immediate: An 8-bit operand is included in the 2nd byte of the instruction. 1st byte 2nd byte Relative: The relative addressing mode is used by jump and call instructions. An effective address is calculated by summing the PC and a 8-bit signed displacement in the 2nd byte of the instruction. The relative addressing span is from -126 to +129 from the op-code address. DISP SS implied Register: Certain op-codes automatically imply register usage, such as CTR which inherently reference the CPU register. | @HITACHI Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 1185

GPUARCHITECTURE. The CPU register functions are summarized in Table 2-1. Table 2-1 CPU Register Function Register Symbol Function Program Counter = PC 16 bit PC contains the address of instruction to be executed. Lower 14 bits of the PC effectively support 16k-byte address space, while upper 2 bits are ignored. PC is initialized to $3400 during Reset. General Purpose RO-R15 General Purpose Registers can be used as both Register address and data registers. Depending on the instruction, these registers can be used as individual 8-bit registers (RO, Rl, ----, R15) or 16-bit register pairs (RIRO, R3R2, ----, R15R14). R14 also functions as Stack Pointer (SP) during subroutine calls. Registers are not initialized by reset. Condition ccR CCR consists of Carry (C), Zero (Z), and Code Register Negative (N), and reflects the result of logical and arithmetic instructions. Each function is described in Table 2-2. They are not initialized by reset. Table 2-2 Condition Code Register Description Condition Code Symbol Function Negative N Bit 2. Set if the result is negative (MSB=1); reset otherwise. a Zero Zz Bit 1. Set if the result is zero; reset otherwise. a carry c Bit 0, Set if a "carry" or “borrow" occurs from the MSB of the result; reset otherwise. A "carry" or "borrow" occurs after the following instruction executions. (a) Addition (b) Subtraction (c) Shift and Rotation @ HITACHI | 1186 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. @ Brisbane, CA 94005-1819 (415) 589-8300

2.1.3 Subroutine calls

CALL: CALL pushes the PC onto the stack and then the CPU begins the sub- routine. Then R14 functions as Stack Pointer for stacking. SP. oT (ria) sp—of (R14) RAM RAM Before CALL execution After CALL execution (After RET execution) (Before RET execution) Because the SP (R14) is an 8-bit register, the stack area ranges from $00 to SFF in the memory address space. The SP pointing to the next available address of the stack is decremented by two after CALL execution. RET: RET pops the PC from the stack. Then, the SP is incremented by two.

2.1.4 Instruction format

Peat | Nenory Register f[eafea ras oF (store (fsa oo] eam Song (erative [ops ofa of com] [® [o 0 0 0} sum tnaizect) fla fe ifs 1 9] bse cnLL (Relative) els ofa afar) (2 tt 0] cn Cantirece) [ofa ifa a 110 0 0 0 0 111 Of RET Note: FN : Function field IMM : Immediate data COND: Jump condition DISP: Displacement S : Source register field D =: Destination register field R : Register field @ HITACHI | Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 » (415) 589-8300 1187 i

2.2 CPU Basic Timing

2.2.2 Machine cycle

The external clock (CLK) is divided by four to generate an S clock. One cycle of S clock makes up one machine cycle (one memory cycle). The machine cycle is shown in Figure 2-2. CLK LALLY LLL LLL s_I Uw sl Ls LL _S Address TX X TT >*X pata <)> {>

1 Machine Cycle’

1 Memory Cycle

2.2.2 Instruction execution timing

All instructions are executed in four machine cycles except CALL and RET instructions which require five machine cycles for execution. Figures 2-3 2-11 illustrate basic instruction execution timings. so sl s2 s3 so s_I LF US tt tl Li Address (TRC YF FC) op-1 op-2 NEXT_OP a *Wigh" WRITE LD Rl, $10 Next Inst. Figure 2-3 LD R1, $10 Execution Timing (Immediate) @HITACHI 1188 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 « (415) 589-8300

2.2.3 Reset and restart timing

When RES is asserted LOW, the MCU enters the reset mode. To complete reset, RES must be asserted LOW for at least 5 machine cycles (20 external clock cycles). When RES is brought HIGH again, the CPU restarts operations from $3400 (Starting address of ROM). RES must also be brought LOW to facilitate power-on reset. Reset and restart timing is shown in Figure 2-12. ax TI, $k s ALLS RES Address $3400 READ $ \\ [ Data Figure 2-12 Reset Timing | @HITACHI i . \\ Hitachi America, Ltd. * Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 1193

2.3 Memory Map

Figure 2-13 shows the memory configuration. $0000 $0001 $0002 Vl Li) $0080 RAM 128 bytes SOOFF $1800 EEPROM 2k bytes Y S1FFF TEST ROM * 1k bytes $33FF $3400 ROM 3k bytes S3FFF NOTE: * TEST ROM is used only for testing and users cannot access the TEST ROM. DR (Data Register) DDR (Data Direction Register) ECR (EEPROM Control Resister) Figure 2-13 Memory Map @ HITACHI 1194 Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

Section 3. On-Chip Peripherals

3.1 EEPROM

3.1.1 On-chip EEPROM overview

The MCU incorporates EEPROM; electrically erasable and programmable ROM. The on-chip EEPROM features are as follows. . 2k bytes . Located in memory address space . Byte erase/write . Page erase/write . Address, data, and control latches for erase/write . On-chip high voltage generation circuit . On-chip clock generator and timer . Maximum 104 erase/write times . 10 year data retention

3.1.2 EEPROM block diagram

ew TP, Latch Latch Latch EEPROM Page Data Latch (32-byte) High Voltage Generation Timer Oscillator Circuit Figure 3-1 EEPROM Block Diagram @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 1195

Table 3-1 summarizes the ECR functions. Table 3-1 ECR Function 4 4 ; . Initial Bit Bit Name Symbol Function Read/Write Value 7 READY/BUSY BSY Reflects the condition of EEPROM. Read If BSY=0, EEPROM is in the erase/ * write cycle. a, "1 If BSY=1, EEPROM erase/write cycle is completed. Note that EEPROM can be accessed only when BSY=1. Oe 1 Write Wr Inhibits the EEPROM writing. *2 o *1 Inhibit If WI=0, EEPROM writing is Read/Write enabled. If WI=1, EEPROM writing is prevented. WI is utilized for page erasure. a 0 Erase EL Inhibits the EEPROM erasure. *2 o *1 Inhibit If EI=0, EEPROM erasure is Read/Write enabled. If EI=1, EEPROM erasure 1S inhibited. The EEPROM data can be programmed from 1 to 0, but it cannot be reprogrammed from 0 to 1 (equivalent to PROM). EET Notes: *1. I£ the RES pin is asserted LOW during the erase-write cycle, EEPROM stops the erase-write operation. And then the BSY, wi and EI bits are initialized by reset. It may cause a wrong erase or a wrong write. So it should not be reset during the erase/write operation. *2, WI and EI are programmable only when BSY=1. *3. Unused bits of the ECR (bit 2-6) are always "1".

3.1.3 EEPROM read operation

The EEPROM can be directly read by the CPU in the same way as ROM and RAM only when BSY in the ECR is set to 1. If the EEPROM is read when BSY=0, the MCU performs data polling to check whether the erase/write operation is completed or not. Refer to 3.1.4 (7) Data polling for further details. Figure 3-4 shows the EEPROM read timing. @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. ® Brisbane, GA 94005-1819 « (415) 589-8300 1197

address TX F=X READ \\ / Data — > Figure 3-4 EEPROM Read Timing

3.1.4 EEPROM erase/write

(1) EEPROM erase/write sequence: EEPROM erase/write is done by the ST instruction like RAM. Once the ST instruction is executed, EEPROM begins the erase and write operation. First, EEPROM latches the address and data, second, it erases the old data and finally it writes the new data which is latched in the first. These sequence is controlled and done automatically by the internal control circuit. Figure 3-5 summarizes EEPROM erase/write sequence. (2) Byte erase/write (EI=0): The EEPROM can be programmed on a byte basis with ST instruction. The EEPROM erase/write time specification is 15ms (max.). BSY in the ECR can be used to check whether the erase/write cycle has been completed or not. Figure 3-6 shows byte erase/write timing. (3) Byte write (EI=1): If EI=l, the EEPROM can be written on a byte basis but it can not be erased. Because byte locations are not erased prior to a new data write, the existing data and new data are logically ANDed to obtain new programmed data. Ex. existing data 10010110 new data 10001111 new programmed data 10000110 | @ HITACHI | 1198 Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300

“~<e> Yes Latch data and address, BSY + 0 Save the selected page data (32-byte) on the page data latch Data latch Rewrite the selected byte in the page data latch <> EEPROM erasure Yes S EEPROM write Yes Program the data of the page data latch into the EEPROM Figure 3-5 EEPROM Erase/Write Sequence @HITACHI | Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1199

© JULAULIUL Write Address Write Data ——— san a WRITE 35ys __ min BSY \\ tepw _15ms. max Figure 3-6 Byte Erase/Write Timing | @HITACHI 1200 Hitachi America, Ltd. « Hitachi Plaza e 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300

When reading EEPROM during erase/write operations, an inverted data of the last written data is read out to the MSB. "Qs" are read to the lower 7 bits regardless of write data. (Refer to Figure 3-8.) the ast written data |»? [ss |e [9 [ve | | Pe Read data during Pd writing Figure 3-8 Data Polling (8) Others: When write operations are performed with WI and EI of ECR set, the BSY is held at "0" for a maximum of 15ms. The memory contents are not changed. (Data polling also functions.) EEPROM operation modes are summerised in Table 3-2. Table 3-2 EEPROM Operation Mode Control ECR Mode READ WRITE WI EL BSY Read oO 1 - = 1 Data Polling ie} i = = Le) Erase-Write * 1 C) it] ie) 1+0 Write 1 (¢) oO i 1+0 Page Erasure 1 i) 1 ie} 1>0 Erase Write Inhibit 1 Co} i 1 1+0 Notes: * Byte write and page write operations are the same in terms of operation mode. The difference is that in number of bytes to be written at one time. | @ HITACHI 1202 Hitachi America, Ltd. Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300

Data Direction Register (DDR): DDR is a l-bit register. When writing "1" to bit 0, the I/O pin is used as output, while writing "0", I/O pin becomes input. DDR is a “write-only" register. If it is read, $FF appears. DDR becomes "0" (input) by reset. Data Register (DR): DR is a l-bit "write-only" register. The content of bit 0 is output to the I/O pin. If it is read, the I/O pin status is read instead of the contents of DR ("ls" are read except for bit 0). DR is not initialized by reset. (Undefined after power-on.) 3.2.2 1/0 pin timing >t LJ LJ Address $0000 WRITE \\ / r/o y Data (bit 0) Figure 3-11 1/0 pin Output Timing | @HITACHI | 1204 Hitachi America, Ltd. » Hitachi Plaza « 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 + (415) 589-8300

Section 4. Instruction Set Overview

4.1 Instruction Set Details

The symbols used in the Instruction Set Details and Instruction Set Summary are described as follows.

4.1.1 Specifying register

ri and rj are symbols for specifying a register. A register is specified (g-bit register or 16-bit register pair) by an instruction. The correspond- ing register is as follows. 86-bit ri Ri 16-bit ri Ri Ri-1 io) RO 1 Rl RO

1 Rl 3 R3 R2

4.1.2 Specifying conditions

f£ is a symbol which specifies a condition when executing a jump instruction. The conditions corresponding to each f are as follows. £ Condition NZ non zero v4 zero NC non carry c carry Pp positive N negative

4.1.3 Addressing mode

Refer to "2.1.2 Addressing mode" for details. REG : Register Direct REGI: Register Indirect IMM : Immediate REL : Relative IMP : Implied Register i | @ HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 * (415) 589-8300 1205

a INSTRUCTION SET OVERVIEW UNS LAU TIN Dee Ae

4.1.4 Condition code

The following symbols are used with respect to condition code changes. * : Not changed. ¢ : Changed according to operation results.

4.1.5 Others

(R )m : content in the memory addressed by R m : 8-bit immediate data g : 8-bit displacement Hor L : "H", attached to mor g, shows upper 4 bits and "L" shows lower 4 bits. S + Source addressing mode D : Destination addressing mode

4.1.6 Precautions

For (Rj)q, the contents of the register pair Rj Rj-1 are used as address if "j" is an odd number, while the content of the Register Rj is used as lower 8 bit address and upper 8 bit address is "0" if "j" is an even number. When using the instruction ADDD, SUBD, JP, or CALL (Indirect), designate "i" of Ri as an odd number because the instructions specify a register pair (16 bits). ; @HITACH! | 1206 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

ADC (Add with Carry) FORMAT CONDITION CODES ADC Ri, m C: Set if a carry is generated from the most significant bit of the result; cleared otherwise Z: Set if the result is 0; cleared otherwise OPERATION N: Set if the most significant Ritm+CrRi pit of the result is 1; cleared otherwise

DESCRIPTION

Adds the contents of the carry bit C to the sum of the contents of the Ri and an 8-bit data m, and places the result in the Ri- ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ‘ OPERAND INSTRUCTION CODE NUMBER OF MNEMONIC | rs {| »o | 1 TYPE Byte 1 | Byte 2. | MACHINE CYCLES yy ‘ ‘ ‘ ; ' : \\ ‘ ' : : : ' ' , ' : : @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 1207

ADC (Add with Carry) FORMAT CONDITION CODES SRL, RG C: Set if a carry is generated from the most significant bit of the result; cleared otherwise Z: Set if the result is 0; cleared otherwise OPERATION N: Set if the most significant bit of the result is 1; i+ Cc > Ri Rit Ri + + cleared otherwise Adds the contents of the carry bit C to the sum of the contents of register Ri and Rj, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE | OPERAND INSTRUCTION CODE NUMBER OF fos [| o. | MNEMONT | TYPE Byte 1 ! Byte 2 MACHINE CYCLES - ie ' : 1 t ' : ‘ ‘ ‘ : 1 ‘ 4 ‘ ' ' 1 : | @HITACHI | 1208 Hitachi America, Ltd. ¢ Hitachi Plaza 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300

ADC (Add with Carry) FORMAT CONDITION CODES Cc: i i d from tl ape Ri, (R3) Set if a carry is generated from the most significant bit of the result; cleared otherwise Z: Set if the result is 0; cleared otherwise OPERATION N: Set if the most significant bit of the result is 1; Ri + (Rj)m + © * RE cleared otherwise Adds the contents of the carry bit C to the sum of the contents of register Ri, and the data addressed by the contents of the Rj. The result is placed in Ri. when the Rj is an odd-numbered register (j=1,3,5,..++,15), the memory address is contained in the register pair RjRj-). While,when the Rj is an even-numbered register, the lower byte of memory address is contained in the Rj and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE | OPERAND INSTRUCTION CODE NUMBER OF MNEMONIC | type [_sytel | Byte 2 | 1 1 Byte 2 MACHINE CYCLES : ; 7 a t : H ' ' ‘ t : ‘ t | f ' 1 : ‘ : H i | : : @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1209

ADD Ri, m C: Set if a carry is generated from the most significant bit of the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; Ri + > R me Re cleared otherwise Adds an 8-bit data m, to the contents of register Ri (i=0,1,2,3, ...--, 15) and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES | OPERAND NUMBER OF MNEMONIC | Ty bd ; : ' : ' : ' ' ' ' ‘ ' ' ' ' ! | @ HITACHI | 1210 Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 i

ADD (Add without Carry) CONDITION CODES ADD Ri, Bi C: Set if a carry is generated from the most significant bit of the result; cleared otherwise Z: Set if the result is 0; cleared otherwise OPERATION N: Set if the most significant bit of the result is 1; Ri + Rj > i+ Rj > RA cleared otherwise Adds the contents of register Rj to the contents of register Ri, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE c ' OPERAND INSTRUCTION CODE NUMBER OF ee MNEMONIC | qypE Byte 1 | Byte 2 | MACHINE CYCLES | a ' t ‘ H ' H 1 ! ' H ' ‘ 1 1 f ' ' : ' : t 1 ' ' ' ' t ' ‘ H ‘ : @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 1211

ADD (Add without Carry) FORMAT CONDITION CODES ADD Ri, (R}) C: Set if a carry is generated from the most significant bit of the result; cleared otherwise Z: Set if the result is 0; cleared otherwise OPERATION N: Set if the most significant bit of the result is 1; R. R: i it (Ry > RE cleared otherwise Adds the data in the memory addressed by the contents of register Rj, to the contents of register Ri, and place the result in the Ri. When the Rj is an odd-numbered register (j=1,3,5,....,15), the memory address is contained in the register pair RjRj-1. While, when the Rj is an even-numbered register, the lower byte of memory address ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE NEMONIC | OPERAND INSTRUCTION CODE NUMBER OF fos {| o. | ml TYPE Byte 1 | Byte 2 | MACHINE CYCLES ; ie ‘ ' ' ' 1 : ' ' f ' | : : ' i @HITACHI 1212 Hitachi America, Ltd. ¢ Hitachi Plaza 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300

ADDD (Add Double) FORMAT CONDITION CODES ADDD Ri, Rj (i=1,3,5,-.++/25) C1 Not affected Z: Set if the result is 0; cleared other wise N: Not affected OPERATION Ri-1 + Rj > Ri-1 Ri + Carry” > Ri *:Carry from the result of lower byte addition. C flag of CCR will not change. Adds the contents of register Rj to the contents of register pair RiRi-1 (i=1,3,5,...++, 15), and places the result in the register pair RiRi-}. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDFESSING MODE INEMONIC ‘ OPERAND INSTRUCTION CODE NUMBER OF ps |. »o | " t_ TYPE Byte 1 ; Byte 2 MACHINE CYCLES ae 1 1 ' : t : : ' \\ ' ' ! 1 ‘ H ' { ‘ @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-8300 1213

ADDD (Add Double) FORMAT CONDITION CODES ADDD Ri, (Rj) (i=1,3,5,...., 15) C: Not affected Z: Set if the results 0; cleared otherwise N: Not affected OPERATION Ri-1 + (Rj)y * Ri-t Ri + Carry* + Ri *:Carry from the result of lower byte addition. C flag of CCR will not change. Adds the data in the memory addressed by the contents of register Rj, to the contents of register pair RiRi-1(i=1,3,5, ...., 15), and places When the Rj is an odd-numbered register (j=1,3,5,....,15), the memory address is specified by contents of register pair RjRj-1- While, when the Rj is an even-numbered register, the lower byte of memory address ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE T OPERAND INSTRUCTION CODE NUMBER OF js |». | MNEMONIC 1 TYPE Byte 1 | Byte 2 | MACHINE CYCLES ; i | ; 7 t ' ' A i : ' ‘ ' ' 1 H ‘ : ' : f i | : | @ HITACHI | 1214 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

AND (Logical AND) FORMAT CONDITION CODES AND Ri, m C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant OPERATION bit of the result is 1; cleared otherwise Ri Am > Ri Performs logical AND operation between the contents of register Ri and an 8-bit data m, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE $ OPERAND INSTRUCTION CODE NUMBER OF rs [> 4 MNEMONIC | pypE [_ayte 1 | Byte 2 | MACHINE CYCLES ; yy ‘ : ' ‘ 1 i : H \\ ‘ ' ' ' ' ‘ ! 1 ‘ | @HITACHI A Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 1215

AND (Logical AND) AND Ri, Rj C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise Ri A Rj > Ri Performs logical AND operation between the contents of registers Ri and Rj, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES T OPBRAND SOMBER OF H : Sy try Hq : 1 : 1 : ' : , ‘ \\ : ‘ H ‘ i @HITACHI 1216 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300

AND (Logical AND) FORMAT CONDITION CODES AND Ri, (Rj) C: Not affected. Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; OPERATION cleared otherwise Ri A (R})m > Ri Performs logical AND operation between the contents of register Ri and the data in the memory addressed by the contents of register Rj. when the Rj is an odd-numbered register (j=1,3,5,.-..,15), the memory address is specified by contents of register pair RjRj-1- While, when the Rj is an even-numbered register, the lower byte of memory address ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE M ¢ | OPERAND INSTRUCTION CODE NUMBER OF H H 7 | ‘ ' ' : 1 : ' : Hy H ‘ ‘ : ‘ ' ‘ ' : ' : ' : | @HITACHI | Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 1217

CALL (Call Subroutine) CALL g C: Not affected Z: Not affected N: Not affected PCL > (SP)m PCH > (SP - ly sp - 2+ SP PC +g + PC The contents of the PC is pushed onto the stack in order of lower 8-bit and upper 8-bit. The program counter PC that shows the address of instruction followed by CALL is added with displacement g. Then a branch occurs to the address specified by the PC. ADDRESSING MODE & NUMBER OF MACHINE CYCLES cane? OPERAND NUMBER OF ae : ' 1 : j 1 : 1 ‘ t ‘ 1 i | @ HITACHI 1218 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

CALL (Call Subroutine) CALL (Ri) (i=1,3/5,--+-, 15) C: Not affected Z: Not affected N: Not affected PCL > (SP)M PCH > (SP - Ly SP - 2 + SP RiRi-1 + PC The contents of program counter PC, which shows the address of instruction followed by CALL, is pushed onto the stack in order of lower 8-bit and upper 8-bit. A branch occurs to the address specified by the contents of register pair RiRi-1 ADDRESSING MODE & NUMBER OF MACHINE CYCLES T OPERAND WMBER OF MNEMONIC ! fs | »e | \\ TYPE Byte 1 | Byte 2 | MACHINE CYCLES , H ‘ : ' ' ‘ A i H ! i ‘ ‘ ‘ : ' i 1 ‘ ‘ ‘ ' t @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 1219

CMP (Compare) CONDITION CODES CMP Ri, m C: Set if a borrow is generated from the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of OPERATION the result is 1; Ri-m cleared otherwise Compares the contents of register Ri and an 8-bit data m. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE > OPERAND INSTRUCTION CODE MNEMONIC } NUMBER OF (fs |[ > | $TYPE Byte 1 ! Byte 2 MACHINE CYCLES : ; | } ; Z : ‘ , : 1 ‘ | : | i | @ HITACHI | 1220 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300

a INSTRUCTION SET OVERVIEW ARITHMETIC OPERATION CMP (Compare) CONDITION CODES CMP Ri, Rj C: Set if a borrow is generated from the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: hi i ifi bit OPERATION Set if the most significant bit of the result is 1; Ri - Rj cleared otherwise Compares the contents of registers Ri and Rj. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE MNEMON ‘ OPERAND INSTRUCTION CODE NUMBER OF er INEMONIC | TyPE Byte 1 | Byte 2 | MACHINE CYCLES S| ie : ! ' ' ' : ' ' | @HITACHI | Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 1221

CMP Ri, (Rj) C: Set if a borrow is generated from the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: Set if the most significant OPERATION bit of the result is 1; Ri - (Rim cleared otherwise Compares the contents of register Ri and the data in the memory addressed by the contents of register Rj. When the Rj is an odd-numbered register (j=1,3,5,....,15), the memory address is specified by contents of register pair RjRj-1- While, when the Rj is an even-numbered register, the lower byte of memory address ADDRESSING MODE & NUMBER OF MACHINE CYLES ADDRESSING MODE Tyre | OPERAND SEER OF REG/REGI MP | Ri, (R3) 33 to rgri ‘ i t i , ‘ 1 : ' H | ' ‘ | ; : | ' ' | ‘ ‘ 1 ‘ | 1 ‘ ‘ : | @HITACHI | 1222 Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

a INSTRUCTION SET OVERVIEW CTR (Condition Code to Register) CTR Ri C: Not affected Z: Not affected N: Not affected ccR + Ri Transfer the contents of condition code register to the register Ri. The upper 5 bits (bit 3 to bit 7) are cleared. Cc + Ri bit 0 Z + Ri bit 1 N > Ri bit 2 "o" > Ri bit 3 to 7 ADDRESSING MODE & NUMBER OF MACHINE CYCLES MNEMONIC ! yyy ' ' ' H ' ! ‘ H : ‘ ‘ ‘ ' ' H : ' H 1 ' ' ' 1 1 @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 1223

DEC (Decrement) FORMAT CONDITION CODES DEC Ri C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise Ri- 17> Ri Subtracts one from the contents of register Ri (i=0,1,2,..., 15), and places the result in the Ri, ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE | OPERAND INSTRUCTION CODE NUMBER OF REG DEC {RL 09 {Ori ‘ : 1 ' Hy : 1 ‘ ‘ : 1 i | @ HITACHI | 1224 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

EOR (Exclusive OR) FORMAT CONDITION CODES EOR Ri, m C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; OPERATION cleared otherwise Ri @ m>Ri Performs the logical EXCLUSIVE OR operation between the contents of register Ri and an 8-bit data m, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ' OPERAND INSTRUCTION CODE NUMBER OF MNEMONIC | ros |. »o | ‘TYPE Byte 1 | Byte 2 | MACHINE CYCLES 7 yey. ' ‘ ' ‘ ' : t : \\ ' ' H 1 H @HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 589-8300 1225

EOR (Exclusive OR) EOR Ri, Rj C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise Ri @ Rj} + Ri Performs the logical EXCLUSIVE OR operation between the contents of registers Ri, and the Rj, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES Toperano [INSTRUCTION CODE | WOMBER OF [_s |» | MNEMONIC | oypE [ Byte 1 | Byte 2 | MACHINE CYCLES H ‘ yy ' : ' ' ' , i H 1 ' Hy H i ' ' H f H { : ' i | @HITACHI | 1226 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 » (415) 589-8300

. LOGICAL OPERATION EOR EOR (Exclusive OR) FORMAT CONDITION CODES EOR Ri, (Rj) C: Not affected. 2: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; OPERATION cleared otherwise Ri ® (Ridy * Ri Performs the logical EXCLUSIVE OR operation between the contents of register Ri and the data in the memory addressed by the contents of register Rj. The result is placed in the Ri. When the Rj is an odd-numbered register (j=1,3,5,-.-.,15), the memory address is specified by the contents of register pair RjRj-1- while, when the Rj is an even-numbered register, the lower byte of memory address is specified by the contents of Rj (j=0,2,---++,14) and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE MON: A OPERAND INSTRUCTION CODE NUMBER OF rs [| > | MNEMONIC | type Byte 1 | Byte 2 | MACHINE CYCLES ; - Py 1 t H ' ' ‘ 1 ' ' : s 4 \\ t H : \\ H 1 ‘ fl ‘ ‘ ' 1 @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 + (415) 589-8300 1227

INC (Increment) FORMAT CONDITION CODES INC Ri C: Not affected. Z: Set if the result is 0; cleared otherwise N: Set if the most significant GPERATION bit of the result is 1; cleared otherwise Ri +1 > Ri Adds one to the contents of register Ri, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE M c ! OPERAND INSTRUCTION CODE NUMBER OF a MNENONTC {TYPE Byte 1 | Byte 2 | MACHINE CYCLES H ; | ye , ‘ ' ' H , : i : ' ' ' ' ' : ' : ' ' i t ' | : | @HITACHI 1228 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300

JP (Ri) C: Not affected (i=1,3,5,++++, 15) Z: Not affected N: Not affected RiRi-1 > PC Stores the contents of register pair RiRi-1 (i=1,3,5,-+-+, 15) to the program counter PC. A branch occures to the address specified by the contents of register pair RiRi-1. ADDRESSING MODE & NUMBER OF MACHINE CYCLES MNEMONIC } " 1 ' ant ' ' ' ' ' ‘ ‘ ' 1 ' 1 ‘ ‘ ‘ @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300 1229

a INSTRUCTION SET OVERVIEW PROGRAM CONTROL JP (Jump on Condition) CONDITION CODES. ge £, (Ri) C: Not affected (4=1,3,5,7°'+, 15) Z: Not affected N: Not affected OPERATION f is true : RiRi-1 > PC £ is false : Continue Tests the status of condition codes (C,NC,N,P,Z,NZ). When the condition is true, a branch occurs to the address specified by the contents of register pair RiRi-1 (i=1,3,5,*+*+, 15), otherwise the next sequential instruction is executed. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ' OPERAND INSTRUCTION CODE NUMBER OF fs |p| NNMONTIC | ype [ Byte 1 | Byte 2 | MACHINE CYCLES REGI gp | Py (Ri) 52 ‘rio 4 up 1 oN, (Ri) 53 + rio 4 JP | NZ, (Ri) 54 1 rid 4 Jp ! 2, (Ri) 55 1 rid 4 oP 1 NC, (Ri) 56 trio 4 oP 1c, (Ri) 57 ! rio 4 1 i ' : | @HITACHI | 1230 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 (415) 589-8300 i

a INSTRUCTION SET OVERVIEW PROGRAM CONTROL JR (Jump Relative) CONDITION CODES JR og C: Not affected Z: Not affected N: Not affected OPERATION PC +g + PC The program counter PC, which shows the address of instruction followed by JR, is added with displacement g. Then, a branch occurs to the address specified by the PC. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE tT OPERAND INSTRUCTION CODE NUMBER OF H : 1 - ' A f H ' ‘ ' H ' : H ; ‘ ‘ H H \\ : ' ' 1 t i} ' ' | @ HITACHI | Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 1231

SR (Jump Relative on Condition) FORMAT CONDITION CODES oR £,9 C: Not affected Z: Not affected N: Not affected OPERATION fis true : PC +g* PC f is false : Continue Tests the status Of condition codes (C, NC, N, P, Z, NZ). If the condition is true, the program counter, which shows the address of instruction followed by JR, is added with displacement g, and then branches to the address specified by the PC. If the condition is false, the next sequential instruction is executed. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ! OPERAND INSTRUCTION CODE NUMBER OF rs |.» MNEMONIC ' TYPE Byte 1 | Byte 2 MACHINE CYCLES REL JR ! Bg 42 1 gHgL 4 i ‘ : OR 1 ON g 43 ! gHgL 4 oR 1 NZ, g 44 ! gHgL 4 : : IR Sag 45 { glgh 4 : : OR tN, g 46 ! gHgL 4 oR 1 Gg 47 1 glgL 4 ‘ : ‘ ‘ ‘ ‘ 1 ‘ | H | @ HITACHI | 1232 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

LD (Load) FORMAT CONDITION CODES LD Ri, m C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant OPERATION bit of the result is 1; cleared otherwise m > Ri Loads an 8-bit data m into the register Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE T” OPERAND INSTRUCTION CODE | NUMBER OF [_s | > | MNEMONTC 1 oypE [Byte 1 | Byte 2 | MACHINE CYCLES Ty yy ' ; fl ' : : ‘ ‘ 1 ‘ 1 H i H @ HITACHI | Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1233

LD (Load) FORMAT CONDITION CODES LD Ri, (Rj) C: Not affected 2: Set if the result is 0; cleared otherwise N: Set if the most significant OPERATION bit of the result is 1; cleared otherwise (R3)y > Ri Loads the data in the memory addressed by the contents of register Rj into register Ri. When the Rj is an odd-numbered register (j=1,3,5,"+**,15), the memory address is specified by contents of register pair RjRj-1- While, when the Rj is an even-numbered register, the lower byte of memory address is specified by the contents of Rj (j=0,2,+++++,14) and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ‘ OPERAND INSTRUCTION CODE NUMBER OF [fs [| op. | MNEMONTC ! TYPE Byte 1, Byte 2 | MACHINE CYCLES , : ae , H : i , ‘ ‘ : 1 \\ ' ' ' ‘ | t ‘ @HITACHI 1234 Hitachi America, Ld. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

MV Ri, Rj C: Not affected 2: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; OPERATION cleared otherwise Rj + Ri Moves the contents of register Rj into the register Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ic : OPERAND INSTRUCTION CODE NUMBER OF Py yyy ' ' ' : 1 : \\ ' 1 ‘ ' i t H 1 ' i ‘ i | L ‘ @ HITACHI Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 1235

OR (Inclusive OR) CONDITION CODES OR Ri, m C: Not affected 2: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; OPERATION cleared otherwise Ri V m+ Ri Performs logical OR operation between the contents of register Ri and an 8-bit data m, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE c { OPERAND INSTRUCTION CODE NUMBER OF rs T . | MNEMONIC | TyPE [Byte 1 | Byte 2 | MACHINE CYCLES 7 ne ' : t ; 1 H 1 ‘ ! ' ‘ : ‘ ‘ 1 t | @HITAcHt | 1236 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

OR (Inclusive OR) FORMAT CONDITION CODES OR Ri, RJ C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; OPERATION cleared otherwise Ri V Rj > Ri Performs logical OR operation between the contents of registers Ri and Rj, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE rc | OPERAND INSTRUCTION CODE NUMBER OF fs T NEMONTC yee, Byte 1 | Byte 2 | MACHINE CYCLES OR ' Ri, Rj 04 : rjri ' i 4 : ' : 1 : 1 : ‘ ‘ ‘ : ‘ H : ‘ i : : @ HITACHI Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1237

——eeeeeeeSSSSSSSSSeSeSeeseeSeeeeeeeeeseseseseseseseseseeee INSTRUCTION SET OVERVIEW LOGICAL OPERATION OR (Inclusive OR) FORMAT CONDITION CODES OR Ri, (R3) C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; OPERATION cleared otherwise Ri V (Rj)M > Ri Performs logical OR operation between the contents of register Ri and the data in memory addressed by contents of register Rj. The result is placed in the Ri. When the Rj is an odd-numbered register (j=1,3,5,:+--, 15), the memory address is specified by contents of register pair RJRj-1. While, when the Rj is an even-numbered register, the lower byte of memory address is specified by the contents of Rj (j=0,2,-+--+,14) and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE { OPERAND INSTRUCTION CODE NUMBER OF rs | > | MNEMONIC | qypE [Byte 1 | Byte 2 | MACHINE CYCLES 7 | - Le 1 : ‘ : ' : 1 : t ‘ t ‘ : ‘ H : ' t : ' ‘ ' 1 ' i @ HITACHI ' 1238 Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300

RET C: Not affected Z: Not affected N: Not affected OPERATION (SP + 1)q * PCH (SP + 2) % PCL SP + 2 > SP Returns the PC from stack and causes a branch to the address specified by the PC. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE | OPERAND INSTRUCTION CODE NUMBER OF Po MNEMONIC | oypp [Byte 1 | Byte 2 | MACHINE CYCLES ail | | i H @HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300 1239

ROL (Rotate Left) FORMAT CONDITION CODES : toi i ROL Ri C: Set if the most significant bit of the register Ri is 1 before executing the instruction; cleared otherwise Z: Set if the result is 0; OPERATION cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise c b?7 bo Rotates left the contents of register Ri by one bit. Bit 7 is transferred to the carry bit C, and C is transferred to bit 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ontc | OPERAND INSTRUCTION CODE NUMBER OF REG ROL} Ri 1F : Ori ‘ ‘ ' H 1 : 1 ‘ 1 : t ' | : | @HITACHI | 1240 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300

ROR (Rotate Right) FORMAT CONDITION CODES ROR Ri C: Set if the bit 0 of register Ri is 1 before executing the instruction; cleared otherwise Z: Set if the result is 0; OPERATION cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise b7 bo c Rotates right the contents of register Ri by one bit. Bit 0 is transferred to the carry bit C, and C is transferred to bit 7- ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE onc OPERAND INSTRUCTION CODE NUMBER OF se MNEMONIC | pyPE Byte 1 | Byte 2 | MACHINE CYCLES H ‘ ye 4 t ' ‘ ' : ¥ ‘ 1 H ‘ ‘ 1 ' 1 H H : i : H | @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 1241

RTC (Register to Condition Code) CONDITION CODES RTC Ri C: Bit 0 of register Ri 2: Bit 1 of register Ri N: Bit 2 of register Ri OPERATION Ri + CCR Transfers the contents of register Ri to the condition code register. Ri bit 0+C bit 1 +2 bit 2+ N ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE rc | OPERAND INSTRUCTION CODE NUMBER OF rs [>| MNEMONTC | yee Byte 1 | Byte 2 | MACHINE CYCLES ' ' ' ‘ 1 : : : \\ ‘ ' H 1 : 1 ‘ , : ; : : | @ HITACHI | 1242 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300

a ____ INSTRUCTION SET OVERVIEW ARITHMETIC OPERATION SBC (Subtract with Carry) FORMAT CONDITION CODES SBC Ri, m C: Set if a borrow is generated from the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of OPERATION the result is 1; cleared otherwise Ri- m- C > Ri Subtracts an 8-bit data m and carry bit C from the contents of register Ri, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ! OPERAND INSTRUCTION CODE NUMBER OF ' : 1 : ' : Hl ' i : : | @HITACHI Hitachi America, Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 ¢ (415) 589-8300 1243

SBC (Subtract with Carry) FORMAT CONDITION CODES SBC Ri, Rj C: Set if a borrow is generated from the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of OPERATION the result is 1; cleared otherwise Ri - RJ - C+ Ri Subtracts the contents of register Rj and carry bit C from the contents of register Ri, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ! OPERAND INSTRUCTION CODE NUMBER OF rs [To | MMMONTC | over Byte 1 | Byte 2 | MACHINE CYCLES REG spc} Ri, Rj 03) of) orgri 4 H ' ' ‘ i : ' ‘ f ‘ ' ' i ' 1 | ' ' i i | : : | @HITACHI . | 1244 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

SBC (Subtract with Carry) FORMAT CONDITION CODES SBC Ri, (Rj) C: Set if a borrow is generated from the result; cleared otherwise Zz: Set if the result is 0; cleared otherwise N: Set if the most significant OPERATION bit of the result is 1; hi Ri - (R)q - C7 Ri cleared otherwise Subtracts the carry bit C and the data in the memory addressed by the contents of register Rj from register Ri. The result is placed in the Ri. When the Rj is an odd-numbered register (j=1,3,5,°°*° ,15), the memory address is specified by contents of register pair RjRj-). While, when the Rj is an even-numbered register, the lower byte of memory address is specified by the contents of Rj (j=0,2,+++-+ +14) and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE 2 c ‘ OPERAND INSTRUCTION CODE NUMBER OF rs | > | MNEMONIC | pyPE Byte 1 | Byte 2 | MACHINE CYCLES 7 Py ‘ : 1 ' ' : ' : ' : ' ‘ ' ' @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 1245

SL (Shift Left) FORMAT CONDITION CODES SL Ri C: Set if the most significant bit of register Ri is 1 before executing the instruction; cleared otherwise Z: Set if the result is 0; OPERATION cleared otherwise N: Set if the most significant c 7 bo cleared otherwise Shifts the contents of register Ri by one bit to the left. Bit 0 is cleared, and bit 7 is transferred to the carry bit C. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE . OPERAND INSTRUCTION CODE NUMBER OF MNEMONIC ! [fs [ o | ! TYPE Byte 1 | Byte 2 | MACHINE CYCLES i REG SL t Ri oF } ori ‘ ' ' ' ' : 1 : ' ' ' : 1 : ' ‘ | t ' | 1 H | H ‘ | ‘ i ‘ ' : : | @ HITACHI | 1246 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

a INSTRUCTION SET OVERVIEW SHIFT OPERATION SRA SRA (Shift Right Arithmetic) CONDITION CODES SRA RA C: Set if bit 0 of register Ri is 1 before executing the instruction; cleared otherwise 2: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise b7 bo c shifts the contents of register Ri by one bit to the right. Bit 0 is transferred to the carry bit C, while bit 7 is not affected. ADDRESSING MODE & NUMBER OF MACHINE CYCLES T opERAND wansR GF rs |» | MNEMONIC | ype [Byte 1 | Byte 2_ | MACHINE CYCLES yyy ' : ' H t : ' H ' ' ' H \\ H 1 H t ' ' : | @HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 1247

—_ee ee eee Eee SHIFT OPERATION SRL (Shift Right Logical) FORMAT CONDITION CODES SRL Ri C: Set if bit 0 of register Ri is 1 before executing the instruction; cleared otherwise Z: Set if the result is 0; cleared otherwise OPERATION N: Cleared o-LT TTT TTT }- b7 bo c Shift the contents of register Ri by one bit to the right. Bit 0 is transferred to the carry bit C, while bit 7 is cleared. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE mwonre | OPERAND INSTRUCTION CODE NUMBER OF [ss |» | MNEMONIC | oypE Byte 1 | Byte 2 | MACHINE CYCLES i He ' : ! ' f ‘ ' ' ‘ ' i : | @HITACHI | 1248 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

sT (Ri), RJ C: Not affected Z: Set if the data is 0; cleared otherwise N: Set if the most significant bit of the data is 1; OPERATION cleared otherwise Rj > (Ridy Stores the contents of register Rj into the memory addressed by the contents of register Ri. when the Ri is an odd-numbered register (i=1,3,5,77**,15), the memory address is specified by the contents of register pair RiRi-l. While, when the Ri is an even-numbered register, the lower byte of memory address is specified by the contents of Ri (i=0,2,+++++,14) and the upper byte Pecomes Oo. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE c+ OPERAND INSTRUCTION CODE NUMBER OF fs [| » | MNEMONIC | pypE [Byte 1 | Byte 2 | MACHINE CYCLES REG Rect ef ny | ae | ies 7 H ‘ 1 : ' ‘ 1 ‘ t ‘ 1 ' | @ HITACHI | Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 1249

SUB (Subtract without Carry) FORMAT CONDITION CODES Cc: i SUB Ri, R} Set if a borrow is generated from the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of OPERATION the result is 1; Ri - Rj > Ri cleared otherwise Subtracts the contents of register Rj from the contents of register Ri, and places the result in the Ri. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE | OPERAND INSTRUCTION CODE NUMBER OF [_s | D MNEMONIC ' TYPE Byte 1 | Byte 2 MACHINE CYCLES | | ey ' : ' t \\ H ' ‘ ' : 1 : H : 1 i | H | @HITACHI | 1250 Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300

SUB (Subtract without Carry) FORMAT CONDITION CODES SUB Ri, (R3) C: Set if a borrow is generated from the result; cleared otherwise Z: Set if the result is 0; cleared otherwise N: Set if the most significant OPERATION bit of the result is l; cleared otherwise Ri - (Rj)M > Ri Subtracts the data in the memory addressed by the contents of register Rj from the contents of register Ri. The result is placed in Ri. When the Rj is an odd-numbered register (j=1,3,5,°***,15), the memory address is specified by contents of register pair RjRj-1. While, when the Rj is an even-numbered register, the lower byte of memory address is specified by the contents of Rj (j=0,2,+++++,14) and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE ‘ OPERAND INSTRUCTION CODE NUMBER OF MNEMONIC ! fs | oi | TYPE Byte l | Byte 2 MACHINE CYCLES H ‘ 7 7 | ry ' ' ' ‘ t H : H : : 1 ‘ ‘ : 1 ' 1 ‘ : ' 1 ' @HITACHI Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1251

SUBD (Subtract Double) FORMAT CONDITION CODES SUBD Ri, Rj C: Not affected (i=1,3,5,+¢++,15) Z: Set if the result is 0; cleared otherwise N: Not affected OPERATION Ri-1 - Rj + Ri-1 Ri - Borrow* > Ri *:Borrow from the result of lower byte subtraction. C flag of CCR will not change. Subtracts the contents of register Rj from the contents of register pair ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE 0 T OPERAND INSTRUCTION CODE NUMBER OF fF os fo | MNEMONTC ‘TYPE Byte 1 ! Byte 2 MACHINE CYCLES REG SUBD | Ri, Rj 12 {0 xjri ' ‘ I ‘ ‘ : 1 : 1 ‘ ' ‘ 1 ' ‘ ‘ ' ' ' ' ' : 1 i : : @HITACHI 1252 Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

a ——— INSTRUCTION SET OVERVIEW ARITHMETIC OPERATION SUBD (Subtract Double) CONDITION CODES SUBD Ri, (Rj) C: Not affected (4=1,3,5,7777, 15) Z: Set if the result is 0; cleared otherwise N: Not affected OPERATION Ri-1 - (R3)m > Ri-2 Ri - Borrow* > Riv *:Borrow from the result of lower byte subtraction. C flag of CCR will not change. Subtracts the data in the memory addressed by the contents of register Rj, from the contents of register pair RiRi-1 (i=1,3,5,''',15). The result is placed in RiRi-1. When the Rj is an odd-numbered register (j=1,3,5,°*'*, 15), the memory address is specified by contents of register pair RjRj-1. While, when the Rj is an even-numbered register, the lower byte of memory address is specified by the contents of Rj (j=0,2,'''**,14) and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES ADDRESSING MODE MNEMONIC | OPERAND INSTRUCTION CODE NUMBER OF ce ee ee Byte 1 | Byte 2 | MACHINE CYCLES H Hl 7 | ; Z ‘ Hl ' t ‘ ‘ : : : 1 ‘ ‘ ‘ 1 : , : ' H i i ' : @ HITACHI Hitachi America, Ltd. « Hitachi Plaza « 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 1253

TST Ri, Rj C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise Ri A RJ Performs logical AND operation between the contents of register Ri and register Rj. ADDRESSING MODE & NUMBER OF MACHINE CYCLES Ty ey : ! i : ‘ ' H : H ' ' : i @HITACHI | 1254 Hitachi America, Ltd. # Hitachi Plaza « 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

TsT Ri, (Rj) C: Not affected Z: Set if the result is 0; cleared otherwise N: Set if the most significant bit of the result is 1; cleared otherwise Ri A (Ri)M Performs logical AND operation between the contents of register Ri and the data in the memory addressed by the contents of register Rj- When the Rj is an odd-numbered register (j=1,3,5,'"*",15), the memory address is specified by contents of register pair RjRj-1. While, when the Rj is an even-numbered register, the lower byte of memory address is specified by the contents of Rj (j=-0,2,+++++,14) and the upper byte becomes 0. ADDRESSING MODE & NUMBER OF MACHINE CYCLES mone | OPERAND onsen OF T j Tye ‘ : ' H ' H 1 t ' H ' H ' H ‘ ‘ ' ' 1 t ' ' ‘ ' H ' ' \\ | @HITACHI | Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 1255

alu[*o oe Go sa rs oo Galspo ow oe loool ow] owa azo oe ol] oe ol oe] onan 4 4 z Z 4 “ a fo 2 + 4 4 ko Z| 2 Z| z g + 0 ns) ° Sol + + rel + + gfe ®oefo Sot | Beef o 28 i + a | E a 1 2 $ Ble © Sle @ ele e e @ & 8 iS & & a toe oe t+ o4 F to rood 6 4 at soa aig | a oa a 2 7 . 2 se Zz s a og oe oO ret) % @ 3 2 ls ag Fs Bog a o |= Dn 9 nit Q Sfx 5 a vy m rf t ° . Sos ca Su a 3 3 ~ a v - + 832 3 ao inl DOW e2 6 dowoia da wo wf ow ow loa a ow 23 e i Pore 5 e]/e SS) EB Sf) ee] eg ee S38 8 & MM we & MW M wy co) & Me he “oS 4 ! ral ral cal a ° tay 4 fo © i Bim in | ge 20 o a | a o w]on | aio aw 4 > hel ij = 3 nm nS 5 3 oo a2 B 8 & 4 om 7 4 a 4 mm & 4 3 3 1 & & & & gh a S See) 4 ‘aod 4 ‘dood qo 4 » ™ 2 a ee oe o 5 a ea eg eg a m Q oo ® 8 z 68 8 8 8 8 2 2 B & = a2 2 a «a a 2B fo & & 5 : Bow 4 pos

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a fo} 1S) *@ e e e e e gas + ~~ —- os ad NZ e e e e tt + a a a 4 et ono tag iy ee Or Z 4 <7 4 + at tt 4 +? Set +3 Sze a S Fal cael ie) =o = ‘ of oF of Be 2 ° g gio 2k ge et a 3 y OE8 B £8 | 2 & 2 o a ors a1 oat |< < 5 j ) D j aod dod oMh oho ‘dood 2 mm mm mm am 4 4 cS Z 3 a og A a a“ os Df 2 3 It % x g |= ~ ® é |= 33 g |+ BO al: : % E + § % a 4 ers by cng EI «0 9° 4 see Lol Zoe = a “4 4 a «| ef ¢ o | a a wg wo $$ g| 43 a eR * 4] 82 8 ra a mE rae 2 3 ° "8 4 oa °o ° Nn nN oO oO a oOo 3° & 7 a a 4m ao | 23 = = cg = a = a a & con) a = oO ~~ ~ 4 7 o tl Sfos me oo. os ES ga 2(°3 F3 Py Pg . 2 ° C4 4 4 m A rel y & 4 4 o : § | 2 a g 8 ° w 2s | 8 a ga 3 sg | ites a E} a a @oe a 8 ee gH : 2B» Ba 8 3 2 nen & 5 . fa] a a cn Q § Qa a ist ba a Q 2 n ta Nm Oo-# an i Hoe RK | @ HITACHI | Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 1257

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Galo} o o o ees alz| oo o - eo g o 4 fs 0 4 = fod 2 don % = o fo) eke bob a = + + S ‘ 2 2 - Gs a & ~ 4 4 oO 4 oO , | | : a o @ qa fa) dg % o ag BOs % 4 3 zt ° 2 8 sg ]= oO 5 . 2 na o 3 |F Ss Holt ° a g %B |x od « U ~ i 4 u a = z sue t so Bu z d¢ » Bo EI g ae So. ao 7 a - a — 4 Fa iy S S13 9 § 3 4 ka 4 £8

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a olo}*e e . ° e . ° Buls} e «© ° . ° . . NZ e e e e e e e 2 & E4 & Eq & o e av o vo eo g t 3 t 3 2 * 2 * 3 + 3 & oe me of we OE OF a 9 4 A a 5 A 4 3 2 423 42 +B +3 42 +3 6 z € € = £ @ we + ogo Vo 90 vo oo vo 3 £8 £8 £8 FS RS a8 & o o + 2 Od fo On HO On BO § o FT TP FT TR Fa TF 2 a 2a 2a NN NN ioe} ome} oO Q Zz a i} . os @ s Fay a Ps] o °o ° 3° lo} ° fo} o o 3 8 1% a8 + 23 D S |= a 3 § ~ 2 a o a |= a 3 |? > 3 m8 3 |m < 8 fa a + a % q A % a 3 fan z a 3 La A a 3 3 a a gw a a a a ooM o > > > z D ey cy Boo 8 > & cS) > cy cl cy 6 i “ 4 eS 38 7 oo < ° 7 * 7 Eo & 6 a a Cy D 3 A e oe 2 2 8 a & mo A Zz z N z ) ° g Py Ey oO = Fed fed ra ro o 4 4 » @ 58 5 5 5 5 5 33 Bu i ao 5 & 3 § @ a 3 8 a 8| 5 cae & 2) 5 _ aoa aos | @HITACHI | Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 1261

ry) g a & & 4 & 4 t t + + + + ve oe ote ot. ote 5 y Sag Bae Sag Pae Soe Mae § B TTS *TR t Ts tyes ees sts g we 4B 42 ue 42 ME 3 s ga BS oR BR oe ts 3s | 2 .%g “og g #3 Mg S/S. .2 .2 2.2 12 le C8 2 a 1 38 38 38 36 ag 48 $ a A ao a oO ao ao ao moO c o om Hy > $4 46 64 46 54 Sé cf > 27 TF 8 TP RT FF 4 22 2z NN an OV ee) $ 2 . 6 ° °o o o °o °o ° e g a: ia wo Oo $38 ~ es Oo » |* 38 § ls x oO 7 “og 3 |= a8 woIt D 3 & 3 = |= a a ba € 4 § e 5 3 BY a + ag 9 & z 23 I af Ze 8 4a A&M & & A 2 ES) ” 4 M is iM u a os oO ° i . a ° N ” v w o i a 2 o wn a) wn ra wo wo i 3 —e ¢ = = 3 a = = a ~ 4 ~~ 8 3 3 2€ @ € 3 Sy & » 8 ¢ a Zz 2 is) z is) 3 8 4 = ood a a a oa a ae pM 5 5 Led 5 n 5 5 a io” By 8 S 8 i go 8 4 3 ~ § on 8 cael me 8 2 Bel a a a5] 3 tas oz 5 woe o« i @ HITACHI 1262 Hitachi America, Ltd. « Hitachi Plaza ° 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

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4.4 Precautions for Programming

NOP (No operation): The MCU doesn't have NOP (No operation) instruction. However, the same operation as NOP instruction can be realized by JP instruction. Refer to Figure 4-1 for details. NOP } JP NEXT ADD Ri, Rj NEXT ADD Ri, Rj Figure 4-1 No Operation by JP Instruction Power ON/OFF sequence: Power ON/OFF must be done as follows to prevent a wrong write of EEPROM or latch-up. Power ON . Power ON with RES=CLK="LOW" and I/O="LOW" (or high-impedance) . . Supply the CLK after power up. . RES must be held "LOW" more than 20 CLK cycles. Power OFF . RES="LOwW" and I/0="LOW" (or high-impedance) . CLK="LOW" after holding the RES="LOW" more than 20 CLK cycles. + Power OFF within Ims after CLK="LOW" Page write of EEPROM: In page write operation, all data written at one time must be in the same page. If the data in different pages are written at one time, all data will be written in one page which is selected by the first data. For example, if the addresses from $1810 to $182F are written at one time, addresses from $1810 to $181F will be written correctly, but the data which must be written to the addresses from $1820 to $182F properly, will be written in $1800 to $180F. In this case the addresses from $1810 to $181F and $1820 to $182F must be written separately. | @ HITACHI | Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 1265

Section 5. ROM Ordering Concerning ROM ordering, please refer "Single Chip Microcomputer ROM Ordering Manual". If the ROM code media is an EPROM, please pay attention to the program addresses of the EPROM. Table 5-1 provides the address correspondence between mask ROM and EPROM. All data in unused addresses must be SFP. Table 5-1 Address correspondence between mask ROM and EPROM Mask ROM Addresses El M T: en PROM Addresses EPROM Type $3400 $1400 HN482764 wo €_) to un27c64 $3FFF S$LPFF or equivalents | @ HITACHI | 1266 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

Section 6. Electrical Characteristics Absolute Maximum Ratings Item Symbol value Unit a Supply voltage vec -0.3 to +7.0 v a Input voltage Vin -0.3 to vect0.3 v Operating temperature — qy.y 0 to +50 °C range Storage temperature Tstg 0 to +50 °c Storage temperature MStg DC Characteristics (Vcc=5V+10%, Vss=0V, Ta=0 to +50°C) Item Symbol Min. Typ. Max. Unit Test Condition a Input high RES Vin 4.0 Vect0.3 Vv CLK 2.4 Vect0.3 I/O Port 2.0 Vect0.3 Input low RES Vin -0.3 0.6 v CLK -0.3 0.5 1/0 Port -0.3 0.8 a Output high Vou 2.4 Voc Vv Tog = -LOOpA voltage Se 3.8 vec Ion = -20UA a Output low voltage Von (o) 6.4 Vv Ion = lm Dutput tow votFage Vom RO Input leakage . vin=0.5 to —— I . current (RES, CLK) |tin| 10.0 va vcc-0.5V Three state Vin=0.5 to 1 . leakage current (I/O) |t91.| 10.0 ya Vec-0.5V eakage current tijee Power dissipation Icc 10 mA £=5MHz oe ; Vin=0V, £=1MHz Pin capacitance Cp 15 PF nan25ee @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 1267

ELECTRICAL CHARACTERISTICS

AC Characteristics (Voc=5V410%, Vgs=0V, Ta=O to +50°C) Item Symbol Min. Typ. Max. Unit Test Condition Clock cycle time teye G.2 0.33 us Fig. 6-1 Clock pulse width high tcy 0.4 0.6 teye Fig. 6-1 Clock pulse width low tcy 0.4 0.6 teye Fig. 6-1 Clock fall time ter 20 ns Fig. 6-1 Clock rise time ter 20 ns Fig. 6-1 I/O port fall time te 1.0 us Fig. 6-2 I/O port rise time tr 1.0 us Fig. 6-2 RES pulse width tRWL 20 teye Fig. 2-12 BEPROH erase/write tEPW 10 15 ms Fig. 3-6 @HITACHI | 1268 Hitachi America, Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 + (415) 589-8300

Product Information

HD65901 specifications and overview.

Summary

MCU(MICROCOMPUTER UNIT)

Description

MCU(MICROCOMPUTER UNIT)

Source title HD65901 Datasheet(PDF) - Hitachi Semiconductor

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