HD6412350

Renesas Technology Corp

The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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Datasheet sections

1.1 Overview
1.2 Block Diagram
1.3 Pin Description
1.3.1 Pin Arrangement
1.3.2 Pin Functions in Each Operating Mode
1.3.3 Pin Functions
2.1 Overview
2.1.1 Features
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
2.1.3 Differences from H8/300 CPU
2.1.4 Differences from H8/300H CPU
2.2 CPU Operating Modes
2.3 Address Space
2.4 Register Configuration
2.4.1 Overview
2.4.2 General Registers
2.4.3 Control Registers
2.4.4 Initial Register Values
2.5 Data Formats
2.5.1 General Register Data Formats
2.5.2 Memory Data Formats
2.6 Instruction Set
2.6.1 Overview
2.6.2 Instructions and Addressing Modes
2.6.3 Table of Instructions Classified by Function
2.6.4 Basic Instruction Formats
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Mode
2.7.2 Effective Address Calculation
2.8 Processing States
2.8.1 Overview
2.8.2 Reset State
2.8.3 Exception-Handling State
2.8.4 Program Execution State
2.8.5 Bus-Released State
2.8.6 Power-Down State

Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

H8S/2351, HD6432351, H8S/2350, HD6412350 Hardware Manual ADE-602-111A Rev. 2.0 3/10/03 Hitachi, Ltd. MC-Setsu

When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.

The H8S/2350 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. On-chip memory consists of large-capacity ROM (H8S/2351 only) and RAM. On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2350 Series enables easy implementation of compact, high-performance systems capable of processing large volumes of data. This manual describes the hardware of the H8S/2350 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set.

7.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,

Appendix F Timing of Transition to and Recovery from Hardware

1.1 Overview

The H8S/2350 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include DMA controller (DMAC) and data transfer controller (DTC) bus masters, ROM (H8S/2351 only) and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. The H8S/2351 has on-chip mask ROM. The H8S/2351 supports seven operating modes (modes 1 to 7), while the H8S/2350 supports three operating modes (modes 1, 4, and 5). There is a choice of address space and single-chip mode or expansion mode. The features of the H8S/2350 Series are shown in Table 1-1.

CPU • General-register machine ¾ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

High-speed operation suitable for realtime control ¾ Maximum clock rate: 20 MHz ¾ High-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 · 16-bit register-register multiply : 1000 ns 32 ÷ 16-bit register-register divide : 1000 ns
Instruction set suitable for high-speed operation ¾ Sixty-five basic instructions ¾ 8/16/32-bit move/arithmetic and logic instructions ¾ Unsigned/signed multiply and divide instructions ¾ Powerful bit-manipulation instructions
Two CPU operating modes ¾ Normal mode : 64-kbyte address space ¾ Advanced mode : 16-Mbyte address space Bus controller • Address space divided into 8 areas, with bus specifications settable independently for each area
Chip select output possible for each area
Choice of 8-bit or 16-bit access space for each area
2-state or 3-state access space can be designated for each area
Number of program wait states can be set for each area
Burst ROM directly connectable
Maximum 8-Mbyte DRAM directly connectable (or use of interval timer possible)
External bus release function DMA controller (DMAC)
Choice of short address mode or full address mode
4 channels in short address mode
2 channels in full address mode
Transfer possible in repeat mode, block transfer mode, etc.
Single address mode transfer possible
Can be activated by internal interrupt

Table 1-1 Overview (cont) Item Specification Data transfer controller (DTC)

Can be activated by internal interrupt or software
Multiple transfers or multiple types of transfer possible for one activation source
Transfer possible in repeat mode, block transfer mode, etc.
Request can be sent to CPU for interrupt that activated DTC 16-bit timer-pulse unit (TPU)
6-channel 16-bit timer on-chip
Pulse I/O processing capability for up to 16 pins'
Automatic 2-phase encoder count capability Programmable pulse generator (PPG)
Maximum 16-bit pulse output possible with TPU as time base
Output trigger selectable in 4-bit groups
Non-overlap margin can be set
Direct output or inverse output setting possible Watchdog timer • Watchdog timer or interval timer selectable Serial communica- tion interface (SCI) 2 channels
Asynchronous mode or synchronous mode selectable
Multiprocessor communication function
Smart card interface function A/D converter • Resolution: 10 bits
Input: 8 channels
High-speed conversion : 6.7 µs minimum conversion time (at 20 MHz operation)
Single or scan mode selectable
Sample and hold circuit
A/D conversion can be activated by external trigger or timer trigger D/A converter • Resolution: 8 bits
Output: 2 channels I/O ports • 87 I/O pins, 8 input-only pins Memory • Mask ROM
High-speed static RAM Product Name ROM RAM H8S/2350 — 2 kbytes H8S/2351 64 kbytes 2 kbytes Interrupt controller• Nine external interrupt pins (NMI, IRQ0 to IRQ7)
42 internal interrupt sources
Eight priority levels settable

Table 1-1 Overview (cont) Item Specification Power-down state • Medium-speed mode

Sleep mode
Module stop mode
Software standby mode
Hardware standby mode Operating modes Seven MCU operating modes Mode CPU Operating Mode On-Chip Description ROM External Data Bus Initial Maximum Value Value

1 Normal On-chip ROM disabled Disabled

2* On-chip ROM enabled Enabled expansion mode 8 bits 16 bits 3* Single-chip mode Enabled —

4 Advanced On-chip ROM disabled Disabled

5 On-chip ROM disabled Disabled

6* On-chip ROM enabled Enabled expansion mode 8 bits 16 bits 7* Single-chip mode Enabled — Note: * Only applies to the H8S/2351. Clock pulse generator

Built-in duty correction circuit Packages • 120-pin plastic TQFP (TFP-120)
128-pin plastic QFP (FP-128) Product lineup Model Name ROMless Version Mask ROM Version ROM/RAM (Bytes) Packages — HD6432351 64 k/2 k TFP-120 FP-128 HD6412350 — —/2 k TFP-120 FP-128

1.2 Block Diagram

Figure 1-1 shows an internal block diagram of the H8S/2350 Series. PE 7/D7 PE 6/D6 PE 5/D5 PE 4/D4 PE 3/D3 PE 2/D2 PE 1/D1 PE 0/D0 PD 7/D15 PD 6/D14 PD 5/D13 PD 4/D12 PD 3/D11 PD 2/D10 PD 1/D9 PD 0/D8 Port D VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS Port A PA 7/A23/IRQ7 PA 6/A22/IRQ6 PA 5/A21/IRQ5 PA 4/A20/IRQ4 PA 3/A19 PA 2/A18 PA 1/A17 PA 0/A16 PB 7/A15 PB 6/A14 PB 5/A13 PB 4/A12 PB 3 /A11 PB 2/A10 PB 1/A9 PB 0/A8 PC 7/A7 PC 6/A6 PC 5/A5 PC 4/A4 PC 3/A3 PC 2/A2 PC 1/A1 PC 0/A0 P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 P50 P51 P52 P53/ADTRG P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Vref AV CC AV SS P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3 P23/PO3/TIOCD3 P24/PO4/TIOCA4 P25/PO5/TIOCB4 P26/PO6/TIOCA5 P27/PO7/TIOCB5 P10/PO8/TIOCA0/ DACK0 P11/PO9/TIOCB0/ DACK1 P12/PO10/TIOCC0/TCLKA P13/PO11/TIOCD0/TCLKB P14/PO12/TIOCA1 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2 P17/PO15/TIOCB2/TCLKD P67/CS7/IRQ3 P66/CS6/IRQ2 P65/IRQ1 P64/IRQ0 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 P60/DREQ0/CS4 PG 4/CS0 PG 3/CS1 PG 2/CS2 PG 1/CS3 PG 0/CAS PF 7/ø PF 6/AS PF 5/RD PF 4/HWR PF 3/LWR PF 2/WAIT/LCAS/BREQO PF 1/BACK PF 0/BREQ Clock pulse generator ROM * RAM WDT TPU Note: * Only applies to the H8S/2351. SCI PPG MD 2 MD 1 MD 0 EXTAL XTAL STBY/CR RES/CR WDTOVF NMI Bus controller H8S/2000 CPU DTCInterrupt controller Port E DMAC Internal data bus Internal address bus Port B Port C Port Port Port 4Port 2Port 1 Port Port G Port F Peripheral data bus Peripheral address bus D/A converter A/D converter Figure 1-1 Block Diagram

1.3 Pin Description

1.3.1 Pin Arrangement

Figures 1-2 and 1-3 show the pin arrangement of the H8S/2350 Series. VCC PC 0/A0 PC 1/A1 PC 2/A2 PC 3/A3 VSS PC 4/A4 PC 5/A5 PC 6/A6 PC 7/A7 PB 0/A8 PB 1/A9 PB 2/A10 PB 3/A11 VSS PB 4/A12 PB 5/A13 PB 6/A14 PB 7/A15 PA 0/A16 PA 1 /A17 PA 2/A18 PA 3/A19 VSS PA 4/A20/IRQ4 PA 5/A21/IRQ5 PA 6/A22/IRQ6 PA 7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 P52 P53/ADTRG/CR AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AV SS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/ DACK1/CR P10/PO8/TIOCA0/ DACK0/CR MD 0 MD 1 MD 2 PG 0/CAS/CR PG 1/CS3/CR PG 2/CS2/CR PG 3/CS1/CR PG 4/CS0 P51 P50 PF 0/BREQ PF 1/BACK PF 2/LCAS/WAIT/BREQO PF 3/LWR PF 4/HWR PF 5/RD PF 6/AS VCC PF 7/ø VSS EXTAL XTAL V CC STBY NMI RES WDTOVF/CR 0/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3 P23/PO3/TIOCD3 P24/PO4/TIOCA4 P25/PO5/TIOCB4 P26/PO6/TIOCA5 P27/PO7/TIOCB5 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 P60/DREQ0/CS4 VSS P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 VCC PD 7/D15 PD 6/D14 PD 5/D13 PD 4/D12 VSS PD 3/D11 PD 2/D10 PD 1/D9 PD 0/D8 PE 7/D7 PE 6/D6 PE 5/D5 PE 4/D4 VSS PE 3/D3 PE 2/D2 PE 1/D1 PE 0/D0 VCC P64/IRQ0 P65/IRQ1 Figure 1-2 Pin Arrangement (TFP-120: Top View)

PF 7/ø VSS EXTAL XTAL V CC STBY NMI RES WDTOVF 0/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3 P23/PO3/TIOCD3 P24/PO4/TIOCA4 P25/PO5/TIOCB4 P26/PO6/TIOCA5 P27/PO7/TIOCB5 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 VSS VSS P60/DREQ0/CS4 VSS 102 101 100 Figure 1-3 Pin Arrangement (FP-128: Top View)

1.3.2 Pin Functions in Each Operating Mode

Table 1-2 shows the pin functions of the H8S/2350 Series in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. Pin Name TFP-120 FP-128 Mode 1 Mode 2 * Mode 3 * Mode 4 Mode 5 Mode 6 * Mode 7 *

15 V CC VCC VCC VCC VCC VCC VCC

26 A 0 PC 0/A0 PC 0 A0 A0 PC 0/A0 PC 0

37 A 1 PC 1/A1 PC 1 A1 A1 PC 1/A1 PC 1

48 A 2 PC 2/A2 PC 2 A2 A2 PC 2/A2 PC 2

59 A 3 PC 3/A3 PC 3 A3 A3 PC 3/A3 PC 3

61 0 V SS VSS VSS VSS VSS VSS VSS 71 1 A 4 PC 4/A4 PC 4 A4 A4 PC 4/A4 PC 4 81 2 A 5 PC 5/A5 PC 5 A5 A5 PC 5/A5 PC 5 91 3 A 6 PC 6/A6 PC 6 A6 A6 PC 6/A6 PC 6 10 14 A 7 PC 7/A7 PC 7 A7 A7 PC 7/A7 PC 7 11 15 A 8 PB 0/A8 PB 0 A8 A8 PB 0/A8 PB 0 12 16 A 9 PB 1/A9 PB 1 A9 A9 PB 1/A9 PB 1 13 17 A 10 PB 2/A10 PB 2 A10 A10 PB 2/A10 PB 2 14 18 A 11 PB 3/A11 PB 3 A11 A11 PB 3/A11 PB 3 15 19 V SS VSS VSS VSS VSS VSS VSS 16 20 A 12 PB 4/A12 PB 4 A12 A12 PB 4/A12 PB 4 17 21 A 13 PB 5/A13 PB 5 A13 A13 PB 5/A13 PB 5 18 22 A 14 PB 6/A14 PB 6 A14 A14 PB 6/A14 PB 6 19 23 A 15 PB 7/A15 PB 7 A15 A15 PB 7/A15 PB 7 20 24 PA 0 PA 0 PA 0 A16 A16 PA 0/A16 PA 0 21 25 PA 1 PA 1 PA 1 A17 A17 PA 1/A17 PA 1 22 26 PA 2 PA 2 PA 2 A18 A18 PA 2/A18 PA 2 23 27 PA 3 PA 3 PA 3 A19 A19 PA 3/A19 PA 3 24 28 V SS VSS VSS VSS VSS VSS VSS 25 29 PA 4/IRQ4 PA 4/IRQ4 PA 4/IRQ4 A20 A20 PA 4/A20/ IRQ4 PA 4/IRQ4 26 30 PA 5/IRQ5 PA 5/IRQ5 PA 5/IRQ5 PA 5/A21/ IRQ5 PA 5/A21/ IRQ5 PA 5/A21/ IRQ5 PA 5/IRQ5 27 31 PA 6/IRQ6 PA 6/IRQ6 PA 6/IRQ6 PA 6/A22/ IRQ6 PA 6/A22/ IRQ6 PA 6/A22/ IRQ6 PA 6/IRQ6

Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. Pin Name TFP-120 FP-128 Mode 1 Mode 2 * Mode 3 * Mode 4 Mode 5 Mode 6 * Mode 7 * 28 32 PA 7/IRQ7 PA 7/IRQ7 PA 7/IRQ7 PA 7/A23/ IRQ7 PA 7/A23/ IRQ7 PA 7/A23/ IRQ7 PA 7/IRQ7 29 33 P6 7/IRQ3 P67/IRQ3 P67/IRQ3 P67/IRQ3/ CS7 P67/IRQ3/ CS7 P67/IRQ3/ CS7 P67/IRQ3 30 34 P6 6/IRQ2 P66/IRQ2 P66/IRQ2 P66/IRQ2/ CS6 P66/IRQ2/ CS6 P66/IRQ2/ CS6 P66/IRQ2 —3 5 V SS VSS VSS VSS VSS VSS VSS —3 6 V SS VSS VSS VSS VSS VSS VSS 31 37 P6 5/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 P65/IRQ1 32 38 P6 4/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 P64/IRQ0 33 39 V CC VCC VCC VCC VCC VCC VCC 34 40 PE 0/D0 PE 0/D0 PE 0 PE 0/D0 PE 0/D0 PE 0/D0 PE 0 35 41 PE 1/D1 PE 1/D1 PE 1 PE 1/D1 PE 1/D1 PE 1/D1 PE 1 36 42 PE 2/D2 PE 2/D2 PE 2 PE 2/D2 PE 2/D2 PE 2/D2 PE 2 37 43 PE 3/D3 PE 3/D3 PE 3 PE 3/D3 PE 3/D3 PE 3/D3 PE 3 38 44 V SS VSS VSS VSS VSS VSS VSS 39 45 PE 4/D4 PE 4/D4 PE 4 PE 4/D4 PE 4/D4 PE 4/D4 PE 4 40 46 PE 5/D5 PE 5/D5 PE 5 PE 5/D5 PE 5/D5 PE 5/D5 PE 5 41 47 PE 6/D6 PE 6/D6 PE 6 PE 6/D6 PE 6/D6 PE 6/D6 PE 6 42 48 PE 7/D7 PE 7/D7 PE 7 PE 7/D7 PE 7/D7 PE 7/D7 PE 7 43 49 D 8 D 8 PD 0 D 8 D 8 D 8 PD 0 44 50 D 9 D 9 PD 1 D 9 D 9 D 9 PD 1 45 51 D 10 D 10 PD 2 D 10 D 10 D 10 PD 2 46 52 D 11 D 11 PD 3 D 11 D 11 D 11 PD 3 47 53 V SS VSS VSS VSS VSS VSS VSS 48 54 D 12 D 12 PD 4 D 12 D 12 D 12 PD 4 49 55 D 13 D 13 PD 5 D 13 D 13 D 13 PD 5 50 56 D 14 D 14 PD 6 D 14 D 14 D 14 PD 6 51 57 D 15 D 15 PD 7 D 15 D 15 D 15 PD 7 52 58 V CC VCC VCC VCC VCC VCC VCC 53 59 P3 0/TxD0 P3 0/TxD0 P3 0/TxD0 P3 0/TxD0 P3 0/TxD0 P3 0/TxD0 P3 0/TxD0 54 60 P3 1/TxD1 P3 1/TxD1 P3 1/TxD1 P3 1/TxD1 P3 1/TxD1 P3 1/TxD1 P3 1/TxD1 55 61 P3 2/RxD0 P3 2/RxD0 P3 2/RxD0 P3 2/RxD0 P3 2/RxD0 P3 2/RxD0 P3 2/RxD0

Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. Pin Name TFP-120 FP-128 Mode 1 Mode 2 * Mode 3 * Mode 4 Mode 5 Mode 6 * Mode 7 * 56 62 P3 3/RxD1 P3 3/RxD1 P3 3/RxD1 P3 3/RxD1 P3 3/RxD1 P3 3/RxD1 P3 3/RxD1 57 63 P3 4/SCK0 P3 4/SCK0 P3 4/SCK0 P3 4/SCK0 P3 4/SCK0 P3 4/SCK0 P3 4/SCK0 58 64 P3 5/SCK1 P3 5/SCK1 P3 5/SCK1 P3 5/SCK1 P3 5/SCK1 P3 5/SCK1 P3 5/SCK1 59 65 V SS VSS VSS VSS VSS VSS VSS 60 66 P6 0/ DREQ0 P60/ DREQ0 P60/ DREQ0 P60/ DREQ0/ CS4 P60/ DREQ0/ CS4 P60/ DREQ0/ CS4 P60/ DREQ0 —6 7 V SS VSS VSS VSS VSS VSS VSS —6 8 V SS VSS VSS VSS VSS VSS VSS 61 69 P6 1/ TEND0 P61/ TEND0 P61/ TEND0 P61/ TEND0/ CS5 P61/ TEND0/ CS5 P61/ TEND0/ CS5 P61/ TEND0 62 70 P6 2/ DREQ1 P62/ DREQ1 P62/ DREQ1 P62/ DREQ1 P62/ DREQ1 P62/ DREQ1 P62/ DREQ1 63 71 P6 3/ TEND1 P63/ TEND1 P63/ TEND1 P63/ TEND1 P63/ TEND1 P63/ TEND1 P63/ TEND1 64 72 P2 7/PO7/ TIOCB5 P27/PO7/ TIOCB5 P27/PO7/ TIOCB5 P27/PO7/ TIOCB5 P27/PO7/ TIOCB5 P27/PO7/ TIOCB5 P27/PO7/ TIOCB5 65 73 P2 6/PO6/ TIOCA5 P26/PO6/ TIOCA5 P26/PO6/ TIOCA5 P26/PO6/ TIOCA5 P26/PO6/ TIOCA5 P26/PO6/ TIOCA5 P26/PO6/ TIOCA5 66 74 P2 5/PO5/ TIOCB4 P25/PO5/ TIOCB4 P25/PO5/ TIOCB4 P25/PO5/ TIOCB4 P25/PO5/ TIOCB4 P25/PO5/ TIOCB4 P25/PO5/ TIOCB4 67 75 P2 4/PO4/ TIOCA4 P24/PO4/ TIOCA4 P24/PO4/ TIOCA4 P24/PO4/ TIOCA4 P24/PO4/ TIOCA4 P24/PO4/ TIOCA4 P24/PO4/ TIOCA4 68 76 P2 3/PO3/ TIOCD3 P23/PO3/ TIOCD3 P23/PO3/ TIOCD3 P23/PO3/ TIOCD3 P23/PO3/ TIOCD3 P23/PO3/ TIOCD3 P23/PO3/ TIOCD3 69 77 P2 2/PO2/ TIOCC3 P22/PO2/ TIOCC3 P22/PO2/ TIOCC3 P22/PO2/ TIOCC3 P22/PO2/ TIOCC3 P22/PO2/ TIOCC3 P22/PO2/ TIOCC3 70 78 P2 1/PO1/ TIOCB3 P21/PO1/ TIOCB3 P21/PO1/ TIOCB3 P21/PO1/ TIOCB3 P21/PO1/ TIOCB3 P21/PO1/ TIOCB3 P21/PO1/ TIOCB3 71 79 P2 0/PO0/ TIOCA3 P20/PO0/ TIOCA3 P20/PO0/ TIOCA3 P20/PO0/ TIOCA3 P20/PO0/ TIOCA3 P20/PO0/ TIOCA3 P20/PO0/ TIOCA3 72 80 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF 73 81 RES RES RES RES RES RES RES 74 82 NMI NMI NMI NMI NMI NMI NMI

Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. Pin Name TFP-120 FP-128 Mode 1 Mode 2 * Mode 3 * Mode 4 Mode 5 Mode 6 * Mode 7 * 75 83 STBY STBY STBY STBY STBY STBY STBY 76 84 V CC VCC VCC VCC VCC VCC VCC 77 85 XTAL XTAL XTAL XTAL XTAL XTAL XTAL 78 86 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 79 87 V SS VSS VSS VSS VSS VSS VSS 80 88 PF 7/ø PF 7/ø PF 7/ø PF 7/ø PF 7/ø PF 7/ø PF 7/ø 81 89 V CC VCC VCC VCC VCC VCC VCC 82 90 AS AS PF 6 AS AS AS PF 6 83 91 RD RD PF 5 RD RD RD PF 5 84 92 HWR HWR PF 4 HWR HWR HWR PF 4 85 93 LWR LWR PF 3 LWR LWR LWR PF 3 86 94 PF 2/WAIT/ BREQO PF 2/WAIT/ BREQO PF 2 PF 2/LCAS/ WAIT/ BREQO PF 2/LCAS/ WAIT/ BREQO PF 2/LCAS/ WAIT/ BREQO PF 2 87 95 PF 1/BACK PF 1/BACK PF 1 PF 1/BACK PF 1/BACK PF 1/BACK PF 1 88 96 PF 0/BREQ PF 0/BREQ PF 0 PF 0/BREQ PF 0/BREQ PF 0/BREQ PF 0 89 97 P5 0 P50 P50 P50 P50 P50 P50 90 98 P5 1 P51 P51 P51 P51 P51 P51 —9 9 V SS VSS VSS VSS VSS VSS VSS — 100 V SS VSS VSS VSS VSS VSS VSS 91 101 P5 2 P52 P52 P52 P52 P52 P52 92 102 P5 3/ ADTRG P53/ ADTRG P53/ ADTRG P53/ ADTRG P53/ ADTRG P53/ ADTRG P53/ ADTRG 93 103 AV CC AV CC AV CC AV CC AV CC AV CC AV CC 94 104 V ref Vref Vref Vref Vref Vref Vref 95 105 P4 0/AN0 P4 0/AN0 P4 0/AN0 P4 0/AN0 P4 0/AN0 P4 0/AN0 P4 0/AN0 96 106 P4 1/AN1 P4 1/AN1 P4 1/AN1 P4 1/AN1 P4 1/AN1 P4 1/AN1 P4 1/AN1 97 107 P4 2/AN2 P4 2/AN2 P4 2/AN2 P4 2/AN2 P4 2/AN2 P4 2/AN2 P4 2/AN2 98 108 P4 3/AN3 P4 3/AN3 P4 3/AN3 P4 3/AN3 P4 3/AN3 P4 3/AN3 P4 3/AN3 99 109 P4 4/AN4 P4 4/AN4 P4 4/AN4 P4 4/AN4 P4 4/AN4 P4 4/AN4 P4 4/AN4 100 110 P4 5/AN5 P4 5/AN5 P4 5/AN5 P4 5/AN5 P4 5/AN5 P4 5/AN5 P4 5/AN5 101 111 P4 6/AN6/ DA0 P46/AN6/ DA0 P46/AN6/ DA0 P46/AN6/ DA0 P46/AN6/ DA0 P46/AN6/ DA0 P46/AN6/ DA0

Table 1-2 Pin Functions in Each Operating Mode (cont) Pin No. Pin Name TFP-120 FP-128 Mode 1 Mode 2 * Mode 3 * Mode 4 Mode 5 Mode 6 * Mode 7 * 102 112 P4 7/AN7/ DA1 P47/AN7/ DA1 P47/AN7/ DA1 P47/AN7/ DA1 P47/AN7/ DA1 P47/AN7/ DA1 P47/AN7/ DA1 103 113 AV SS AV SS AV SS AV SS AV SS AV SS AV SS 104 114 V SS VSS VSS VSS VSS VSS VSS 105 115 P1 7/PO15/ TIOCB2/ TCLKD 7/PO15/ TIOCB2/ TCLKD 7/PO15/ TIOCB2/ TCLKD 7/PO15/ TIOCB2/ TCLKD 7/PO15/ TIOCB2/ TCLKD 7/PO15/ TIOCB2/ TCLKD 7/PO15/ TIOCB2/ TCLKD 106 116 P1 6/PO14/ TIOCA2 P16/PO14/ TIOCA2 P16/PO14/ TIOCA2 P16/PO14/ TIOCA2 P16/PO14/ TIOCA2 P16/PO14/ TIOCA2 P16/PO14/ TIOCA2 107 117 P1 5/PO13/ TIOCB1/ TCLKC 5/PO13/ TIOCB1/ TCLKC 5/PO13/ TIOCB1/ TCLKC 5/PO13/ TIOCB1/ TCLKC 5/PO13/ TIOCB1/ TCLKC 5/PO13/ TIOCB1/ TCLKC 5/PO13/ TIOCB1/ TCLKC 108 118 P1 4/PO12/ TIOCA1 P14/PO12/ TIOCA1 P14/PO12/ TIOCA1 P14/PO12/ TIOCA1 P14/PO12/ TIOCA1 P14/PO12/ TIOCA1 P14/PO12/ TIOCA1 109 119 P1 3/PO11/ TIOCD0/ TCLKB 3/PO11/ TIOCD0/ TCLKB 3/PO11/ TIOCD0/ TCLKB 3/PO11/ TIOCD0/ TCLKB 3/PO11/ TIOCD0/ TCLKB 3/PO11/ TIOCD0/ TCLKB 3/PO11/ TIOCD0/ TCLKB 110 120 P1 2/PO10/ TIOCC0/ TCLKA 2/PO10/ TIOCC0/ TCLKA 2/PO10/ TIOCC0/ TCLKA 2/PO10/ TIOCC0/ TCLKA 2/PO10/ TIOCC0/ TCLKA 2/PO10/ TIOCC0/ TCLKA 2/PO10/ TIOCC0/ TCLKA 111 121 P1 1/PO9/ TIOCB0/ DACK1 1/PO9/ TIOCB0/ DACK1 1/PO9/ TIOCB0/ DACK1 1/PO9/ TIOCB0/ DACK1 1/PO9/ TIOCB0/ DACK1 1/PO9/ TIOCB0/ DACK1 1/PO9/ TIOCB0/ DACK1 112 122 P1 0/PO8/ TIOCA0/ DACK0 0/PO8/ TIOCA0/ DACK0 0/PO8/ TIOCA0/ DACK0 0/PO8/ TIOCA0/ DACK0 0/PO8/ TIOCA0/ DACK0 0/PO8/ TIOCA0/ DACK0 0/PO8/ TIOCA0/ DACK0 113 123 MD 0 MD 0 MD 0 MD 0 MD 0 MD 0 MD 0 114 124 MD 1 MD 1 MD 1 MD 1 MD 1 MD 1 MD 1 115 125 MD 2 MD 2 MD 2 MD 2 MD 2 MD 2 MD 2 116 126 PG 0 PG 0 PG 0 PG 0/CAS PG 0/CAS PG 0/CAS PG 0 117 127 PG 1 PG 1 PG 1 PG 1/CS3 PG 1/CS3 PG 1/CS3 PG 1 118 128 PG 2 PG 2 PG 2 PG 2/CS2 PG 2/CS2 PG 2/CS2 PG 2 119 1 PG 3 PG 3 PG 3 PG 3/CS1 PG 3/CS1 PG 3/CS1 PG 3 120 2 PG 4/CS0 PG 4/CS0 PG 4 PG 4/CS0 PG 4/CS0 PG 4/CS0 PG 4 —3 V SS VSS VSS VSS VSS VSS VSS — 4 NC NC NC NC NC NC NC Note: NC pins should be connected to VSS or left open. * Only applies to the H8S/2351.

1.3.3 Pin Functions

Table 1-3 outlines the pin functions of the H8S/2350 Series. Table 1-3 Pin Functions Pin No. Type Symbol TFP-120 FP-128 I/O Name and Function Power V CC 1, 33, 52, 76, 5, 39, 58, 84, Input Power supply: For connection to the power supply. All V CC pins should be connected to the system power supply. VSS 6, 15, 24, 38, 47, 59, 79, 104 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 Input Ground: For connection to ground (0 V). All V SS pins should be connected to the system power supply (0 V). Clock XTAL 77 85 Input Connects to a crystal oscillator. See section 19, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. EXTAL 78 86 Input Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 19, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. ø 80 88 Output System clock: Supplies the system clock to an external device.

Table 1-3 Pin Functions (cont) Pin No. Type Symbol TFP-120 FP-128 I/O Name and Function Operating mode control MD 2 to MD 0 115 to 113 125 to 123 Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD 2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2350 Series is operating. MD2 MD1 MD0 Operating Mode 000—

1 Mode 1

1 0 Mode 2 *

1 Mode 3 *

1 Mode 5

1 0 Mode 6 *

1 Mode 7 *

Note: * Only applies to the H8S/2351. System controlRES 73 81 Input Reset input: When this pin is driven low, the chip is reset. The type of reset can be selected according to the NMI input level. At power-on, the NMI pin input level should be set high. STBY 75 83 Input Standby: When this pin is driven low, a transition is made to hardware standby mode. BREQ 88 96 Input Bus request: Used by an external bus master to issue a bus request to the H8S/2350 Series. BREQO 86 94 Output Bus request output: The external bus request signal used when an internal bus master accesses external space in the external bus-released state. BACK 87 95 Output Bus request acknowledge: Indicates that the bus has been released to an external bus master.

Table 1-3 Pin Functions (cont) Pin No. Type Symbol TFP-120 FP-128 I/O Name and Function Interrupts NMI 74 82 Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. IRQ7 to IRQ0 28 to 25, 29 to 32 32 to 29, 33, 34, 37, 38 Input Interrupt request 7 to 0: These pins request a maskable interrupt. Address bus A 23 to 28 to 25, 23 to 16, 14 to 7, 5 to 2 32 to 29, 27 to 20, 18 to 11, 9 to 6 Output Address bus: These pins output an address. Data bus D 15 to D 0 51 to 48, 46 to 39, 37 to 34 57 to 54, 52 to 45, 43 to 40 I/O Data bus: These pins constitute a bidirectional data bus. Bus control CS7 to CS0 29, 30, 61, 60, 117 to 120 33, 34, 69, 66, 127, 128, 1, 2 Output Chip select: Signals for selecting areas 7 to 0. AS 82 90 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. RD 83 91 Output Read: When this pin is low, it indicates that the external address space can be read. HWR 84 92 Output High write/write enable: A strobe signal that writes to external space and indicates that the upper half (D 15 to D8) of the data bus is enabled. The 2CAS type DRAM write enable signal. LWR 85 93 Output Low write: A strobe signal that writes to external space and indicates that the lower half (D 7 to D0) of the data bus is enabled. CAS 116 126 Output Upper column address strobe/column address strobe: The 2CAS type DRAM upper column address strobe signal.

Table 1-3 Pin Functions (cont) Pin No. Type Symbol TFP-120 FP-128 I/O Name and Function Bus control WAIT 86 94 Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. LCAS 86 94 Output Lower column address strobe: The 2- CAS type DRAM lower column address strobe signal DMA controller (DMAC) DREQ1, DREQ0 62, 60 70, 66 Input DMA request 1 and 0: These pins request DMAC activation. TEND1, TEND0 63, 61 71, 69 Output DMA transfer end 1 and 0: These pins indicate the end of DMAC data transfer. DACK1, DACK0 111, 112 121, 122 Output DMA transfer acknowledge 1 and 0: These are the DMAC single address transfer acknowledge pins. 16-bit timer- pulse unit (TPU) TCLKD to TCLKA 105, 107, 109, 110 115, 117, 119, 120 Input Clock input D to A: These pins input an external clock. TIOCA0, TIOCB0, TIOCC0, TIOCD0 112 to 109 122 to 119 I/O Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. TIOCA1, TIOCB1 108, 107 118, 117 I/O Input capture/ output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. TIOCA2, TIOCB2 106, 105 116, 115 I/O Input capture/ output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. TIOCA3, TIOCB3, TIOCC3, TIOCD3 71 to 68 79 to 76 I/O Input capture/ output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins.

Table 1-3 Pin Functions (cont) Pin No. Type Symbol TFP-120 FP-128 I/O Name and Function 16-bit timer- pulse unit (TPU) TIOCA4, TIOCB4 67, 66 75, 74 I/O Input capture/ output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. TIOCA5, TIOCB5 65, 64 73, 72 I/O Input capture/ output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. Programmable pulse generator (PPG) PO15 to PO0 105 to 112, 64 to 71 115 to 122, 72 to 79 Output Pulse output 15 to 0: Pulse output pins. Watchdog timer (WDT) WDTOVF 72 80 Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. Serial communication TxD1, TxD0 54, 53 60, 59 Output Transmit data (channel 0, 1): Data output pins. interface (SCI) Smart Card RxD1, RxD0 56, 55 62, 61 Input Receive data (channel 0, 1): Data input pins. interface SCK1, SCK0 58, 57 64, 63 I/O Serial clock (channel 0, 1): Clock I/O pins. A/D converter AN7 to AN0 102 to 112 to 105 Input Analog 7 to 0: Analog input pins. ADTRG 92 102 Input A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. D/A converter DA1, DA0 102, 101 112, 111 Output Analog output: D/A converter analog output pins.

Table 1-3 Pin Functions (cont) Pin No. Type Symbol TFP-120 FP-128 I/O Name and Function A/D converter and D/A converter AV CC 93 103 Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). AV SS 103 113 Input This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). Vref 94 104 Input This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). I/O ports P1 7 to P10 105 to 112 115 to 122 I/O Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). P27 to P20 64 to 71 72 to 79 I/O Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). P35 to P30 58 to 53 64 to 59 I/O Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). P47 to P40 102 to 112 to 105 Input Port 4: An 8-bit input port. P53 to P50 92 to 89 102, 101, 98, 97 I/O Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR).

Table 1-3 Pin Functions (cont) Pin No. Type Symbol TFP-120 FP-128 I/O Name and Function I/O ports P6 7 to P60 29 to 32, 63 to 60 33, 34, 37, 38, 71 to 69, I/O Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR). PA 7 to PA 0 28 to 25, 23 to 20 32 to 29, 27 to 24 I/O Port A: An 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). PB 7 to PB 0 19 to 16, 14 to 11 23 to 20, 18 to 15 I/O Port B *: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). PC 7 to PC 0 10 to 7, 5 to 2 14 to 11, 9 to 6 I/O Port C *: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). PD 7 to PD 0 51 to 48, 46 to 43 57 to 54, 52 to 49 I/O Port D *: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). PE 7 to PE 0 42 to 39, 37 to 34 48 to 45, 43 to 40 I/O Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). PF 7 to PF 0 80, 82 to 88 88, 90 to 96 I/O Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). PG 4 to PG 0 120 to 116 2, 1, 128 to 126 I/O Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). Note: * Only applies to the H8S/2351.

2.1 Overview

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.

2.1.1 Features

The H8S/2000 CPU has the following features.

Upward-compatible with H8/300 and H8/300H CPUs ¾ Can execute H8/300 and H8/300H object programs
General-register architecture ¾ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
Sixty-five basic instructions ¾ 8/16/32-bit arithmetic and logic instructions ¾ Multiply and divide instructions ¾ Powerful bit-manipulation instructions
Eight addressing modes ¾ Register direct [Rn] ¾ Register indirect [@ERn] ¾ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] ¾ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] ¾ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ¾ Immediate [#xx:8, #xx:16, or #xx:32] ¾ Program-counter relative [@(d:8,PC) or @(d:16,PC)] ¾ Memory indirect [@@aa:8]
16-Mbyte address space ¾ Program: 16 Mbytes ¾ Data: 16 Mbytes (4 Gbytes architecturally)

High-speed operation ¾ All frequently-used instructions execute in one or two states ¾ Maximum clock rate : 20 MHz ¾ 8/16/32-bit register-register add/subtract : 50 ns ¾ 8 · 8-bit register-register multiply : 600 ns ¾ 16 ÷ 8-bit register-register divide : 600 ns ¾ 16 · 16-bit register-register multiply : 1000 ns ¾ 32 ÷ 16-bit register-register divide : 1000 ns
Two CPU operating modes ¾ Normal mode ¾ Advanced mode
Power-down state ¾ Transition to power-down state by SLEEP instruction ¾ CPU clock speed selection

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

Register configuration The MAC register is supported only by the H8S/2600 CPU.
Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU.
Number of execution states The number of exection states of the MULXU and MULXS instructions. Internal Operation Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 There are also differences in the address space, CCR and EXR functions, power-down state, etc., depending on the product.

2.1.3 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

More general registers and control registers ¾ Eight 16-bit expanded registers, and one 8-bit control register, have been added.
Expanded address space ¾ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ¾ Advanced mode supports a maximum 16-Mbyte address space.
Enhanced addressing ¾ The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Enhanced instructions ¾ Addressing modes of bit-manipulation instructions have been enhanced. ¾ Signed multiply and divide instructions have been added. ¾ Two-bit shift instructions have been added. ¾ Instructions for saving and restoring multiple registers have been added. ¾ A test and set instruction has been added.
Higher speed ¾ Basic instructions execute twice as fast.

2.1.4 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

Additional control register ¾ One 8-bit control register has been added.
Enhanced instructions ¾ Addressing modes of bit-manipulation instructions have been enhanced. ¾ Two-bit shift instructions have been added. ¾ Instructions for saving and restoring multiple registers have been added. ¾ A test and set instruction has been added.
Higher speed ¾ Basic instructions execute twice as fast.

2.2 CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. CPU operating modes Normal mode Advanced mode Maximum 64 kbytes, program and data areas combined Maximum 16-Mbytes for program and data areas combined Figure 2-1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.

Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2-2. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector Exception vector 1 Exception vector 2 Exception vector table (Reserved for system use) Figure 2-2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.

Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. (a) Subroutine Branch (b) Exception Handling PC (16 bits) EXR *1 Reserved*1,*3 CCR CCR *3 PC (16 bits) SP SP Notes: 1. When EXR is not used it is not stored on the stack. SP when EXR is not used. Ignored when returning. (SP ) Figure 2-3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used.

Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 H'00000003 H'00000004 H'0000000B H'0000000C Exception vector table Reserved Power-on reset exception vector (Reserved for system use) Reserved Exception vector 1 Reserved Manual reset exception vector H'00000010 H'00000008 H'00000007 Figure 2-4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table.

Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. (a) Subroutine Branch (b) Exception Handling PC (24 bits) EXR *1 Reserved*1,*3 CCR PC (24 bits) SP SP Notes: 1. When EXR is not used it is not stored on the stack. SP when EXR is not used. Ignored when returning. (SP ) *2Reserved Figure 2-5 Stack Structure in Advanced Mode

2.3 Address Space

Figure 2-6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. (b) Advanced Mode H'0000 H'FFFF H'00000000 H'FFFFFFFF H'00FFFFFF (a) Normal Mode Data area Program area Cannot be used by the H8S/2350 Series Figure 2-6 Memory Map

2.4 Register Configuration

2.4.1 Overview

The CPU has the internal registers shown in figure 2-7. There are two types of registers: general registers and control registers. T ———— I2 I1 I0EXR 76543210 PC 23 0 15 07 07 0 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General Registers (Rn) and Extended Registers (En) Control Registers (CR) Legend Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* SP: PC: EXR: I2 to I0: CCR: UI: Note: * In the H8S/2350 Series, this bit cannot be used as an interrupt mask. ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) I UIHUNZVCCCR 76543210 Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Figure 2-7 CPU Registers

2.4.2 General Registers

The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-8 illustrates the usage of the general registers. The usage of each register can be selected independently.

Address registers
32-bit registers • 16-bit registers • 8-bit registers ER registers (ER0 to ER7) E registers (extended registers) (E0 to E7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2-8 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area Stack area SP (ER7) Figure 2-9 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1.

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception- handling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2350 Series, this bit cannot be used as an interrupt mask bit. instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.

2.4.4 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.

2.5 Data Formats

The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2-10 shows the data formats in general registers.

76543210 Don’t care

Don’t care 76543210 4370 Don’t careUpper Lower LSB MSB LSB Data Type Register Number Data Format 1-bit data 1-bit data 4-bit BCD data 4-bit BCD data Byte data Byte data RnH RnL RnH RnL RnH RnL MSB Don’t care Upper Lower 4370 Don’t care Don’t care Figure 2-10 General Register Data Formats

ERn: En: Rn: RnH: RnL: MSB: LSB: MSB LSB Longword data ERn Data Type Register Number Data Format Figure 2-10 General Register Data Formats (cont)

2.5.2 Memory Data Formats

Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. 76543210 MSB LSB MSB LSB MSB LSB Data Type Data Format 1-bit data Byte data Word data Longword data Address Address L Address L Address 2M Address 2M + 1 Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2-11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size.

2.6 Instruction Set

2.6.1 Overview

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Size Types Data transfer MOV BWL 5 POP *1, PUSH*1 WL LDM, STM L MOVFPE, MOVTPE *3 B Arithmetic ADD, SUB, CMP, NEG BWL 19 operations ADDX, SUBX, DAA, DAS B INC, DEC BWL ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS BW EXTU, EXTS WL TAS B Logic operations AND, OR, XOR, NOT BWL 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8 Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B1 4 Branch Bcc *2, JMP, BSR, JSR, RTS — 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9 Block data transfer EEPMOV — 1 Notes: B-byte size; W-word size; L-longword size. @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2350 Series.

2.6.2 Instructions and Addressing Modes

Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes Addressing Modes Function Data transfer Arithmetic operations Instruction MOV BWL BWL BWL BWL BWL BWL B BWL — BWL — — — — Note: * Cannot be used in the H8S/2350 Series. MOVTPE * DIVXU DIVXS #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8

Table 2-2 Combinations of Instructions and Addressing Modes (Cont) Addressing Modes Function Logic operations System control Block data transfer Shift Bit manipulation Branch Instruction XOR ORC, XORC Legend B: Byte W: Word L: Longword #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8

2.6.3 Table of Instructions Classified by Function

Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd General register (destination) * Rs General register (source) * Rn General register * ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction

Multiplication ÷ Division Ù Logical AND Ú Logical OR ¯ Logical exclusive OR ﬁ Move ¬ NOT (logical complement) Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Table 2-3 Instructions Classified by Function Type Instruction Size * Function Data transfer MOV B/W/L (EAs) ﬁ Rd, Rs ﬁ (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2350 Series. MOVTPE B Cannot be used in the H8S/2350 Series. POP W/L @SP+ ﬁ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn ﬁ @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. LDM L @SP+ ﬁ Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) ﬁ @–SP Pushes two or more general registers onto the stack. Note: * Size refers to the operand size. B: Byte W: Word L: Longword

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function Arithmetic operations ADD SUB B/W/L Rd ± Rs ﬁ Rd, Rd ± #IMM ﬁ Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) ADDX SUBX B Rd ± Rs ± C ﬁ Rd, Rd ± #IMM ± C ﬁ Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. INC DEC B/W/L Rd ± 1 ﬁ Rd, Rd ± 2 ﬁ Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd ± 1 ﬁ Rd, Rd ± 2 ﬁ Rd, Rd ± 4 ﬁ Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. DAA DAS B Rd decimal adjust ﬁ Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd · Rs ﬁ Rd Performs unsigned multiplication on data in two general registers: either 8 bits · 8 bits ﬁ 16 bits or 16 bits · 16 bits ﬁ 32 bits. MULXS B/W Rd · Rs ﬁ Rd Performs signed multiplication on data in two general registers: either 8 bits · 8 bits ﬁ 16 bits or 16 bits · 16 bits ﬁ 32 bits. DIVXU B/W Rd ÷ Rs ﬁ Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits ﬁ 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits ﬁ 16-bit quotient and 16- bit remainder. Note: * Size refers to the operand size. B: Byte W: Word L: Longword

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function Arithmetic operations DIVXS B/W Rd ÷ Rs ﬁ Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits ﬁ 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits ﬁ 16-bit quotient and 16- bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 – Rd ﬁ Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) ﬁ Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) ﬁ Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS B @ERd – 0, 1 ﬁ (<bit 7> of @Erd) Tests memory contents, and sets the most significant bit (bit 7) to 1. Note: * Size refers to the operand size. B: Byte W: Word L: Longword

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function Logic operations AND B/W/L Rd Ù Rs ﬁ Rd, Rd Ù #IMM ﬁ Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Ú Rs ﬁ Rd, Rd Ú #IMM ﬁ Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ¯ Rs ﬁ Rd, Rd ¯ #IMM ﬁ Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ¬ (Rd) ﬁ (Rd) Takes the one's complement of general register contents. Shift operations SHAL SHAR B/W/L Rd (shift) ﬁ Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. SHLL SHLR B/W/L Rd (shift) ﬁ Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. ROTL ROTR B/W/L Rd (rotate) ﬁ Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. ROTXL ROTXR B/W/L Rd (rotate) ﬁ Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. Note: * Size refers to the operand size. B: Byte W: Word L: Longword

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function Bit- manipulation instructions BSET B 1 ﬁ (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 ﬁ (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (<bit-No.> of <EAd>) ﬁ (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ¬ (<bit-No.> of <EAd>) ﬁ Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND BIAND B B C Ù (<bit-No.> of <EAd>) ﬁ C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C Ù ¬ (<bit-No.> of <EAd>) ﬁ C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR BIOR B B C Ú (<bit-No.> of <EAd>) ﬁ C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C Ú ¬ (<bit-No.> of <EAd>) ﬁ C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function Bit- manipulation instructions BXOR BIXOR B B C ¯ (<bit-No.> of <EAd>) ﬁ C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ¯ ¬ (<bit-No.> of <EAd>) ﬁ C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD BILD B B (<bit-No.> of <EAd>) ﬁ C Transfers a specified bit in a general register or memory operand to the carry flag. ¬ (<bit-No.> of <EAd>) ﬁ C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST BIST B B C ﬁ (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. ¬ C ﬁ (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High C Ú Z = 0 BLS Low or same C Ú Z = 1 BCC(BHS) Carry clear C = 0 (high or same) BCS(BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ¯ V = 0 BLT Less than N ¯ V = 1 BGT Greater than Z Ú(N ¯ V) = 0 BLE Less or equal Z Ú(N ¯ V) = 1 JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function System control TRAPA — Starts trap-instruction exception handling. instructions RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) ﬁ CCR, (EAs) ﬁ EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR ﬁ (EAd), EXR ﬁ (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR Ù #IMM ﬁ CCR, EXR Ù #IMM ﬁ EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR Ú #IMM ﬁ CCR, EXR Ú #IMM ﬁ EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ¯ #IMM ﬁ CCR, EXR ¯ #IMM ﬁ EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 ﬁ PC Only increments the program counter. Note: * Size refers to the operand size. B: Byte W: Word

Table 2-3 Instructions Classified by Function (cont) Type Instruction Size * Function Block data transfer instruction EEPMOV.B EEPMOV.W if R4L „ 0 then Repeat @ER5+ ﬁ @ER6+ R4L–1 ﬁ R4L Until R4L = 0 else next; if R4 „ 0 then Repeat @ER5+ ﬁ @ER6+ R4–1 ﬁ R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed.

2.6.4 Basic Instruction Formats

The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2-12 shows examples of instruction formats. op op rn rm NOP, RTS, etc. ADD.B Rn, Rm, etc. MOV.B @(d:16, Rn), Rm, etc. (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension rn rmop EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2-12 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions.

2.7 Addressing Modes and Effective Address Calculation

2.7.1 Addressing Mode

The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2-4 Addressing Modes No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

(1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added.

(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:

Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even.
Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2-5 indicates the accessible absolute address ranges. Table 2-5 Absolute Address Access Ranges Absolute Address Normal Mode Advanced Mode Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction address 24 bits (@aa:24)

(6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. (a) Normal Mode (b) Advanced Mode Branch addressSpecified by @aa:8 Specified by @aa:8 Reserved Branch address Figure 2-13 Branch Address Specification in Memory Indirect Mode

If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.)

2.7.2 Effective Address Calculation

Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Register indirect with post-increment @ERn+ No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1 Register direct (Rn)

op rm rn Operand is general register contents. Register indirect (@ERn)2 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn)

Register indirect with pre-decrement @–ERn General register contents General register contents Sign extension disp General register contents 1, 2, or 4 General register contents 1, 2, or 4 Byte Word Longword Operand Size Value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r rop op r rop disp 24 23 Don’t care 24 23 Don’t care 24 23 Don’t care 24 23 Don’t care Table 2-6 Effective Address Calculation

@aa:8 Absolute address @aa:16 @aa:32 Operand is immediate data. No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs absop op abs op IMM H'FFFF Don’t care 24 23 Don’t care 24 23 Don’t care 24 23 Don’t care Sign extension Table 2-6 Effective Address Calculation (cont)

7 Program-counter relative

@(d:8, PC)/@(d:16, PC)

Normal mode
Advanced mode No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) 31 8 7 015 031 8 7 disp H'000000 absH'000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs Sign extension PC contents abs Memory contents Memory contents H'00 Don’t care 24 23 Don’t care Don’t care Table 2-6 Effective Address Calculation (cont)

2.8 Processing States

2.8.1 Overview

The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Power-down state CPU operation is stopped to conserve power.* Sleep mode Software standby mode Hardware standby mode Processing states Note: * The power-down state also includes a medium-speed mode, module stop mode etc. Figure 2-14 Processing States

External interrupt Software standby mode RES = high Reset state STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. From an y state, a transition to hardware standby mode occurs when STBY goes low. SLEEP instruction with SSBY = 0SLEEP instruction with SSBY = 1 Interrupt request End of bus request Bus request Request for exception handling End of exception handling Figure 2-15 State Transitions

2.8.2 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12, Watchdog Timer.

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2-7 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Trace End of instruction execution or end of exception-handling sequence* When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence Interrupt End of instruction execution or end of exception-handling sequence* When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Low Trap instruction When TRAPA instruction is executed Exception handling starts when a trap (TRAPA) instruction is executed* Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state.

(2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exception- handling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2-16 shows the stack after exception handling ends.

(c) Interrupt control mode 0 (d) Interrupt control mode 2 CCR PC (24 bits) SP Note:*Ignored when returning. CCR PC (24 bits) SP EXR Reserved* (a) Interrupt control mode 0 (b) Interrupt control mode 2 CCR CCR * PC (16 bits) SP CCR CCR * PC (16 bits) SP EXR Reserved* Normal mode Advanced mode Figure 2-16 Stack Structure after Exception Handling (Examples)

2.8.4 Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5 Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts. There is one other bus master in addition to the CPU: the data transfer controller (DTC). For further details, refer to section 6, Bus Controller.

2.8.6 Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 20, Power-Down State. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained.

2.9 Basic Timing

2.9.1 Overview

The CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space.

2.9.2 On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2-17 shows the on-chip memory access cycle. Figure 2-18 shows the pin states. Internal address bus Internal read signal Internal data bus Internal write signal Internal data bus ø Bus cycle Address Read data Write data Read access Write access Figure 2-17 On-Chip Memory Access Cycle

HWR, LWR Data bus ø High High High High-impedance state Figure 2-18 Pin States during On-Chip Memory Access

2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access timing for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle T1 T2 Address Read data Write data Internal read signal Internal data bus Internal write signal Internal data bus Read access Write access Internal address bus ø Figure 2-19 On-Chip Supporting Module Access Cycle

HWR, LWR Data bus ø High High High High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access

2.9.4 External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller.

Section 3 MCU Operating Modes

3.1 Overview

3.1.1 H8S/2350 Operating Mode Selection

The H8S/2350 has three operating modes (modes 1, 4, and 5). These modes are determined by the mode pin (MD2 to MD0) settings. The CPU operating mode and initial bus width can be selected as shown in table 3-1. Table 3-1 lists the MCU operating modes. Table 3-1 MCU Operating Mode Selection (H8S/2350) MCU CPU External Data Bus Operating Mode MD 2 MD 1 MD 0 Operating Mode Description On-Chip ROM Initial Width Max. Width 0 000— — — — 1 1 Normal On-chip ROM disabled, expanded mode Disabled 8 bits 16 bits 4 1 0 0 Advanced On-chip ROM disabled, Disabled 16 bits 16 bits 51 expanded mode 8 bits 16 bits The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2350 actually accesses a maximum of 16 Mbytes. Modes 1, 4, and 5 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode.

The H8S/2350 can be used only in modes 1, 4, and 5. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation.

3.1.2 H8S/2351 Operating Mode Selection

The H8S/2351 has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD 2 to MD0). Table 3-2 lists the MCU operating modes. Table 3-2 MCU Operating Mode Selection (H8S/2351) MCU CPU External Data Bus Operating Mode MD 2 MD 1 MD 0 Operating Mode Description On-Chip ROM Initial Width Max. Width 0 000— — — — 1 1 Normal On-chip ROM disabled, expanded mode Disabled 8 bits 16 bits 2 1 0 On-chip ROM enabled, expanded mode Enabled 8 bits 16 bits 3 1 Single-chip mode — 4 1 0 0 Advanced On-chip ROM disabled, Disabled 16 bits 16 bits 51 expanded mode 8 bits 16 bits 6 1 0 On-chip ROM enabled, expanded mode Enabled 8 bits 16 bits 7 1 Single-chip mode — The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2351 actually accesses a maximum of 16 Mbytes. Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode.

The H8S/2351 can be used only in modes 1 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation.

3.1.3 Register Configuration

The H8S/2350 Series has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2350 Series. Table 3-3 summarizes these registers. Table 3-3 MCU Registers Name Abbreviation R/W Initial Value Address * Mode control register MDCR R Undetermined H'FF3B System control register SYSCR R/W H'01 H'FF39 Note: * Lower 16 bits of the address.

3.2 Register Descriptions

3.2.1 Mode Control Register (MDCR)

— * R MDS2 — * R MDS1 — * R Note: * Determined by pins MD2 to MD0. Bit Initial value R/W MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2350 Series. Bit 7—Reserved: Read-only bit, always read as 1. Bits 6 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD 2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits, they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset.

3.2.2 System Control Register (SYSCR)

Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: Read-only bit, always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 Bit 4 INTM0 Interrupt Control Mode Description 0 0 0 Control of interrupts by I bit (Initial value) 1 — Setting prohibited 1 0 2 Control of interrupts by I2 to I0 bits and IPR 1 — Setting prohibited Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description

0 An interrupt is requested at the falling edge of NMI input (Initial value)

1 An interrupt is requested at the rising edge of NMI input

Bit 2—Reserved: Read-only bit, always read as 0. Bit 1—Reserved: Only 0 should be written to this bit. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

3.3 Operating Mode Descriptions

3.3.1 Mode 1

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus.

3.3.2 Mode 2 (H8S/2351 Only)

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and 8-bit bus mode is set. immediately after a reset. Ports B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. The amount of on-chip ROM that can be used is limited to 56 kbytes.

3.3.3 Mode 3 (H8S/2351 Only)

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. The amount of on-chip ROM that can be used is limited to 56 kbytes.

3.3.4 Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.

3.3.5 Mode 5

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, port D function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus.

3.3.6 Mode 6 (H8S/2351 Only)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16 bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus.

3.3.7 Mode 7 (H8S/2351 Only)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports.

3.4 Pin Functions in Each Operating Mode

The pin functions of ports A to F vary depending on the operating mode. Table 3-4 shows their functions in each operating mode. Table 3-4 Pin Functions in Each Mode Port Mode 1 Mode 2 *2 Mode 3*2 Mode 4 Mode 5 Mode 6 *2 Mode 7*2 Port A PA 7 to PA5 PPPP *1/A P *1/A P *1/A P PA 4 to PA0 AA Port B A P *1/ A PAAP *1/A P Port C A P *1/ A PAAP *1/A P Port D D D P DDDP Port E P *1/D P *1/D P P/D *1 P*1/D P *1/D P Port F PF 7 P/C*1 P/C*1 P*1/C P/C *1 P/C*1 P/C*1 P*1/C PF 6 to PF3 CCPCCCP PF 2 to PF0 P*1/C P *1/C P *1/C P *1/C P *1/C Legend P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *1: After reset *2: Only applies to the H8S/2351

3.5 Memory Map in Each Operating Mode

Figure 3-1 shows a memory map for each of the operating modes. The address space is 64 kbytes in modes 1 to 3 (normal modes), and 16 Mbytes in modes 4 to 7 (advanced modes). The H8S/2351’s on-chip ROM contains 64 kbytes, but only 56 kbytes are available in modes 2 and 3 (normal modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 6, Bus Controller.

(normal expanded mode with on-chip ROM disabled) Mode 2*1 (normal expanded mode with on-chip ROM enabled) Mode 3*1 (normal single-chip mode) External address space On-chip ROM On-chip RAM*2 Notes: 1. Modes 2 and 3 only apply to the H8S/2351. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Internal I/O registers On-chip ROM External address space External address space On-chip RAM*2 On-chip RAM Internal I/O registers Internal I/O registers Internal I/O registersInternal I/O registers External address space External address space Internal I/O registers External address space H'0000 H'0000 H'0000 H'DFFF H'E000 H'F400 H'FC00 H'FFFF H'F400 H'FC00 H'FFFF H'F400 H'FBFF H'FFFF H'FE40 H'FE40 H'FF08 H'FF08 H'FE40 H'FF07 H'FF28 H'FF28 H'FF28 Figure 3-1 Memory Map in Each Operating Mode

(advanced expanded modes with on-chip ROM disabled) Mode 6*1 (advanced expanded mode with on-chip ROM enabled) Mode 7*1 (advanced single-chip mode) External address space On-chip ROM On-chip RAM*2 Notes: Internal I/O registers On-chip ROM External address space On-chip RAM*2 On-chip RAM Internal I/O registers Internal I/O registers Internal I/O registersInternal I/O registers External address space External address space Internal I/O registers External address space H'000000 H'000000 H'000000 H'FFF400 H'FFFC00 H'FFFFFF H'FFF400 H'FFFC00 H'FFFFFF H'FFF400 H'FFFBFF H'FFFFFF H'FFFF08 H'FFFF08 H'FFFE40 H'FFFF07 H'FFFF28 H'FFFF28 H'FFFF28 External address space H'FFFE40 H'FFFE40 H'010000 H'00FFFF Modes 6 and 7 only apply to the H8S/2351. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-1 Memory Map in Each Operating Mode (cont)

Section 4 Exception Handling

4.1 Overview

4.1.1 Exception Handling Types and Priority

As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4-1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. Trace*1 Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Interrupt Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued*2 Low Trap instruction (TRAPA) *3 Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state.

4.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out.

4.1.3 Exception Vector Table

The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. Exception sources Reset Trace Interrupts Trap instruction Power-on reset Manual reset External interrupts: NMI, IRQ7 to IRQ0 Internal interrupts: 42 interrupt sources in on-chip supporting modules Figure 4-1 Exception Sources In modes 6 and 7 in the H8S/2351, the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses.

Table 4-2 Exception Vector Table Vector Address*1 Exception Source Vector Number Normal Mode Advanced Mode Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003 Manual reset 1 H'0002 to H'0003 H'0004 to H'0007 Reserved for system use 2 H'0004 to H'0006 H'0008 to H'000B

3 H'0006 to H'0007 H'000C to H'000F

4 H'0008 to H'0009 H'0010 to H'0013

Trace 5 H'000A to H'000B H'0014 to H'0017 Reserved for system use 6 H'000C to H'000D H'0018 to H'001B External interrupt NMI 7 H'000E to H'000F H'001C to H'001F Trap instruction (4 sources) 8 H'0010 to H'0011 H'0020 to H'0023

9 H'0012 to H'0013 H'0024 to H'0027

10 H'0014 to H'0015 H'0028 to H'002B

11 H'0016 to H'0017 H'002C to H'002F

Reserved for system use 12 H'0018 to H'0019 H'0030 to H'0033

13 H'001A to H'001B H'0034 to H'0037

14 H'001C to H'001D H'0038 to H'003B

15 H'001E to H'001F H'003C to H'003F

External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043 IRQ1 17 H'0022 to H'0023 H'0044 to H'0047 IRQ2 18 H'0024 to H'0025 H'0048 to H'004B IRQ3 19 H'0026 to H'0027 H'004C to H'004F IRQ4 20 H'0028 to H'0029 H'0050 to H'0053 IRQ5 21 H'002A to H'002B H'0054 to H'0057 IRQ6 22 H'002C to H'002D H'0058 to H'005B IRQ7 23 H'002E to H'002F H'005C to H'005F Internal interrupt*2 24 ç H'0030 to H'0031 ç H'00B6 to H'00B7 H'0060 to H'0063 ç H'016C to H'016F Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table.

4.2 Reset

4.2.1 Overview

A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2350 Series enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The level of the NMI pin at reset determines whether the type of reset is a power-on reset or a manual reset. The H8S/2350 Series can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer.

4.2.2 Reset Types

A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in table 4-3. A power-on reset should be used when powering on. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4-3 Reset Types Reset Transition Conditions Internal State Type NMI RES CPU On-Chip Supporting Modules Power-on reset High Low Initialized Initialized Manual reset Low Low Initialized Initialized, except for bus controller and I/O ports A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset.

4.2.3 Reset Sequence

The H8S/2350 Series enters the reset state when the RES pin goes low. To ensure that the H8S/2350 Series is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2350 Series during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the H8S/2350 Series starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4-2 and 4-3 show examples of the reset sequence. Internal address bus Internal read signal Internal write signal Internal data bus (1) (3) Vector fetch Internal processing Prefetch of first program instruction High (1) Reset exception handling vector address ((1) = H'0000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First program instruction (2) (4) ø RES Figure 4-2 Reset Sequence (Modes 2 and 3)

(1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction ø RES (1) (5) High (2) (4) (3) (6) RD HWR, LWR D 15 to D0 Note: * 3 program wait states are inserted. Figure 4-3 Reset Sequence (Mode 4)

4.2.4 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP).

4.2.5 State of On-Chip Supporting Modules after Reset Release

After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC and DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited.

4.3 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4-4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4-4 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 Trace exception handling cannot be used. 2 1 ——0 Legend 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution.

4.4 Interrupts

Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 42 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. Interrupts External interrupts Internal interrupts NMI (1) IRQ7 to IRQ0 (8) WDT *1 (1) Refresh timer*2 (1) TPU (26) SCI (8) DTC (1) DMAC (4) A/D converter (1) Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. When the refresh timer is used as an interval timer, it generates an interrupt request at each compare match. Notes: Figure 4-4 Interrupt Sources and Number of Interrupts

4.5 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4-5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4-5 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 ——— 2 1 ——0 Legend 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution.

4.6 Stack Status after Exception Handling

Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR * PC (16 bits) CCR CCR * PC (16 bits) Reserved* EXR (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes) SP SP CCR PC (24bits) CCR PC (24bits) Reserved* EXR (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4-5 (2) Stack Status after Exception Handling (Advanced Modes)

4.7 Notes on Use of the Stack

When accessing word data or longword data, the H8S/2350 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what happens when the SP value is odd. SP Legend Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. SP SP CCR PC R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF MOV.B R1L, @–ER7 SP set to H'FFFEFF TRAP instruction executed Data saved above SP Contents of CCR lost CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Figure 4-6 Operation when SP Value is Odd

Section 5 Interrupt Controller

5.1 Overview

5.1.1 Features

The H8S/2350 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features:

Two interrupt control modes ¾ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
Priorities settable with IPR ¾ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. ¾ NMI is assigned the highest priority level of 8, and can be accepted at all times.
Independent vector addresses ¾ All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine.
Nine external interrupts ¾ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. ¾ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0.
DTC and DMAC control ¾ DTC and DMAC activation is performed by means of interrupts.

5.1.2 Block Diagram

A block diagram of the interrupt controller is shown in Figure 5-1. SYSCR NMI input IRQ input Internal interrupt request WOVI to TEI INTM1 INTM0 NMIEG NMI input unit IRQ input unit ISR ISCR IER IPR Interrupt controller Priority determination Interrupt request Vector number I, UI I2 to I0 CCR EXR CPU ISCR IER ISR IPR SYSCR : IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register Legend Figure 5-1 Block Diagram of Interrupt Controller

5.1.3 Pin Configuration

Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 7 to 0 IRQ7 to IRQ0 Input Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected

5.1.4 Register Configuration

Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers Name Abbreviation R/W Initial Value Address *1 System control register SYSCR R/W H'01 H'FF39 IRQ sense control register H ISCRH R/W H'00 H'FF2C IRQ sense control register L ISCRL R/W H'00 H'FF2D IRQ enable register IER R/W H'00 H'FF2E IRQ status register ISR R/(W) *2 H'00 H'FF2F Interrupt priority register A IPRA R/W H'77 H'FEC4 Interrupt priority register B IPRB R/W H'77 H'FEC5 Interrupt priority register C IPRC R/W H'77 H'FEC6 Interrupt priority register D IPRD R/W H'77 H'FEC7 Interrupt priority register E IPRE R/W H'77 H'FEC8 Interrupt priority register F IPRF R/W H'77 H'FEC9 Interrupt priority register G IPRG R/W H'77 H'FECA Interrupt priority register H IPRH R/W H'77 H'FECB Interrupt priority register I IPRI R/W H'77 H'FECC Interrupt priority register J IPRJ R/W H'77 H'FECD Interrupt priority register K IPRK R/W H'77 H'FECE Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 Bit 4 INTM0 Interrupt Control Mode Description 0 0 0 Interrupts are controlled by I bit (Initial value) 1 — Setting prohibited 1 0 2 Interrupts are controlled by bits I2 to I0, and IPR 1 — Setting prohibited Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG Description

0 Interrupt request generated at falling edge of NMI input (Initial value)

1 Interrupt request generated at rising edge of NMI input

5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)

The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5-3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3—Reserved: Read-only bits, always read as 0. Table 5-3 Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ2 IRQ3 IRQ4 IRQ5 IPRC IRQ6 IRQ7 DTC IPRD Watchdog timer Refresh timer IPRE — * A/D converter IPRF TPU channel 0 TPU channel 1 IPRG TPU channel 2 TPU channel 3 IPRH TPU channel 4 TPU channel 5 IPRI — * — * IPRJ DMAC SCI channel 0 IPRK SCI channel 1 — * Note: * Reserved bits. These bits cannot be modified and are always read as 1.

As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU.

5.2.3 IRQ Enable Register (IER)

IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IRQ7E R/W IRQ6E R/W IRQ5E R/W IRQ4E R/W IRQ3E R/W IRQ0E R/W IRQ2E R/W IRQ1E R/W Bit Initial value R/W IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE Description

0 IRQn interrupts disabled (Initial value)

1 IRQn interrupts enabled

(n = 7 to 0)

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB IRQ7SCA to IRQ0SCA Description 0 0 Interrupt request generated at IRQ7 to IRQ0 input low level (initial value)

1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input

1 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input

1 Interrupt request generated at both falling and rising edges of

5.2.5 IRQ Status Register (ISR)

R/(W)* IRQ6F R/(W)* IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ0F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* Bit Initial value R/W Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF Description 0 [Clearing conditions] (Initial value)

Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high
When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 1 [Setting conditions]
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1)
When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0)
When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0)

5.3 Interrupt Sources

Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (42 sources).

5.3.1 External Interrupts

There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2350 Series from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:

Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
The interrupt priority level can be set with IPR.
The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5-2. IRQn interrupt request IRQnE IRQnF S R Q Clear signal Edge/level detection circuit IRQnSCA, IRQnSCB IRQn input Note: n: 7 to 0 Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0

Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function.

5.3.2 Internal Interrupts

There are 42 sources for internal interrupts from on-chip supporting modules.

For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller.
The interrupt priority level can be set by means of IPR.
The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. When the DMAC or DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected.

5.3.3 Interrupt Exception Handling Vector Table

Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5-4.

Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Vector Address* Interrupt Source Interrupt Source Vector Number Normal Mode Advanced Mode IPR Priority NMI External 7 H'000E H'001C High IRQ0 pin 16 H'0020 H'0040 IPRA6 to 4 IRQ1 17 H'0022 H'0044 IPRA2 to 0 IRQ2 IRQ3 H'0024 H'0026 H'0048 H'004C IPRB6 to 4 IRQ4 IRQ5 H'0028 H'002A H'0050 H'0054 IPRB2 to 0 IRQ6 IRQ7 H'002C H'002E H'0058 H'005C IPRC6 to 4 SWDTEND (software activation interrupt end) DTC 24 H'0030 H'0060 IPRC2 to 0 WOVI (interval timer) Watchdog timer

25 H'0032 H'0064 IPRD6 to 4

CMI (compare match) Refresh controller

26 H'0034 H'0068 IPRD2 to 0

Reserved — 27 H'0036 H'006C IPRE6 to 4 ADI (A/D conversion end) A/D 28 H'0038 H'0070 IPRE2 to 0 Reserved — 29 H'003A H'003C H'003E H'0074 H'0078 H'007C TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) TPU channel 0 H'0040 H'0042 H'0044 H'0046 H'0048 H'0080 H'0084 H'0088 H'008C H'0090 IPRF6 to 4 Reserved — 37 H'004A H'004C H'004E H'0094 H'0098 H'009C Low Note: * Lower 16 bits of the start address.

Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Vector Address* Interrupt Source Interrupt Source Vector Number Normal Mode Advanced Mode IPR Priority TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TPU channel 1 H'0050 H'0052 H'0054 H'0056 H'00A0 H'00A4 H'00A8 H'00AC IPRF2 to 0 High TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TPU channel 2 H'0058 H'005A H'005C H'005E H'00B0 H'00B4 H'00B8 H'00BC IPRG6 to 4 TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) TPU channel 3 H'0060 H'0062 H'0064 H'0066 H'0068 H'00C0 H'00C4 H'00C8 H'00CC H'00D0 IPRG2 to 0 Reserved — 53 H'006A H'006C H'006E H'00D4 H'00D8 H'00DC TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TPU channel 4 H'0070 H'0072 H'0074 H'0076 H'00E0 H'00E4 H'00E8 H'00EC IPRH6 to 4 TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) TPU channel 5 H'0078 H'007A H'007C H'007E H'00F0 H'00F4 H'00F8 H'00FC IPRH2 to 0 Low Note: * Lower 16 bits of the start address.

Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Vector Address* Interrupt Source Interrupt Source Vector Number Normal Mode Advanced Mode IPR Priority Reserved — 64 H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C High DEND0A (channel 0/ channel 0A transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/ channel 1A transfer end) DEND1B (channel 1B transfer end) DMAC 72 H'0090 H'0092 H'0094 H'0096 H'0120 H'0124 H'0128 H'012C IPRJ6 to 4 Reserved — 76 H'0098 H'009A H'009C H'009E H'0130 H'0134 H'0138 H'013C ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) SCI channel 0 H'00A0 H'00A2 H'00A4 H'00A6 H'0140 H'0144 H'0148 H'014C IPRJ2 to 0 ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) SCI channel 1 H'00A8 H'00AA H'00AC H'00AE H'0150 H'0154 H'0158 H'015C IPRK6 to 4 Reserved — 88 H'00B0 H'00B2 H'00B4 H'00B6 H'0160 H'0164 H'0168 H'016C IPRK2 to 0 Low Note: * Lower 16 bits of the start address.

5.4 Interrupt Operation

5.4.1 Interrupt Control Modes and Interrupt Operation

Interrupt operations in the H8S/2350 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5-5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR. Table 5-5 Interrupt Control Modes Interrupt SYSCR Priority Setting Interrupt Control Mode INTM1 INTM0 Registers Mask Bits Description 0 0 0 — I Interrupt mask control is performed by the I bit. — 1 — — Setting prohibited 2 1 0 IPR I2 to I0 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. — 1 — — Setting prohibited

Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt acceptance control 8-level mask control Default priority determination Vector number Interrupt control mode 2 IPR Interrupt source I2 to I0 Interrupt control mode 0 I Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5-6 shows the interrupts selected in each interrupt control mode. Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts

1 NMI interrupts

2 * All interrupts Legend * : Don't care

(2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt Control Mode Selected Interrupts

0 All interrupts

2 Highest-priority-level (IPR) interrupt whose priority level is greater

than the mask level (IPR > I2 to I0). (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5-8 shows operations and control signal functions in each interrupt control mode. Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Control Setting Interrupt Acceptance Control 8-Level ControlDefault Priority T Mode INTM1 INTM0 I I2 to I0 IPR Determination (Trace) 00 0 IM X — — *2 — 21 0 X — *1 IM PR T Legend : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. — : Not used. *1 : Set to 1 when interrupt is accepted. *2 : Keep the initial setting.

5.4.2 Interrupt Control Mode 0

Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.

Interrupt generated? NMI IRQ0 IRQ1 TEI2 I=0 Save PC and CCR I← 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0

5.4.3 Interrupt Control Mode 2

Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.

Interrupt generated? NMI Level 6 interrupt? Mask level 5 or below? Level 7 interrupt? Mask level 6 or below? Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt? Mask level 0 Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2

5.4.4 Interrupt Exception Handling Sequence

Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.

operationVector fetchStack Instruction prefetch Internal operation Interrupt acceptance Interrupt level determination Wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data us ø (3) (1) (2) (4) (3) (5) (7) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4 Saved PC and saved CCR Vector address Interrupt handling routine start address (vector address contents) Interrupt handling routine start address ((13) = (10) (12)) First instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) Figure 5-7 Interrupt Exception Handling

5.4.5 Interrupt Response Times

The H8S/2350 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM* and the stack area in on-chip RAM, enabling high- speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5-9 are explained in table 5-10. Note: * Only applies to the H8S/2351. Table 5-9 Interrupt Response Times Normal Mode Advanced Mode No. Execution Status INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1

1 Interrupt priority determination*1 3333

2 Number of wait states until executing

instruction ends*2 1 to 19+2·SI 1 to 19+2·S I 1 to 19+2·S I 1 to 19+2·S I

3 PC, CCR, EXR stack save 2·S K 3·SK 2·SK 3·SK

4 Vector fetch S I SI 2·SI 2·SI

5 Instruction fetch*3 2·SI 2·SI 2·SI 2·SI

6 Internal processing*4 2222

Total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 Notes: 1. Two states in case of internal interrupt. 2. Refers to MULXS and DIVXS instructions. 3. Prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device

8 Bit Bus 16 Bit Bus

Instruction fetch S I 1 4 6+2m 2 3+m Branch address read S J Stack manipulation S K Legend m : Number of wait states in an external device access.

5.5 Usage Notes

5.5.1 Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5-8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0. Internal address bus Internal write signal ø TGIEA TGFA TGI0A interrupt signal TIER0 write cycle by CPU TGI0A exception handling TIER0 address Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.

5.5.2 Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.

5.5.3 Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

5.5.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1

5.6 DTC and DMAC Activation by Interrupt

5.6.1 Overview

The DTC and DMAC can be activated by an interrupt. In this case, the following options are available:

Interrupt request to CPU
Activation request to DTC
Activation request to DMAC
Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC or DMAC, see section 8, Data Transfer Controller, and section 7, DMA Controller.

5.6.2 Block Diagram

Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller. DMAC Selection circuit DTCER DTVECR Control logic Determination of priority CPU DTC DTC activation request vector number Clear signal CPU interrupt request vector number Select signal Interrupt request Interrupt source clear signal IRQ interrupt On-chip supporting module Disable signal Clear signal Clear signal Interrupt controller I, I2 to I0 SWDTE clear signal Figure 5-9 Interrupt Control for DTC and DMAC

5.6.3 Operation

The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is to be managed by the DMAC can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt source constituting that DMAC activation source is not a DTC activation source or CPU interrupt source. For interrupt sources other than interrupts managed by the DMAC, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCEA to DTCEF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective priorities. With the DMAC, the activation source is input directly to each channel. (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCEA to DTCEF in the DTC and the DISEL bit of MRB in the DTC.

Table 5-12 Interrupt Source Selection and Clearing Control Settings DMAC DTC Interrupt Source Selection/Clearing Control DTA DTCE DISEL DMAC DTC CPU 00 * X D

10 D X

1 ** D XX Legend D : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care (4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DMAC or DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit.

6.1 Overview

The H8S/2350 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC).

6.1.1 Features

The features of the bus controller are listed below.

Manages external address space in area units ¾ In advanced mode, manages the external space as 8 areas of 2-Mbytes ¾ In normal mode, manages the external space as a single area ¾ Bus specifications can be set independently for each area ¾ DRAM/burst ROM interfaces can be set
Basic bus interface ¾ Chip select (CS0 to CS7) can be output for areas 0 to 7 ¾ 8-bit access or 16-bit access can be selected for each area ¾ 2-state access or 3-state access can be selected for each area ¾ Program wait states can be inserted for each area
DRAM interface ¾ DRAM interface can be set for areas 2 to 5 (in advanced mode) ¾ Row address/column address multiplexed output (8/9/10 bits) ¾ Two byte access methods (2-CAS) ¾ Burst operation (fast page mode) ¾ T P cycle insertion to secure RAS precharging time ¾ Choice of CAS-before-RAS refreshing or self-refreshing
Burst ROM interface ¾ Burst ROM interface can be set for area 0 ¾ Choice of 1- or 2-state burst access

Idle cycle insertion ¾ An idle cycle can be inserted in case of an external read cycle between different areas ¾ An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle
Write buffer functions ¾ External write cycle and internal access can be executed in parallel ¾ DMAC single-address mode and internal access can be executed in parallel
Bus arbitration function ¾ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
Other features ¾ Refresh counter (refresh timer) can be used as an interval timer ¾ External bus release function

6.1.2 Block Diagram

Figure 6-1 shows a block diagram of the bus controller. Area decoder Bus controller ABWCR ASTCR BCRH BCRL Internal address bus CS0 to CS7 External bus control signals BREQ BACK BREQO Internal control signals Wait controller WCRH WCRL Bus mode signal DRAM/PSRAM controller RTCNT RTCOR DRAMCR MCR Bus arbiter CPU bus request signal DTC bus request signal DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal External DRAM signals WAIT Internal data bus Figure 6-1 Block Diagram of Bus Controller

6.1.3 Pin Configuration

Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write/write enable HWR Output Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. 2-CAS DRAM write enable signal. Low write LWR Output Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Chip select 0 CS0 Output Strobe signal indicating that area 0 is selected. Chip select 1 CS1 Output Strobe signal indicating that area 1 is selected. Chip select 2/row address strobe 2 CS2 Output Strobe signal indicating that area 2 is selected. DRAM row address strobe signal when area 2 is in DRAM space. Chip select 3/row address strobe 3 CS3 Output Strobe signal indicating that area 3 is selected. DRAM row address strobe signal when area 3 is in DRAM space. Chip select 4/row address strobe 4 CS4 Output Strobe signal indicating that area 4 is selected. DRAM row address strobe signal when area 4 is in DRAM space. Chip select 5/row address strobe 5 CS5 Output Strobe signal indicating that area 5 is selected. DRAM row address strobe signal when area 5 is in DRAM space. Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected. Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected.

Table 6-1 Bus Controller Pins (cont) Name Symbol I/O Function Upper column address strobe CAS Output 2-CAS DRAM upper column address strobe signal. Lower column strobe LCAS Output DRAM lower column address strobe signal. Wait WAIT Input Wait request signal when accessing external 3-state access space. Bus request BREQ Input Request signal that releases bus to external device. Bus request acknowledge BACK Output Acknowledge signal indicating that bus has been released. Bus request output BREQO Output External bus request signal used when internal bus master accesses external space when external bus is released.

6.1.4 Register Configuration

Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Initial Value Name Abbreviation R/W Power-On Reset Manual Reset Address *1 Bus width control register ABWCR R/W H'FF/H'00 *2 Retained H'FED0 Access state control register ASTCR R/W H'FF Retained H'FED1 Wait control register H WCRH R/W H'FF Retained H'FED2 Wait control register L WCRL R/W H'FF Retained H'FED3 Bus control register H BCRH R/W H'D0 Retained H'FED4 Bus control register L BCRL R/W H'3C Retained H'FED5 Memory control register MCR R/W H'00 Retained H'FED6 DRAM control register DRAMCR R/W H'00 Retained H'FED7 Refresh timer/counter RTCNT R/W H'00 Retained H'FED8 Refresh time constant register RTCOR R/W H'FF Retained H'FED9 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode.

6.2 Register Descriptions

6.2.1 Bus Width Control Register (ABWCR)

Bit : Initial value: Modes 1 to 3, 5 to 7* Mode 4 :RW Initial value: :RW ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1, 2, 3, and 5, 6, 7*, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Note: * Modes 2, 3, 6 and 7 only apply to the H8S/2351. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode, only part of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for 8-bit access or 16-bit access . Bit n ABWn Description

0 Area n is designated for 16-bit access

1 Area n is designated for 8-bit access

(n = 7 to 0)

6.2.2 Access State Control Register (ASTCR)

ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. In normal mode, the settings of bits AST7 to AST1 have no effect on operation. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. In normal mode, only part of area 0 is enabled, and the AST0 bit selects whether external space is to be designated for 2-state access or 3-state access. Wait state insertion is enabled or disabled at the same time. Bit n ASTn Description

0 Area n is designated for 2-state access

Wait state insertion in area n external space is disabled

1 Area n is designated for 3-state access (Initial value)

Wait state insertion in area n external space is enabled (n = 7 to 0)

6.2.3 Wait Control Registers H and L (WCRH, WCRL)

WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area is 0 is enabled, and bits W01 and W00 select the number of program wait states for the external space . The settings of bits W71, W70 to W11, and W10 have no effect on operation. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. (1) WCRH W71 R/W W70 R/W W61 R/W W60 R/W W51 R/W W40 R/W W50 R/W W41 R/W Bit Initial value R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 Bit 6 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (Initial value)

Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 Bit 4 W60 Description 0 0 Program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 Bit 2 W50 Description 0 0 Program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 Bit 0 W40 Description 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (Initial value)

(2) WCRL W31 R/W W30 R/W W21 R/W W20 R/W W11 R/W W00 R/W W10 R/W W01 R/W Bit Initial value R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 Bit 6 W30 Description 0 0 Program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 Bit 4 W20 Description 0 0 Program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (Initial value)

Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 Bit 2 W10 Description 0 0 Program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 Bit 0 W00 Description 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (Initial value)

6.2.4 Bus Control Register H (BCRH)

BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description

0 Idle cycle not inserted in case of successive external read cycles in different areas

1 Idle cycle inserted in case of successive external read cycles in different areas

(Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 Description

0 Idle cycle not inserted in case of successive external read and external write cycles

1 Idle cycle inserted in case of successive external read and external write cycles

(Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode, the selection can be made from the entire external space. Bit 5 BRSTRM Description

0 Area 0 is basic bus interface (Initial value)

1 Area 0 is burst ROM interface

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description

0 Burst cycle comprises 1 state

1 Burst cycle comprises 2 states (Initial value)

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access (Initial value) 1 Max. 8 words in burst access Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as DRAM interface. Bit 2 RMTS2 Bit 1 RMTS1 Bit 0 RMTS0

Description

Area 5 Area 4 Area 3 Area 2 0 0 0 Normal space

1 Normal space DRAM space

1 0 Normal space DRAM space

1 DRAM space

1 ——— Note: When areas selected in DRAM space are all 8-bit space, the PF2 pin can be used as an I/O port, BREQO, or WAIT.

6.2.5 Bus Control Register L (BCRL)

BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the LCAS signal, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE Description 0 External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports. (Initial value) 1 External bus release is enabled. Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE Description 0 BREQO output disabled. BREQO can be used as I/O port. (Initial value) 1 BREQO output enabled. Bit 5—Reserved: Only 1 should be written to this bit. Bit 4—LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface. LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input cannot be used when LCAS signal is used.

Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface. Bit 3 DDS Description

0 When DMAC single address transfer is performed in DRAM space, full access is

DACK signal goes low from Tr or T1 cycle

1 Burst access is possible when DMAC single address transfer is performed in DRAM

DACK signal goes low from Tc1 or T2 cycle (Initial value) Bit 2—Reserved: Only 1 should be written to this bit. Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle. Bit 1 WDBE Description

0 Write data buffer function not used (Initial value)

1 Write data buffer function used

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE Description 0 Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. (Initial value)

1 Wait input by WAIT pin enabled

6.2.6 Memory Control Register (MCR)

MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5 are designated as DRAM interface. MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (T P) is to be used when areas 2 to 5 designated as DRAM space are accessed. Bit 7 TPC Description 0 1-state precharge cycle is inserted (Initial value) 1 2-state precharge cycle is inserted Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM space. DRAM space burst access is performed in fast page mode. Bit 6 BE Description

0 Burst disabled (always full access) (Initial value)

1 For DRAM space access, access in fast page mode

Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode). RAS down mode cannot be used with the 2-CAS method. When selecting RAS down mode, set the BE bit to 1. Bit 5 RCDM Description

0 DRAM interface: RAS up mode selected (Initial value)

1 DRAM interface: RAS down mode selected

Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 CW2 Description 0 16-bit DRAM space selected (Initial value) 1 8-bit DRAM space selected

Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM interface, these bits also select the row address to be used for comparison. Bit 3 MXC1 Bit 2 MXC0 Description 0 0 8-bit shift (Initial value)

When 8-bit access space is designated: Row address A23 to A8 used for comparison
When 16-bit access space is designated: Row address A23 to A9 used for comparison 1 9-bit shift
When 8-bit access space is designated: Row address A23 to A9 used for comparison
When 16-bit access space is designated: Row address A23 to A10 used for comparison 1 0 10-bit shift
When 8-bit access space is designated: Row address A23 to A10 used for comparison
When 16-bit access space is designated: Row address A23 to A11 used for comparison Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled. Bit 1 RLW1 Bit 0 RLW0 Description 0 0 No wait state inserted (Initial value) 1 1 wait state inserted 1 0 2 wait states inserted 1 3 wait states inserted

6.2.7 DRAM Control Register (DRAMCR)

DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not performed, the refresh timer can be used as an interval timer. Refresh control is not performed in normal mode. Bit 7 RFSHE Description

0 Refresh control is not performed (Initial value)

1 Refresh control is performed

Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before- RAS refreshing. Bit 6 RCW Description

0 Wait state insertion in CAS-before-RAS refreshing disabled (Initial value)

1 One wait state inserted in CAS-before-RAS refreshing

Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), this bit selects whether normal refreshing (CAS-before-RAS refreshing for the DRAM interface) or self- refreshing is performed. Bit 5 RMODE Description

0 DRAM interface

CAS-before-RAS refreshing used (Initial value)

1 Self-refreshing used

Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 CMF Description 0 [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag (Initial value) 1 [Setting condition] Set when RTCNT = RTCOR Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0. Bit 3 CMIE Description

0 Interrupt request (CMI) by CMF flag disabled (Initial value)

1 Interrupt request (CMI) by CMF flag enabled

Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 internal clocks obtained by dividing the system clock (ø). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Description 0 0 0 Count operation disabled (Initial value)

1 Count uses ø/2

1 0 Count uses ø/8

1 Count uses ø/32

1 0 0 Count uses ø/128

1 Count uses ø/512

1 0 Count uses ø/2048

1 Count uses ø/4096

6.2.8 Refresh Timer/Counter (RTCNT)

RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in DRAMCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode.

6.2.9 Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode.

6.3 Overview of Bus Control

6.3.1 Area Partitioning

In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode, it controls a 64-kbyte address space comprising part of area 0. Figure 6-2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area. Area 0 (2Mbytes) H'000000 H'FFFFFF H'0000 H'1FFFFF H'200000 Area 1 (2Mbytes) H'3FFFFF H'400000 Area 2 (2Mbytes) H'5FFFFF H'600000 Area 3 (2Mbytes) H'7FFFFF H'800000 Area 4 (2Mbytes) H'9FFFFF H'A00000 Area 5 (2Mbytes) H'BFFFFF H'C00000 Area 6 (2Mbytes) H'DFFFFF H'E00000 Area 7 (2Mbytes) H'FFFF (1) Advanced mode (2) Normal mode Figure 6-2 Overview of Area Partitioning

6.3.2 Bus Specifications

The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3- state access is selected functions as a 3-state access space. With the DRAM interface and burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6-3 shows the bus specifications for each basic bus interface area.

Table 6-3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWCR ABWn ASTCR ASTn Wn1 Wn0 Bus Width Access States Program Wait States 00— — 1 6 2 0 10 0 3 0 10 2 10— — 8 2 0 10 0 3 0 10 2

6.3.3 Memory Interfaces

The H8S/2350 Series memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space.

6.3.4 Advanced Mode

The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.4, 6.5, and 6.7) should be referred to for further details. Area 0: Area 0 includes on-chip ROM*, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM* is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Note: * Only applies to the H8S/2351. Areas 1 and 6: In external expansion mode, all of areas 1 and 6 is external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. Areas 2 to 5: In external expansion mode, all of areas 2 to 5 is external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface.

6.3.5 Areas in Normal Mode

In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expansion mode* the space excluding the on-chip ROM*, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When external space is accessed, the CS0 signal can be output. The basic bus interface or burst ROM interface can be selected. Note: * Only applies to the H8S/2351.

6.3.6 Chip Select Signals

The H8S/2350 Series can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. In normal mode, only the CS0 signal can be output. Figure 6-3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS7. In the H8S/2351’s ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-on reset, and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals. Bus cycle T1 T2 T3 Area n external addressAddress bus ø CSn Figure 6-3 CSn Signal Output Timing (n = 0 to 7)

6.4 Basic Bus Interface

6.4.1 Overview

The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3).

6.4.2 Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D 15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6-4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. D 15 D 8 D 7 D 0 Upper data bus Lower data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6-4 Access Sizes and Data Alignment Control (8-Bit Access Space)

16-Bit Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. D 15 D 8 D 7 D 0 Upper data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size

Even address Byte size • Odd address Lower data bus Figure 6-5 Access Sizes and Data Alignment Control (16-Bit Access Space)

6.4.3 Valid Strobes

Table 6-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6-4 Data Buses Used and Valid Strobes Area Access Size Read/ Write Address Valid Strobe Upper Data Bus (D15 to D8) Lower data bus (D7 to D0) 8-bit access Byte Read — RD Valid Invalid space Write — HWR Hi-Z 16-bit access Byte Read Even RD Valid Invalid space Odd Invalid Valid Write Even HWR Valid Hi-Z Odd LWR Hi-Z Valid Word Read — RD Valid Valid Write — HWR, LWR Valid Valid Note: Hi-Z: High impedance Invalid: Input state; input value is ignored.

6.4.4 Basic Timing

8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 Address bus ø CSn AS RD D 15 to D8 Valid D 7 to D0 Invalid Read HWR LWR D 15 to D8 Valid D 7 to D0 High impedance Write Note: n = 0 to 7 High Figure 6-6 Bus Timing for 8-Bit 2-State Access Space

8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 Address bus ø CSn AS RD D 15 to D8 Valid D 7 to D0 Invalid Read HWR LWR D 15 to D8 Valid D 7 to D0 High impedance Write High Note: n = 0 to 7 Figure 6-7 Bus Timing for 8-Bit 3-State Access Space

16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 Address bus ø CSn AS RD D 15 to D8 Valid D 7 to D0 Invalid Read HWR LWR D 15 to D8 Valid D 7 to D0 High impedance Write High Note: n = 0 to 7 Figure 6-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)

ø CSn AS RD D 15 to D8 Invalid D 7 to D0 Valid Read HWR LWR D 15 to D8 High impedance D 7 to D0 Valid Write Note: n = 0 to 7 High Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)

ø CSn AS RD D 15 to D8 Valid D 7 to D0 Valid Read HWR LWR D 15 to D8 Valid D 7 to D0 Valid Write Note: n = 0 to 7 Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)

16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 Address bus ø CSn AS RD D 15 to D8 Valid D 7 to D0 Invalid Read HWR LWR D 15 to D8 Valid D 7 to D0 High impedance Write High Note: n = 0 to 7 Figure 6-11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)

ø CSn AS RD D 15 to D 8 Invalid D 7 to D 0 Valid Read HWR LWR D 15 to D 8 High impedance D 7 to D 0 Valid Write High Note: n = 0 to 7 Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)

ø CSn AS RD D 15 to D8 Valid D 7 to D0 Valid Read HWR LWR D 15 to D8 Valid D 7 to D0 Valid Write Note: n = 0 to 7 Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)

6.4.5 Wait Control

When accessing external space, the H8S/2350 Series can extend the bus cycle by inserting one or more wait states (Tw ). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T 2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the WAIT pin is low at the falling edge of ø in the last T 2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas.

6.5 DRAM Interface

6.5.1 Overview

When the H8S/2350 Series is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2350 Series. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode.

6.5.2 Setting DRAM Space

Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6-5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6-5 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 1 Normal space DRAM space 1 0 Normal space DRAM space

6.5.3 Address Multiplexing

With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6-6 shows the relation between the settings of MXC1 and MXC0 and the shift size. Table 6-6 Address Multiplexing Settings by Bits MXC1 and MXC0 MCR Shift Address Pins MXC1 MXC0 Size A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row 0 0 8 bits A 23 to A13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 address 1 9 bits A 23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 1 0 10 bits A 23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

1 Setting

——— A 23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

6.5.4 Data Bus

If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, · 16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D 15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment.

6.5.5 Pins Used for DRAM Interface

Table 6-7 shows the pins used for DRAM interfacing and their functions. Table 6-7 DRAM Interface Pins Pin With DRAM Setting Name I/O Function HWR WE Write enable Output When 2-CAS system is set, write enable for DRAM space access. LCAS LCAS Lower column address strobe Output Lower column address strobe for 16-bit DRAM space access CS2 RAS2 Row address strobe 2 Output Row address strobe when area 2 is designated as DRAM space. CS3 RAS3 Row address strobe 3 Output Row address strobe when area 3 is designated as DRAM space. CS4 RAS4 Row address strobe 4 Output Row address strobe when area 4 is designated as DRAM space. CS5 RAS5 Row address strobe 5 Output Row address strobe when area 5 is designated as DRAM space. CAS UCAS Upper column address strobe Output Upper column address strobe for DRAM space access WAIT WAIT Wait Input Wait request signal A12 to A0 A12 to A0 Address pins Output Row address/column address multiplexed output D 15 to D0 D 15 to D0 Data pins I/O Data input/output pins

6.5.6 Basic Timing

Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle. The 4 states of the basic timing consist of one T p (precharge cycle) state, one Tr (row address output cycle), and two Tc (column address output cycle) states, Tc1 and Tc2. Tp ø CSn (RAS) Read Write CAS, LCAS HWR, LWR D 15 to D0 HWR, LWR D 15 to D0 A23 to A0 Tr Tc1 Tc2 row column (UWE, LWE) (UWE, LWE) Note: n = 2 to 5 Figure 6-15 Basic Access Timing (2-WE System)

6.5.7 Precharge State Control

When DRAM is accessed, RAS precharging time must be secured. With the H8S/2350 Series, one Tp state is always inserted when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of Tp cycles according to the DRAM connected and the operating frequency of the H8S/2350 Series. Figure 6-16 shows the timing when two T p states are inserted. When the TCP bit is set to 1, two Tp states are also used for refresh cycles. Tp1 ø CSn (RAS) Read Write CAS, LCAS D 15 to D0 D 15 to D0 A23 to A0 Tp2 Tr Tc1 row column Tc2 HWR, LWR HWR, LWR (UWE, LWE) (UWE, LWE) Note: n = 2 to 5 Figure 6-16 Timing with Two Precharge States (2-WE System)

6.5.8 Wait Control

There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the T c1 state and Tc2 state, according to the settings of WCRH and WCRL. Pin Wait Insertion When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of ø in the last T c1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figure 6-17 shows an example of wait state insertion timing.

ø CSn (RAS) CAS Data bus Read data Read CAS Write data Write Notes: indicates the timing of WAIT pin sampling. WAIT Data bus Tr Tc1 Tw Tw Tc2 By WAIT pin n = 2 to 5 Figure 6-17 Example of Wait State Insertion Timing (CW2 = 1, 8-Bit Area Setting for Entire Space)

6.5.9 Byte Access Control

When DRAM with a ·16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2-CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection. When only DRAM with a ·8 configuration is connected, set the CW2 bit to 1 in MCR. Tp ø CSn (RAS) Byte control A23 to A0 Tr Tc1 Tc2 Row CAS LCAS HWR (WE) Column Note: n = 2 to 5 Figure 6-18 2-CAS System Control Timing (Upper Byte Write Access)

(Address shift size set to 9 bits) CS (RAS) 2-CAS type 4-Mbit DRAM 256-kbyte x 16-bit configuration 9-bit column address OE RAS CAS UCAS LCAS LCAS HWR (WE) WE A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D 15 to D0 D 15 to D0 Low address input: A8 to A0 Column address input: A 8 to A0 Figure 6-19 Example of 2-CAS System Connection

6.5.10 Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1. (1) Burst Access (Fast Page Mode) Operation Timing Figure 6-20 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC1 and MXC0 in MCR. Tp ø CSn (RAS) Read Write CAS, LCAS HWR (WE) D 15 to D0 HWR (WE) D 15 to D0 A23 to A0 Tr Tc1 Tc2 row column1 column2 Tc1 Tc2 Note: n = 2 to 5 Figure 6-20 Operation Timing in Fast Page Mode (2-WE System) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details, see section 6.5.8, Wait Control.

(2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again.

RAS down mode To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6-21 shows an example of the timing in RAS down mode. Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down mode. External space access Tp A23 to A0 ø CSn (RAS) CAS, LCAS D 15 to D0 Tr Tc1 Tc2 T1 T2 DRAM accessDRAM access Tc1 Tc2 Note: n = 2 to 5 Figure 6-21 Example of Operation Timing in RAS Down Mode

RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6-22 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level. CSn (RAS) CAS, LCAS External space access Tp A23 to A0 ø D 15 to D0 Tr Tc1 Tc2 Tc1 Tc2 DRAM accessDRAM access T1 T2 Note: n = 2 to 5 Figure 6-22 Example of Operation Timing in RAS Up Mode

6.5.11 Refresh Control

The H8S/2350 Series is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. (1) CAS-before-RAS (CBR) Refreshing To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Do not clear the CMF flag when refresh control is being performed (RFSHE = 1). RTCNT operation is shown in figure 6-23, compare match timing in figure 6-24, and CBR refresh timings in figure 6-25. RTCOR H'00 Refresh request RTCNT Figure 6-23 RTCNT Operation

6.6 DMAC Single Address Mode and DRAM Interface

When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed is selected.

6.6.1 When DDS = 1

Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low from the T C1 state in the case of the DRAM interface. Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1. Tp ø Read Write CSn (RAS) HWR, (WE) D 15 to D0 HWR, (WE) DACK D 15 to D0 A23 to A0 Tr Tc1 Tc2 Row Column CAS, (UCAS) LCAS (LCAS) Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access)

6.6.2 When DDS = 0

When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6-29 shows the DACK output timing for the DRAM interface when DDS = 0. Tp ø Read Write CSn (RAS) HWR, (WE) D 15 to D0 HWR, (WE) DACK D 15 to D0 A23 to A0 Tr Tc1 Tc2 Row Column CAS, (UCAS) LCAS (LCAS) Figure 6-29 DACK Output Timing when DDS = 0 (Example of DRAM Access)

6.7 Burst ROM Interface

6.7.1 Overview

With the H8S/2350 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access.

6.7.2 Basic Timing

The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6-30 (a) and (b). The timing shown in figure 6-30 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6-30 (b) is for the case where both these bits are cleared to 0.

ø CS0 AS Data bus T2 T3 T1 T2 T1 Full access RD Burst access Only lower address changed Read data Read data Read data Figure 6-30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)

ø CS0 AS Data bus T2 T1 T1 Full access RD Burst access Only lower address changed Read data Read data Read data Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)

6.7.3 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle.

6.8 Idle Cycle

6.8.1 Operation

When the H8S/2350 Series accesses external space , it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6-31 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Address bus ø RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Bus cycle A Bus cycle B Long output floating time Data collision (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Address bus ø RD Data bus T2 T3 TI T1 T2 CS (area A) CS (area B) CS (area A) CS (area B) Figure 6-31 Example of Idle Cycle Operation (1)

(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6-33. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Address bus ø RD Bus cycle A T2 T3 T1 T2 Bus cycle B Possibility of overlap between CS (area B) and RD Address bus ø Bus cycle A T2 T3 TI T1 Bus cycle B CS (area A) CS (area B) RD CS (area A) CS (area B) (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6-33 Relationship between Chip Select (CS) and Read (RD) (4) Usage Notes When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access, only a T p cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6-34. However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this case is shown in figures 6-35 (a) and (b).

Tp Tr Tc1 Tc2 T1 T1 T2 T3 Tc1 Tc2Tc1 EXTAL Address RD RAS CAS, LCAS Data bus DRAM space read External read DRAM space write Idle cycle HWR Figure 6-35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1)

6.8.2 Pin States in Idle Cycle

Table 6-8 shows pin states in an idle cycle. Table 6-8 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D 15 to D0 High impedance CSn High* CAS High AS High RD High HWR High LWR High DACKn High Note: * Remains low in DRAM space RAS down mode or a refresh cycle.

6.9 Write Data Buffer Function

The H8S/2350 Series has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6-36 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write or DMA single address mode transfer continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. Internal address bus A23 to A0 External write cycle HWR, LWR T2 TW TW T3 On-chip memory readInternal I/O register read Internal read signal CSn D 15 to D0 External address Internal memory External space write Internal I/O register address Figure 6-36 Example of Timing when Write Data Buffer Function is Used

6.10 Bus Release

6.10.1 Overview

The H8S/2350 Series can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request is generated, it can issue a bus request off-chip.

6.10.2 Operation

In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2350 Series. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Even if a refresh request is generated in the external bus released state, refresh control is deferred until the external bus master drops the bus request. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, or when a refresh request is generated, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations.

6.10.3 Pin States in External Bus Released State

Table 6-9 shows pin states in the external bus released state. Table 6-9 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D 15 to D0 High impedance CSn High impedance CAS High impedance AS High impedance RD High impedance HWR High impedance LWR High impedance DACKn High

6.10.4 Transition Timing

Figure 6-37 shows the timing for transition to the bus-released state. CPU cycleExternal bus released stateCPU cycle Address Minimum 1 state T0 T1 T2 ø Address bus Data bus AS HWR, LWR BREQ BACK High impedance [1] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T 2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. High impedance High impedance High impedance RD High impedance Figure 6-37 Bus-Released State Transition Timing

6.10.5 Usage Note

When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep mode.

6.11 Bus Arbitration

6.11.1 Overview

The H8S/2350 Series has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation.

6.11.2 Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC > DTC > CPU (Low) An internal bus access by an internal bus master, external bus release, and refreshing, can be executed in parallel. In the event of simultaneous external bus release request, refresh request, and internal bus master external access request generation, the order of priority is as follows: (High) Refresh > External bus release (Low) (High) External bus release > Internal bus master external access (Low) As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations.

6.11.3 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows:

The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See Appendix A-5, Bus States During Instruction Execution, for timings at which the bus is not transferred.
If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of a transfer.

6.11.4 External Bus Release Usage Note

External bus release can be performed on completion of an external bus cycle. The RD signal, DRAM interface RAS and CAS signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD, RAS, and CAS signals may change from the low level to the high-impedance state.

6.12 Resets and the Bus Controller

In a power-on reset, the H8S/2350, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller’s registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored. Also, since the DMAC is initialized by a manual reset, DACK and TEND output is disabled and these pins become I/O ports controlled by DDR and DR.

7.1 Overview

The H8S/2350 Series has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels.

7.1.1 Features

The features of the DMAC are listed below.

Choice of short address mode or full address mode Short address mode ¾ Maximum of 4 channels can be used ¾ Choice of dual address mode or single address mode ¾ In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as16 bits ¾ In single address mode, transfer source or transfer destination address only is specified as 24 bits ¾ In single address mode, transfer can be performed in one bus cycle ¾ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode ¾ Maximum of 2 channels can be used ¾ Transfer source and transfer destination address specified as 24 bits ¾ Choice of normal mode or block transfer mode
16-Mbyte address space can be specified directly
Byte or word can be set as the transfer unit
Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) ¾ Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts ¾ Serial communication interface (SCI0, SCI1) transmission complete interrupt, reception complete interrupt ¾ A/D converter conversion end interrupt ¾ External request ¾ Auto-request

Module stop mode can be set ¾ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode

7.1.2 Block Diagram

A block diagram of the DMAC is shown in figure 7-1. Internal address bus Address buffer Processor Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0/CR DREQ1/CR TEND0/CR TEND1/CR DACK0/CR DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Control logic DMAWER DMACR1B DMACR1A DMACR0B DMACR0A DMATCR DMABCR Data buffer Internal data bus MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Legend : DMA write enable register : DMA terminal control register : DMA band control register (for all channels) : DMA control register : Memory address register : I/O address register : Executive transfer counter register Channel 0Channel 1 Channel 0AChannel 0BChannel 1AChannel 1B Module data bus DMAWER DMATCR DMABCR DMACR MAR IOAR ETCR Figure 7-1 Block Diagram of DMAC

7.1.3 Overview of Functions

Tables 7-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7-1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination Dual address mode

Sequential mode ¾ 1-byte or 1-word transfer executed for one transfer request ¾ Memory address incremented/decremented by 1 or 2 ¾ 1 to 65536 transfers
Idle mode ¾ 1-byte or 1-word transfer executed for one transfer request ¾ Memory address fixed ¾ 1 to 65536 transfers
Repeat mode ¾ 1-byte or 1-word transfer executed for one transfer request ¾ Memory address incremented/ decremented by 1 or 2 ¾ After specified number of transfers (1 to 256), initial state is restored and operation continues
TPU channel 0 to 5 compare match/input capture A interrupt
SCI transmission complete interrupt
SCI reception complete interrupt
A/D converter conversion end interrupt
External request 24/16 16/24 Single address mode
1-byte or 1-word transfer executed for one transfer request
Transfer in 1 bus cycle using DACK pin in place of address specifying I/O
Specifiable for sequential, idle, and repeat modes
External request 24/DACK DACK /24

Table 7-1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination Normal mode

Auto-request ¾ Transfer request retained internally ¾ Transfers continue for the specified number of times (1 to 65536) ¾ Choice of burst or cycle steal transfer
Auto-request 24 24
External request ¾ 1-byte or 1-word transfer executed for one transfer request ¾ 1 to 65536 transfers
External request Block transfer mode
Specified block size transfer executed for one transfer request
1 to 65536 transfers
Either source or destination specifiable as block area
Block size: 1 to 256 bytes or words
TPU channel 0 to 5 compare match/input capture A interrupt
SCI transmission complete interrupt
SCI reception complete interrupt
External request
A/D converter conversion end interrupt 24 24

7.1.4 Pin Configuration

Table 7-2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output. With regard to the DACK pins, setting single address transfer automatically sets the corresponding port to output, functioning as a DACK pin. With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting. Table 7-2 DMAC Pins Channel Pin Name Symbol I/O Function

0 DMA request 0 DREQ0 Input DMAC channel 0 external

DMA transfer acknowledge 0DACK0 Output DMAC channel 0 single address transfer acknowledge DMA transfer end 0 TEND0 Output DMAC channel 0 transfer end

1 DMA request 1 DREQ1 Input DMAC channel 1 external

DMA transfer acknowledge 1DACK1 Output DMAC channel 1 single address transfer acknowledge DMA transfer end 1 TEND1 Output DMAC channel 1 transfer end

7.1.5 Register Configuration

Table 7-3 summarizes the DMAC registers. Table 7-3 DMAC Registers Channel Name Abbreviation R/W Initial Value Address * Bus Width

0 Memory address register 0A MAR0A R/W Undefined H'FEE0 16 bits

I/O address register 0A IOAR0A R/W Undefined H'FEE4 16 bits Transfer count register 0A ETCR0A R/W Undefined H'FEE6 16 bits Memory address register 0B MAR0B R/W Undefined H'FEE8 16 bits I/O address register 0B IOAR0B R/W Undefined H'FEEC 16 bits Transfer count register 0B ETCR0B R/W Undefined H'FEEE 16 bits

1 Memory address register 1A MAR1A R/W Undefined H'FEF0 16 bits

I/O address register 1A IOAR1A R/W Undefined H'FEF4 16 bits Transfer count register 1A ETCR1A R/W Undefined H'FEF6 16 bits Memory address register 1B MAR1B R/W Undefined H'FEF8 16 bits I/O address register 1B IOAR1B R/W Undefined H'FEFC 16 bits Transfer count register 1B ETCR1B R/W Undefined H'FEFE 16 bits 0, 1 DMA write enable register DMAWER R/W H'00 H'FF00 8 bits DMA terminal control register DMATCR R/W H'00 H'FF01 8 bits DMA control register 0A DMACR0A R/W H'00 H'FF02 16 bits DMA control register 0B DMACR0B R/W H'00 H'FF03 16 bits DMA control register 1A DMACR1A R/W H'00 H'FF04 16 bits DMA control register 1B DMACR1B R/W H'00 H'FF05 16 bits DMA band control register DMABCR R/W H'0000 H'FF06 16 bits Module stop control register MSTPCR R/W H'3FFF H'FF3C 8 bits Note: * Lower 16 bits of the address.

7.2 Register Descriptions (1) (Short Address Mode)

Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7-4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7-4 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) FAE0 Description

0 Short address mode specified (channels A and B operate independently)

MAR0A Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A Channel 0B MAR0B IOAR0B ETCR0B DMACR0B

1 Full address mode specified (channels A and B operate in combination)

MAR0A Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B

7.2.1 Memory Address Registers (MAR)

*: Undefined Bit MAR Initial value R/W MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode.

7.2.2 I/O Address Register (IOAR)

*: Undefined IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so that the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode.

7.2.3 Execute Transfer Count Register (ETCR)

ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) Sequential Mode and Idle Mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit ETCR Initial value R/W Transfer Counter *: Undefined In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends.

(2) Repeat Mode Transfer Number Storage Bit ETCRH Initial value R/W *: Undefined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer Counter Bit ETCRL Initial value R/W In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode.

7.2.4 DMA Control Register (DMACR)

DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode.

Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ Description

0 Byte-size transfer (Initial value)

1 Word-size transfer

Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. Bit 6 DTID Description

0 MAR is incremented after a data transfer (Initial value)

When DTSZ = 0, MAR is incremented by 1 after a transfer
When DTSZ = 1, MAR is incremented by 2 after a transfer

1 MAR is decremented after a data transfer

When DTSZ = 0, MAR is decremented by 1 after a transfer
When DTSZ = 1, MAR is decremented by 2 after a transfer Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE DMABCR DTIE Description 0 0 Transfer in sequential mode (no transfer end interrupt) (Initial value)

1 Transfer in sequential mode (with transfer end interrupt)

1 0 Transfer in repeat mode (no transfer end interrupt)

1 Transfer in idle mode (with transfer end interrupt)

For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode,

Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR SAE Bit 4 DTDIR Description 0 0 Transfer with MAR as source address and IOAR as destination address (Initial value)

1 Transfer with IOAR as source address and MAR as destination address

1 0 Transfer with MAR as source address and DACK pin as write strobe

1 Transfer with DACK pin as read strobe and MAR as destination address

Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel Channel A Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0000— (Initial value)

1 Activated by A/D converter conversion end interrupt

10— 1 0 0 Activated by SCI channel 0 transmission complete interrupt

1 Activated by SCI channel 0 reception complete interrupt

1 0 Activated by SCI channel 1 transmission complete interrupt

1 Activated by SCI channel 1 reception complete interrupt

1000 Activated by TPU channel 0 compare match/input capture

1 Activated by TPU channel 1 compare match/input capture

1 0 Activated by TPU channel 2 compare match/input capture A interrupt

1 Activated by TPU channel 3 compare match/input capture

1 0 0 Activated by TPU channel 4 compare match/input capture A interrupt

1 Activated by TPU channel 5 compare match/input capture

10—

0000— (Initial value) 1 0 Activated by DREQ pin falling edge input*

1 Activated by DREQ pin low-level input

1 0 0 Activated by SCI channel 0 transmission complete interrupt 1 0 Activated by SCI channel 1 transmission complete interrupt 1 0 Activated by TPU channel 2 compare match/input capture A interrupt 1 0 0 Activated by TPU channel 4 compare match/input capture A interrupt 10— Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation.

7.2.5 DMA Band Control Register (DMABCR)

0 Short address mode (Initial value)

1 Full address mode

Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B are used as independent channels. Bit 14 FAE0 Description

Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. Bit 13 SAE1 Description

0 Transfer in dual address mode (Initial value)

1 Transfer in single address mode

This bit is invalid in full address mode. Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. Bit 12 SAE0 Description This bit is invalid in full address mode. Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting.

Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting. Bit 11 DTA1B Description

0 Clearing of selected internal interrupt source at time of DMA transfer is disabled

(Initial value)

1 Clearing of selected internal interrupt source at time of DMA transfer is enabled

Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting. Bit 10 DTA1A Description (Initial value) Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting. Bit 9 DTA0B Description (Initial value) Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A Description (Initial value)

Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows:

When initialization is performed
When the specified number of transfers have been completed in a transfer mode other than repeat mode
When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows:
When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B. Bit 7 DTE1B Description

0 Data transfer disabled (Initial value)

1 Data transfer enabled

Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A Description

Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B. Bit 5 DTE0B Description Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A Description Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B Description

0 Transfer end interrupt disabled (Initial value)

1 Transfer end interrupt enabled

Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A Description

Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt. Bit 1 DTIE0B Description Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt. Bit 0 DTIE0A Description

7.3 Register Descriptions (2) (Full Address Mode)

Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7-4.

7.3.1 Memory Address Register (MAR)

*: Undefined Bit MAR Initial value R/W MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode.

7.3.2 I/O Address Register (IOAR)

IOAR is not used in full address transfer.

7.3.3 Execute Transfer Count Register (ETCR)

ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. (1) Normal Mode ETCRA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit ETCR Initial value R/W Transfer Counter *: Undefined In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode. (2) Block Transfer Mode ETCRA Holds block size Bit ETCRAH Initial value R/W *: Undefined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block size counter Bit ETCRAL Initial value R/W

In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000.

7.3.4 DMA Control Register (DMACR)

DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in standby mode. DMACRA DTSZ R/W SAID R/W SAIDE R/W BLKDIR R/W BLKE R/W R/W R/W R/W Bit DMACRA Initial value R/W DMACRB R/W DAID R/W DAIDE R/W R/W DTF3 R/W DTF0 R/W DTF2 R/W DTF1 R/W Bit DMACRB Initial value R/W

Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ Description Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 14 SAID Bit 13 SAIDE Description 0 0 MARA is fixed (Initial value)

1 MARA is incremented after a data transfer

When DTSZ = 0, MARA is incremented by 1 after a transfer
When DTSZ = 1, MARA is incremented by 2 after a transfer 1 0 MARA is fixed

1 MARA is decremented after a data transfer

When DTSZ = 0, MARA is decremented by 1 after a transfer
When DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12—Block Direction (BLKDIR) Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR Bit 11 BLKE Description 0 0 Transfer in normal mode (Initial value)

1 Transfer in block transfer mode, destination side is block area

1 0 Transfer in normal mode

1 Transfer in block transfer mode, source side is block area

For operation in normal mode and block transfer mode, see section 7.5, Operation.

Bits 10 to 7—Reserved: Can be read or written to. Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 DAID Bit 5 DAIDE Description 0 0 MARB is fixed (Initial value)

1 MARB is incremented after a data transfer

When DTSZ = 0, MARB is incremented by 1 after a transfer
When DTSZ = 1, MARB is incremented by 2 after a transfer 1 0 MARB is fixed

1 MARB is decremented after a data transfer

When DTSZ = 0, MARB is decremented by 1 after a transfer
When DTSZ = 1, MARB is decremented by 2 after a transfer Bit 4—Reserved: Can be read or written to. Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode.
Normal Mode Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0000— (Initial value) 1 0 Activated by DREQ pin falling edge input

10 * — 1 0 Auto-request (cycle steal)

1 Auto-request (burst)

1 *** — *: Don't care

Block Transfer Mode Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0000— (Initial value)

1 0 Activated by DREQ pin falling edge input* 1 0 0 Activated by SCI channel 0 transmission complete interrupt 1 0 Activated by SCI channel 1 transmission complete interrupt 1 0 Activated by TPU channel 2 compare match/input capture A interrupt 1 0 0 Activated by TPU channel 4 compare match/input capture A interrupt 10— Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation.

7.3.5 DMA Band Control Register (DMABCR)

DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. Bit 15 FAE1 Description Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 Description

Bits 13 and 12—Reserved: Can be read or written to. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. Bit 11 DTA1 Description (Initial value) Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0 Description (Initial value)

Bits 10 and 8—Reserved: Can be read or written to. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows:

When initialization is performed
When NMI is input in burst mode
When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows:
When 1 is written to DTME after DTME is read as 0 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel Bit 7 DTME1 Description 0 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt (Initial value)

Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel Bit 5 DTME0 Description 0 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value)

Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows:

When initialization is performed
When the specified number of transfers have been completed
When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows:
When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1. Bit 6 DTE1 Description

Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 Description Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.

Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B Description

0 Transfer break interrupt disabled (Initial value)

1 Transfer break interrupt enabled

Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B Description Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A Description Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A Description

7.4 Register Descriptions (3)

7.4.1 DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Figure 7-2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels. DTC MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMATCR DMACR0B DMACR1B DMAWER DMACR0A DMACR1A DMABCRSecond transfer area using chain transfer First transfer area Figure 7-2 Areas for Register Re-Setting by DTC (Example: Channel 0A)

DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC. Bit 3 WE1B Description

0 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

are disabled (Initial value)

1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR by the DTC. Bit 2 WE1A Description

0 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled

(Initial value)

1 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled

Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. Bit 1 WE0B Description

0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

are disabled (Initial value)

1 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. Bit 0 WE0A Description

0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled

(Initial value)

1 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled

Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted.

7.4.2 DMA Terminal Control Register (DMATCR)

DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in standby mode. Bits 7 and 6—Reserved: Read-only bits, always read as 0. Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output. Bit 5 TEE1 Description

0 TEND1 pin output disabled (Initial value)

1 TEND1 pin output enabled

Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0 Description

0 TEND0 pin output disabled (Initial value)

1 TEND0 pin output enabled

The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0—Reserved: Read-only bits, always read as 0.

7.4.3 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 15—Module Stop (MSTP15): Specifies the DMAC module stop mode. Bits 15 MSTP15 Description

0 DMAC module stop mode cleared (Initial value)

1 DMAC module stop mode set

7.5 Operation

7.5.1 Transfer Modes

Table 7-5 lists the DMAC modes. Table 7-5 DMAC Transfer Modes Transfer Mode Transfer Source Remarks Short address mode Dual address mode (1) Sequential mode (2) Idle mode (3) Repeat mode

TPU channel 0 to 5 compare match/input capture A interrupt
SCI transmission complete interrupt
SCI reception complete interrupt
A/D converter conversion end interrupt
External request
Up to 4 channels can operate independently
External request applies to channel B only
Single address mode applies to channel B only
Modes (1), (2), and (3) can also be specified for single address mode (4) Single address mode Full address mode (5) Normal mode • External request
Auto-request
Max. 2-channel operation, combining channels A and B (6) Block transfer mode
TPU channel 0 to 5 compare match/input capture A interrupt
SCI transmission complete interrupt
SCI reception complete interrupt
A/D converter conversion end interrupt
External request
With auto-request, burst mode transfer or cycle steal transfer can be selected

Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (2) Idle mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. (3) Repeat mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (4) Single address mode In response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set automatically. The transfer direction is programmable. Modes (1), (2) and (3) can also be specified for single address mode. (5) Normal mode

Auto-request By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits. ¾ Cycle steal mode: The bus is released to another bus master every byte or word transfer. ¾ Burst mode: The bus is held and transfer continued until the specified number of transfers have been completed.

External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. (6) Block transfer mode In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits.

7.5.2 Sequential Mode

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-6 summarizes register functions in sequential mode. Table 7-6 Register Functions in Sequential Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented/ decremented every transfer 23 0 IOAR H'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 015 ETCR Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.

7.5.3 Idle Mode

Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-7 summarizes register functions in idle mode. Table 7-7 Register Functions in Idle Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Fixed 23 0 IOAR H'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 015 ETCR Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.

7.5.4 Repeat Mode

Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-8 summarizes register functions in repeat mode. Table 7-8 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented/ decremented every transfer. Initial setting is restored when value reaches H'0000 23 0 IOAR H'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed ETCRH ETCRL Holds number of transfers Transfer counter Number of transfers Number of transfers Fixed Decremented every transfer. Loaded with ETCRH value when count reaches H'00 Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1) DTID · 2DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared.

7.5.5 Single Address Mode

Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR. Table 7-9 summarizes register functions in single address mode. Table 7-9 Register Functions in Single Address Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source DACK pin Write strobe Read strobe (Set automatically by SAE bit; IOAR is invalid) Strobe for external device 015 ETCR Transfer counter Number of transfers * Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit DACK : Data transfer acknowledge Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output.

7.5.6 Normal Mode

In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7-10 summarizes register functions in normal mode. Table 7-10 Register Functions in Normal Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed 015 ETCRA Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend MARA : Memory address register A MARB : Memory address register B ETCRA : Transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.

7.5.7 Block Transfer Mode

In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7-11 summarizes register functions in block transfer mode. Table 7-11 Register Functions in Block Transfer Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed ETCRAH ETCRAL Holds block size Block size counter Block size Block size Fixed Decremented every transfer; ETCRH value copied when count reaches H'00 15 0 ETCRB Block transfer counter Number of block transfers Decremented every block transfer; transfer ends when count reaches H'0000 Legend MARA : Memory address register A MARB : Memory address register B ETCRA : Transfer count register A ETCRB : Transfer count register B MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB.

ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7-15 shows the operation flow in block transfer mode.

ETCRAL=ETCRAL–1 Transfer request? ETCRAL=H'00 Release bus BLKDIR=0 ETCRAL=ETCRAH ETCRB=ETCRB–1 ETCRB=H'0000 Start (DTE = DTME = 1) Read address specified by MARA MARA=MARA+SAIDE·(–1) SAID·2DTSZ Write to address specified by MARB MARB=MARB+DAIDE·(–1) DAID ·2DTSZ MARB=MARB –DAIDE·(–1)DAID ·2DTSZ ·ETCRAH MARA=MARA –SAIDE·(–1)SAID·2DTSZ ·ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Figure 7-15 Operation Flow in Block Transfer Mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.

7.5.8 DMAC Activation Sources

DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7-12. Table 7-12 DMAC Activation Sources Short Address Mode Full Address Mode Activation Source Channels 0A and 1A Channels 0B and 1B Normal Mode Block Transfer Mode Internal ADI X InterruptsTXI0 X RXI0 X TXI1 X RXI1 X TGI0A X TGI1A X TGI2A X TGI3A X TGI4A X TGI5A X External DREQ pin falling edge input X Requests DREQ pin low-level input X Auto-request X X X Legend : Can be specified X : Cannot be specified Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are not accepted. If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an

activation source for more than one channel, the interrupt request flag is cleared when the highest- priority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Activation by Auto-Request: Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. Single Address Mode: The DMAC can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel. In dual address mode, transfer is performed with the source address and destination address specified separately.

In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the DACK strobe, without regard to the address. Figure 7-16 shows the data bus in single address mode. External memory External device (Read) (Write) RD HWR, LWR A23 to A0 H8S/2350 Series D 15 to D0 (high impedance) DACK Address bus Data bus Figure 7-17 Data Bus in Single Address Mode When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a write strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used. Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. On the external device side, DACK is output in synchronization with the address strobe. For details of bus cycles, see section 7.5.11, DMAC Bus Cycles (Single Address Mode). Do not specify internal space for transfer addresses in single address mode.

7.5.9 Basic DMAC Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7-18. In this example, word- size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. ø Address bus DMAC cycle (1-word transfer) RD LWR HWR Source address Destination address CPU cycle CPU cycle T1 T2 T3T1 T2 T3T1 T2 Figure 7-18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register.

7.5.10 DMAC Bus Cycles (Dual Address Mode)

Short Address Mode: Figure 7-19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read ø Address bus RD LWR TEND HWR Bus release Last transfer cycle DMA write DMA dead DMA read DMA write DMA read DMA write Bus release Bus release Bus release Figure 7-19 Example of Short Address Mode Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter reaches 0.

Full Address Mode (Cycle Steal Mode): Figure 7-20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read ø Address bus RD LWR TEND HWR Bus release Last transfer cycle DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Figure 7-20 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.

Full Address Mode (Burst Mode): Figure 7-21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16- bit, 2-state access space to external 16-bit, 2-state access space. DMA read ø Address bus RD LWR TEND HWR Bus release DMA write DMA dead DMA read DMA write DMA read DMA write Bus release Burst transfer Last transfer cycle Figure 7-21 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.

Full Address Mode (Block Transfer Mode): Figure 7-22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read ø Address bus RD LWR TEND HWR Bus release Block transfer Last block transfer DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Figure 7-22 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one- state DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation.

7.5.11 DMAC Bus Cycles (Single Address Mode)

Single Address Mode (Read): Figure 7-27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read ø Address bus DMA dead RD DACK TEND Bus release DMA read DMA read DMA read Bus release Bus release Bus release Bus release Last transfer cycle Figure 7-27 Example of Single Address Mode (Byte Read) Transfer

Single Address Mode (Write): Figure 7-29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write ø Address bus DMA dead HWR DACK TEND Bus release LWR DMA write DMA write DMA write Bus release Bus release Bus release Bus release Last transfer cycle Figure 7-29 Example of Single Address Mode (Byte Write) Transfer

7.5.12 Write Data Buffer Function

DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7-33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function. ø Internal address Internal read signal HWR, LWR TEND External address DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Figure 7-33 Example of Dual Address Transfer Using Write Data Buffer Function Figure 7-34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory.

ø Internal address Internal read signal RD DACK External address DMA read DMA single CPU read DMA single CPU read Figure 7-34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer.

7.5.13 DMAC Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7- 13 summarizes the priority order for DMAC channels. Table 7-13 DMAC Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1 Channel 1B Low

7.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC, and the DMAC

There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used.

7.5.15 NMI Interrupts and DMAC

When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7-36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel Set DTME bit to 1 Transfer continues [1] [2] DTE= 1 DTME= 0 Transfer ends No Yes [1] [2] Check that DTE = 1 and DTME = 0 in DMABCRL Write 1 to the DTME bit. Figure 7-36 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt

7.5.16 Forced Termination of DMAC Operation

If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7-37 shows the procedure for forcibly terminating DMAC operation by software. Forced termination of DMAC Clear DTE bit to 0 Forced termination [1] [1] Clear the DTE bit in DMABCRL to 0. If you want to prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Figure 7-37 Example of Procedure for Forcibly Terminating DMAC Operation

7.5.17 Clearing Full Address Mode

Figure 7-38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. Clearing full address mode Stop the channel Initialize DMACR Clear FAE bit to 0 Initialization; operation halted [1] [2] [3] [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Figure 7-38 Example of Procedure for Clearing Full Address Mode

7.6 Interrupts

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7-13 shows the interrupt sources and their priority order. Table 7-13 Interrupt Source Priority Order Interrupt Interrupt Source Interrupt Name Short Address Mode Full Address Mode Priority Order DEND0A Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0 High DEND0B Interrupt due to end of transfer on channel 0B Interrupt due to break in transfer on channel 0 DEND1A Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1 DEND1B Interrupt due to end of transfer on channel 1B Interrupt due to break in transfer on channel 1 Low Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7-13. Figure 7-39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0. DTE/ DTME DTIE Transfer end/transfer break interrupt Figure 7-39 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to o while DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting.

7.7 Usage Notes

DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop.

Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
TEND pin enable (TEE = 1)
DACK pin enable (FAE = 0 and SAE = 1) Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-detected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the medium- speed clock.

Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. (a) Write Data Buffer Function and DMAC Register Setting If the setting of is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. The register that controls external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. (b) Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. (c) Write Data Buffer Function and TEND Output A low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level may not be output from the TEND pin if the write data buffer function is used when data transfer is performed between an internal I/O register and on-chip memory. If at least one of the DMAC transfer addresses is an external address, a low level is output from the TEND pin.

Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or an abort should be handled by the CPU as necessary. Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write a 1 to them.

Section 8 Data Transfer Controller

8.1 Overview

The H8S/2350 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data.

8.1.1 Features

The features of the DTC are:

Transfer possible over any number of channels ¾ Transfer information is stored in memory ¾ One activation source can trigger a number of data transfers (chain transfer)
Wide range of transfer modes ¾ Normal, repeat, and block transfer modes available ¾ Incrementing, decrementing, and fixing of source and destination addresses can be selected
Direct specification of 16-Mbyte address space possible ¾ 24-bit transfer source and destination addresses can be specified
Transfer can be set in byte or word units
A CPU interrupt can be requested for the interrupt that activated the DTC ¾ An interrupt request can be issued to the CPU after one data transfer ends ¾ An interrupt request can be issued to the CPU after the specified data transfers have completely ended
Activation by software is possible
Module stop mode can be set ¾ The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode.

8.1.2 Block Diagram

Figure 8-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.Interrupt request Interrupt controller DTC Internal address bus DTC service request Control logic Register information MRA MRB CRA CRB DAR SAR CPU interrupt request On-chip RAM Internal data bus Legend MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR DTCERA to DTCERF DTVECR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register Figure 8-1 Block Diagram of DTC

8.1.3 Register Configuration

Table 8-1 summarizes the DTC registers. Table 8-1 DTC Registers Name Abbreviation R/W Initial Value Address *1 DTC mode register A MRA — *2 Undefined — *3 DTC mode register B MRB — *2 Undefined — *3 DTC source address register SAR — *2 Undefined — *3 DTC destination address register DAR — *2 Undefined — *3 DTC transfer count register A CRA — *2 Undefined — *3 DTC transfer count register B CRB — *2 Undefined — *3 DTC enable registers DTCER R/W H'00 H'FF30 to H'FF35 DTC vector register DTVECR R/W H'00 H'FF37 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0.

8.2 Register Descriptions

8.2.1 DTC Mode Register A (MRA)

MRA is an 8-bit register that controls the DTC operating mode. SM1 SM0 DM1 DM0 MD1 Sz MD0 DTS Bit Initial value Unde- fined R/W : — Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 Bit 6 SM0 Description 0 — SAR is fixed 1 0 SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1)

1 SAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 Bit 4 DM0 Description 0 — DAR is fixed 1 0 DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1)

1 DAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 Bit 2 MD0 Description 0 0 Normal mode

1 Repeat mode

Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS Description

0 Destination side is repeat area or block area

1 Source side is repeat area or block area

Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz Description

0 Byte-size transfer

8.2.2 DTC Mode Register B (MRB)

R/W : — Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE Description

0 End of DTC data transfer (activation waiting state is entered)

1 DTC chain transfer (new register information is read, then data is transferred)

Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL Description

0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is

0 (the DTC clears the interrupt source flag of the activating interrupt to 0)

1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the

interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2350 Series, and should always be written with 0.

8.2.3 DTC Source Address Register (SAR)

R/W : — Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address.

8.2.4 DTC Destination Address Register (DAR)

R/W : — Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address.

8.2.5 DTC Transfer Count Register A (CRA)

15 14 13 12 1 1 1 0 9876543210 CRAH CRAL Bit Initial value Unde- fined R/W : — Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated.

8.2.6 DTC Transfer Count Register B (CRB)

15 14 13 12 1 1 1 0 9876543210Bit Initial value Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined R/W : CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

8.2.7 DTC Enable Registers (DTCER)

The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn Description

0 DTC activation by this interrupt is disabled (Initial value)

[Clearing conditions]

When the DISEL bit is 1 and the data transfer has ended
When the specified number of transfers have ended

1 DTC activation by this interrupt is enabled

[Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number generated for each interrupt controller.

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register.

8.2.8 DTC Vector Register (DTVECR)

R/(W)* DTVEC6 R/W DTVEC5 R/W DTVEC4 R/W DTVEC3 R/W DTVEC0 R/W DTVEC2 R/W DTVEC1 R/W A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. Bit Initial value R/W Note: * DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1. Bit 7 SWDTE Description

0 DTC software activation is disabled (Initial value)

[Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended

1 DTC software activation is enabled

[Holding conditions]

When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended
During data transfer due to software activation Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left- shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.

8.2.9 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 14—Module Stop (MSTP14): Specifies the DTC module stop mode. Bit 14 MSTP14 Description

0 DTC module stop mode cleared (Initial value)

1 DTC module stop mode set

8.3 Operation

8.3.1 Overview

When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 8-2 shows a flowchart of DTC operation. Start Read DTC vector Next transfer Read register information Data transfer Write register information Clear an activation flag CHNE=1 End No No Yes Yes Transfer Counter= 0 or DISEL= 1 Clear DTCER Interrupt exception handling Figure 8-2 Flowchart of DTC Operation The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.

The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 8-2 outlines the functions of the DTC. Table 8-2 DTC Functions Address Registers Transfer Mode Activation Source Transfer Source Transfer Destination

Normal mode ¾ One transfer request transfers one byte or one word ¾ Memory addresses are incremented or decremented by 1 or 2 ¾ Up to 65,536 transfers possible
Repeat mode ¾ One transfer request transfers one byte or one word ¾ Memory addresses are incremented or decremented by 1 or 2 ¾ After the specified number of transfers (1 to 256), the initial state resumes and operation continues
Block transfer mode ¾ One transfer request transfers a block of the specified size ¾ Block size is from 1 to 256 bytes or words ¾ Up to 65,536 transfers possible ¾ A block area can be designated at either the source or destination
IRQ
TPU TGI
SCI TXI or RXI
A/D converter ADI
DMAC DEND
Software 24 bits 24 bits

8.3.2 Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 8-3 shows activation source and DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Table 8-3 Activation Source and DTCER Clearance Activation Source When the DISEL Bit Is 0 and the Specified Number of Transfers Have Not Ended When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The corresponding DTCER bit is cleared to 0 The activation source flag remains set to 1 A request is issued to the CPU for the activation source interrupt Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. On-chip supporting module IRQ interrupt DTVECR Selection circuitInterrupt controller CPU DTC DTCER Clear controller Select Interrupt request Source flag cleared Clear Clear request Interrupt mask Figure 8-3 Block Diagram of DTC Activation Source Control

When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities.

8.3.3 DTC Vector Table

Figure 8-4 shows the correspondence between DTC vector addresses and register information. Table 8-4 shows the correspondence between activation, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM.

Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Source Origin of Interrupt Source Vector Number Vector Address DTCE * Priority Write to DTVECR Software DTVECR H'0400+ (DTVECR [6:0]<<1) — High IRQ0 External pin 16 H'0420 DTCEA7 IRQ1 17 H'0422 DTCEA6 IRQ2 18 H'0424 DTCEA5 IRQ3 19 H'0426 DTCEA4 IRQ4 20 H'0428 DTCEA3 IRQ5 21 H'042A DTCEA2 IRQ6 22 H'042C DTCEA1 IRQ7 23 H'042E DTCEA0 ADI (A/D conversion end) A/D 28 H'0438 DTCEB6 TGI0A (GR0A compare match/ input capture) TPU channel 0

32 H'0440 DTCEB5

TGI0B (GR0B compare match/ input capture)

33 H'0442 DTCEB4

TGI0C (GR0C compare match/ input capture)

34 H'0444 DTCEB3

TGI0D (GR0D compare match/ input capture)

35 H'0446 DTCEB2

TGI1A (GR1A compare match/ input capture) TPU channel 1

40 H'0450 DTCEB1

TGI1B (GR1B compare match/ input capture)

41 H'0452 DTCEB0

TGI2A (GR2A compare match/ input capture) TPU channel 2

44 H'0458 DTCEC7

TGI2B (GR2B compare match/ input capture)

45 H'045A DTCEC6

Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont) Interrupt Source Origin of Interrupt Source Vector Number Vector Address DTCE * Priority TGI3A (GR3A compare match/ input capture) TPU channel 3

48 H'0460 DTCEC5 High

TGI3B (GR3B compare match/ input capture)

49 H'0462 DTCEC4

TGI3C (GR3C compare match/ input capture)

50 H'0464 DTCEC3

TGI3D (GR3D compare match/ input capture)

51 H'0466 DTCEC2

TGI4A (GR4A compare match/ input capture) TPU channel 4

56 H'0470 DTCEC1

TGI4B (GR4B compare match/ input capture)

57 H'0472 DTCEC0

TGI5A (GR5A compare match/ input capture) TPU channel 5

60 H'0478 DTCED5

TGI5B (GR5B compare match/ input capture)

61 H'047A DTCED4

DMTEND0A (DMAC transfer end 0) DMAC 72 H'0490 DTCEE7 DMTEND0B (DMAC transfer end 1) 73 H'0492 DTCEE6 DMTEND1A (DMAC transfer end 2) 74 H'0494 DTCEE5 DMTEND1B (DMAC transfer end 3) 75 H'0496 DTCEE4 RXI0 (reception complete 0) SCI 81 H'04A2 DTCEE3 TXI0 (transmit data empty 0) channel 0 82 H'04A4 DTCEE2 RXI1 (reception complete 1) SCI 85 H'04AA DTCEE1 TXI1 (transmit data empty 1) channel 1 86 H'04AC DTCEE0 Low Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.

start address Register information Chain transfer DTC vector address Figure 8-4 Correspondence between DTC Vector Address and Register Information

8.3.4 Location of Register Information in Address Space

Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFF800 to H'FFFBFF). Register information start address Chain transfer Register information for 2nd transfer in chain transfer MRA SAR MRB DAR CRA CRB 4 bytes Lower address CRA CRB Register information MRA 0 123 SAR MRB DAR Figure 8-5 Location of Register Information in Address Space

8.3.5 Normal Mode

In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. Table 8-5 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used Transfer SAR DAR Figure 8-6 Memory Mapping in Normal Mode

8.3.6 Repeat Mode

In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in repeat mode. Table 8-6 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of transfers DTC transfer count register AL CRAL Designates transfer count (8 bits · 2) DTC transfer count register B CRB Not used Transfer SAR or DAR DAR or SARRepeat area Figure 8-7 Memory Mapping in Repeat Mode

8.3.7 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer mode. Table 8-7 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates transfer source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRAL Designates block size count DTC transfer count register B CRB Transfer count

Figure 8-8 Memory Mapping in Block Transfer Mode

8.3.8 Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer. Source Source Destination Destination DTC vector address Register information start address Register information CHNE = 1 Register information CHNE = 0 Figure 8-9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected.

8.3.9 Operation Timing

Figures 8-10 to 8-12 show an example of DTC operation timing. DTC activation request DTC request Address Vector read Transfer information read Transfer information write Data transfer Read Write ø Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Read Write Read Write Data transfer Transfer information write Transfer information read Vector read ø DTC activation request DTC request Address Figure 8-11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)

Read Write Read WriteAddress ø DTC activation request DTC request Data transfer Data transfer Transfer information write Transfer information write Transfer information read Transfer information read Vector read Figure 8-12 DTC Operation Timing (Example of Chain Transfer)

8.3.10 Number of DTC Execution States

Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status. Table 8-8 DTC Execution Statuses Mode Vector Read I Register Information Read/Write J Data Read K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 N: Block size (initial setting of CRAH and CRAL)

Table 8-9 Number of States Required for Each Execution Status Object to be Accessed On- Chip RAM On- Chip ROM On-Chip I/O Registers External Devices Bus width 32 16 8 16 8 16 Access states 11222323 Vector read S I — 1 — — 4 6+2m 2 3+m Execution status Register S J information read/write Byte data read S K Word data read S K Byte data write SL Word data write SL 3+m 6+2m 3+m 6+2m 3+m 3+m 3+m 3+m Internal operation SM 1 The number of execution states is calculated from the formula below. Note that S means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I · S I + S (J · SJ + K · SK + L · SL ) + M · SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

8.3.11 Procedures for Using DTC

Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested.

8.3.12 Examples of Use of the DTC

(1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. (2) Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). [1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.

[2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. [3] Locate the TPU transfer register information consecutively after the NDR transfer register information. [4] Set the start address of the NDR transfer register information to the DTC vector address. [5] Set the bit corresponding to TGIA in DTCER to 1. [6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. [7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. [8] Set the CST bit in TSTR to 1, and start the TCNT count operation. [9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. [10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. (3) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0).

[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing.

8.4 Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1.

8.5 Usage Notes

Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DMAC Transfer End Interrupt: When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0. DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register.

9.1 Overview

The H8S/2350 Series has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4). Table 9-1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. Ports A to E in the H8S/2351 have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Port 3, and port A in the H8S/2351, have an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports A to E can drive a single TTL load and 90 pF capacitive load, and ports 1, 2, 3, 5, 6, F, and G can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, A, B, and C can drive an LED (10 mA sink current). Port 2, and pins 6 4 to 67 and A4 to A7, are Schmitt-triggered inputs. For block diagrams of the ports see appendix C, I/O Port Block Diagrams.

Port Description Pins Mode 1 Mode 2 *1 Mode 3 *1 Mode 4 Mode 5 Mode 6 *1 Mode 7 *1 Port 1 • 8-bit I/O port P17/PO15/ TIOCB2/ TCLKD 6/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC 4/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB 2/PO10/ TIOCC0/ TCLKA 1/PO9/ TIOCB0/ DACK1 0/PO8/ TIOCA0/ DACK0 8-bit I/O port also functioning as DMA controller output pins (DACK0 and DACK1), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) and PPG output pins (PO15 to PO8) Port 2 • 8-bit I/O port

Schmitt- triggered input 7/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 8-bit I/O port also functioning as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5), and PPG output pins (PO7 to PO0) Port 3 • 6-bit I/O port
Open-drain output capability 5/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 6-bit I/O port also functioning as SCI (channels 0 and 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) Note: 1. Only applies to the H8S/2351.

Table 9-1 Port Functions (cont) Port Description Pins Mode 1 Mode 2 *1 Mode 3 *1 Mode 4 Mode 5 Mode 6 *1 Mode 7 *1 Port 4 • 8-bit input port P47/AN7/ DA1 P46/AN6/ DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs (DA1 and DA0) Port 5 • 4-bit I/O port P53/ADTRG P52 P51 P50 4-bit I/O port also functioning as A/D converter input pin (ADTRG) Port 6 • 8-bit I/O port

Schmitt- triggered input (P6 4 to P67) P67/IRQ3/ CS7 P66/IRQ2/ CS6 P65/IRQ1 P64/IRQ0 P63/TEND1 P62/DREQ1 P61/TEND0/ CS5 P60/DREQ0/ CS4 8-bit I/O port also functioning as DMA controller I/O pins (DREQ0, TEND0, DREQ1, TEND1) and interrupt input pins (IRQ0 to IRQ3) 8-bit I/O port also functioning as DMA controller I/O pins (DREQ0, TEND0, DREQ1, TEND1), bus control output pins (CS4 to CS7), and interrupt input pins (IRQ0 to IRQ3) 8-bit I/O port also function- ing as interrupt input pins (IRQ0 to IRQ3) Note: 1. Only applies to the H8S/2351.

Table 9-1 Port Functions (cont) Port Description Pins Mode 1 Mode 2 *1 Mode 3 *1 Mode 4 Mode 5 Mode 6 *1 Mode 7 *1 Port A • 8-bit I/O port

Built-in MOS input pull-up*
Open-drain output capability*
Schmitt- triggered input (PA to PA7) PA 7/A23/ IRQ7 PA 6/A22/ IRQ6 PA 5/A21/ IRQ5 Dual function as I/O ports and interrupt input pins (IRQ7 to IRQ4) When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ5) When DDR = 1: address output When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ4) Dual function as I/O ports and interrupt input pins (IRQ7 to IRQ4) PA 4/A20/ IRQ4 Address output When DDR = 1: address output PA 3/A19 to PA 0/A16 I/O ports Address output When DDR = 0 (after reset): input ports When DDR = 1: address output I/O ports Port B • 8-bit I/O port*1
Built-in MOS input pull-up* PB 7/A15 to PB 0/A8 Address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O port Address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O port Port C • 8-bit I/O port*1
Built-in MOS input pull-up* PC 7/A7 to PC 0/A0 Address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O port Address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O port Note: 1. Only applies to the H8S/2351.

Table 9-1 Port Functions (cont) Port Description Pins Mode 1 Mode 2 *1 Mode 3 *1 Mode 4 Mode 5 Mode 6 *1 Mode 7 *1 Port D • 8-bit I/O port*1

Built-in MOS input pull-up* PD 7/D15 to PD 0/D8 Data bus input/ output I/O port Data bus input/output I/O port Port E • 8-bit I/O port
Built-in MOS input pull-up* PE 7/D7 to PE 0/D0 In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output I/O port In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output I/O port Port F • 8-bit I/O port PF 7/ø When DDR = 0: input port When DDR = 1 (after reset): ø output When DDR = 0 (after reset): input port When DDR = 1: ø output When DDR = 0: input port When DDR = 1 (after reset): ø output When DDR = 0 (after reset): input port When DDR = 1: ø output PF 6/AS PF 5/RD PF 4/HWR PF 3/LWR AS, RD, HWR, LWR output I/O port AS, RD, HWR, LWR output I/O port PF 2/LCAS/ WAIT/ BREQO When WAITE = 0 and BREQOE = 0 (after reset): I/O port When WAITE = 1 and BREQOE = 0: WAIT input When WAITE = 0 and BREQOE = 1: BREQO input I/O port When WAITE = 0 and BREQOE = 0 (after reset): I/O port When WAITE = 1: and BREQOE = 0: WAIT input When WAITE = 0 and BREQOE = 1: BREQO output When RMTS2 to RMTS0 = B'001 to B'011, CW2 = 0, and LCASS = 0: LCAS output I/O port PF 1/BACK PF 0/BREQ When BRLE = 0 (after reset): I/O port When BRLE = 1: BREQ input, BACK output When BRLE = 0 (after reset): I/O port When BRLE = 1: BREQ input, BACK output Note: 1. Only applies to the H8S/2351.

Table 9-1 Port Functions (cont) Port Description Pins Mode 1 Mode 2 *1 Mode 3 *1 Mode 4 Mode 5 Mode 6 *1 Mode 7 *1 Port G • 5-bit I/O port PG 4/CS0 When DDR= 0 *2: input port When DDR= 1 *3: CS0 output I/O port When DDR = 0*2: input port When DDR = 1*3: CS0 output I/O port PG 3/CS1 PG 2/CS2 PG 1/CS3 I/O port When DDR = 0 (after reset): input port When DDR = 1: CS1, CS2, CS3 output PG 0/CAS DRAM space set: CAS output Otherwise (after reset): I/O port Notes: 1. Only applies to the H8S/2351. 2. After a reset in mode 2 or 6 3. After a reset in mode 1, 4 or 5

9.2 Port 1

9.2.1 Overview

Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1). Port 1 pin functions are the same in all operating modes. Figure 9-1 shows the port 1 pin configuration. P17 (I/O)/PO15 (output)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/PO14 (output)/TIOCA2 (I/O) P15 (I/O)/PO13 (output)/TIOCB1 (I/O)/TCLKC (input) P14 (I/O)/PO12 (output)/TIOCA1 (I/O) P13 (I/O)/PO11 (output)/TIOCD0 (I/O)/TCLKB (input) P12 (I/O)/PO10 (output)/TIOCC0 (I/O)/TCLKA (input) P11 (I/O)/PO9 (output)/TIOCB0 (I/O)/DACK1 (output) P10 (I/O)/PO8 (output)/TIOCA0 (I/O)/DACK0 (output) Port 1 Port 1 pins Figure 9-1 Port 1 Pin Functions

9.2.2 Register Configuration

Table 9-2 shows the port 1 register configuration. Table 9-2 Port 1 Registers Name Abbreviation R/W Initial Value Address * Port 1 data direction register P1DDR W H'00 H'FEB0 Port 1 data register P1DR R/W H'00 H'FF60 Port 1 register PORT1 R Undefined H'FF50 Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) P17DDR W P16DDR W P15DDR W P14DDR W P13DDR W P10DDR W P12DDR W P11DDR W Bit Initial value R/W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the PPG, TPU, and DMAC are initialized by a manual reset, the pin states are determined by the P1DDR and P1DR specifications. Port 1 Data Register (P1DR) P17DR R/W P16DR R/W P15DR R/W P14DR R/W P13DR R/W P10DR R/W P12DR R/W P11DR R/W Bit Initial value R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

Port 1 Register (PORT1) P17 — * R P16 — * R P15 — * R P14 — * R P13 — * R P10 — * R P12 — * R P11 — * R Bit Initial value R/W Note: * Determined by state of pins P1 7 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state after a manual reset, and in software standby mode.

9.2.3 Pin Functions

Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1). Port 1 pin functions are shown in table 9-3. Table 9-3 Port 1 Pin Functions Pin Selection Method and Pin Functions P17/PO15/TIOCB2/ TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bits TPSC2 to TPSC0 in TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR. TPU Channel

2 Setting Table Below (1) Table Below (2)

P17DDR — 0 1 1 NDER15 — — 0 1 Pin function TIOCB2 output P1 7 input P17 output PO15 output TIOCB2 input *1 TCLKD input *2 Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 = 1. 2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. TPU Channel MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-3 Port 1 Pin Functions (cont) Pin Selection Method and Pin Functions P16/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bit NDER14 in NDERH, and bit P16DDR. TPU Channel P16DDR — 0 1 1 NDER14 — — 0 1 Pin function TIOCA2 output P1 6 input P16 output PO14 output TIOCA2 input *1 Note: 1. TIOCA2 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 = 1. TPU Channel MD3 to MD0 B'0000, B'01xx B'001x B'0011 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output *2 PWM mode 2 output x: Don’t care Note: 2. TIOCB2 output is disabled.

Table 9-3 Port 1 Pin Functions (cont) Pin Selection Method and Pin Functions P15/PO13/TIOCB1/ TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR. TPU Channel

1 Setting Table Below (1) Table Below (2)

P15DDR — 0 1 1 NDER13 — — 0 1 Pin function TIOCB1 output P1 5 input P15 output PO13 output TIOCB1 input *1 TCLKC input *2 Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000, B'01xx and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode. TPU Channel MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-3 Port 1 Pin Functions (cont) Pin Selection Method and Pin Functions P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bit NDER12 in NDERH, and bit P14DDR. TPU Channel P14DDR — 0 1 1 NDER12 — — 0 1 Pin function TIOCA1 output P1 4 input P14 output PO12 output TIOCA1 input *1 Note: 1. TIOCA1 input when MD3 to MD0 = B'0000, B'01xx, IOA3 to IOA0 = B'10xx. TPU Channel MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don't care Note: 2. TIOCB1 output is disabled.

Table 9-3 Port 1 Pin Functions (cont) Pin Selection Method and Pin Functions P13/PO11/TIOCD0/ TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR. TPU Channel

0 Setting Table Below (1) Table Below (2)

P13DDR — 0 1 1 NDER11 — — 0 1 Pin function TIOCD0 output P1 3 input P13 output PO11 output TIOCD0 input *1 TCLKB input *2 Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, IOD3 to IOD0 =B'10xx. 2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to TPSC0 = B'101; TCLKB input when channels 1 and 5 are set to phase counting mode. TPU Channel MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'110 B'110 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-3 Port 1 Pin Functions (cont) Pin Selection Method and Pin Functions P12/PO10/TIOCC0/ TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR. TPU Channel P12DDR — 0 1 1 NDER10 — — 0 1 Pin function TIOCC0 output P1 2 input P12 output PO10 output TIOCC0 input *1 TCLKA input *2 Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to TPSC0 = B'100; TCLKA input when channels 1 and 5 are set to phase counting mode. TPU Channel MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOC3 to IOC0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'101 B'101 Output function — Output compare output — PWM mode 1 output*3 PWM mode 2 output x: Don’t care Note: 3. TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies.

Table 9-3 Port 1 Pin Functions (cont) Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ DACK1 The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER9 in NDERH, bit SAE1 in DMABCRH, and bit P11DDR. SAE1 0 1 TPU Channel

0 Setting

Below (1) Table Below (2) P11DDR — 0 1 1 — NDER9 — — 0 1 — Pin function TIOCB0 output P11 input P11 output PO9 output DACK1 output TIOCB0 input *1 Note: 1. TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. TPU Channel MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'010 B'010 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-3 Port 1 Pin Functions (cont) Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ DACK0 The pin function is switched as shown below according to the combination of the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER8 in NDERH, bit SAE0 in DMABCRH, and bit P10DDR. SAE0 0 1 TPU Channel Below (1) Table Below (2) — P10DDR — 0 1 1 — NDER8 — — 0 1 — Pin function TIOCA0 output P10 input P10 output PO8 output DACK0 output TIOCA0 input *1 Note: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. TPU Channel MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'001 B'001 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Note: 2. TIOCB0 output is disabled.

9.3 Port 2

9.3.1 Overview

Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 9-2 shows the port 2 pin configuration. P27 (I/O)/PO7 (output)/TIOCB5 (I/O) P26 (I/O)/PO6 (output)/TIOCA5 (I/O) P25 (I/O)/PO5 (output)/TIOCB4 (I/O) P24 (I/O)/PO4 (output)/TIOCA4 (I/O) P23 (I/O)/PO3 (output)/TIOCD3 (I/O) P22 (I/O)/PO2 (output)/TIOCC3 (I/O) P21 (I/O)/PO1 (output)/TIOCB3 (I/O) P20 (I/O)/PO0 (output)/TIOCA3 (I/O) Port 2 Port 2 pins Figure 9-2 Port 2 Pin Functions

9.3.2 Register Configuration

Table 9-4 shows the port 2 register configuration. Table 9-4 Port 2 Registers Name Abbreviation R/W Initial Value Address* Port 2 data direction register P2DDR W H'00 H'FEB1 Port 2 data register P2DR R/W H'00 H'FF61 Port 2 register PORT2 R Undefined H'FF51 Note: * Lower 16 bits of the address. Port 2 Data Direction Register (P2DDR) P27DDR W P26DDR W P25DDR W P24DDR W P23DDR W P20DDR W P22DDR W P21DDR W Bit Initial value R/W P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the PPG and TPU are initialized by a manual reset, the pin states are determined by the P2DDR and P2DR specifications. Port 2 Data Register (P2DR) P27DR R/W P26DR R/W P25DR R/W P24DR R/W P23DR R/W P20DR R/W P22DR R/W P21DR R/W Bit Initial value R/W P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

Port 2 Register (PORT2) P27 — * R P26 — * R P25 — * R P24 — * R P23 — * R P20 — * R P22 — * R P21 — * R Bit Initial value R/W Note: * Determined by state of pins P2 7 to P20. PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR. If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and P2DR are initialized. PORT2 retains its prior state after a manual reset, and in software standby mode.

9.3.3 Pin Functions

Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Port 2 pin functions are shown in table 9-5. Table 9-5 Port 2 Pin Functions Pin Selection Method and Pin Functions P27/PO7/TIOCB5 The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bit NDER7 in NDERL, and bit P27DDR. TPU Channel

5 Setting

Below (1) Table Below (2) P27DDR — 0 1 1 NDER7 — — 0 1 Pin function TIOCB5 output P27 input P27 output PO7 output TIOCB5 input * Note: * TIOCB5 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 = 1. TPU Channel MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-5 Port 2 Pin Functions (cont) Pin Selection Method and Pin Functions P26/PO6/TIOCA5 The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bit NDER6 in NDERL, and bit P26DDR. TPU Channel Below (1) Table Below (2) P26DDR — 0 1 1 NDER6 — — 0 1 Pin function TIOCA5 output P26 input P26 output PO6 output TIOCA5 input *1 Note: 1. TIOCA5 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 = 1. TPU Channel MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Note: 2. TIOCB5 output is disabled.

Table 9-5 Port 2 Pin Functions (cont) Pin Selection Method and Pin Functions P25/PO5/TIOCB4 The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER5 in NDERL, and bit P25DDR. TPU Channel

4 Setting Table Below (1) Table Below (2)

P25DDR — 0 1 1 NDER5 — — 0 1 Pin function TIOCB4 output P2 5 input P25 output PO5 output TIOCB4 input *1 Note: 1. TIOCB4 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 to IOB0 = B'10xx. TPU Channel MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-5 Port 2 Pin Functions (cont) Pin Selection Method and Pin Functions P24/PO4/TIOCA4 The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER4 in NDERL, and bit P24DDR. TPU Channel P24DDR — 0 1 1 NDER4 — — 0 1 Pin function TIOCA4 output P2 4 input P24 output PO4 output TIOCA4 input *1 TMRI1 input Note: 1. TIOCA4 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 to IOA0 = B'10xx. TPU Channel MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Note: 2. TIOCB4 output is disabled.

Table 9-5 Port 2 Pin Functions (cont) Pin Selection Method and Pin Functions P23/PO3/TIOCD3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER3 in NDERL, and bit P23DDR. TPU Channel

3 Setting Table Below (1) Table Below (2)

P23DDR — 0 1 1 NDER3 — — 0 1 Pin function TIOCD3 output P2 3 input P23 output PO3 output TIOCD3 input *1 Note: 1. TIOCD3 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. TPU Channel MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'110 B'110 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-5 Port 2 Pin Functions (cont) Pin Selection Method and Pin Functions P22/PO2/TIOCC3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER2 in NDERL, and bit P22DDR. TPU Channel P22DDR — 0 1 1 NDER2 — — 0 1 Pin function TIOCC3 output P2 2 input P22 output PO2 output TIOCC3 input *1 Note: 1. TIOCC3 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. TPU Channel MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOC3 to IOC0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'101 B'101 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Note: 2. TIOCD3 output is disabled. When BFA = 1 or BFB = 1 in TMDR3, output is disabled and setting (2) applies.

Table 9-5 Port 2 Pin Functions (cont) Pin Selection Method and Pin Functions P21/PO1/TIOCB3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER1 in NDERL, and bit P21DDR. TPU Channel P21DDR — 0 1 1 NDER1 — — 0 1 Pin function TIOCB3 output P2 1 input P21 output PO1 output TIOCB3 input *1 Note: 1. TIOCB3 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. TPU Channel MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'010 B'010 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Table 9-5 Port 2 Pin Functions (cont) Pin Selection Method and Pin Functions P20/PO0/TIOCA3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER0 in NDERL, and bit P20DDR. TPU Channel P20DDR — 0 1 1 NDER0 — — 0 1 Pin function TIOCA3 output P2 0 input P20 output PO0 output TIOCA3 input *1 Note: 1. TIOCA3 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. TPU Channel MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'001 B'001 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Note: 2. TIOCB3 output is disabled.

9.4 Port 3

9.4.1 Overview

Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are the same in all operating modes. Figure 9-3 shows the port 3 pin configuration. P35 P34 P33 P32 P31 P30 (I/O)/ (I/O)/ (I/O)/ (I/O)/ (I/O)/ (I/O)/ SCK1 (I/O) SCK0 (I/O) RxD1 (input) RxD0 (input) TxD1 (output) TxD0 (output) Port 3 pins Port 3 Figure 9-3 Port 3 Pin Functions

9.4.2 Register Configuration

Table 9-6 shows the port 3 register configuration. Table 9-6 Port 3 Registers Name Abbreviation R/W Initial Value *2 Address*1 Port 3 data direction register P3DDR W H'00 H'FEB2 Port 3 data register P3DR R/W H'00 H'FF62 Port 3 register PORT3 R Undefined H'FF52 Port 3 open drain control register P3ODR R/W H'00 H'FF76 Notes: 1. Lower 16 bits of the address. 2. Value of bits 5 to 0.

Port 3 Data Direction Register (P3DDR) Undefined Undefined P35DDR W P34DDR W P33DDR W P30DDR W P32DDR W P31DDR W Bit Initial value R/W P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read. Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and P3DR specifications. Port 3 Data Register (P3DR) Undefined Undefined P35DR R/W P34DR R/W P33DR R/W P30DR R/W P32DR R/W P31DR R/W Bit Initial value R/W P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. P3DR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

Port 3 Register (PORT3) Undefined Undefined P35 — * R P34 — * R P33 — * R P30 — * R P32 — * R P31 — * R Bit Initial value R/W Note: * Determined by state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and P3DR are initialized. PORT3 retains its prior state after a manual reset, and in software standby mode. Port 3 Open Drain Control Register (P3ODR) Undefined Undefined P35ODR R/W P34ODR R/W P33ODR R/W P30ODR R/W P32ODR R/W P31ODR R/W Bit Initial value R/W P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

9.4.3 Pin Functions

Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are shown in table 9-7. Table 9-7 Port 3 Pin Functions Pin Selection Method and Pin Functions P35/SCK1 The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR. CKE1 0 1 C/A 01 — CKE0 0 1 — — P35DDR 0 1 — — — Pin function P3 5 input pin P35 output pin* SCK1 output pin* SCK1 output pin* SCK1 input pin Note: * When P35ODR = 1, the pin becomes an NMOS open-drain output. P34/SCK0 The pin function is switched as shown below according to the combination of bit C/A in the SCI0 SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 0 1 C/A 01 — CKE0 0 1 — — P34DDR 0 1 — — — Pin function P3 4 input pin P34 output pin* SCK0 output pin* SCK0 output pin* SCK0 input pin Note: * When P34ODR = 1, the pin becomes an NMOS open-drain output.

Table 9-7 Port 3 Pin Functions (cont) Pin Selection Method and Pin Functions P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE 0 1 P33DDR 0 1 — Pin function P3 3 input pin P3 3 output pin* RxD1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. P32/RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR. RE 0 1 P32DDR 0 1 — Pin function P3 2 input pin P3 2 output pin* RxD0 input pin Note: * When P32ODR = 1, the pin becomes an NMOS open-drain output. P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in the SCI1 SCR, and bit P31DDR. TE 0 1 P31DDR 0 1 — Pin function P3 1 input pin P3 1 output pin* TxD1 output pin Note: * When P31ODR = 1, the pin becomes an NMOS open-drain output. P30/TxD0 The pin function is switched as shown below according to the combination of bit TE in the SCI0 SCR, and bit P30DDR. TE 0 1 P30DDR 0 1 — Pin function P3 0 input pin P3 0 output pin* TxD0 output pin Note: * When P30ODR = 1, the pin becomes an NMOS open-drain output.

9.5 Port 4

9.5.1 Overview

Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 9-4 shows the port 4 pin configuration. P47 P46 P45 P44 P43 P42 P41 P40 (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ AN7 (input)/DA1 (output) AN6 (input)/DA0 (output) AN5 (input) AN4 (input) AN3 (input) AN2 (input) AN1 (input) AN0 (input) Port 4 pins Port 4 Figure 9-4 Port 4 Pin Functions

9.5.2 Register Configuration

Table 9-8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9-8 Port 4 Registers Name Abbreviation R/W Initial Value Address* Port 4 register PORT4 R Undefined H'FF53 Note: * Lower 16 bits of the address. Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed. P47 — * R P46 — * R P45 — * R P44 — * R P43 — * R P40 — * R P42 — * R P41 — * R Bit Initial value R/W Note: * Determined by state of pins P47 to P40.

9.5.3 Pin Functions

Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1).

9.6 Port 5

9.6.1 Overview

Port 5 is a 4-bit I/O port. Port 5 pins also function as the A/D converter input pin (ADTRG). Port 5 pin functions are the same in all operating modes. Figure 9-5 shows the port 5 pin configuration. P53 (I/O)/ADTRG (input) P52 (I/O) P51 (I/O) P50 (I/O) Port 5 pins Port 5 Figure 9-5 Port 5 Pin Functions

9.6.2 Register Configuration

Table 9-9 shows the port 5 register configuration. Table 9-9 Port 5 Registers Name Abbreviation R/W Initial Value *2 Address*1 Port 5 data direction register P5DDR W H'0 H'FEB4 Port 5 data register P5DR R/W H'0 H'FF64 Port 5 register PORT5 R Undefined H'FF54 Notes: 1. Lower 16 bits of the address. 2. Value of bits 3 to 0.

Port 5 Data Direction Register (P5DDR) Undefined Undefined Undefined Undefined P53DDR W P50DDR W P52DDR W P51DDR W Bit Initial value R/W P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be read. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port 5 Data Register (P5DR) Undefined Undefined Undefined Undefined P53DR R/W P50DR R/W P52DR R/W P51DR R/W Bit Initial value R/W P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P53 to P50). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. P5DR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port 5 Register (PORT5) Undefined Undefined Undefined Undefined P53 — * R P50 — * R P52 — * R P51 — * R Bit Initial value R/W Note: * Determined by state of pins P53 to P50. PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 5 pins (P53 to P50) must always be performed on P5DR.

Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT5 contents are determined by the pin states, as P5DDR and P5DR are initialized. PORT5 retains its prior state after a manual reset, and in software standby mode.

9.6.3 Pin Functions

Port 5 pins also function as the A/D converter input pin (ADTRG). Port 5 pin functions are shown in table 9-10. Table 9-10 Port 5 Pin Functions Pin Selection Method and Pin Functions P53/ADTRG The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in the A/D converter ADCR, and bit P53DDR. P53DDR 0 1 Pin function P5 3 input pin P5 3 output pin ADTRG input pin* Note: * ADTRG input when TRGS0 = TRGS1 = 1. P52 The pin function is switched as shown below according to bit P52DDR. P52DDR 0 1 Pin function P5 2 input pin P5 2 output pin P51 The pin function is switched as shown below according to bit P51DDR. P51DDR 0 1 Pin function P5 1 input pin P5 1 output pin P50 The pin function is switched as shown below according to bit P50DDR. P50DDR 0 1 Pin function P5 0 input pin P5 0 output pin

9.7 Port 6

9.7.1 Overview

Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). The functions of pins P65 to P62 are the same in all operating modes, while the functions of pins P67, P66, P61, and P60 change according to the operating mode. Pins P67 to P64 are schmitt-triggered inputs. Figure 9-6 shows the port 6 pin configuration. P67/IRQ3/CS7/CR P66/IRQ2/CS6 P65/IRQ1 P64/IRQ0 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 P60/DREQ0/CS4 P67 (I/O)/IRQ3 (input) P66 (I/O)/IRQ2 (input) P65 (I/O)/IRQ1 (input) P64 (I/O)/IRQ0 (input) P63 (I/O)/TEND1 (output) P62 (I/O)/DREQ1 (input) P61 (I/O)/TEND0 (output) P60 (I/O)/DREQ0 (input) /CR /CR /CR /CR /CR /CR /CR /CR Port 6 pins Pin functions in modes 1, 2, 3, and 7 * 7 (input)/IRQ3 (input)/CS7 (output) P66 (input)/IRQ2 (input)/CS6 (output) P65 (I/O)/IRQ1 (input) P64 (I/O)/IRQ0 (input) P63 (I/O)/TEND1 (output) P62 (I/O)/DREQ1 (input) P61 (input)/TEND0 (output)/CS5 (output) P60 (input)/DREQ0 (input)/CS4 (output) /CR /CR /CR /CR /CR /CR /CR Pin functions in modes 4 to 6* /CR /CR /CR /CR /CR /CR /CR /CR Port 6 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-6 Port 6 Pin Functions

9.7.2 Register Configuration

Table 9-11 shows the port 6 register configuration. Table 9-11 Port 6 Registers Name Abbreviation R/W Initial Value Address * Port 6 data direction register P6DDR W H'00 H'FEB5 Port 6 data register P6DR R/W H'00 H'FF65 Port 6 register PORT6 R Undefined H'FF55 Note: * Lower 16 bits of the address. Port 6 Data Direction Register (P6DDR) P67DDR W P66DDR W P65DDR W P64DDR W P63DDR W P60DDR W P62DDR W P61DDR W Bit Initial value R/W P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P6DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the DMAC is initialized by a manual reset, the pin states are determined by the P6DDR and P6DR specifications. Port 6 Data Register (P6DR) P67DR R/W P66DR R/W P65DR R/W P64DR R/W P63DR R/W P60DR R/W P62DR R/W P61DR R/W Bit Initial value R/W P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). P6DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

Port 6 Register (PORT6) P67 — * R P66 — * R P65 — * R P64 — * R P63 — * R P60 — * R P62 — * R P61 — * R Bit Initial value RW Note: * Determined by state of pins P67 to P60. PORT6 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 6 pins (P67 to P60) must always be performed on P6DR. If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT6 contents are determined by the pin states, as P6DDR and P6DR are initialized. PORT6 retains its prior state after a manual reset, and in software standby mode.

9.7.3 Pin Functions

Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). Port 6 pin functions are shown in table 9-12. Table 9-12 Port 6 Pin Functions Pin Selection Method and Pin Functions P67/IRQ3/CS7 The pin function is switched as shown below according to bit P67DDR. Mode Modes 1, 2, 3, 7 * Modes 4 to 6* P67DDR 0 1 0 1 Pin function P6 7 input pin P67 output pin P67 input pinCS7 output pin IRQ3 interrupt input pin P66/IRQ2/CS6 The pin function is switched as shown below according to bit P66DDR. Mode Modes 1, 2, 3, 7 * Modes 4 to 6* P66DDR 0 1 0 1 Pin function P6 6 input pin P66 output pin P66 input pinCS6 output pin IRQ2 interrupt input pin P65/IRQ1 The pin function is switched as shown below according to bit P65DDR. P65DDR 0 1 Pin function P6 5 input pin P6 5 output pin IRQ1 interrupt input pin P64/IRQ0 The pin function is switched as shown below according to bit P64DDR. P64DDR 0 1 Pin function P6 4 input pin P6 4 output pin IRQ0 interrupt input pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.

Table 9-12 Port 6 Pin Functions (cont) Pin Selection Method and Pin Functions P63/TEND1 The pin function is switched as shown below according to the combination of bit TEE1 in the DMAC DMATCR, and bit P63DDR. TEE1 0 1 P63DDR 0 1 — Pin function P6 3 input pin P6 3 output pin TEND1 output P62/DREQ1 The pin function is switched as shown below according to bit P62DDR. P62DDR 0 1 Pin function P6 2 input pin P6 2 output pin DERQ1 input P61/TEND0/CS5 The pin function is switched as shown below according to the combination of bit TEE0 in the DMAC DMATCR, and bit P61DDR. Mode Modes 1, 2, 3, 7 * Modes 4 to 6* TEE0 0 1 0 1 P61DDR 0 1 — 0 1 — Pin function P6 1 input pin P61 output pin TEND0 output P61 input pin CS5 output pin TEND0 output P60/DREQ0/CS4 The pin function is switched as shown below according to bit P60DDR. Mode Modes 1, 2, 3, 7 * Modes 4 to 6* P60DDR 0 1 0 1 Pin function P6 0 input pin P60 output pin P60 input pinCS4 output pin DREQ0 input Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.

9.8 Port A

9.8.1 Overview

Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and interrupt input pins (IRQ4 to IRQ7). The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Pins PA7 to PA4 are schmitt-triggered inputs. Figure 9-7 shows the port A pin configuration. PA 7/A23/IRQ7 PA 6/A22/IRQ6 PA 5/A21/IRQ5 PA 4/A20/IRQ4/CR PA 3/A19 PA 2/A18 PA 1/A17 PA 0/A16 PA 7 (input)/A23(output)/IRQ7 (input) PA 6 (input)/A22(output)/IRQ6 (input) PA 5 (input)/A21 (output)/IRQ5 (input) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) Port A pins Pin functions in modes 4 and 5* Pin functions in mode 6* PA 7 (I/O)/IRQ7 (input) PA 6 (I/O)/IRQ6 (input) PA 5 (I/O)/IRQ5 (input) PA 4 (I/O)/IRQ4 (input) PA 3 (I/O) PA 2 (I/O) PA 1 (I/O) PA 0 (I/O) Pin functions in modes 1, 2, 3, and 7* PA 7 (input)/A23 (output)/IRQ7 (input) PA 6 (input)/A22 (output)/IRQ6 (input) PA 5 (input)/A21 (output)/IRQ5 (input) PA 4 (input)/A20 (output)/IRQ4 (input) PA 3 (input)/A19 (output) PA 2 (input)/A18 (output) PA 1 (input)/A17 (output) PA 0 (input)/A16 (output) Port A Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-7 Port A Pin Functions

9.8.2 Register Configuration

Table 9-13 shows the port A register configuration. Table 9-13 Port A Registers Name Abbreviation R/W Initial Value Address *1 Port A data direction register PADDR W H'00 H'FEB9 Port A data register PADR R/W H'00 H'FF69 Port A register PORTA R Undefined H'FF59 Port A MOS pull-up control register*2 PAPCR R/W H'00 H'FF70 Port A open-drain control register*2 PAODR R/W H'00 H'FF77 Notes: 1. Lower 16 bits of the address. 2. Only applies to the H8S/2351. Port A Data Direction Register (PADDR) PA7DDR W PA6DDR W PA5DDR W PA4DDR W PA3DDR W PA0DDR W PA2DDR W PA1DDR W Bit Initial value R/W PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Modes 1, 2, 3, and 7* Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port.
Modes 4 and 5 The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to PA0DDR. Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port.

Mode 6* Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the pin an input port. Note: * Modes 2 3, 6, and 7 only applies to the H8S/2351. Port A Data Register (PADR) PA7DR R/W PA6DR R/W PA5DR R/W PA4DR R/W PA3DR R/W PA0DR R/W PA2DR R/W PA1DR R/W Bit Initial value R/W PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA 0). PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Register (PORTA) PA7 — * R PA6 — * R PA5 — * R PA4 — * R PA3 — * R PA0 — * R PA2 — * R PA1 — * R Bit Initial value R/W Note: * Determined by state of pins PA 7 to PA0. PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA7 to PA0) must always be performed on PADR. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset, and in software standby mode.

Port A MOS Pull-Up Control Register (PAPCR) [H8S/2351 Only] PA7PCR R/W PA6PCR R/W PA5PCR R/W PA4PCR R/W PA3PCR R/W PA0PCR R/W PA2PCR R/W PA1PCR R/W Bit Initial value R/W PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. All the bits are valid in modes 1, 2, 3, 6, and 7, and bits 7 to 5 are valid in modes 4 and 5. When a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PAPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Open Drain Control Register (PAODR) [H8S/2351 Only] PA7ODR R/W PA6ODR R/W PA5ODR R/W PA4ODR R/W PA3ODR R/W PA0ODR R/W PA2ODR R/W PA1ODR R/W Bit Initial value R/W PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA7 to PA0). All bits are valid in modes 1, 2, 3, and 7. Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

9.8.3 Pin Functions

Mode 1 [H8S/2350]; Modes 1, 2, 3 and 7 [H8S/2351]: In mode 1, 2, 3, and 7*, port A pins function as I/O ports and interrupt input pins. Input or output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A pin functions in modes 1, 2, 3, and 7* are shown in figure 9-8. Note: * Modes 2, 3, and 7 only apply to the H8S/2351. PA 7 (I/O)/IRQ7 (input) PA 6 (I/O)/IRQ6 (input) PA 5 (I/O)/IRQ5 (input) PA 4 (I/O)/IRQ4 (input) PA 3 (I/O) PA 2 (I/O) PA 1 (I/O) PA 0 (I/O) Port A Figure 9-8 Port A Pin Functions (Modes 1, 2, 3, and 7)

9.8.4 MOS Input Pull-Up Function [H8S/2351 Only]

Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA7 to PA5 in modes 4 and 5, and by all pins in modes 1, 2, 3, 6, and 7. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-14 summarizes the MOS input pull-up states. Table 9-14 MOS Input Pull-Up States (Port A) Modes Power-On Reset Hardware Standby Mode Manual Reset Software Standby Mode In Other Operations 1 to 3, 6, 7 PA7 to PA0 OFF ON/OFF 4, 5 PA 7 to PA5 ON/OFF PA 4 to PA0 OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PADDR = 0 and PAPCR = 1; otherwise off.

9.9 Port B

9.9.1 Overview

Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. However, in the H8S/2350, port B pins function only as address outputs. Port B has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Figure 9-11 shows the port B pin configuration. PB 7/A15 PB 6/A14 PB 5/A13 PB 4/A12 PB 3/A11 PB 2/A10 PB 1/A9 PB 0/A8 PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ A A14 A13 A12 A11 A10 (output) (output) (output) (output) (output) (output) (output) (output) Port B pins Pin functions in modes 2 and 6* Pin functions in modes 3 and 7* A A14 A13 A12 A11 A10 (output) (output) (output) (output) (output) (output) (output) (output) Pin functions in modes 1, 4, and 5 PB PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Port B Figure 9-11 Port B Pin Functions

9.9.2 Register Configuration [H8S/2351 Only]

Table 9-15 shows the port B register configuration. Table 9-15 Port B Registers Name Abbreviation R/W Initial Value Address * Port B data direction register PBDDR W H'00 H'FEBA Port B data register PBDR R/W H'00 H'FF6A Port B register PORTB R Undefined H'FF5A Port B MOS pull-up control register PBPCR R/W H'00 H'FF71 Note: * Lower 16 bits of the address. Port B Data Direction Register (PBDDR) [H8S/2351 Only] PB7DDR W PB6DDR W PB5DDR W PB4DDR W PB3DDR W PB0DDR W PB2DDR W PB1DDR W Bit Initial value R/W PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Modes 1, 4, and 5 The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Modes 2 and 6 Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port.
Modes 3 and 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port.

Port B Data Register (PBDR) [H8S/2351 Only] PB7DR R/W PB6DR R/W PB5DR R/W PB4DR R/W PB3DR R/W PB0DR R/W PB2DR R/W PB1DR R/W Bit Initial value R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port B Register (PORTB) [H8S/2351 Only] PB7 — * R PB6 — * R PB5 — * R PB4 — * R PB3 — * R PB0 — * R PB2 — * R PB1 — * R Bit Initial value R/W Note: * Determined by state of pins PB 7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state after a manual reset, and in software standby mode.

Port B MOS Pull-Up Control Register (PBPCR) [H8S/2351 Only] PB7PCR R/W PB6PCR R/W PB5PCR R/W PB4PCR R/W PB3PCR R/W PB0PCR R/W PB2PCR R/W PB1PCR R/W Bit Initial value R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. When a PBDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

9.9.3 Pin Functions

Modes 1, 4, and 5: In modes 1, 4, and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 1, 4, and 5 are shown in figure 9-12. A15 A14 A13 A12 A11 A10 (output) (output) (output) (output) (output) (output) (output) (output) Port B Figure 9-12 Port B Pin Functions (Modes 1, 4, and 5)

9.9.4 MOS Input Pull-Up Function [H8S/2351 Only]

Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PBDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-16 summarizes the MOS input pull-up states. Table 9-16 MOS Input Pull-Up States (Port B) Modes Power-On Reset Hardware Standby Mode Manual Reset Software Standby Mode In Other Operations 1, 4, 5 OFF OFF 2, 3, 6, 7 ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PBDDR = 0 and PBPCR = 1; otherwise off.

9.10 Port C

9.10.1 Overview

Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. However, in the H8S/2350, port C pins function only as address outputs. Port C has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 Only). Figure 9-15 shows the port C pin configuration. PC 7/A7 PC 6/A6 PC 5/A5 PC 4/A4 PC 3/A3 PC 2/A2 PC 1/A1 PC 0/A0 Port C PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ A (output) (output) (output) (output) (output) (output) (output) (output) Port C pins Pin functions in modes 2 and 6* Pin functions in modes 3 and 7* A (output) (output) (output) (output) (output) (output) (output) (output) Pin functions in modes 1, 4, and 5 PC PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Figure 9-15 Port C Pin Functions

9.10.2 Register Configuration [H8S/2351 Only]

Table 9-17 shows the port C register configuration. Table 9-17 Port C Registers Name Abbreviation R/W Initial Value Address * Port C data direction register PCDDR W H'00 H'FEBB Port C data register PCDR R/W H'00 H'FF6B Port C register PORTC R Undefined H'FF5B Port C MOS pull-up control register PCPCR R/W H'00 H'FF72 Note: * Lower 16 bits of the address. Port C Data Direction Register (PCDDR) [H8S/2351 Only] PC7DDR W PC6DDR W PC5DDR W PC4DDR W PC3DDR W PC0DDR W PC2DDR W PC1DDR W Bit Initial value R/W PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Modes 1, 4, and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
Modes 2 and 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port.
Modes 3 and 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port.

Port C Data Register (PCDR) [H8S/2351 Only] PC7DR R/W PC6DR R/W PC5DR R/W PC4DR R/W PC3DR R/W PC0DR R/W PC2DR R/W PC1DR R/W Bit Initial value R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port C Register (PORTC) [H8S/2351 Only] PC7 — * R PC6 — * R PC5 — * R PC4 — * R PC3 — * R PC0 — * R PC2 — * R PC1 — * R Bit Initial value R/W Note: * Determined by state of pins PC 7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state after a manual reset, and in software standby mode.

Port C MOS Pull-Up Control Register (PCPCR) [H8S/2351] PC7PCR R/W PC6PCR R/W PC5PCR R/W PC4PCR R/W PC3PCR R/W PC0PCR R/W PC2PCR R/W PC1PCR R/W Bit Initial value R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. When a PCDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

9.10.3 Pin Functions

Modes 1, 4, and 5: In modes 1, 4, and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 1, 4, and 5 are shown in figure 9-16. (output) (output) (output) (output) (output) (output) (output) (output) Port C Figure 9-16 Port C Pin Functions (Modes 1, 4, and 5)

9.10.4 MOS Input Pull-Up Function [H8S/2351 Only]

Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PCDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-18 summarizes the MOS input pull-up states. Table 9-18 MOS Input Pull-Up States (Port C) Modes Power-On Reset Hardware Standby Mode Manual Reset Software Standby Mode In Other Operations 1, 4, 5 OFF OFF 2, 3, 6, 7 ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PCDDR = 0 and PCPCR = 1; otherwise off.

9.11 Port D

9.11.1 Overview

Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. However, in the H8S/2350, port D pins function only as data bus pins. Port D has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Figure 9-19 shows the port D pin configuration. PD 7/D15 PD 6/D14 PD 5/D13 PD 4/D12 PD 3/D11 PD 2/D10 PD 1/D9 PD 0/D8 Port D Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Port D pins Pin functions in modes 1, 2, 4, 5, and 6 * PD PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Pin functions in modes 3 and 7* Figure 9-19 Port D Pin Functions

9.11.2 Register Configuration [H8S/2351 Only]

Table 9-19 shows the port D register configuration. Table 9-19 Port D Registers Name Abbreviation R/W Initial Value Address * Port D data direction register PDDDR W H'00 H'FEBC Port D data register PDDR R/W H'00 H'FF6C Port D register PORTD R Undefined H'FF5C Port D MOS pull-up control register PDPCR R/W H'00 H'FF73 Note: * Lower 16 bits of the address. Port D Data Direction Register (PDDDR) [H8S/2351 Only] PD7DDR W PD6DDR W PD5DDR W PD4DDR W PD3DDR W PD0DDR W PD2DDR W PD1DDR W Bit Initial value R/W PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.. PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

Modes 1, 2, 4, 5, and 6 The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O.
Modes 3 and 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.

Port D Data Register (PDDR) [H8S/2351 Only] PD7DR R/W PD6DR R/W PD5DR R/W PD4DR R/W PD3DR R/W PD0DR R/W PD2DR R/W PD1DR R/W Bit Initial value R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD 0). PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port D Register (PORTD) [H8S/2351 Only] PD7 R PD6 R PD5 R PD4 R PD3 R PD0 R PD2 R PD1 R Bit Initial value R/W Note: * Determined by state of pins PD 7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state after a manual reset, and in software standby mode.

Port D MOS Pull-Up Control Register (PDPCR) [H8S/2351 Only] PD7PCR R/W PD6PCR R/W PD5PCR R/W PD4PCR R/W PD3PCR R/W PD0PCR R/W PD2PCR R/W PD1PCR R/W Bit Initial value R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

9.11.3 Pin Functions

Modes 1, 4, and 5 [H8S/2351]; Modes 1, 2, 4, 5, and 6 [H8S/2351]: In modes 1, 2, 4, 5, and 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 9-20. D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 Port D (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Figure 9-20 Port D Pin Functions (Modes 1, 2, 4, 5, and 6) Modes 3 and 7 [H8S/2351 Only]: In modes 3 and 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.

Port D pin functions in modes 3 and 7 are shown in figure 9-21. PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 Port D (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Figure 9-21 Port D Pin Functions (Modes 3 and 7)

9.11.4 MOS Input Pull-Up Function [H8S/2351 Only]

Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 3 and 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-20 summarizes the MOS input pull-up states. Table 9-20 MOS Input Pull-Up States (Port D) Modes Power-On Reset Hardware Standby Mode Manual Reset Software Standby Mode In Other Operations 1, 2, 4 to 6 OFF OFF 3, 7 ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PDDDR = 0 and PDPCR = 1; otherwise off.

9.12 Port E

9.12.1 Overview

Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Figure 9-22 shows the port E pin configuration. PE 7/D7 PE 6/D6 PE 5/D5 PE 4/D4 PE 3/D3 PE 2/D2 PE 1/D1 PE 0/D0 PE 7 PE 6 PE 5 PE 4 PE 3 PE 2 PE 1 PE 0 (I/O)/ (I/O)/ (I/O)/ (I/O)/ (I/O)/ (I/O)/ (I/O)/ (I/O)/ Port E pins Pin functions in modes 1, 2, 4, 5, and 6 * Pin functions in modes 3 and 7* D D 6 D 5 D 4 D 3 D 2 D 1 D 0 (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) PE PE 6 PE 5 PE 4 PE 3 PE 2 PE 1 PE 0 (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Port E Note: * Modes 2, 3, 6, and 7 onl y apply to the H8S/2351. Figure 9-22 Port E Pin Functions

9.12.2 Register Configuration

Table 9-21 shows the port E register configuration. Table 9-21 Port E Registers Name Abbreviation R/W Initial Value Address *1 Port E data direction register PEDDR W H'00 H'FEBD Port E data register PEDR R/W H'00 H'FF6D Port E register PORTE R Undefined H'FF5D Port E MOS pull-up control register*2 PEPCR R/W H'00 H'FF74 Notes: 1. Lower 16 bits of the address. 2. Only applies to the H8S/2351. Port E Data Direction Register (PEDDR) PE7DDR W PE6DDR W PE5DDR W PE4DDR W PE3DDR W PE0DDR W PE2DDR W PE1DDR W Bit Initial value R/W PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

Modes 1, 4, 5 [H8S/2350]; modes 1, 2, 4, 5, and 6 [H8S/2351] When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
Modes 3 and 7 [H8S/2351 only] Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.

Port E Data Register (PEDR) PE7DR R/W PE6DR R/W PE5DR R/W PE4DR R/W PE3DR R/W PE0DR R/W PE2DR R/W PE1DR R/W Bit Initial value R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port E Register (PORTE) PE7 R PE6 R PE5 R PE4 R PE3 R PE0 R PE2 R PE1 R Bit Initial value R/W Note: * Determined by state of pins PE 7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state after a manual reset, and in software standby mode. Port E MOS Pull-Up Control Register (PEPCR) [H8S/2351 Only] PE7PCR R/W PE6PCR R/W PE5PCR R/W PE4PCR R/W PE3PCR R/W PE0PCR R/W PE2PCR R/W PE1PCR R/W Bit Initial value R/W PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis.

When a PEDDR bit is cleared to 0 (input port setting) when 8-bit bus mode is selected in mode 1, 2, 4, 5, or 6, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode.

9.12.3 Pin Functions

Modes 1, 4, and 5 [H8S/2350]; Modes 1, 2, 4, 5, and 6 [H8S/2351]: In modes 1, 2, 4, 5, and 6, when 8-bit access is designated and 8-bit bus mode is selected, port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. Port E pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 9-23. PE 7 PE 6 PE 5 PE 4 PE 3 PE 2 PE 1 PE 0 Port E D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) 8-bit bus mode 16-bit bus mode (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Figure 9-23 Port E Pin Functions (Modes 1, 2, 4, 5, and 6) Modes 3 and 7 [H8S/2351 Only]: In modes 3 and 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.

Port E pin functions in modes 3 and 7 are shown in figure 9-24. PE 7 PE 6 PE 5 PE 4 PE 3 PE 2 PE 1 PE 0 Port E (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Figure 9-24 Port E Pin Functions (Modes 3 and 7)

9.12.4 MOS Input Pull-Up Function [H8S/2351 Only]

Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 1, 2, 4, 5, and 6 when 8-bit bus mode is selected, or in mode 3 or 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 1, 2, 4, 5, or 6 when 8-bit bus mode is selected, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-22 summarizes the MOS input pull-up states. Table 9-22 MOS Input Pull-Up States (Port E) Modes Power-On Reset Hardware Standby Mode Manual Reset Software Standby Mode In Other Operations 3, 7 OFF ON/OFF 1, 2, 4 to 6 8-bit bus 16-bit bus OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PEDDR = 0 and PEPCR = 1; otherwise off.

9.13 Port F

9.13.1 Overview

Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. Figure 9-25 shows the port F pin configuration. PF 7/ø PF 6/AS PF 5/RD PF 4/HWR PF 3/LWR PF 2/LCAS/WAIT/BREQO PF 1/BACK/CR PF 0/BREQ Port F PF 7 AS RD HWR LWR PF PF 1 PF 0 (input) / (output) (output) (output) (output) (I/O)/ (I/O)/ (I/O)/ Port F pins Pin functions in modes 1 and 2 * PF PF 6 PF 5 PF 4 PF 3 PF 2 PF 1 PF 0 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. (input)/ (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) Pin functions in modes 3 and 7* ø WAIT BACK BREQ (input) (output) (input) /BREQO (output) ø (output) (output) PF AS RD HWR LWR PF PF 1 PF 0 (input) / (output) (output) (output) (output) (I/O)/ LCAS (I/O)/ BACK (output) (I/O)/ BREQ Pin functions in modes 4 to 6* (output) /WAIT (input) /BREQO (output) (input) ø (output) Figure 9-25 Port F Pin Functions

9.13.2 Register Configuration

Table 9-23 shows the port F register configuration. Table 9-23 Port F Registers Name Abbreviation R/W Initial Value Address *1 Port F data direction register PFDDR W H'80/H'00 *2 H'FEBE Port F data register PFDR R/W H'00 H'FF6E Port F register PORTF R Undefined H'FF5E Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode. Port F Data Direction Register (PFDDR) PF7DDR W W PF6DDR W W PF5DDR W W PF4DDR W W PF3DDR W W PF0DDR W W PF2DDR W W PF1DDR W W Bit Modes 1, 2, 4, 5, 6 Initial value R/W Modes 3 and 7 Initial value R/W PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2, 4, 5, and 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Modes 1, 4, and 5 [H8S/2350]; modes 1, 2, 4, 5, and 6 [H8S/2351] Pin PF 7 functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are automatically designated as bus control outputs (AS, RD, HWR, and LWR).

Pins PF2 to PF0 are designated as bus control input/output pins (LCAS, WAIT, BREQO, BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port.

Modes 3 and 7 [H8S/2351 only] Setting a PFDDR bit to 1 makes the corresponding port F pin PF 6 to PF0 an output port, or in the case of pin PF7, the ø output pin. Clearing the bit to 0 makes the pin an input port. Port F Data Register (PFDR) PF7DR R/W PF6DR R/W PF5DR R/W PF4DR R/W PF3DR R/W PF0DR R/W PF2DR R/W PF1DR R/W Bit Initial value R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port F Register (PORTF) PF7 — * R PF6 — * R PF5 — * R PF4 — * R PF3 — * R PF0 — * R PF2 — * R PF1 — * R Bit Initial value R/W Note: * Determined by state of pins PF 7 to PF0. PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and in software standby mode.

9.13.3 Pin Functions

Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. The pin functions differ between modes 1, 2, 4, 5, and 6, and modes 3 and 7. Port F pin functions are shown in table 9-24. Table 9-24 Port F Pin Functions Pin Selection Method and Pin Functions PF 7/ø The pin function is switched as shown below according to bit PF7DDR. PF7DDR 0 1 Pin function PF 7 input pin ø output pin PF 6/AS The pin function is switched as shown below according to the operating mode and bit PF6DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* PF6DDR — 0 1 Pin function AS output pin PF 6 input pin PF 6 output pin PF 5/RD The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* PF5DDR — 0 1 Pin function RD output pin PF 5 input pin PF 5 output pin PF 4/HWR The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* PF4DDR — 0 1 Pin function HWR output pin PF 4 input pin PF 4 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.

Table 9-24 Port F Pin Functions (cont) Pin Selection Method and Pin Functions PF 3/LWR The pin function is switched as shown below according to the operating mode and bit PF3DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* PF3DDR — 0 1 Pin function LWR output pin PF 3 input pin PF 3 output pin PF 2/LCAS/WAIT/ BREQO The pin function is switched as shown below according to the combination of the operating mode, and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE, ABW5 to ABW2, and PF2DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* LCASS 0 1 * — BREQOE 0 1 — — WAITE 0 1 — — — PF2DDR 0 1 — — — 0 1 Pin function PF 2 input pin PF 2 output pin WAIT input pin BREQO output pin LCAS output pin PF 2 input pin PF 2 output pin Note: 1. Only in DRAM space 16-bit access in modes 4 to 6 when RMTS2 to RMTS0 = B'001 to B'011. PF 1/BACK The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF1DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* BRLE 0 1 — PF1DDR 0 1 — 0 1 Pin function PF 1 input pin PF 1 output pin BACK output pin PF 1 input pin PF 1 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.

Table 9-24 Port F Pin Functions (cont) Pin Selection Method and Pin Functions PF 0/BREQ The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* BRLE 0 1 — PF0DDR 0 1 — 0 1 Pin function PF 0 input pin PF 0 output pin BREQ input pin PF 0 input pin PF 0 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.

9.14 Port G

9.14.1 Overview

Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). Figure 9-26 shows the port G pin configuration. PG 4/CS0 PG 3/CS1 PG 2/CS2/CR PG 1/CS3 PG 0/CAS PG 4 PG 3 PG 2 PG 1 PG 0 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. (I/O) (I/O) (I/O) (I/O) (I/O) Port G pins Pin functions in modes 3 and 7* Pin functions in modes 4 to 6* PG PG 3 PG 2 PG 1 PG 0 (input)/ (I/O) (I/O) (I/O) (I/O) CS0 (output) Pin functions in modes 1 and 2* PG 4 (input)/CS0 (output) PG 3 (input)/CS1 (output) PG 2 (input)/CS2 (output) PG 1 (input)/CS3 (output) PG 0 (I/O)/CAS (output) Port G Figure 9-26 Port G Pin Functions

9.14.2 Register Configuration

Table 9-25 shows the port G register configuration. Table 9-25 Port G Registers Name Abbreviation R/W Initial Value *2 Address*1 Port G data direction register PGDDR W H'10/H'00 *3 H'FEBF Port G data register PGDR R/W H'00 H'FF6F Port G register PORTG R Undefined H'FF5F Notes: 1. Lower 16 bits of the address. 2. Value of bits 4 to 0. 3. Initial value depends on the mode. Port G Data Direction Register (PGDDR) Undefined Undefined Undefined Undefined Undefined Undefined PG4DDR W W PG3DDR W W PG0DDR W W PG2DDR W W PG1DDR W W Bit Modes 1, 4, 5 Initial value R/W Modes 2, 3, 6, 7 Initial value R/W PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read. The PG4DDR bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes 1, 4, and 5, and to 0 in modes 2, 3, 6, and 7. It retains its prior state after a manual reset and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Mode 1 [H8S/2350]; modes 1 and 2 [H8S/2351] Pin PG 4 functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set to 1, and as an input port when the bit is cleared to 0. For pins PG3 to PG0, setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port.

Modes 3 and 7 [H8S/2351 only] Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing the bit to 0 makes the pin an input port.
Modes 4 and 5 [H8S/2350]; modes 4, 5, and 6 [H8S/2351] Pins PG4 to PG1 function as bus control output pins (CS0 to CS3) when the corresponding PGDDR bits are set to 1, and as input ports when the bits are cleared to 0. Pin PG0 functions as the CAS output pin when DRAM interface is designated. Otherwise, setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. For details of the DRAM interfaces, see section 6, Bus Controller. Port G Data Register (PGDR) Undefined Undefined Undefined PG4DR R/W PG3DR R/W PG0DR R/W PG2DR R/W PG1DR R/W Bit Initial value R/W PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG 0). Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port G Register (PORTG) Undefined Undefined Undefined PG4 — * R PG3 — * R PG0 — * R PG2 — * R PG1 — * R Bit Initial value R/W Note: * Determined by state of pins PG 4 to PG0. PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG4 to PG0) must always be performed on PGDR. Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset, and in software standby mode.

9.14.3 Pin Functions

Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). The pin functions are different in modes 1 and 2, modes 3 and 7, and modes 4 to 6. Port G pin functions are shown in table 9-26. Table 9-26 Port G Pin Functions Pin Selection Method and Pin Functions PG 4/CS0 The pin function is switched as shown below according to the operating mode and bit PG4DDR. Operating Mode Modes 1, 2, 4, 5, 6 * Modes 3 and 7* PG4DDR 0 1 0 1 Pin function PG 4 input pinCS0 output pin PG4 input pin PG4 output pin PG 3/CS1 The pin function is switched as shown below according to the operating mode and bit PG3DDR. Operating Mode Modes 1, 2, 3, 7 * Modes 4 to 6* PG3DDR 0 1 0 1 Pin function PG 3 input pin PG3 output pin PG3 input pinCS1 output pin PG 2/CS2 The pin function is switched as shown below according to the operating mode and bit PG2DDR. Operating Mode Modes 1, 2, 3, 7 * Modes 4 to 6* PG2DDR 0 1 0 1 Pin function PG 2 input pin PG2 output pin PG2 input pinCS2 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.

Table 9-26 Port G Pin Functions (cont) Pin Selection Method and Pin Functions PG 1/CS3 The pin function is switched as shown below according to the operating mode and bit PG1DDR. Operating Mode Modes 1, 2, 3, 7 * Modes 4 to 6* PG1DDR 0 1 0 1 Pin function PG 1 input pin PG1 output pin PG1 input pinCS3 output pin PG 0/CAS The pin function is switched as shown below according to the combination of the operating mode and bits RMTS2 to RMTS0 and PG0DDR. Operating Mode Modes 1, 2, 3, 7 * Modes 4 to 6* RMTS2 to RMTS0 — B'000, B'100 to B'111 B'001 to B'011 PG0DDR 0101 — Pin function PG 0 input pin PG 0 output pin PG 0 input pin PG 0 output pin CAS output Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.

Section 10 16-Bit Timer Pulse Unit (TPU)

10.1 Overview

The H8S/2350 Series has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.

10.1.1 Features

Maximum 16-pulse input/output ¾ A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ¾ TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
Selection of 8 counter input clocks for each channel
The following operations can be set for each channel: ¾ Waveform output at compare match: Selection of 0, 1, or toggle output ¾ Input capture function: Selection of rising edge, falling edge, or both edge detection ¾ Counter clear operation: Counter clearing possible by compare match or input capture ¾ Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously ¾ Simultaneous clearing by compare match and input capture possible ¾ Register simultaneous input/output possible by counter synchronous operation ¾ PWM mode: Any PWM output duty can be set ¾ Maximum of 15-phase PWM output possible by combination with synchronous operation
Buffer operation settable for channels 0 and 3 ¾ Input capture register double-buffering possible ¾ Automatic rewriting of output compare register possible
Phase counting mode settable independently for each of channels 1, 2, 4, and 5 ¾ Two-phase encoder pulse up/down-count possible
Cascaded operation ¾ Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow
Fast access via internal 16-bit bus ¾ Fast access is possible via a 16-bit bus interface

26 interrupt sources ¾ For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ¾ For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently
Automatic transfer of register data ¾ Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) or DMA controller (DMAC) activation
Programmable pulse generator (PPG) output trigger can be generated ¾ Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger
A/D converter conversion start trigger can be generated ¾ Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger
Module stop mode can be set ¾ As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 10-1 lists the functions of the TPU.

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock ø/1 ø/4 ø/16 ø/64 TCLKA TCLKB TCLKC TCLKD ø/1 ø/4 ø/16 ø/64 ø/256 TCLKA TCLKB ø/1 ø/4 ø/16 ø/64 ø/1024 TCLKA TCLKB TCLKC ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096 TCLKA ø/1 ø/4 ø/16 ø/64 ø/1024 TCLKA TCLKC ø/1 ø/4 ø/16 ø/64 ø/256 TCLKA TCLKC TCLKD General registers TGR0A TGR0B TGR1A TGR1B TGR2A TGR2B TGR3A TGR3B TGR4A TGR4B TGR5A TGR5B General registers/ buffer registers TGR0C TGR0D — — TGR3C TGR3D I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation —— —— Legend : Possible — : Not possible

Table 10-1 TPU Functions (cont) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DMAC activation TGR0A compare match or input capture TGR1A compare match or input capture TGR2A compare match or input capture TGR3A compare match or input capture TGR4A compare match or input capture TGR5A compare match or input capture DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture A/D converter trigger TGR0A compare match or input capture TGR1A compare match or input capture TGR2A compare match or input capture TGR3A compare match or input capture TGR4A compare match or input capture TGR5A compare match or input capture PPG trigger TGR0A/ TGR0B compare match or input capture TGR1A/ TGR1B compare match or input capture TGR2A/ TGR2B compare match or input capture TGR3A/ TGR3B compare match or input capture Interrupt sources 5 sources

Compare match or input capture 0A
Compare match or input capture 0B
Compare match or input capture 0C
Compare match or input capture 0D
Overflow 4 sources
Compare match or input capture 1A
Compare match or input capture 1B
Overflow
Underflow 4 sources
Compare match or input capture 2A
Compare match or input capture 2B
Overflow
Underflow 5 sources
Compare match or input capture 3A
Compare match or input capture 3B
Compare match or input capture 3C
Compare match or input capture 3D
Overflow 4 sources
Compare match or input capture 4A
Compare match or input capture 4B
Overflow
Underflow 4 sources
Compare match or input capture 5A
Compare match or input capture 5B
Overflow
Underflow Legend — : Not possible

10.1.2 Block Diagram

Figure 10-1 shows a block diagram of the TPU. Channel 3 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 4 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 3 to 5 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB TGRC Channel 1 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 0 TMDR TSR TCR TIORH TIER Control logic for channels 0 to 2 TGRA TCNT TGRB TGRD TSYRTSTR Input/output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Clock input ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096 TCLKA TCLKB TCLKC TCLKD Input/output pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3: Channel 4: Channel 5: Interrupt request signals Channel 0: Channel 1: Channel 2: Internal data bus A/D conversion start request signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Channel 3: Channel 4: Channel 5: Internal clock: External clock: Channel 0: Channel 1: Channel 2: Channel 2 Common Channel 5 Bus interface Figure 10-1 Block Diagram of TPU

10.1.3 Pin Configuration

Table 10-2 summarizes the TPU pins. Table 10-2 TPU Pins Channel Name Symbol I/O Function All Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) Clock input C TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) Clock input D TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input)

0 Input capture/out

TIOCA0 I/O TGR0A input capture input/output compare output/PWM output pin Input capture/out compare match B0 TIOCB0 I/O TGR0B input capture input/output compare output/PWM output pin Input capture/out compare match C0 TIOCC0 I/O TGR0C input capture input/output compare output/PWM output pin Input capture/out compare match D0 TIOCD0 I/O TGR0D input capture input/output compare output/PWM output pin

1 Input capture/out

TIOCA1 I/O TGR1A input capture input/output compare output/PWM output pin Input capture/out compare match B1 TIOCB1 I/O TGR1B input capture input/output compare output/PWM output pin

2 Input capture/out

TIOCA2 I/O TGR2A input capture input/output compare output/PWM output pin Input capture/out compare match B2 TIOCB2 I/O TGR2B input capture input/output compare output/PWM output pin

Table 10-2 TPU Pins (cont) Channel Name Symbol I/O Function

3 Input capture/out

TIOCA3 I/O TGR3A input capture input/output compare output/PWM output pin Input capture/out compare match B3 TIOCB3 I/O TGR3B input capture input/output compare output/PWM output pin Input capture/out compare match C3 TIOCC3 I/O TGR3C input capture input/output compare output/PWM output pin Input capture/out compare match D3 TIOCD3 I/O TGR3D input capture input/output compare output/PWM output pin

4 Input capture/out

TIOCA4 I/O TGR4A input capture input/output compare output/PWM output pin Input capture/out compare match B4 TIOCB4 I/O TGR4B input capture input/output compare output/PWM output pin

5 Input capture/out

TIOCA5 I/O TGR5A input capture input/output compare output/PWM output pin Input capture/out compare match B5 TIOCB5 I/O TGR5B input capture input/output compare output/PWM output pin

10.1.4 Register Configuration

Table 10-3 summarizes the TPU registers. Table 10-3 TPU Registers Channel Name Abbreviation R/W Initial Value Address *1

0 Timer control register 0 TCR0 R/W H'00 H'FFD0

Timer mode register 0 TMDR0 R/W H'C0 H'FFD1 Timer I/O control register 0H TIOR0H R/W H'00 H'FFD2 Timer I/O control register 0L TIOR0L R/W H'00 H'FFD3 Timer interrupt enable register 0 TIER0 R/W H'40 H'FFD4 Timer status register 0 TSR0 R/(W) *2 H'C0 H'FFD5 Timer counter 0 TCNT0 R/W H'0000 H'FFD6 Timer general register 0A TGR0A R/W H'FFFF H'FFD8 Timer general register 0B TGR0B R/W H'FFFF H'FFDA Timer general register 0C TGR0C R/W H'FFFF H'FFDC Timer general register 0D TGR0D R/W H'FFFF H'FFDE

1 Timer control register 1 TCR1 R/W H'00 H'FFE0

Timer mode register 1 TMDR1 R/W H'C0 H'FFE1 Timer I/O control register 1 TIOR1 R/W H'00 H'FFE2 Timer interrupt enable register 1 TIER1 R/W H'40 H'FFE4 Timer status register 1 TSR1 R/(W) *2 H'C0 H'FFE5 Timer counter 1 TCNT1 R/W H'0000 H'FFE6 Timer general register 1A TGR1A R/W H'FFFF H'FFE8 Timer general register 1B TGR1B R/W H'FFFF H'FFEA

2 Timer control register 2 TCR2 R/W H'00 H'FFF0

Timer mode register 2 TMDR2 R/W H'C0 H'FFF1 Timer I/O control register 2 TIOR2 R/W H'00 H'FFF2 Timer interrupt enable register 2 TIER2 R/W H'40 H'FFF4 Timer status register 2 TSR2 R/(W) *2 H'C0 H'FFF5 Timer counter 2 TCNT2 R/W H'0000 H'FFF6 Timer general register 2A TGR2A R/W H'FFFF H'FFF8 Timer general register 2B TGR2B R/W H'FFFF H'FFFA

Table 10-3 TPU Registers (cont) Channel Name Abbreviation R/W Initial Value Address *1

3 Timer control register 3 TCR3 R/W H'00 H'FE80

Timer mode register 3 TMDR3 R/W H'C0 H'FE81 Timer I/O control register 3H TIOR3H R/W H'00 H'FE82 Timer I/O control register 3L TIOR3L R/W H'00 H'FE83 Timer interrupt enable register 3 TIER3 R/W H'40 H'FE84 Timer status register 3 TSR3 R/(W) *2 H'C0 H'FE85 Timer counter 3 TCNT3 R/W H'0000 H'FE86 Timer general register 3A TGR3A R/W H'FFFF H'FE88 Timer general register 3B TGR3B R/W H'FFFF H'FE8A Timer general register 3C TGR3C R/W H'FFFF H'FE8C Timer general register 3D TGR3D R/W H'FFFF H'FE8E

4 Timer control register 4 TCR4 R/W H'00 H'FE90

Timer mode register 4 TMDR4 R/W H'C0 H'FE91 Timer I/O control register 4 TIOR4 R/W H'00 H'FE92 Timer interrupt enable register 4 TIER4 R/W H'40 H'FE94 Timer status register 4 TSR4 R/(W) *2 H'C0 H'FE95 Timer counter 4 TCNT4 R/W H'0000 H'FE96 Timer general register 4A TGR4A R/W H'FFFF H'FE98 Timer general register 4B TGR4B R/W H'FFFF H'FE9A

5 Timer control register 5 TCR5 R/W H'00 H'FEA0

Timer mode register 5 TMDR5 R/W H'C0 H'FEA1 Timer I/O control register 5 TIOR5 R/W H'00 H'FEA2 Timer interrupt enable register 5 TIER5 R/W H'40 H'FEA4 Timer status register 5 TSR5 R/(W) *2 H'C0 H'FEA5 Timer counter 5 TCNT5 R/W H'0000 H'FEA6 Timer general register 5A TGR5A R/W H'FFFF H'FEA8 Timer general register 5B TGR5B R/W H'FFFF H'FEAA All Timer start register TSTR R/W H'00 H'FFC0 Timer synchro register TSYR R/W H'00 H'FFC1 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

10.2 Register Descriptions

10.2.1 Timer Control Register (TCR)

Channel 0: TCR0 Channel 3: TCR3 CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC0 R/W TPSC2 R/W TPSC1 R/W Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 Bit Initial value R/W The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and in hardware standby mode. TCR register settings should be made only when TCNT operation is stopped.

Bits 7, 6, 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source. Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3 0 0 0 TCNT clearing disabled (Initial value)

1 TCNT cleared by TGRA compare match/input

1 0 TCNT cleared by TGRB compare match/input capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/ synchronous operation * 1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture *2 1 0 TCNT cleared by TGRD compare match/input capture *2 channel performing synchronous clearing/ synchronous operation * Channel Bit 7 Reserved*3 Bit 6 CCLR1 Bit 5 CCLR0 Description 1, 2, 4, 5 0 0 0 TCNT clearing disabled (Initial value) 1 0 TCNT cleared by TGRB compare match/input capture channel performing synchronous clearing/ synchronous operation * Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Bit 4 CKEG1 Bit 3 CKEG0 Description 0 0 Count at rising edge (Initial value)

1 Count at falling edge

1 — Count at both edges Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is ignored if the input clock is ø/1, or when overflow/underflow of another channel is selected. Bits 2, 1, and 0—Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 10-4 shows the clock sources that can be set for each channel. Table 10-4 TPU Clock Sources Internal Clock External Clock Overflow/ Underflow on Another Channel ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096 TCLKA TCLKB TCLKC TCLKD Channel Legend : Setting Blank : No setting

0000 Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

1000 Internal clock: counts on ø/1 (Initial value)

1 0 Internal clock: counts on ø/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on ø/256

1 Counts on TCNT2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode. Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description

2000 Internal clock: counts on ø/1 (Initial value)

1 0 Internal clock: counts on ø/16 1 0 0 External clock: counts on TCLKA pin input 1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on ø/1024

Note: This setting is ignored when channel 2 is in phase counting mode.

3000 Internal clock: counts on ø/1 (Initial value)

1 0 Internal clock: counts on ø/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on ø/256

1 Internal clock: counts on ø/4096

4000 Internal clock: counts on ø/1 (Initial value)

1 0 Internal clock: counts on ø/16 1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on ø/1024

1 Counts on TCNT5 overflow/underflow

Note: This setting is ignored when channel 4 is in phase counting mode. Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description

5000 Internal clock: counts on ø/1 (Initial value)

1 0 Internal clock: counts on ø/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on ø/256 Note: This setting is ignored when channel 5 is in phase counting mode.

10.2.2 Timer Mode Register (TMDR)

Channel 0: TMDR0 Channel 3: TMDR3 MD3 R/W MD0 R/W MD2 R/W MD1 R/W Bit Initial value R/W Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TMDR register settings should be made only when TCNT operation is stopped. Bits 7 and 6—Reserved: Read-only bits, always read as 1. Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB Description

0 TGRB operates normally (Initial value)

1 TGRB and TGRD used together for buffer operation

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4 BFA Description

0 TGRA operates normally (Initial value)

1 TGRA and TGRC used together for buffer operation

Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3 MD3 *1 Bit 2 MD2 *2 Bit 1 MD1 Bit 0 MD0 Description

0000 Normal operation (Initial value)

1 Reserved

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 Phase counting mode 4

1 *** — *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.

10.2.3 Timer I/O Control Register (TIOR)

Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 IOD3 R/W IOD2 R/W IOD1 R/W IOD0 R/W IOC3 R/W IOC0 R/W IOC2 R/W IOC1 R/W Channel 0: TIOR0L Channel 3: TIOR3L Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Bit Initial value R/W The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR registers are initialized to H'00 by a reset, and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.

Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 0 0000 TGR0B is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 1/count clock Input capture at TCNT1 count- up/count-down* *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated.

0 0000 TGR0D is Output disabled (Initial value) output compare register* Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match register* Capture input source is TIOCD0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 1/count clock Input capture at TCNT1 count-up/count-down* *: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

1 0000 TGR1B is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is TGR0C compare match/ input capture Input capture at generation of TGR0C compare match/input capture *: Don’t care Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 2 0000 TGR2B is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match 1 * 0 TGR2B is input capture register Capture input source is TIOCB2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care

3 0000 TGR3B is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 4/count clock Input capture at TCNT4 count-up/count-down* *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated.

3 0000 TGR3D is Output disabled (Initial value) output compare register* Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match register* Capture input source is TIOCD3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 4/count clock Input capture at TCNT4 count-up/count-down* *: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

4 0000 TGR4B is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is TGR3C compare match/ input capture Input capture at generation of TGR3C compare match/ input capture *: Don’t care Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 5 0000 TGR5B is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match 1 * 0 TGR5B is input capture register Capture input source is TIOCB5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care

Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Description 0 0000 TGR0A is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 1/ count clock Input capture at TCNT1 count-up/count-down *: Don’t care

0 0000 TGR0C is Output disabled (Initial value) output compare register* Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match register* Capture input source is TIOCC0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 1/count clock Input capture at TCNT1 count-up/count-down *: Don’t care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

1 0000 TGR1A is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is TGR0A compare match/ input capture Input capture at generation of channel 0/TGR0A compare match/input capture *: Don’t care Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Description 2 0000 TGR2A is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match 1 * 0 TGR2A is input capture register Capture input source is TIOCA2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care

3 0000 TGR3A is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 4/count clock Input capture at TCNT4 count-up/count-down *: Don’t care

3 0000 TGR3C is Output disabled (Initial value) output compare register* Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match register* Capture input source is TIOCC3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is channel 4/count clock Input capture at TCNT4 count-up/count-down *: Don’t care Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

4 0000 TGR4A is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 1 ** Capture input source is TGR3A compare match/ input capture Input capture at generation of TGR3A compare match/input capture *: Don’t care Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Description 5 0000 TGR5A is Output disabled (Initial value) output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 10 output 1 output at compare match 1 * 0 TGR5A is input capture register Capture input source is TIOCA5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care

10.2.4 Timer Interrupt Enable Register (TIER)

Channel 0: TIER0 Channel 3: TIER3 TTGE R/W TCIEU R/W TCIEV R/W TGIEA R/W TGIEB R/W Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit Initial value R/W The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode.

Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE Description

0 A/D conversion start request generation disabled (Initial value)

1 A/D conversion start request generation enabled

Bit 6—Reserved: Read-only bit, always read as 1. Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU Description

0 Interrupt requests (TCIU) by TCFU disabled (Initial value)

1 Interrupt requests (TCIU) by TCFU enabled

Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV Description

0 Interrupt requests (TCIV) by TCFV disabled (Initial value)

1 Interrupt requests (TCIV) by TCFV enabled

Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGIED Description

0 Interrupt requests (TGID) by TGFD bit disabled (Initial value)

1 Interrupt requests (TGID) by TGFD bit enabled

Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC Description

0 Interrupt requests (TGIC) by TGFC bit disabled (Initial value)

1 Interrupt requests (TGIC) by TGFC bit enabled

Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB Description

0 Interrupt requests (TGIB) by TGFB bit disabled (Initial value)

1 Interrupt requests (TGIB) by TGFB bit enabled

Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA Description

0 Interrupt requests (TGIA) by TGFA bit disabled (Initial value)

1 Interrupt requests (TGIA) by TGFA bit enabled

10.2.5 Timer Status Register (TSR)

R/(W)* TGFD R/(W)* TGFA R/(W)* TGFC R/(W)* TGFB R/(W)* Bit Initial value R/W Note: * Can only be written with 0 for flag clearing. Channel 0: TSR0 Channel 3: TSR3 TCFD R TCFU R/(W)* TCFV R/(W)* TGFA R/(W)* TGFB R/(W)* Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit Initial value R/W Note: * Can only be written with 0 for flag clearing. The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode.

Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD Description

0 TCNT counts down

1 TCNT counts up (Initial value)

Bit 6—Reserved: Read-only bit, always read as 1. Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCFU Description 0 [Clearing condition] (Initial value) When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV Description 0 [Clearing condition] (Initial value) When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )

Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD Description 0 [Clearing conditions] (Initial value)

When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions]
When TCNT = TGRD while TGRD is functioning as output compare register
When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGFC Description 0 [Clearing conditions] (Initial value)
When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFC after reading TGFC = 1 1 [Setting conditions]
When TCNT = TGRC while TGRC is functioning as output compare register
When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register

Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB Description 0 [Clearing conditions] (Initial value)

When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions]
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA Description 0 [Clearing conditions] (Initial value)
When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is
When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions]
When TCNT = TGRA while TGRA is functioning as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register

10.2.6 Timer Counter (TCNT)

Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Note : * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.

10.2.7 Timer General Register (TGR)

The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.

10.2.8 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bits 7 and 6—Reserved: Should always be written with 0. Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn Description

0 TCNTn count operation is stopped (Initial value)

1 TCNTn performs count operation

n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value.

10.2.9 Timer Synchro Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 6—Reserved: Should always be written with 0. Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels* 1, and synchronous clearing through counter clearing on another channel*2 are possible. Bit n SYNCn Description

0 TCNTn operates independently (TCNT presetting/clearing is unrelated to

other channels) (Initial value)

1 TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0 Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR.

10.2.10 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 13—Module Stop (MSTP13): Specifies the TPU module stop mode. Bit 13 MSTP13 Description

0 TPU module stop mode cleared

1 TPU module stop mode set (Initial value)

10.3 Interface to Bus Master

10.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2. Bus interface H Internal data bus L Bus master Module data bus TCNTH TCNTL Figure 10-2 16-Bit Register Access Operation [Bus Master « TCNT (16 Bits)] 10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units.

10.4 Operation

10.4.1 Overview

Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation

When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR.
When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4 counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32- bit counter. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input.

10.4.2 Basic Functions

Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.

Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure. Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count operation <Periodic counter> [1] [2] [4] [3] [5] Free-running counter Start count operation <Free-running counter> [5] [1] [2] [3] [4] [5] Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the TGR selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the TGR selected in [2]. Set the CST bit in TSTR to 1 to start the counter operation. Figure 10-6 Example of Counter Operation Setting Procedure

10.4.3 Synchronous Operation

In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10-14 shows an example of the synchronous operation setting procedure. Set synchronous operation Synchronous operation selection Set TCNT Synchronous presetting <Synchronous presetting> [1] [2] Synchronous clearing Select counter clearing source <Counter clearing> [3] Start count [5] Set synchronous counter clearing <Synchronous clearing> [4] Start count [5] Clearing sourcegeneration channel? No Yes [1] [2] [3] [4] [5] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10-14 Example of Synchronous Operation Setting Procedure

Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 10.4.6, PWM Modes. TCNT0 to TCNT2 values H'0000 TIOC0A TIOC1A Time TGR0B Synchronous clearing by TGR0B compare match TGR2A TGR1A TGR2B TGR0A TGR1B TIOC2A Figure 10-15 Example of Synchronous Operation

10.4.4 Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10-5 shows the register combinations used in buffer operation. Table 10-5 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register

0 TGR0A TGR0C

3 TGR3A TGR3C

When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10-16. Buffer register Timer general register TCNTComparator Compare match signal Figure 10-16 Compare Match Buffer Operation

When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10-17. Buffer register Timer general register TCNT Input capture signal Figure 10-17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer operation setting procedure. Select TGR function Buffer operation Set buffer operation Start count <Buffer operation> [1] [2] [3] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Figure 10-18 Example of Buffer Operation Setting Procedure

10.4.5 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10-6 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 10-6 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT1 TCNT2 Channels 4 and 5 TCNT4 TCNT5 Example of Cascaded Operation Setting Procedure: Figure 10-21 shows an example of the setting procedure for cascaded operation. Set cascading Cascaded operation Start count <Cascaded operation> [1] [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B’111 to select TCNT2 (TCNT5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.Figure 10-21 Cascaded Operation Setting Procedure

10.4.6 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.

PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible.
PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10-7.

Table 10-7 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2

0 TGR0A TIOCA0 TIOCA0

1 TGR1A TIOCA1 TIOCA1

2 TGR2A TIOCA2 TIOCA2

3 TGR3A TIOCA3 TIOCA3

4 TGR4A TIOCA4 TIOCA4

5 TGR5A TIOCA5 TIOCA5

Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. Select counter clock PWM mode Select counter clearing source Select waveform output level <PWM mode> [1] [2] [3] Set TGR [4] Set PWM mode [5] Start count [6] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Figure 10-24 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10-25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty.

10.4.7 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10-8 shows the correspondence between external clock pins and channels. Table 10-8 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 or 5 is set to phase counting mode TCLKA TCLKB When channel 2 or 4 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10-28 shows an example of the phase counting mode setting procedure. Select phase counting mode Phase counting mode Start count <Phase counting mode> [1] [2] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 10-28 Example of Phase Counting Mode Setting Procedure

Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the compare match function, and are set with the speed control period and position control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. This procedure enables accurate position/speed detection to be achieved.

(speed period capture) TGR0A (speed control period) TGR1B (position period capture) TGR0C (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 TCLKA TCLKB Edge detection circuit Figure 10-33 Phase Counting Mode Application Example

10.5 Interrupts

10.5.1 Interrupt Sources and Priorities

There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10-13 lists the TPU interrupt sources.

Table 10-13 TPU Interrupts Channel Interrupt Source Description DMAC Activation DTC Activation Priority

0 TGI0A TGR0A input capture/compare match Possible Possible High

TGI0B TGR0B input capture/compare match Not possible Possible TGI0C TGR0C input capture/compare match Not possible Possible TGI0D TGR0D input capture/compare match Not possible Possible TCI0V TCNT0 overflow Not possible Not possible

1 TGI1A TGR1A input capture/compare match Possible Possible

TGI1B TGR1B input capture/compare match Not possible Possible TCI1V TCNT1 overflow Not possible Not possible TCI1U TCNT1 underflow Not possible Not possible

2 TGI2A TGR2A input capture/compare match Possible Possible

TGI2B TGR2B input capture/compare match Not possible Possible TCI2V TCNT2 overflow Not possible Not possible TCI2U TCNT2 underflow Not possible Not possible

3 TGI3A TGR3A input capture/compare match Possible Possible

TGI3B TGR3B input capture/compare match Not possible Possible TGI3C TGR3C input capture/compare match Not possible Possible TGI3D TGR3D input capture/compare match Not possible Possible TCI3V TCNT3 overflow Not possible Not possible

4 TGI4A TGR4A input capture/compare match Possible Possible

TGI4B TGR4B input capture/compare match Not possible Possible TCI4V TCNT4 overflow Not possible Not possible TCI4U TCNT4 underflow Not possible Not possible

5 TGI5A TGR5A input capture/compare match Possible Possible

TGI5B TGR5B input capture/compare match Not possible Possible TCI5V TCNT5 overflow Not possible Not possible TCI5U TCNT5 underflow Not possible Not possible Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.

Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.

10.5.2 DTC/DMAC Activation

DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller. A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. DMAC Activation: The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC activation sources, one for each channel.

10.5.3 A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.

10.6 Operation Timing

10.6.1 Input/Output Timing

TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. TCNT TCNT input clock Internal clock ø N–1 N N+1 N+2 Falling edge Rising edge Figure 10-34 Count Timing in Internal Clock Operation TCNT TCNT input clock External clock ø N–1 N N+1 N+2 Rising edge Falling edgeFalling edge Figure 10-35 Count Timing in External Clock Operation

10.6.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. TGR TCNT TCNT input clock ø N N N+1 Compare match signal TGF flag TGI interrupt Figure 10-42 TGI Interrupt Timing (Compare Match)

TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. TGR TCNT Input capture signal ø N N TGF flag TGI interrupt Figure 10-43 TGI Interrupt Timing (Input Capture)

10.7 Usage Notes

Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10-48 shows the input clock conditions in phase counting mode. Overlap Phase differ- ence Phase differ- enceOverlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = ø (N + 1) Where f : Counter frequency ø : Operating frequency N : TGR set value

Section 11 Programmable Pulse Generator (PPG)

11.1 Overview

The H8S/2350 Series has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate both simultaneously and independently.

11.1.1 Features

PPG features are listed below.

16-bit output data ¾ Maximum 16-bit data can be output, and output can be enabled on a bit-by-bit basis
Four output groups ¾ Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs
Selectable output trigger signals ¾ Output trigger signals can be selected for each group from the compare match signals of four TPU channels
Non-overlap mode ¾ A non-overlap margin can be provided between pulse outputs
Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) ¾ The compare match signals selected as output trigger signals can activate the DTC or DMAC for sequential output of data without CPU intervention
Settable inverted output ¾ Inverted data can be output for each group
Module stop mode can be set ¾ As the initial setting, PPG operation is halted. Register access is enabled by exiting module stop mode

11.1.2 Block Diagram

Figure 11-1 shows a block diagram of the PPG. Compare match signals PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Legend : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next data register L : Output data register H : Output data register L Internal data bus PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL Pulse output pins, group 3 Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 PODRHPODRL NDRH NDRL Control logic NDERH PMR NDERL PCR Figure 11-1 Block Diagram of PPG

11.1.3 Pin Configuration

Table 11-1 summarizes the PPG pins. Table 11-1 PPG Pins Name Symbol I/O Function Pulse output 0 PO0 Output Group 0 pulse output Pulse output 1 PO1 Output Pulse output 2 PO2 Output Pulse output 3 PO3 Output Pulse output 4 PO4 Output Group 1 pulse output Pulse output 5 PO5 Output Pulse output 6 PO6 Output Pulse output 7 PO7 Output Pulse output 8 PO8 Output Group 2 pulse output Pulse output 9 PO9 Output Pulse output 10 PO10 Output Pulse output 11 PO11 Output Pulse output 12 PO12 Output Group 3 pulse output Pulse output 13 PO13 Output Pulse output 14 PO14 Output Pulse output 15 PO15 Output

11.1.4 Registers

Table 11-2 summarizes the PPG registers. Table 11-2 PPG Registers Name Abbreviation R/W Initial Value Address *1 PPG output control register PCR R/W H'FF H'FF46 PPG output mode register PMR R/W H'F0 H'FF47 Next data enable register H NDERH R/W H'00 H'FF48 Next data enable register L NDERL R/W H'00 H'FF49 Output data register H PODRH R/(W) *2 H'00 H'FF4A Output data register L PODRL R/(W) *2 H'00 H'FF4B Next data register H NDRH R/W H'00 H'FF4C *3 H'FF4E Next data register L NDRL R/W H'00 H'FF4D *3 H'FF4F Port 1 data direction register P1DDR W H'00 H'FEB0 Port 2 data direction register P2DDR W H'00 H'FEB1 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Bits used for pulse output cannot be written to. 3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FF4C. When the output triggers are different, the NDRH address is H'FF4E for group 2 and H'FF4C for group 3. Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FF4D. When the output triggers are different, the NDRL address is H'FF4F for group 0 and H'FF4D for group 1.

11.2 Register Descriptions

11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)

NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from NDR to PODR and the output value does not change. NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. NDERH Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 Description

0 Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not

transferred to POD15 to POD8) (Initial value)

1 Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred

to POD15 to POD8)

NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 Description

0 Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not

transferred to POD7 to POD0) (Initial value)

1 Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to

POD7 to POD0)

11.2.2 Output Data Registers H and L (PODRH, PODRL)

R/(W)* POD14 R/(W)* POD13 R/(W)* POD12 R/(W)* POD11 R/(W)* POD8 R/(W)* POD10 R/(W)* POD9 R/(W)* Bit Initial value R/W PODRH POD7 R/(W)* POD6 R/(W)* POD5 R/(W)* POD4 R/(W)* POD3 R/(W)* POD0 R/(W)* POD2 R/(W)* POD1 R/(W)* PODRL Bit Initial value R/W Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output.

11.2.3 Next Data Registers H and L (NDRH, NDRL)

NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access. NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode.

11.2.4 Notes on NDR Access

The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the same compare match event, the NDRH address is H'FF4C. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FF4E consists entirely of reserved bits that cannot be modified and are always read as 1. Address H'FF4C NDR15 R/W NDR14 R/W NDR13 R/W NDR12 R/W NDR11 R/W NDR8 R/W NDR10 R/W NDR9 R/W Bit Initial value R/W Address H'FF4E Bit Initial value R/W If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FF4D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FF4F consists entirely of reserved bits that cannot be modified and are always read as 1.

Address H'FF4D NDR7 R/W NDR6 R/W NDR5 R/W NDR4 R/W NDR3 R/W NDR0 R/W NDR2 R/W NDR1 R/W Bit Initial value R/W Address H'FF4F Bit Initial value R/W Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FF4C and the address of the lower 4 bits (group 2) is H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4 of address H'FF4E are reserved bits that cannot be modified and are always read as 1. Address H'FF4C NDR15 R/W NDR14 R/W NDR13 R/W NDR12 R/W Bit Initial value R/W Address H'FF4E NDR11 R/W NDR8 R/W NDR10 R/W NDR9 R/W Bit Initial value R/W If pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in NDRL (group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F. Bits 3 to 0 of address H'FF4D and bits 7 to 4 of address H'FF4F are reserved bits that cannot be modified and are always read as 1.

Address H'FF4D NDR7 R/W NDR6 R/W NDR5 R/W NDR4 R/W Bit Initial value R/W Address H'FF4F NDR3 R/W NDR0 R/W NDR2 R/W NDR1 R/W Bit Initial value R/W

11.2.5 PPG Output Control Register (PCR)

PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a group-by-group basis. PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match that triggers pulse output group 3 (pins PO15 to PO12). G3CMS0 Output Trigger for Pulse Output Group 3 0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8). G2CMS0 Output Trigger for Pulse Output Group 2 0 0 Compare match in TPU channel 0 1 0 Compare match in TPU channel 2 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). G1CMS0 Output Trigger for Pulse Output Group 1 0 0 Compare match in TPU channel 0 1 0 Compare match in TPU channel 2 Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match that triggers pulse output group 0 (pins PO3 to PO0). G0CMS0 Output Trigger for Pulse Output Group 0 0 0 Compare match in TPU channel 0 1 0 Compare match in TPU channel 2

11.2.6 PPG Output Mode Register (PMR)

PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA. The output values change at compare match A and B. For details, see section 11.3.4, Non-Overlapping Pulse Output. PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output group 3 (pins PO15 to PO12). Bit 7 G3INV Description

0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)

(Initial value) Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output group 2 (pins PO11 to PO8). Bit 6 G2INV Description

0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)

(Initial value)

Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). Bit 5 G1INV Description

0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)

(Initial value) Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output group 0 (pins PO3 to PO0). Bit 4 G0INV Description

0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)

(Initial value) Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse output group 3 (pins PO15 to PO12). Bit 3 G3NOV Description

0 Normal operation in pulse output group 3 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at

compare match A or B in the selected TPU channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse output group 2 (pins PO11 to PO8). Bit 2 G2NOV Description

0 Normal operation in pulse output group 2 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). Bit 1 G1NOV Description

0 Normal operation in pulse output group 1 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at

compare match A or B in the selected TPU channel) Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse output group 0 (pins PO3 to PO0). Bit 0 G0NOV Description

0 Normal operation in pulse output group 0 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

11.2.7 Port 1 Data Direction Register (P1DDR)

W P16DDR W P15DDR W P14DDR W P13DDR W P10DDR W P12DDR W P11DDR W Bit Initial value R/W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further information about P1DDR, see section 9.2, Port 1.

11.2.8 Port 2 Data Direction Register (P2DDR)

W P26DDR W P25DDR W P24DDR W P23DDR W P20DDR W P22DDR W P21DDR W Bit Initial value R/W P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1. For further information about P2DDR, see section 9.3, Port 2.

11.2.9 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP11 bit in MSTPCR is set to 1, PPG operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 11—Module Stop (MSTP11): Specifies the PPG module stop mode. Bit 11 MSTP11 Description

0 PPG module stop mode cleared

1 PPG module stop mode set (Initial value)

11.3 Operation

11.3.1 Overview

PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating conditions. Output trigger signal Pulse output pin Internal data bus Normal output/inverted output/CR /CR C PODRQD NDER Q NDRQD DDR Q Figure 11-2 PPG Output Operation Table 11-3 PPG Operating Conditions NDER DDR Pin Function 0 0 Generic input port

1 Generic output port

1 0 Generic input port (but the PODR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the PODR bit)

1 PPG pulse output

Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. For details of non-overlapping operation, see section 11.3.4, Non- Overlapping Pulse Output.

11.3.2 Output Timing

If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N+1 ø TGRA N Compare match A signal NDRH mnPODRH PO8 to PO15 n mn Figure 11-3 Timing of Transfer and Output of NDR Contents (Example)

11.3.3 Normal Pulse Output

Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output. Select TGR functions [1] Set TGRA value Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Normal PPG output No Yes TPU setup Port and PPG setup TPU setup [2] [3] [4] [5] [6] [7] [8] [9] [10] Compare match? [1] Set TIOR to make TGRA an output compare register (with output disabled) [2] Set the PPG output trigger period [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10]At each TGIA interrupt, set the next output values in NDR. Figure 11-4 Setup Procedure for Normal Pulse Output (Example)

Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TCNT TGRA H'0000 NDRH 00 80 C0 40 60 20 30 10 18 08 88PODRH PO15 PO14 PO13 PO12 PO11 Time Compare match C080 C080 40 60 20 30 10 18 08 88 80 C0 40 Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output compare register and the counter will be cleared by compare match A. Set the trigger period in TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt. [2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. [3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. [4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU.

11.3.4 Non-Overlapping Pulse Output

Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample procedure for setting up non-overlapping pulse output. Select TGR functions [1] Set TGR values Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start counter Set next pulse output data Compare match? No Yes TPU setup PPG setup TPU setup Non-overlapping PPG output Set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled) [2] Set the pulse output trigger period in TGRB and the non-overlap margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 11-6 Setup Procedure for Non-Overlapping Pulse Output (Example)

Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11-7 shows an example in which pulse output is used for four- phase complementary non-overlapping pulse output. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non-overlap margin Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)

[1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. [2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. [3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. [4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU.

11.3.5 Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 11-8 Inverted Pulse Output (Example)

11.3.6 Pulse Output Triggered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11-9 shows the timing of this output. ø N M N TIOC pin Input capture signal NDR PODR MNPO Figure 11-9 Pulse Output Triggered by Input Capture (Example)

11.4 Usage Notes

Operation of Pulse Output Pins: Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Note on Non-Overlapping Output: During non-overlapping operation, the transfer of NDR bit values to PODR bits takes place as follows.

NDR bits are always transferred to PODR bits at compare match A.
At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11-10 illustrates the non-overlapping pulse output operation. Compare match A Compare match B Pulse output pin Normal output/inverted output/CR /CR C PODRQD NDER Q NDRQD Internal data bus DDR Figure 11-10 Non-Overlapping Pulse Output

12.1 Overview

The H8S/2350 Series has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2350 Series. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.

12.1.1 Features

WDT features are listed below.

Switchable between watchdog timer mode and interval timer mode
WDTOVF output when in watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire H8S/2350 Series is reset at the same time. This internal reset can be a power-on reset or a manual reset.
Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt.
Choice of eight counter clock sources.

12.1.2 Block Diagram

Figure 12-1 shows a block diagram of the WDT. Overflow Interrupt controlWOVI (interrupt request signal) WDTOVF Internal reset signal* Reset control RSTCSR TCNT TSCR ø/2 ø/64 ø/128 ø/512 ø/2048 ø/8192 ø/32768 ø/131072 Clock Clock select Internal clock sources Bus interfaceModule bus Legend TCSR TCNT RSTCSR Note: * : Timer control/status register : Timer counter : Reset control/status register Internal bus WDT The type of internal reset signal depends on a register setting. Either power-on reset or manual reset can be selected. Figure 12-1 Block Diagram of WDT

12.1.3 Pin Configuration

Table 12-1 describes the WDT output pin. Table 12-1 WDT Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog timer mode

12.1.4 Register Configuration

The WDT has three registers, as summarized in table 12-2. These registers control clock selection, WDT mode switching, and the reset signal. Table 12-2 WDT Registers Address*1 Name Abbreviation R/W Initial Value Write *2 Read Timer control/status register TCSR R/(W) *3 H'18 H'FFBC H'FFBC Timer counter TCNT R/W H'00 H'FFBC H'FFBD Reset control/status register RSTCSR R/(W) *3 H'1F H'FFBE H'FFBF Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 12.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag.

12.2 Register Descriptions

12.2.1 Timer Counter (TCNT)

TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access.

12.2.2 Timer Control/Status Register (TCSR)

R/(W)* WT/ IT R/W TME R/W CKS0 R/W CKS2 R/W CKS1 R/W Bit Initial value R/W Note: * Can only be written with 0 for flag clearing. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access.

Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 OVF Description 0 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF (Initial value) 1 [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal when TCNT overflows. Bit 6 WT/ IT Description

0 Interval timer: Sends the CPU an interval timer interrupt request (WOVI)

when TCNT overflows (Initial value)

1 Watchdog timer: Generates the WDTOVF signal when TCNT overflows

Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 12.2.3, Reset Control/Status Register (RSTCSR). Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME Description

0 TCNT is initialized to H'00 and halted (Initial value)

1 TCNT counts

Bits 4 and 3—Reserved: Read-only bits, always read as 1.

Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (ø), for input to TCNT. CKS0 Clock Overflow Period (when ø = 20 MHz) * 0 0 0 ø/2 (initial value) 25.6 µs 1 ø/64 819.2 µs 1 0 ø/128 1.6 ms 1 ø/512 6.6 ms 1 0 0 ø/2048 26.2 ms 1 ø/8192 104.9 ms 1 0 ø/32768 419.4 ms 1 ø/131072 1.68 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs.

12.2.3 Reset Control/Status Register (RSTCSR)

R/(W)* RSTE R/W RSTS R/W Note: * Can only be written with 0 for flag clearing. Bit Initial value R/W RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access.

Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF Description 0 [Clearing condition] (Initial value) Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF 1 [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2350 Series if TCNT overflows during watchdog timer operation. Bit 6 RSTE Description

0 Reset signal is not generated if TCNT overflows* (Initial value)

1 Reset signal is generated if TCNT overflows

Note: * The modules within the H8S/2350 Series are not reset, but TCNT and TCSR within the WDT are reset. Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of resets, see section 4, Exception Handling. Bit 5 RSTS Description

0 Power-on reset (Initial value)

1 Manual reset

Bits 4 to 0—Reserved: Read-only bits, always read as 1.

12.2.4 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write TCSR write Address: H'FFBC Address: H'FFBC H'5A Write data 15 8 7 0 H'A5 Write data 15 8 7 0 Figure 12-2 Format of Data Written to TCNT and TCSR

12.3 Operation

12.3.1 Watchdog Timer Operation

To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This is shown in figure 12-4. This WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2350 Series internally is generated at the same time as the WDTOVF signal. This reset can be selected as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. TCNT count H'00 Time H'FF WT/ IT=1 TME=1 H'00 written to TCNT WT/ IT=1 TME=1 H'00 written to TCNT 132 states*2 518 states WDTOVF signal Internal reset signal*1 WT/ IT TME Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. Overflow WDTOVF and internal reset are generated WOVF=1 : Timer mode select bit : Timer enable bit Legend Figure 12-4 Watchdog Timer Operation

12.3.2 Interval Timer Operation

To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 12-5. This function can be used to generate interrupt requests at regular intervals. TCNT count H'00 Time H'FF WT/ IT=0 TME=1 WOVI Overflow Overflow Overflow Overflow Legend WOVI: Interval timer interrupt request generation WOVI WOVI WOVI Figure 12-5 Interval Timer Operation

12.3.3 Timing of Setting Overflow Flag (OVF)

The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 12-6.

ø TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 12-6 Timing of Setting of OVF

12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)

The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2350 Series chip. Figure 12-7 shows the timing in this case. ø TCNT H'FF H'00 Overflow signal (internal signal) WOVF WDTOVF signal Internal reset signal 132 states 518 states Figure 12-7 Timing of Setting of WOVF

12.4 Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.

12.5 Usage Notes

12.5.1 Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12-8 shows this operation. Address ø Internal write signal TCNT input clock TCNT NM T1 T2 TCNT write cycle Counter write data Figure 12-8 Contention between TCNT Write and Increment

12.5.2 Changing Value of CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.

12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode.

12.5.4 System Reset by WDTOVF Signal

If the WDTOVF output signal is input to the RES pin of the H8S/2350 Series, the H8S/2350 Series will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 12-9. Reset input Reset signal to entire system H8S/2350 Series RES WDTOVF Figure 12-9 Circuit for System Reset by WDTOVF Signal (Example)

12.5.5 Internal Reset in Watchdog Timer Mode

The H8S/2350 Series is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.

Section 13 Serial Communication Interface (SCI)

13.1 Overview

The H8S/2350 Series is equipped with a two-channel serial communication interface (SCI). All two channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).

13.1.1 Features

SCI features are listed below.

Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode ¾ Serial data communication executed using asynchronous system in which synchronization is achieved character by character ¾ Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) ¾ A multiprocessor communication function is provided that enables serial data communication with a number of processors ¾ Choice of 12 serial data transfer formats Data length : 7 or 8 bits Stop bit length : 1 or 2 bits Parity : Even, odd, or none Multiprocessor bit : 1 or 0 ¾ Receive error detection : Parity, overrun, and framing errors ¾ Break detection : Break can be detected by reading the RxD pin level directly in case of a framing error Clocked Synchronous mode ¾ Serial data communication synchronized with a clock ¾ Serial data communication can be carried out with other chips that have a synchronous communication function ¾ One serial data transfer format ¾ Data length : 8 bits ¾ Receive error detection : Overrun errors detected

Full-duplex communication capability ¾ The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ¾ Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data
On-chip baud rate generator allows any bit rate to be selected
Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin
Four interrupt sources ¾ Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive error — that can issue requests independently ¾ The transmit-data-empty interrupt and receive data full interrupts can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer
Choice of LSB-first or MSB-first transfer ¾ Can be selected regardless of the communication mode* (except in the case of asynchronous mode bit data)
Module stop mode can be set ¾ As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. Note: * Descriptions in this section refer to LSB-first transfer.

13.1.2 Block Diagram

Figure 13-1 shows a block diagram of the SCI. Bus interface TDR RSR RDR Module data bus TSR SCMR SSR SCR Transmission/ reception control BRR Baud rate generator Internal data bus RxD TxD SCK Parity generation Parity check Clock External clock ø ø/4 ø/16 ø/64 TXI TEI RXI ERI SMR Legend SCMR RSR RDR TSR TDR SMR SCR SSR BRR : Smart Card mode register : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register : Serial status register : Bit rate register Figure 13-1 Block Diagram of SCI

13.1.3 Pin Configuration

Table 13-1 shows the serial pins for each SCI channel. Table 13-1 SCI Pins Channel Pin Name Symbol I/O Function

0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output

Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output

1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output

Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output

13.1.4 Register Configuration

The SCI has the internal registers shown in table 13-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 13-2 SCI Registers Channel Name Abbreviation R/W Initial Value Address *1

0 Serial mode register 0 SMR0 R/W H'00 H'FF78

Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A Transmit data register 0 TDR0 R/W H'FF H'FF7B Serial status register 0 SSR0 R/(W) *2 H'84 H'FF7C Receive data register 0 RDR0 R H'00 H'FF7D Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E

1 Serial mode register 1 SMR1 R/W H'00 H'FF80

Bit rate register 1 BRR1 R/W H'FF H'FF81 Serial control register 1 SCR1 R/W H'00 H'FF82 Transmit data register 1 TDR1 R/W H'FF H'FF83 Serial status register 1 SSR1 R/(W) *2 H'84 H'FF84 Receive data register 1 RDR1 R H'00 H'FF85 Smart card mode register 1 SCMR1 R/W H'F2 H'FF86 All Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

13.2 Register Descriptions

13.2.1 Receive Shift Register (RSR)

RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU.

13.2.2 Receive Data Register (RDR)

R R R R R R R R Bit Initial value R/W RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode.

13.2.3 Transmit Shift Register (TSR)

TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU.

13.2.4 Transmit Data Register (TDR)

TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode.

13.2.5 Serial Mode Register (SMR)

SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7—Communication Mode (C/ A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode. Bit 7 C/A Description

0 Asynchronous mode (Initial value)

1 Clocked synchronous mode

Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR Description 0 8-bit data (Initial value) 1 7-bit data * Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer.

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE Description

0 Parity bit addition and checking disabled (Initial value)

1 Parity bit addition and checking enabled*

Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E Description

0 Even parity *1 (Initial value)

1 Odd parity *2

Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.

Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description 0 1 stop bit : In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 1 2 stop bits : In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication Function. Bit 2 MP Description

0 Multiprocessor function disabled (Initial value)

1 Multiprocessor format selected

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, Bit Rate Register. Bit 1 CKS1 Bit 0 CKS0 Description 0 0 ø clock (Initial value) 1 ø/4 clock 1 0 ø/16 clock 1 ø/64 clock

13.2.6 Serial Control Register (SCR)

SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE Description

0 Transmit data empty interrupt (TXI) requests disabled* (Initial value)

1 Transmit data empty interrupt (TXI) requests enabled

Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE Description

0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

disabled* (Initial value)

1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.

Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE Description

0 Transmission disabled *1 (Initial value)

1 Transmission enabled *2

Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE Description

0 Reception disabled *1 (Initial value)

1 Reception enabled *2

Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1.

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description

0 Multiprocessor interrupts disabled (normal reception performed) (Initial value)

[Clearing conditions]

When the MPIE bit is cleared to 0
When MPB= 1 data is received

1 Multiprocessor interrupts enabled *

Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE Description

0 Transmit end interrupt (TEI) request disabled* (Initial value)

1 Transmit end interrupt (TEI) request enabled*

Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI’s operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 13-9 in section 13-3, Operation. Bit 1 CKE1 Bit 0 CKE0 Description 0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port *1 Clocked synchronous mode Internal clock/SCK pin functions as serial clock output

1 Asynchronous mode Internal clock/SCK pin functions as clock output*2

Internal clock/SCK pin functions as serial clock output 1 0 Asynchronous mode External clock/SCK pin functions as clock input *3 Clocked synchronous mode External clock/SCK pin functions as serial clock input

1 Asynchronous mode External clock/SCK pin functions as clock input *3

External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate.

13.2.7 Serial Status Register (SSR)

R/(W)* RDRF R/(W)* ORER R/(W)* FER R/(W)* PER R/(W)* MPBT R/W TEND R MPB R Bit Initial value R/W Note: Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode or module stop mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE Description 0 [Clearing conditions]

When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR 1 [Setting conditions] (Initial value)
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF Description 0 [Clearing conditions] (Initial value)
When 0 is written to RDRF after reading RDRF = 1
When the DMAC or DTC is activated by an RXI interrupt and read data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.

Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description 0 [Clearing condition] (Initial value) *1 When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER Description 0 [Clearing condition] (Initial value) *1 When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.

Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER Description 0 [Clearing condition] (Initial value) * When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND Description 0 [Clearing conditions]

When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR 1 [Setting conditions] (Initial value)
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB Description 0 [Clearing condition] (Initial value) * When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format.

Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. Bit 0 MPBT Description

0 Data with a 0 multiprocessor bit is transmitted (Initial value)

1 Data with a 1 multiprocessor bit is transmitted

13.2.8 Bit Rate Register (BRR)

BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode or module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR settings in clocked synchronous mode.

Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) ø = 2 MHz ø = 2.097152 MHz ø = 2.4576 MHz ø = 3 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 9600 0 6 — 0 6 –2.48 0 7 0.00 0 9 –2.34 19200 0 2 — 0 2 — 0 3 0.00 0 4 –2.34 31250 0 1 0.00 0 1 — 0 1 — 0 2 0.00 38400 0 1 — 0 1 — 0 1 0.00 — — — ø = 3.6864 MHz ø = 4 MHz ø = 4.9152 MHz ø = 5 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 — 0 7 0.00 0 7 1.73 31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00 38400 0 2 0.00 0 2 — 0 3 0.00 0 3 1.73

Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) ø = 6 MHz ø = 6.144 MHz ø = 7.3728 MHz ø = 8 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 — ø = 9.8304 MHz ø = 10 MHz ø = 12 MHz ø = 12.288 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00 31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00

Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) ø = 14 MHz ø = 14.7456 MHz ø = 16 MHz ø = 17.2032 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 –0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 –0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 –1.70 0 15 0.00 0 16 1.20 38400 0 10 — 0 11 0.00 0 12 0.16 0 13 0.00 ø = 18 MHz ø = 19.6608 MHz ø = 20 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 –0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 –1.36 31250 0 17 0.00 0 19 –1.70 0 19 0.00 38400 0 14 –2.34 0 15 0.00 0 15 1.73

Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate ø = 2 MHz ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz (bit/s) n N n N n N n N n N n N 110 3 70 — — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 — — 1 k 1 124 1 249 2 124 — — 2 249 — — 2.5 k 0 199 1 99 1 199 1 249 2 99 2 124 5 k 0 99 0 199 1 99 1 124 1 199 1 249 10 k 0 49 0 99 0 199 0 249 1 99 1 124 25 k 0 19 0 39 0 79 0 99 0 159 0 199 5 0 k 0901 9 03 9 04 9 07 9 09 9 100 k 040901 9 02 4 03 9 04 9 250 k 0103070901 5 01 9 500 k 0 0 * 0103040709

1 M 0 0 * 01— — 0304

5 M ——0 0 *

Note: As far as possible, the setting should be made so that the error is no more than 1%. Legend Blank : Cannot be set. — : Can be set, but there will be a degree of error. * : Continuous transfer is not possible.

The BRR setting is found from the following formulas. Asynchronous mode: N = ø 64 · 22n–1 · B

106 – 1 Clocked synchronous mode: N = ø 8 · 22n–1 · B
106 – 1 Where B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 £ N £ 255) ø: Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n Clock CKS1 CKS0 0ø 0 0 1 ø/4 0 1 2 ø/16 1 0 3 ø/64 1 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { ø · 106 – 1} · 100

Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6 and 13-7 show the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0

Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500

Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3

13.2.9 Smart Card Mode Register (SCMR)

SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see 14.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written in this bit.

13.2.10 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP6 and MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 6—Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode. Bit 6 MSTP6 Description

0 SCI channel 1 module stop mode cleared

1 SCI channel 1 module stop mode set (Initial value)

Bit 5—Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode. Bit 5 MSTP5 Description

0 SCI channel 0 module stop mode cleared

1 SCI channel 0 module stop mode set (Initial value)

13.3 Operation

13.3.1 Overview

The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 13-8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13-9. Asynchronous Mode

Data length: Choice of 7 or 8 bits
Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length)
Detection of framing, parity, and overrun errors, and breaks, during reception
Choice of internal or external clock as SCI clock source ¾ When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ¾ When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode
Transfer format: Fixed 8-bit data
Detection of overrun errors during reception
Choice of internal or external clock as SCI clock source ¾ When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip ¾ When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock

Table 13-8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR MP PE STOP Mode SCI Transfer Format Multi Data Processor Parity Stop Bit Length Bit Bit Length

00000 Asynchronous 8-bit data No No 1 bit

0 1 — 0 Asynchronous 8-bit data Yes No 1 bit mode (multi- processor format) 7-bit data 2 bits 1 bit 2 bits 1 ———— Clocked synchronous mode 8-bit data No None Table 13-9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting SCI Transmit/Receive Clock Bit 7 Bit 1 Bit 0 Clock C/A CKE1 CKE0 Mode Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use SCK pin 1 mode Outputs clock with same frequency as bit rate 1 0 External Inputs clock with frequency of 16 times 1 the bit rate 1 0 0 Clocked Internal Outputs serial clock synchronous mode External Inputs serial clock

13.3.2 Operation in Asynchronous Mode

In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSB- first order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. LSB Start bit MSB Idle state (mark state) Stop bit Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none One unit of transfer data (character or frame) Figure 13-2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting.

Table 13-10 Serial Transfer Formats (Asynchronous Mode) PE S 8-bit data STOP S 7-bit data STOP S 8-bit data STOP STOP S 8-bit data P STOP S 7-bit data STOPP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data STOPMPB S 7-bit data STOPMPB STOP S 7-bit data STOPSTOP CHR MP STOP SMR Settings 123456789 1 0 1 1 1 2 Serial Transfer Format and Frame Length STOPS 8-bit data P STOP S 7-bit data STOPP STOP Legend S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit

Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3. 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 Figure 13-3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations:

SCI initialization (asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain.

In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.

<End> [3] Error processing Parity error processing No Yes Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER= 1 FER= 1 Break? PER= 1 Clear RE bit in SCR to 0 Figure 13-7 Sample Serial Reception Data Flowchart (cont)

In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 13-11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated.

13.3.3 Multiprocessor Communication Function

The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 13-9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format: There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 13-10. Clock: See the section on asynchronous mode.

<End> [1] Yes Initialization Start transmission Read TDRE flag in SSR [2] Write transmit data to TDR and set MPBT bit in SSR No Yes No Yes Read TEND flag in SSR [3] No Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 TDRE= 1 All data transmitted? TEND= 1 Break output? Clear TDRE flag to 0 SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0. [1] [2] [3] [4] Figure 13-10 Sample Multiprocessor Serial Transmission Flowchart

In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated.

<End> [1] No Initialization Start reception No Yes [4] Clear RE bit in SCR to 0 Error processing (Continued on next page) [5]No Yes FER ∨ORER= 1 RDRF= 1 All data received? Read MPIE bit in SCR [2] Read ORER and FER flags in SSR Read RDRF flag in SSR [3] Read receive data in RDR No Yes This station's ID? Read ORER and FER flags in SSR Yes No Read RDRF flag in SSR No Yes FER ∨ORER= 1 Read receive data in RDR RDRF= 1 SCI initialization: The RxD pin is automatically designated as the receive data input pin. ID reception cycle: Set the MPIE bit in SCR to 1. SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [1] [2] [3] [4] [5] Figure 13-12 Sample Multiprocessor Serial Reception Flowchart

0 D0 D1 D7 1 1 0 D0 D1 D7 0 1

Data (ID1)Start bit MPB Stop bit Start bit Data (Data1) MPB Stop bit RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 Idle state (mark state) RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state ID1 (a) Data does not match station’s ID MPIE RDR value Data (ID2)Start bit MPB Stop bit Start bit Data (Data2) MPB Stop bit RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 Idle state (mark state) RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt service routine MPIE bit set to 1 again ID2 (b) Data matches station’s ID Data2ID1 Figure 13-13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

13.3.4 Operation in Clocked Synchronous Mode

In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-14 shows the general format for clocked synchronous serial communication. Don’t careDon’t care One unit of transfer data (character or frame) Bit 0Serial data Serial clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * High except in continuous transfer Figure 13-14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the

In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 13-17 shows an example of SCI operation in transmission.

<End> [1] No Initialization Start reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Error processing (Continued below) [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER= 1 RDRF= 1 All data received? Read ORER flag in SSR [1] [2] [3] [4] [5] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. <End> Error processing Overrun error processing [3] Clear ORER flag in SSR to 0 Figure 13-18 Sample Serial Reception Flowchart

<End> [1] No Initialization Start transmission/reception [5] Error processing [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER= 1 All data received? [2]Read TDRE flag in SSR No Yes TDRE= 1 Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes RDRF= 1 Read ORER flag in SSR [4]Read RDRF flag in SSR Clear TE and RE bits in SCR to 0 Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. [1] [2] [3] [4] [5] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Figure 13-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

13.4 SCI Interrupts

The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 13-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DMAC or DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. The DMAC and DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC or DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. The DMAC and DTC cannot be activated by an ERI interrupt request.

Table 13-12 SCI Interrupt Sources Channel Interrupt Source Description DTC Activation DMAC Activation Priority*

0 ERI Interrupt due to receive error

(ORER, FER, or PER) Not possible Not possible High RXI Interrupt due to receive data full state (RDRF) Possible Possible TXI Interrupt due to transmit data empty state (TDRE) Possible Possible TEI Interrupt due to transmission end (TEND) Not possible Not possible

1 ERI Interrupt due to receive error

(ORER, FER, or PER) Not possible Not possible RXI Interrupt due to receive data full state (RDRF) Possible Possible TXI Interrupt due to transmit data empty state (TDRE) Possible Possible TEI Interrupt due to transmission end (TEND) Not possible Not possible Low Note: * This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of the interrupt controller. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case.

13.5 Usage Notes

The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 13-13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 13-13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags Receive Data Transfer RDRF ORER FER PER RSR to RDR Receive Error Status 1100X Overrun error

0010 Framing error

0001 Parity error

1110X Overrun error + framing error 1101X Overrun error + parity error

0011 Framing error + parity error

1111X Overrun error + framing error + parity error Notes: : Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR.

Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 13-21.

(RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing 15 0 7 15 007 Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 – 1 N (1 + F) | · 100% ... Formula (1) Where M : Reception margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 – 1 2 · 16 ) · 100% = 46.875% ... Formula (2) However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.

Restrictions on Use of DMAC or DTC

When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ø clock cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 13-22)
When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). t LSB Serial data SCK D1 D3 D4 D5D2 D6 D7 Note: When operating on an external clock, set t >4 clocks. TDRE Figure 13-22 Example of Clocked Synchronous Transmission by DTC

Section 14 Smart Card Interface

14.1 Overview

SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting.

14.1.1 Features

Features of the Smart Card interface supported by the H8S/2357 are as follows.

Asynchronous mode ¾ Data length: 8 bits ¾ Parity bit generation and checking ¾ Transmission of error signal (parity error) in receive mode ¾ Error signal detection and automatic data retransmission in transmit mode ¾ Direct convention and inverse convention both supported
On-chip baud rate generator allows any bit rate to be selected
Three interrupt sources ¾ Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently ¾ The transmit data empty interrupt and receive data full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer

14.1.2 Block Diagram

Figure 14-1 shows a block diagram of the Smart Card interface. Bus interface TDR RSR RDR Module data bus TSR SCMR SSR SCR Transmission/ reception control BRR Baud rate generator Internal data bus RxD TxD SCK Parity generation Parity check Clock ø ø/4 ø/16 ø/64 TXI RXI ERI SMR Legend SCMR RSR RDR TSR TDR SMR SCR SSR BRR : Smart Card mode register : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register : Serial status register : Bit rate register Figure 14-1 Block Diagram of Smart Card Interface

14.1.3 Pin Configuration

Table 14-1 shows the Smart Card interface pin configuration. Table 14-1 Smart Card Interface Pins Channel Pin Name Symbol I/O Function Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output

14.1.4 Register Configuration

Table 14-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface. Table 14-2 Smart Card Interface Registers Channel Name Abbreviation R/W Initial Value Address *1 Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A Transmit data register 0 TDR0 R/W H'FF H'FF7B Serial status register 0 SSR0 R/(W) *2 H'84 H'FF7C Receive data register 0 RDR0 R H'00 H'FF7D Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E Bit rate register 1 BRR1 R/W H'FF H'FF81 Serial control register 1 SCR1 R/W H'00 H'FF82 Transmit data register 1 TDR1 R/W H'FF H'FF83 Serial status register 1 SSR1 R/(W) *2 H'84 H'FF84 Receive data register 1 RDR1 R H'00 H'FF85 Smart card mode register 1 SCMR1 R/W H'F2 H'FF86 All Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

14.2 Register Descriptions

Registers added with the Smart Card interface and bits for which the function changes are described here.

14.2.1 Smart Card Mode Register (SCMR)

B i t: 76543210 Initial value : 1 1 1 1 0 0 1 0 R/W : — — — — R/W R/W — R/W SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR Description Receive data is stored in RDR LSB-first Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 14.3.4, Register Settings. Bit 2 SINV Description

0 TDR contents are transmitted as they are (Initial value)

Receive data is stored as it is in RDR

1 TDR contents are inverted before being transmitted

Receive data is stored in inverted form in RDR

Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF Description

0 Smart Card interface function is disabled (Initial value)

1 Smart Card interface function is enabled

14.2.2 Serial Status Register (SSR)

B i t: 76543210 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 R/W : R/(W) * R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS Description 0 [Clearing condition] (Initial value)

Upon reset, and in standby mode or module stop mode
When 0 is written to ERS after reading ERS = 1 1 [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state.

Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND Description 0 [Clearing conditions] (Initial value)

When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR 1 [Setting conditions]
Upon reset, and in standby mode or module stop mode
When the TE bit in SCR is 0 and the ERS bit is also 0
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit)

14.2.3 Serial Mode Register (SMR)

B i t: 76543210 GM CHR PE O/ E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Set value* :G M 0 1 O / E 1 0 CKS1 CKS0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Note: * When the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. The function of bit 7 of SMR changes in smart card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR).

0 Normal smart card interface mode operation (Initial value)

TEND flag generation 12.5 etu after beginning of start bit
Clock output ON/OFF control only

1 GSM mode smart card interface mode operation

TEND flag generation 11.0 etu after beginning of start bit
High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.5, Serial Mode Register (SMR).

14.2.4 Serial Control Register (SCR)

B i t: 76543210 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 13.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low.

SMIF C/ A, GM CKE1 CKE0 SCK Pin Function

0 See the SCI

1 0 0 0 Operates as port I/O pin 1 0 0 1 Outputs clock as SCK output pin 1 1 0 0 Operates as SCK output pin, with output fixed low 1 1 0 1 Outputs clock as SCK output pin 1 1 1 0 Operates as SCK output pin, with output fixed high 1 1 1 1 Outputs clock as SCK output pin

14.3 Operation

14.3.1 Overview

The main functions of the Smart Card interface are as follows.

One frame consists of 8-bit data plus a parity bit.
In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit.
If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer.
Only asynchronous communication is supported; there is no clocked synchronous communication function.

14.3.2 Pin Connections

Figure 14-2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the V CC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. TxD RxD SCK Rx (port) H8S/2350 I/O CLK RST VCC Connected equipment IC card Data line Clock line Reset line Figure 14-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.

14.3.3 Data Format

Figure 14-3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When there is no parity error Transmitting station output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When a parity error occurs Transmitting station output DE Receiving station output : Start bit : Data bits : Parity bit : Error signal Legend Ds D0 to D7 Dp DE Figure 14-3 Smart Card Interface Data Format

The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data.

14.3.4 Register Settings

Table 14-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 14-3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMR GM 0 1 O/ E 1 0 CKS1 CKS0 BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCR TIE RIE TE RE 0 0 CKE1 * CKE0 TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR TDRE RDRF ORER ERS PER TEND 0 0 RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 SCMR ———— SDIR SINV — SMIF Notes: — : Unused bit. *: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 14.3.5, Clock. BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 13, Serial Communication Interface. Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.

Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention).

Direct convention (SDIR = SINV = O/E = 0) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp AZZAZZZAAZ(Z) (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card.
Inverse convention (SDIR = SINV = O/E = 1) Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp AZZAAAAAAZ(Z) (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2357, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception).

14.3.5 Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 14-5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B = ø

106 Where: N = Value set in BRR (0 £ N £ 255) B = Bit rate (bit/s) ø = Operating frequency (MHz) n = See table 14-4 Table 14-4 Correspondence between n and CKS1, CKS0 n CKS1 CKS0 000 210 Table 14-5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) ø (MHz) 0 13441 14400 17473 19200 21505 24194 26882 1 6720 7200 8737 9600 10753 12097 13441 2 4480 4800 5824 6400 7168 8065 8961 Note: Bit rates are rounded to the nearest whole number.

The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 £ N £ 255, and the smaller error is specified. N = ø 1488 · 22n–1 · B

106 – 1 Table 14-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0) ø (MHz) bit/s N Error N Error N Error N Error N Error N Error N Error N Error Table 14-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ø (MHz) Maximum Bit Rate (bit/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 The bit rate error is given by the following formula: Error (%) = ( ø
106 – 1) · 100

14.3.6 Data Transfer Operations

Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis.

Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 14-6. If the DMAC or DTC is activated by a TXI request, the number of bytes set in the DMAC or DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DMAC or DTC below.

Write data to TDR, and clear TDRE flag in SSR to 0 Error processing Error processing TEND=1? All data transmitted? TEND=1? ERS=0? ERS=0? Figure 14-4 Example of Transmission Processing Flow

Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 14-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Initialization Read RDR and clear RDRF flag in SSR to 0 Clear RE bit to 0 Start reception Start Error processing No No No Yes Yes ORER = 0 and PER = 0 RDRF=1? All data received? Yes Figure 14-7 Example of Reception Processing Flow

When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 14-8. Table 14-8 Smart Card Mode Operating States and Interrupt Sources Operating State Flag Enable Bit Interrupt Source DMAC Activation DTC Activation Transmit Mode Normal operation TEND TIE TXI Possible Possible Error ERS RIE ERI Not possible Not possible Receive Mode Normal operation RDRF RIE RXI Possible Possible Error PER, ORER RIE ERI Not possible Not possible Data Transfer Operation by DMAC or DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or DTC before carrying out SCI setting. For details of the DMAC and DTC setting procedures, see section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC). In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared.

14.3.7 Operation in GSM Mode

Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty.

When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state.
When returning to smart card interface mode from software standby mode [7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set smart card interface mode and output the clock. Signal generation is started with the normal duty. Software standbyNormal operation Normal operation Figure 14-9 Clock Halt and Restart Procedure

Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output.

14.4 Usage Notes

The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card Interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 14-10. Internal basic clock 372 clocks 186 clocks Receive data (RxD) Synchro- nization sampling timing D0 D1 Data sampling timing 185 371 0371185 00 Start bit Figure 14-10 Receive Data Sampling Timing in Smart Card Mode

Thus the reception margin in asynchronous mode is given by the following formula. M = œ (0.5 – 1 N (1 + F)œ · 100% Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, = 49.866% Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and transmit mode as described below.

Retransfer operation when SCI is in receive mode Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DMAC or DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission.

15.1 Overview

The H8S/2350 Series incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected.

15.1.1 Features

A/D converter features are listed below

10-bit resolution
Eight input channels
Settable analog conversion voltage range ¾ Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage
High-speed conversion ¾ Minimum conversion time: 6.7 µs per channel (at 20 MHz operation)
Choice of single mode or scan mode ¾ Single mode: Single-channel A/D conversion ¾ Scan mode: Continuous A/D conversion on 1 to 4 channels
Four data registers ¾ Conversion results are held in a 16-bit data register for each channel
Sample and hold function
Three kinds of conversion start ¾ Choice of software or timer conversion start trigger (TPU), or ADTRG pin
A/D conversion end interrupt generation ¾ A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion
Module stop mode can be set ¾ As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode.

15.1.2 Block Diagram

Figure 15-1 shows a block diagram of the A/D converter. Module data bus Control circuit Internal data bus 10-bit D/A Comparator Sample-and- hold circuit ø/8 ø/16 ADI interrupt Bus interface A D C S R A D C R A D D R D A D D R C A D D R B A D D R A AV CC Vref AV SS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG Conversion start trigger from TPU Successive approximations register Multiplexer ADCR ADCSR ADDRA ADDRB ADDRC ADDRD : A/D control register : A/D control/status register : A/D data register A : A/D data register B : A/D data register C : A/D data register D Figure 15-1 Block Diagram of A/D Converter

15.1.3 Pin Configuration

Table 15-1 summarizes the input pins used by the A/D converter. The AV CC and AVSS pins are the power supply pins for the analog block in the A/D converter. The V ref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 15-1 A/D Converter Pins Pin Name Symbol I/O Function Analog power supply pin AV CC Input Analog block power supply Analog ground pin AV SS Input Analog block ground and A/D conversion reference voltage Reference voltage pin V ref Input A/D conversion reference voltage Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Group 1 analog inputs Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input A/D external trigger input pinADTRG Input External trigger input for starting A/D conversion

15.1.4 Register Configuration

Table 15-2 summarizes the registers of the A/D converter. Table 15-2 A/D Converter Registers Name Abbreviation R/W Initial Value Address *1 A/D data register AH ADDRAH R H'00 H'FF90 A/D data register AL ADDRAL R H'00 H'FF91 A/D data register BH ADDRBH R H'00 H'FF92 A/D data register BL ADDRBL R H'00 H'FF93 A/D data register CH ADDRCH R H'00 H'FF94 A/D data register CL ADDRCL R H'00 H'FF95 A/D data register DH ADDRDH R H'00 H'FF96 A/D data register DL ADDRDL R H'00 H'FF97 A/D control/status register ADCSR R/(W) *2 H'00 H'FF98 A/D control register ADCR R/W H'3F H'FF99 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing.

15.2 Register Descriptions

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

R Bit Initial value R/W AD8 R AD7 R AD6 R AD5 R AD4 R AD3 R AD2 R AD1 R AD0 R R R R R R R There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 15- ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 15.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 15-3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 Group 1 A/D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD

15.2.2 A/D Control/Status Register (ADCSR)

R/(W)* ADIE R/W ADST R/W SCAN R/W CKS R/W CH0 R/W CH2 R/W CH1 R/W Bit Initial value R/W Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF Description 0 [Clearing conditions] (Initial value)

When 0 is written to the ADF flag after reading ADF = 1
When the DTC is activated by an ADI interrupt and ADDR is read 1 [Setting conditions]
Single mode: When A/D conversion ends
Scan mode: When A/D conversion ends on all specified channels Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE Description

0 A/D conversion end interrupt (ADI) request disabled (Initial value)

1 A/D conversion end interrupt (ADI) request enabled

Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description 0 • A/D conversion stopped (Initial value) 1 • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends

Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 15.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN Description

0 Single mode (Initial value)

1 Scan mode

Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while conversion is stopped (ADST = 0). Bit 3 CKS Description 0 Conversion time = 266 states (max.) (Initial value) 1 Conversion time = 134 states (max.) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0).

Selection Channel Selection Description CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 (Initial value) AN0

1 AN1 AN0, AN1

1 AN3 AN0 to AN3

1 AN5 AN4, AN5

1 AN7 AN4 to AN7

15.2.3 A/D Control Register (ADCR)

ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 Bit 6 TRGS0 Description 0 0 A/D conversion start by software is enabled (Initial value)

1 A/D conversion start by TPU conversion start trigger is enabled

10—

1 A/D conversion start by external trigger pin (ADTRG) is enabled

Bits 5 to 0—Reserved: These bits are reserved; they are always read as 1 and cannot be modified.

15.2.4 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9—Module Stop (MSTP9): Specifies the A/D converter module stop mode. Bit 9 MSTP9 Description

0 A/D converter module stop mode cleared

1 A/D converter module stop mode set (Initial value)

15.3 Interface to Bus Master

ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15-2 shows the data flow for ADDR access. Bus master (H'AA) ADDRnH (H'AA) ADDRnL (H'40) Lower byte read ADDRnH (H'AA) ADDRnL (H'40) TEMP (H'40) TEMP (H'40) (n = A to D) (n = A to D) Module data bus Module data busBus interface Upper byte read Bus master (H'40) Bus interface Figure 15-2 ADDR Access Operation (Reading H'AA40)

15.4 Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode.

15.4.1 Single Mode (SCAN = 0)

Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15-3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated.

State of channel 0 (AN0) A/D conversion starts ADDRA ADDRB ADDRC ADDRD State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Note: * Vertical arrows ( ) indicate instructions executed by software. Set* Set* Clear*Clear* A/D conversion result 1 A/D conversion A/D conversion result 2 Read conversion resultRead conversion result Idle Idle Idle Idle Idle Idle A/D conversion Set* Figure 15-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

15.4.2 Scan Mode (SCAN = 1)

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 15-4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).

State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Set*

1 Clear*1

Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Clear*1 Idle Idle A/D conversion time Idle Continuous A/D conversion execution A/D conversion 1Idle Idle Idle Idle Idle Transfer A/D conversion 3 A/D conversion 2 A/D conversion 5 A/D conversion 4 A/D conversion result 1 A/D conversion result 2 A/D conversion result 3 A/D conversion result 4 Figure 15-4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)

15.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15-5 shows the A/D conversion timing. Table 15-4 indicates the A/D conversion time. As indicated in figure 15-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15-4. In scan mode, the values given in table 15-4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) (2) tD tSPL tCONV ø Input sampling timing ADF Address bus Write signal Legend (1) : ADCSR write cycle (2) : ADCSR address t D : A/D conversion start delay tSPL : Input sampling time tCONV : A/D conversion time Figure 15-5 A/D Conversion Timing

Table 15-4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conversion start delay t D 1 0—1 76 —9 Input sampling time t SPL —6 3——3 1— A/D conversion time t CONV 259 — 266 131 — 134 Note: Values in the table are the number of states.

15.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 15-6 shows the timing. ø ADTRG/CR Internal trigger signal ADST A/D conversion Figure 15-6 External Trigger Input Timing

15.5 Interrupts

The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 15-5. Table 15-5 A/D Converter Interrupt Source Interrupt Source Description DTC or DMAC Activation ADI Interrupt due to end of conversion Possible

15.6 Usage Notes

The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AV SS £ ANn £ Vref. (2) Relation between AVCC , AVSS and VCC , VSS As the relationship between AVCC , AVSS and VCC , VSS , set AVSS = VSS . If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref £ AV CC . If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values.

Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVCC ) by the analog ground (AVSS ). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS ) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (V ref) should be connected between AVCC and AVSS as shown in figure 15- Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS . If a filter capacitor is connected as shown in figure 15-7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance in), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AV CC *1 *1 Vref AN0 to AN7 AV SS Notes: Values are reference values. 2. Rin: Input impedance R in*2 100 Ω 0.1 µF 0.01 µF10 µF Figure 15-7 Example of Analog Input Protection Circuit

Figure 15-9 A/D Conversion Precision Definitions (1)

Figure 15-10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2350 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kW or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kW , charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kW , and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted.

Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AV SS . Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. A/D converter equivalent circuit H8/2350 Series 20 pFC in = 15 pF 10 kΩto 10 kΩ Low-pass filter C to 0.1 µF Sensor output impedance Sensor input Note: Values are reference values. Figure 15-11 Example of Analog Input Circuit

16.1 Overview

The H8S/2350 Series includes a two-channel D/A converter.

16.1.1 Features

D/A converter features are listed below

8-bit resolution
Two output channels
Maximum conversion time of 10 µs (with 20 pF load)
Output voltage of 0 V to Vref
D/A output hold function in software standby mode
Module stop mode can be set ¾ As the initial setting, D/A converter operation is halted. Register access is enabled by exiting module stop mode.

16.1.2 Block Diagram

Figure 16-1 shows a block diagram of the D/A converter. Module data bus Internal data bus Vref AV CC DA1 DA0 AV SS 8-bit D/A Control circuit DADR0 Bus interface DADR1 DACR Figure 16-1 Block Diagram of D/A Converter

16.1.3 Pin Configuration

Table 16-1 summarizes the input and output pins of the D/A converter. Table 16-1 Pin Configuration Pin Name Symbol I/O Function Analog power pin AV CC Input Analog power source Analog ground pin AV SS Input Analog ground and reference voltage Analog output pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference voltage pin V ref Input Analog reference voltage

16.1.4 Register Configuration

Table 16-2 summarizes the registers of the D/A converter. Table 16-2 D/A Converter Registers Name Abbreviation R/W Initial Value Address * D/A data register 0 DADR0 R/W H'00 H'FFA4 D/A data register 1 DADR1 R/W H'00 H'FFA5 D/A control register DACR R/W H'1F H'FFA6 Module stop control register MSTPCR R/W H'3FFF H'FF3C Note:* Lower 16 bits of the address.

16.2 Register Descriptions

16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)

DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode.

16.2.2 D/A Control Register (DACR)

DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output for channel Bit 7 DAOE1 Description

0 Analog output DA1 is disabled (Initial value)

1 Channel 1 D/A conversion is enabled; analog output DA1 is enabled

Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output for channel Bit 6 DAOE0 Description

0 Analog output DA0 is disabled (Initial value)

1 Channel 0 D/A conversion is enabled; analog output DA0 is enabled

Bit 5—D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together. Output of resultant conversions is always controlled independently by the DAOE0 and DAOE1 bits. Bit 7 DAOE1 Bit 6 DAOE0 Bit 5 DAE Description 00 * Channel 0 and 1 D/A conversions disabled 1 0 Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled

1 Channel 0 and 1 D/A conversions enabled

1 0 0 Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 * Channel 0 and 1 D/A conversions enabled *: Don’t care If the H8S/2350 Series enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear both the DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0—Reserved: Read-only bits, always read as 1.

16.2.3 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10—Module Stop (MSTP10): Specifies the D/A converter module stop mode. Bit 10 MSTP10 Description

0 D/A converter module stop mode cleared

1 D/A converter module stop mode set (Initial value)

16.3 Operation

The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 16- 2 shows the timing of this operation. [1] Write the conversion data to DADR0. [2] Set the DAOE0 bit in DACR to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents · V ref 256 The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin.

result 1High-impedance state tDCONV DADR0 write cycle DA0 DAOE0 DADR0 Address ø DACR write cycle Conversion data 2 Conversion result 2 tDCONV Legend tDCONV : D/A conversion time DADR0 write cycle DACR write cycle Figure 16-2 Example of D/A Converter Operation

17.1 Overview

The H8S/2350 Series has 2 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR).

17.1.1 Block Diagram

Figure 17-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFF400 H'FFF402 H'FFF404 H'FFFBFE H'FFF401 H'FFF403 H'FFF405 H'FFFBFF Figure 17-1 Block Diagram of RAM

17.1.2 Register Configuration

The on-chip RAM is controlled by SYSCR. Table 17-1 shows the address and initial value of SYSCR. Table 17-1 RAM Register Name Abbreviation R/W Initial Value Address * System control register SYSCR R/W H'01 H'FF39 Note: * Lower 16 bits of the address.

17.2 Register Descriptions

17.2.1 System Control Register (SYSCR)

The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME Description

17.3 Operation

When the RAME bit is set to 1, accesses to addresses H'FFF400 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address.

17.4 Usage Note

DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0.

Section 18 ROM (H8S/2351 Only)

18.1 Overview

The H8S/2351 has 64 kbytes of on-chip ROM (mask ROM). The ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD 2, MD1, and MD0) and bit EAE in BCRL.

18.1.1 Block Diagram

Figure 18-1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000004 H'00FFFE H'000001 H'000003 H'000004 H'00FFFF Figure 18-1 Block Diagram of ROM (H8S/2351)

18.2 Operation

The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD 2, MD1, and MD0). These settings are shown in table 18-1. In normal mode, a maximum of 56 kbytes of ROM can be used. Table 18-1 Operating Modes and ROM Area Mode Pin Operating Mode MD 2 MD 1 MD 0 On-Chip ROM Mode 1 Normal expanded mode with on-chip ROM disabled 0 0 1 Disabled Mode 2 Normal expanded mode with on-chip ROM enabled 1 0 Enabled (56 kbytes) Mode 3 Normal single-chip mode 1 Mode 4 Advanced expanded mode with on-chip ROM disabled 1 0 0 Disabled Mode 5 Advanced expanded mode with on-chip ROM disabled Mode 6 Advanced expanded mode with on-chip ROM enabled 1 0 Enabled Mode 7 Advanced single-chip mode 1

Section 19 Clock Pulse Generator

19.1 Overview

The H8S/2350 Series has a built-in clock pulse generator (CPG) that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium- speed clock divider, and a bus master clock selection circuit.

19.1.1 Block Diagram

Figure 19-1 shows a block diagram of the clock pulse generator. EXTAL XTAL Duty adjustment circuit Oscillator Medium- speed divider System clock to ø pin Internal clock to supporting modules Bus master clock to CPU, DTC, and DMAC ø/2 to ø/32 SCK2 to SCK0 SCKCR Bus master clock selection circuit Figure 19-1 Block Diagram of Clock Pulse Generator

19.1.2 Register Configuration

The clock pulse generator is controlled by SCKCR. Table 19-1 shows the register configuration. Table 19-1 Clock Pulse Generator Register Name Abbreviation R/W Initial Value Address * System clock control register SCKCR R/W H'00 H'FF3A Note:* Lower 16 bits of the address.

19.2 Register Descriptions

19.2.1 System Clock Control Register (SCKCR)

SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium- speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—ø Clock Output Disable (PSTOP): Controls ø output. PSTOP Normal Operation Sleep Mode Software Standby Mode Hardware Standby Mode 0 ø output (initial value) ø output Fixed high High impedance

1 Fixed high Fixed high Fixed high High impedance

Bit 6—Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 Bit 1 SCK1 Bit 0 SCK0 Description 0 0 0 Bus master is in high-speed mode (Initial value)

1 Medium-speed clock is ø/2

1 0 Medium-speed clock is ø/4

1 Medium-speed clock is ø/8

1 0 0 Medium-speed clock is ø/16

1 Medium-speed clock is ø/32

1— —

19.3 Oscillator

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.

19.3.1 Connecting a Crystal Resonator

Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 19-2. Select the damping resistance Rd according to table 19-2. An AT-cut parallel-resonance crystal should be used. EXTAL XTAL R d C L2 C L1 C L1 = CL2 = 10 to 22pF Figure 19-2 Connection of Crystal Resonator (Example) Table 19-2 Damping Resistance Value Frequency (MHz) 2481 2 1 6 2 0 R d (W ) 1k 500 200 0 0 0 Crystal Resonator: Figure 19-3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 19-3 and the same resonance frequency as the system clock (ø). XTAL C L AT-cut parallel-resonance type EXTAL C 0 LR s Figure 19-3 Crystal Resonator Equivalent Circuit

Table 19-3 Crystal Resonator Parameters Frequency (MHz) 2481 2 1 6 2 0 R S max (W ) 500 120 80 60 50 40 C 0 max (pF) 777777 Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 19-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. C L2 Signal A Signal B C L1 H8S/2350 Series XTAL EXTAL Avoid Figure 19-4 Example of Incorrect Board Design

19.3.2 External Clock Input

Circuit Configuration: An external clock signal can be input as shown in the examples in figure 19-5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL XTAL External clock input Open (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 19-5 External Clock Input (Examples) External Clock: The external clock signal should have the same frequency as the system clock (ø). Table 19-4 and figure 19-6 show the input conditions for the external clock.

Table 19-4 External Clock Input Conditions VCC = 2.7 V to 5.5 V VCC = 5.0 V ± 10% Item Symbol Min Max Min Max Unit Test Conditions External clock input low pulse width t EXL 40 — 20 — ns Figure 19-6 External clock input high pulse width tEXH 40 — 20 — ns External clock rise time tEXr —1 0—5 n s External clock fall time tEXf —1 0—5 n s Clock low pulse width tCL 0.4 0.6 0.4 0.6 t cyc ø ‡ 5 MHz Figure 21-4 level 80 — 80 — ns ø < 5 MHz Clock high pulse width tCH 0.4 0.6 0.4 0.6 t cyc ø ‡ 5 MHz level 80 — 80 — ns ø < 5 MHz tEXH tEXL tEXr tEXf VCC × 0.5EXTAL Figure 19-6 External Clock Input Timing

19.4 Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (ø).

19.5 Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.

19.6 Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed clocks (ø/2, ø/4, or ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR.

Section 20 Power-Down Modes

20.1 Overview

In addition to the normal program execution state, the H8S/2350 Series has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2350 Series operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode Of these, (2) to (6) are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the H8S/2350 Series is in high-speed mode. Table 20-1 shows the conditions for transition to the various modes, the status of the CPU, on-chip supporting modules, etc., and the method of clearing each mode.

Table 20-1 Operating Modes Operating Transition Clearing CPU Modules Mode Condition Condition Oscillator Registers Registers I/O Ports High speed mode Control register Functions High speed Functions High speed Functions High speed Medium- speed mode Control register Functions Medium speed Functions High/ medium speed * Functions High speed Sleep mode Instruction Interrupt Functions Halted Retained High speed Functions High speed Module stop mode Control register Functions High/ medium speed Functions Halted Retained/ reset * Retained Software standby mode Instruction External interrupt Halted Halted Retained Halted Retained/ reset * Retained Hardware standby mode Pin Halted Halted Undefined Halted Reset High impedance Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. The SCI and A/D converter are reset, and other on-chip supporting modules retain their state.

20.1.1 Register Configuration

Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 20-2 summarizes these registers. Table 20-2 Power-Down Mode Registers Name Abbreviation R/W Initial Value Address * Standby control register SBYCR R/W H'08 H'FF38 System clock control register SCKCR R/W H'00 H'FF3A Module stop control register H MSTPCRH R/W H'3F H'FF3C Module stop control register L MSTPCRL R/W H'FF H'FF3D Note: * Lower 16 bits of the address.

20.2 Register Descriptions

20.2.1 Standby Control Register (SBYCR)

SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode. Remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. The SSBY bit should be cleared by writing 0 to it. Bit 7 SSBY Description

0 Transition to sleep mode after execution of SLEEP instruction (Initial value)

1 Transition to software standby mode after execution of SLEEP instruction

Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 20-4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection can be made. Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Standby time = 8192 states (Initial value)

1 Standby time = 16384 states

1 0 Standby time = 32768 states

1 Standby time = 65536 states

1 0 0 Standby time = 131072 states

1 Standby time = 262144 states

1 Standby time = 16 states

Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance state in software standby mode. Bit 3 OPE Description

0 In software standby mode, address bus and bus control signals are high-impedance

1 In software standby mode, address bus and bus control signals retain output state

(Initial value) Bits 2 and 1—Reserved: Read-only bits, always read as 0. Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.

20.2.2 System Clock Control Register (SCKCR)

SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium- speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—ø Clock Output Disable (PSTOP): Controls ø output. 0 ø output (initial value) ø output Fixed high High impedance Bits 6—Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3—Reserved: Read-only bits, always read as 0.

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 Bit 1 SCK1 Bit 0 SCK0 Description 0 0 0 Bus master in high-speed mode (Initial value) 1 0 Medium-speed clock is ø/4 1 0 0 Medium-speed clock is ø/16 1— —

20.2.3 Module Stop Control Register (MSTPCR)

MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 15 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 20-3 for the method of selecting on-chip supporting modules. Bits 15 to 0 MSTP15 to MSTP0 Description

0 Module stop mode cleared

1 Module stop mode set

20.3 Medium-Speed Mode

When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium- speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC and DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (ø). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 20-1 shows the timing for transition to and clearance of medium-speed mode. Bus master clock supporting module clock Internal address bus Internal write signal Medium-speed mode SCKCRSCKCR Figure 20-1 Medium-Speed Mode Transition and Clearance Timing

20.4 Sleep Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state. Sleep mode is not cleared if interrupts are disabled, or if interrupts other than NMI are masked by the CPU. When the STBY pin is driven low, a transition is made to hardware standby mode.

20.5 Module Stop Mode

20.5.1 Module Stop Mode

Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 20-3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and A/D converter are retained. After reset clearance, all modules other than DMAC and DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Do not make a transition to sleep mode with MSTPCR set to H'FFFF, as this will halt operation of the bus controller.

Table 20-3 MSTP Bits and Corresponding On-Chip Supporting Modules Register Bit Module MSTPCRH MSTP15 DMA controller (DMAC) MSTP14 Data transfer controller (DTC) MSTP13 16-bit timer pulse unit (TPU) MSTP12 — MSTP11 Programmable pulse generator (PPG) MSTP10 D/A converter MSTP9 A/D converter MSTP8 — MSTPCRL MSTP7 — MSTP6 Serial communication interface (SCI) channel 1 MSTP5 Serial communication interface (SCI) channel 0 MSTP4 — MSTP3 — MSTP2 — MSTP1 — MSTP0 — Note: Bits 12, 8, 7, and 4 to 0 can be read or written to, but do not affect operation.

20.5.2 Usage Notes

DMAC/DTC Module Stop: Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller. On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU.

20.6 Software Standby Mode

20.6.1 Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced.

20.6.2 Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ2), or by means of the RES pin or STBY pin.

Clearing with an interrupt When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire H8S/2350 Series chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source.
Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2350 Series chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling.
Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode.

20.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode

Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 20-4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 20-4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time MHz MHz MHz MHz MHz MHz MHz MHz Unit : Recommended time setting Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended.

20.6.4 Software Standby Mode Application Example

Figure 20-2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.

ø NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 SLEEP instruction Software standby mode (power-down mode) Oscillation stabilization time t OSC2 NMI exception handling Figure 20-2 Software Standby Mode Application Example

20.6.5 Usage Notes

I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 6.9, Write Data Buffer Function, for details of the write data buffer function.

20.7 Hardware Standby Mode

20.7.1 Hardware Standby Mode

When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD 2 to MD0) while the H8S/2350 Series is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state.

20.7.2 Hardware Standby Mode Timing

Figure 20-3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.

Figure 20-3 Hardware Standby Mode Timing (Example) 20.8 ø Clock Output Disabling Function Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle, and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set. Table 20-5 shows the state of the ø pin in each processing state. Table 20-5 ø Pin State in Each Processing State DDR 0 1 PSTOP — 0 1 Hardware standby mode High impedance Software standby mode High impedance Fixed high Sleep mode High impedance ø output Fixed high Normal operating state High impedance ø output Fixed high

Section 21 Electrical Characteristics

21.1 Absolute Maximum Ratings

Table 21-1 lists the absolute maximum ratings. Table 21-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage V CC –0.3 to +7.0 V Input voltage (except port 4) Vin –0.3 to VCC +0.3 V Input voltage (port 4) V in –0.3 to AVCC +0.3 V Reference voltage V ref –0.3 to AVCC +0.3 V Analog power supply voltage AV CC –0.3 to +7.0 V Analog input voltage V AN –0.3 to AVCC +0.3 V Operating temperature T opr Regular specifications: –20 to +75 °C Wide-range specifications: –40 to +85 °C Storage temperature T stg –55 to +125 °C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.

21.2 DC Characteristics

Table 21-2 lists the DC characteristics. Table 21-3 lists the permissible output currents. Table 21-2 DC Characteristics Conditions: V CC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions Schmitt trigger input voltage Port 2, 4 to P67, PA 4 to PA7 VT VT VT + – VT 1.0 0.4 VCC · 0.7 V V V Input high voltage RES, STBY, NMI, MD2 to MD0 VIH VCC – 0.7 — V CC + 0.3 V EXTAL V CC · 0.7 — V CC + 0.3 V Port 1, 3, 5, B to G, 0 to P63, PA 0 to PA3 2.0 — V CC + 0.3 V Port4 2.0 — AV CC + 0.3 V Input low voltage RES, STBY, MD 2 to MD0 VIL –0.3 — 0.5 V NMI, EXTAL, Port 1, 3 to 5, B to G, 0 to P63, PA 0 to PA3 –0.3 — 0.8 V Output high All output pins VOH VCC – 0.5 — — V I OH = –200 µA voltage 3.5 — — V I OH = –1 mA Output low All output pins VOL — — 0.4 V I OL = 1.6 mA voltage Port 1, A to C — — 1.0 V I OL = 10 mA Input leakageRES | I in | — — 10.0 µA V in = current STBY, NMI, MD 2 to MD0 — — 1.0 µA 0.5 to VCC – 0.5 V Port 4 — — 1.0 µA V in = 0.5 to AVCC – 0.5 V Note: 1. If the A/D and D/A converters are not used,do not leave the AVCC , AVSS , and Vref pins open. Connect AVCC and Vref to VCC , and connect AVSS to VSS .

Table 21-2 DC Characteristics (cont) Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions Three-state leakage current (off state) Port 1 to 3, 5, 6, A to G TSI‰ — — 1.0 µA V in = 0.5 to VCC – 0.5 V MOS input pull-up current* Port A to E –I P 50 — 300 µA V in = 0 V Input capacitance RES NMI All input pins except RES and NMI C in — pF pF pF Vin = 0 V f = 1 MHz T a = 25°C Current dissipation* Normal operation I CC*4 —6 0 (5.0 V) 95 mA f = 20 MHz Sleep mode — 45 (5.0 V) 78 mA f = 20 MHz Standby — 0.01 5.0 µA T a £ 50°C mode *3 — — 20 50°C < T a Analog power supply current During A/D and D/A conversion Al CC — 0.8 (5.0 V) 2.0 mA Idle — 0.01 5.0 µA Reference current During A/D and D/A conversion Al CC — 1.9 (5.0 V) 3.0 mA Idle — 0.01 5.0 µA RAM standby voltage V RAM 2.0 — — V Notes: 1. If the A/D and D/A converters are not used,do not leave the AVCC , AVSS , and Vref pins open. Connect AV CC and Vref to VCC , and connect AVSS to VSS . 2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5V with all output pins unloaded and the on-chip pull-up transistors in the off state. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 0.85 (mA/(MHz · V)) · VCC · f [normal mode] I CC max = 1.0 (mA) + 0.7 (mA/(MHz · V)) · VCC · f [sleep mode] 5. Only applies to the H8S/2351.

Table 21-2 DC Characteristics (cont) Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions Schmitt trigger input voltage Port 2, 4 to P67, PA 4 to PA7 VT VT VT + – VT VCC · 0.2 VCC · 0.07 VCC · 0.7 V V V Input high voltage RES, STBY, NMI, MD2 to MD0 VIH VCC · 0.9 — V CC +0.3 V EXTAL V CC · 0.7 — V CC +0.3 V Port 1, 3, 5, B to G, 0 to P63, PA 0 to PA3 VCC · 0.7 — V CC +0.3 V Port 4 V CC · 0.7 — AV CC +0.3 V Input low voltage RES, STBY, MD 2 to MD0 VIL –0.3 — V CC · 0.1 V NMI, EXTAL, Port 1, 3 to 5, B to G, 0 to P63, –0.3 — V CC · 0.2 V V CC < 4.0 V PA 0 to PA3 0.8 V CC = 4.0 to 5.5 V Output high All output pins VOH VCC – 0.5 — — V I OH = –200 µA voltage VCC – 1.0 — — V I OH = –1 mA Output low All output pins VOL — — 0.4 V I OL = 1.6 mA voltage Port 1, A to C — — 1.0 V V CC £ 4 V I OL = 5 mA 4.0 < VCC £ 5.5 V I OL = 10 mA Input leakageRES | I in | — — 10.0 µA V in = current STBY, NMI, MD 2 to MD0 — — 1.0 µA 0.5 to VCC – 0.5V Port 4 — — 1.0 µA V in = 0.5 to AVCC – 0.5V Note: 1. If the A/D and D/A converters are not used,do not leave the AVCC , AVSS , and Vref pins open. Connect AVCC and Vref to VCC , and connect AVSS to VSS .

Table 21-2 DC Characteristics (cont) Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions Three-state leakage current (off state) Port 1 to 3, 5, 6, A to G TSI‰ — — 1.0 µA V in = 0.5 to VCC –0.5 V MOS input pull-up current* Port A to E –I P 10 — 300 µA V CC = 2.7 V to

5.5 V, Vin = 0 V

C in — pF pF pF Vin = 0 V f = 1 MHz Ta = 25°C Current dissipation* Normal operation I CC*4 —2 0 (3.0 V) 48 mA f = 10 MHz Sleep mode — 12 (3.0 V) 40 mA f = 10 MHz Standby — 0.01 5.0 µA T a £ 50°C mode *3 — — 20 50°C < T a Analog power supply current During A/D and D/A conversion Al CC — 0.2 (3.0 V) 2.0 mA Idle — 0.01 5.0 µA Reference current During A/D and D/A conversion Al CC — 1.2 (3.0 V) 3.0 mA Idle — 0.01 5.0 µA RAM standby voltage V RAM 2.0 — — V Notes: 1. If the A/D and D/A converters are not used,do not leave the AVCC , AVSS , and Vref pins open. Connect AV CC and Vref to VCC , and connect AVSS to VSS . 2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5V with all output pins unloaded and the on-chip pull-up transistors in the off state. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 0.85 (mA/(MHz · V)) · VCC · f [normal mode] I CC max = 1.0 (mA) + 0.70 (mA/(MHz · V)) · VCC · f [sleep mode] 5. Only applies to the H8S/2351.

Table 21-3 Permissible Output Currents Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output Port 1, A to C I OL ——1 0m A low current (per pin)Other output pins — — 2.0 mA Permissible output low current (total) Total of 32 pins including port 1 and A to C å I OL ——8 0m A Total of all output pins, including the above — — 120 mA Permissible output high current (per pin) All output pins –I OH — — 2.0 mA Permissible output high current (total) Total of all output pins å –I OH ——4 0m A Notes: 1. To protect chip reliability, do not exceed the output current values in table 21-3. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 21-1 and 21-2. 2k Ω H8S/2350 Series Port Darlington Pair Figure 21-1 Darlington Pair Drive Circuit (Example)

600 Ω H8S/2350 Series Port 1, A to C LED Figure 21-2 LED Drive Circuit (Example)

21.3 AC Characteristics

Figure 21-3 show, the test conditions for the AC characteristics. C LSI output pin R H R L C = 90 pF: Port 1, A to F C = 30 pF: Port 2, 3, 5, 6, G R L = 2.4 kΩ R H = 12 kΩ I/O timing test levels

Low level: 0.8 V
High level: 2.0 V 5 V Figure 21-3 Output Load Circuit

21.3.1 Clock Timing

Table 21-4 lists the clock timing Table 21-4 Clock Timing Condition A: V V SS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , V SS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions Clock cycle time t cyc 100 500 50 500 ns Figure 21-4 Clock high pulse width t CH 35 — 20 — ns Figure 21-4 Clock low pulse width t CL 35 — 20 — ns Clock rise time t Cr —1 5—5 n s Clock fall time t Cf —1 5—5 n s Clock oscillator setting time at reset (crystal) t OSC1 20 — 10 — ms Figure 21-5 Clock oscillator setting time in software standby (crystal) t OSC2 20 — 10 — ms Figure 20-2 External clock output stabilization delay time t DEXT 500 — 500 — µs Figure 21-5 tCH tCf tcyc tCL tCr ø Figure 21-4 System Clock Timing

ø tDEXT tDEXT Figure 21-5 Oscillator Settling Timing

21.3.2 Control Signal Timing

Table 21-5 lists the control signal timing. Table 21-5 Control Signal Timing— Condition A: V V SS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , V SS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions RES setup time t RESS 200 — 200 — ns Figure 21-6 RES pulse width t RESW 20 — 20 — t cyc NMI reset setup time t NMIRS 250 — 200 — ns NMI reset hold time t NMIRH 200 — 200 — NMI setup time t NMIS 250 — 150 — ns Figure 21-7 NMI hold time t NMIH 10 — 10 — NMI pulse width (exiting software standby mode) t NMIW 200 — 200 — ns IRQ setup time t IRQS 250 — 150 — ns IRQ hold time t IRQH 10 — 10 — ns IRQ pulse width (exiting software standby mode) t IRQW 200 — 200 — ns

21.3.3 Bus Timing

Table 21-6 lists the bus timing. Table 21-6 Bus Timing Condition A: V V SS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , V SS = AVSS = 0 V, ø= 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions Address delay time t AD — 40 — 20 ns Figure 21-8 to Address setup time t AS 0.5 · t cyc – 30 — 0.5 · t cyc – 15 —n s Figure 21-15 Address hold time t AH 0.5 · t cyc – 20 — 0.5 · t cyc – 10 —n s Precharge time t PCH 1.5 · t cyc – 40 — 1.5 · t cyc – 20 —n s CS delay time 1 t CSD1 — 40 — 20 ns CS delay time 2 t CSD2 — 40 — 20 ns AS delay time t ASD — 40 — 20 ns RD delay time 1 t RSD1 — 40 — 20 ns RD delay time 2 t RSD2 — 40 — 20 ns CAS delay time t CASD — 40 — 20 ns Read data setup time t RDS 30 — 15 — ns Read data hold time t RDH 0—0—n s Read data access time1 t ACC1 — 1.0 · t cyc – 50 — 1.0 · t cyc – 25 ns Read data access time2 t ACC2 — 1.5 · t cyc – 50 — 1.5 · t cyc – 25 ns Read data access time3 t ACC3 — 2.0 · t cyc – 50 — 2.0 · t cyc – 25 ns

Table 21-6 Bus Timing (cont) V SS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , V SS = AVSS = 0 V, ø= 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions Read data access time 4 t ACC4 — 2.5 · t cyc – 50 — 2.5 · t cyc – 25 ns Figure 21-8 to Figure 21-15 Read data access time 5 t ACC5 — 3.0 · t cyc – 50 — 3.0 · t cyc – 25 ns WR delay time 1 t WRD1 — 40 — 20 ns WR delay time 2 t WRD2 — 40 — 20 ns WR pulse width 1 t WSW1 1.0 · t cyc – 40 — 1.0 · t cyc – 20 —n s WR pulse width 2 t WSW2 1.5 · t cyc – 40 — 1.5 · t cyc – 20 —n s Write data delay time t WDD — 60 — 30 ns Write data setup time t WDS 0.5 · t cyc – 40 — 0.5 · t cyc – 20 —n s Write data hold time t WDH 0.5 · t cyc – 20 — 0.5 · t cyc – 10 —n s WR setup time t WCS 0.5 · t cyc – 20 — 0.5 · t cyc – 10 —n s WR hold time t WCH 0.5 · t cyc – 20 — 0.5 · t cyc – 10 —n s CAS setup time t CSR 0.5 · t cyc – 20 — 0.5 · t cyc – 10 — ns Figure 21-12 WAIT setup time t WTS 60 — 30 — ns Figure 21-10 WAIT hold time t WTH 1 0 —5—n s BREQ setup time t BRQS 60 — 30 — ns Figure 21-16 BACK delay time t BACD — 30 — 15 ns Bus-floating time t BZD — 100 — 50 ns BREQO delay time t BRQOD — 60 — 30 ns Figure 21-17

ø tAD AS A23 to A0 tASD RD (read) tCSD1 tAS tAH tASD tACC2 tAS tAS tRSD1 tACC3 tRDS tRDH tWRD2 tWRD2 tWDD tWSW1 tWDH tAH CS7 to CS0 D 15 to D0 (read) HWR, LWR (write) D 15 to D0 (write) Figure 21-8 Basic Bus Timing (Two-State Access)

ø AS A23 to A0 tASD RD (read) tAS tAH tASD tACC4tRSD1 tACC5 tAS tRDS tRDH tWRD1 tWRD2 tWDS tWSW2 tWDH tAH CS7 to CS0 D 15 to D0 (read) HWR, LWR/CR (write) D 15 to D0 (write) tCSD1 tWDD tAD Figure 21-9 Basic Bus Timing (Three-State Access)

ø TW AS A23 to A0 RD (read) CS7 to CS0 D 15 to D0 (read) HWR, LWR/CR (write) D 15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 21-10 Basic Bus Timing (Three-State Access with One Wait State)

ø TC1 CAS A23 to A0 tACC1 TC2 tAHtAS tCSD2 tCSD1 tACC3 tWRD1 tWDD tWDH CS5 to CS2 (RAS) D 15 to D0 (read) HWR, LWR (write) D 15 to D0 (write) Tr tPCH tAD tCASD tACC4 tRDS tAD tCASD tWRD1 Tp tWCS tWDS tWCH Figure 21-11 DRAM Bus Timing

ø AS A23 to A0 tAH tACC3 tRDS CS7 to CS0 D 15 to D0 (read) T2 or T3 tAS tASD tASD tRDH tAD RD (read) Figure 21-14 Burst ROM Access Timing (Two-State Access)

ø AS A23 to A0 tACC1 CS7 to CS0 D 15 to D0 (read) T2 or T3 tRDH tAD RD (read) tRDS Figure 21-15 Burst ROM Access Timing (One-State Access)

21.3.4 DMAC Timing

Table 21-7 lists the DMAC timing. Table 21-7 DMAC Timing Condition A: V V SS = AVSS = 0V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , V SS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions DREQ setup time t DRQS 40 — 30 — ns Figure 21-21 DREQ hold time t DRQH 10 — 10 — TEND delay time t TED — 40 — 20 Figure 21-20 DACK delay time 1 t DACD1 — 40 — 20 ns Figure 21-18, DACK delay time 2 t DACD2 —4 0—2 0 Figure 21-19

ø AS A23 to A0 RD (read) CS7 to CS0 D 15 to D0 (read) HWR, LWR (write) D 15 to D0 (write) tDACD1 tDACD2 DACK0 , DACK1 Figure 21-18 DMAC Single Address Transfer Timing (Two-State Access)

ø AS A23 to A0 RD (read) CS7 to CS0 D 15 to D0 (read) HWR, LWR (write) D 15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 21-19 DMAC Single Address Transfer Timing (Three-State Access)

21.3.5 Timing of On-Chip Supporting Modules

Table 21-8 lists the timing of on-chip supporting modules. Table 21-8 Timing of On-Chip Supporting Modules Condition A: V V SS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , V SS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions PORT Output data delay time t PWD — 100 — 50 ns Figure 21-22 Input data setup time t PRS 50 — 30 — Input data hold time t PRH 50 — 30 — PPG Pulse output delay time t POD — 100 — 50 ns Figure 21-23 TPU Timer output delay time t TOCD — 100 — 50 ns Figure 21-24 Timer input setup time t TICS 50 — 30 — Timer clock input setup time t TCKS 50 — 30 — ns Figure 21-25 Timer clock Single edge t TCKWH 1.5 — 1.5 — t cyc pulse width Both edges t TCKWL 2.5 — 2.5 —

Table 21-8 Timing of On-Chip Supporting Modules (cont) V SS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , V SS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions WDT Overflow output delay time t WOVD — 100 — 50 ns Figure 21-26 SCI Input clock Asynchro- nous t Scyc 4—4—t cyc Figure 21-27 cycle Synchro- nous 6—6— Input clock pulse width t SCKW 0.4 0.6 0.4 0.6 t Scyc Input clock rise time t SCKr — 1.5 — 1.5 t cyc Input clock fall time t SCKf — 1.5 — 1.5 Transmit data delay time t TXD — 100 — 50 ns Figure 21-28 Receive data setup time (synchronous) t RXS 100 — 50 — ns Receive data hold time (synchronous) t RXH 100 — 50 — ns A/D converter Trigger input setup time t TRGS 50 — 30 — ns Figure 21-29

21.4 A/D Conversion Characteristics

Table 21-9 lists the A/D conversion characteristics. Table 21-9 A/D Conversion Characteristics Condition A: V CC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC , VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 bits Conversion time — — 13.4 — — 6.7 µs Analog input capacitance — — 20 — — 20 pF Permissible signal-source — — 10 *1 ——1 0 *3 kW Nonlinearity error — — ±6.0 — — ±3.0 LSB Offset error — — ±4.0 — — ±2.0 LSB Full-scale error — — ±4.0 — — ±2.0 LSB Quantization — — ±0.5 — — ±0.5 LSB Absolute accuracy — — ±8.0 — — ±4.0 LSB Notes: 1. 4.0 V £ AVCC £ 5.5 V 2. 2.7 V £ AVCC < 4.0 V 3. ø £ 12 MHz 4. ø > 12 MHz

21.5 D/A Convervion Characteristics

Table 21-10 lists the D/A conversion characteristics Table 21-10 D/A Conversion Characteristics Condition A: V CC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC , VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC , VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Min Typ Max Min Typ Max Unit Test Conditions Resolution 888888b i t Conversion time — — 10 — — 10 µs 20-pF capacitive load Absolute accuracy — ±2.0 ±3.0 — ±1.0 ±1.5 LSB 2-M W resistive load — — ±2.0 — — ±1.0 LSB 4-M W resistive load

21.6 Usage Note

Although both the ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the ZTAT version, a similar evaluation should also be performed using the mask ROM version.

Appendix A Instruction Set A.1 Instruction List Operand Notation Rd General register (destination) *1 Rs General register (source) *1 Rn General register *1 ERn General register (32-bit register) MAC Multiply-and-accumulate register (32-bit register) *2 (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Add – Subtract

Multiply ÷ Divide Ù Logical AND Ú Logical OR ¯ Logical exclusive OR ﬁ Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ¬ Logical NOT (logical complement) ( ) < > Contents of operand Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. The MAC register cannot be used in the H8S/2350 Series.

Changes according to the result of instruction * Undetermined (no guaranteed value)

0 Always cleared to 0

1 Always set to 1

— Not affected by execution of the instruction

(1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic MOV MOV.B #xx:8,Rd B 2 MOV.B Rs,Rd B 2 MOV.B @ERs,Rd B 2 MOV.B @(d:16,ERs),Rd B 4 MOV.B @(d:32,ERs),Rd B 8 MOV.B @ERs+,Rd B 2 MOV.B @aa:8,Rd B 2 MOV.B @aa:16,Rd B 4 MOV.B @aa:32,Rd B 6 MOV.B Rs,@ERd B 2 MOV.B Rs,@(d:16,ERd) B 4 MOV.B Rs,@(d:32,ERd) B 8 MOV.B Rs,@-ERd B 2 MOV.B Rs,@aa:8 B 2 MOV.B Rs,@aa:16 B 4 MOV.B Rs,@aa:32 B 6 MOV.W #xx:16,Rd W 4 MOV.W Rs,Rd W 2 MOV.W @ERs,Rd W 2 Rs8→ Rd8 — — 0 — 1 @ERs → Rd8,ERs32+1→ ERs32 — — 0 — 3 ERd32-1→ ERd32,Rs8→ @ERd — — 0 — 3 Rs16→ Rd16 — — 0 — 1 Operation Condition Code NormalIHNZV C Advanced No. of States*

Table A-1 Instruction Set (cont) (1) Data Transfer Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic MOV MOV.W @(d:16,ERs),Rd W 4 MOV.W @(d:32,ERs),Rd W 8 MOV.W @ERs+,Rd W 2 MOV.W @aa:16,Rd W 4 MOV.W @aa:32,Rd W 6 MOV.W Rs,@ERd W 2 MOV.W Rs,@(d:16,ERd) W 4 MOV.W Rs,@(d:32,ERd) W 8 MOV.W Rs,@-ERd W 2 MOV.W Rs,@aa:16 W 4 MOV.W Rs,@aa:32 W 6 MOV.L #xx:32,ERd L 6 MOV.L ERs,ERd L 2 MOV.L @ERs,ERd L 4 MOV.L @(d:16,ERs),ERd L 6 MOV.L @(d:32,ERs),ERd L 10 MOV.L @ERs+,ERd L 4 MOV.L @aa:16,ERd L 6 MOV.L @aa:32,ERd L 8 @ERs → Rd16,ERs32+2→ ERs32 — — 0 — 3 ERd32-2→ ERd32,Rs16→ @ERd — — 0 — 3 ERs32 → ERd32 — — 0 — 1 @(d:16,ERs)→ ERd32 — — 0 — 5 @(d:32,ERs)→ ERd32 — — 0 — 7 @ERs → ERd32,ERs32+4 → ERs32 —— 0 — 5 Operation Condition Code NormalIHNZV C Advanced No. of States*1

Table A-1 Instruction Set (cont) (1) Data Transfer Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic MOV POP PUSH LDM STM MOVFPE MOVTPE MOV.L ERs,@ERd L 4 MOV.L ERs,@(d:16,ERd) L 6 MOV.L ERs,@(d:32,ERd) L 10 MOV.L ERs,@-ERd L 4 MOV.L ERs,@aa:16 L 6 MOV.L ERs,@aa:32 L 8 POP.W Rn W 2 POP.L ERn L 4 PUSH.W Rn W 2 PUSH.L ERn L 4 LDM @SP+,(ERm-ERn) L 4 STM (ERm-ERn),@-SP L 4 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 ERd32-4→ ERd32,ERs32 → @ ERd —— 0 — 5 @SP → ERn32,SP+4 → SP — — 0 — 5 SP-4→ SP,ERn32 → @SP — — 0 — 5 Repeated for each register restored Repeated for each register saved [2] [2] Operation Condition Code NormalIHNZV C Advanced No. of States* Cannot be used in the H8S/2350 Series Cannot be used in the H8S/2350 Series

(2) Arithmetic Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic ADD ADDX ADDS INC DAA SUB ADD.B #xx:8,Rd B 2 ADD.B Rs,Rd B 2 ADD.W #xx:16,Rd W 4 ADD.W Rs,Rd W 2 ADD.L #xx:32,ERd L 6 ADD.L ERs,ERd L 2 ADDX #xx:8,Rd B 2 ADDX Rs,Rd B 2 ADDS #1,ERd L 2 ADDS #2,ERd L 2 ADDS #4,ERd L 2 INC.B Rd B 2 INC.W #1,Rd W 2 INC.W #2,Rd W 2 INC.L #1,ERd L 2 INC.L #2,ERd L 2 DAA Rd B 2 SUB.B Rs,Rd B 2 SUB.W #xx:16,Rd W 4 Rd8+#xx:8→ Rd8 — 1 Rd8+Rs8 → Rd8 — 1 Rd16+Rs16 → Rd16 — [3] 1 ERd32+#xx:32→ ERd32 — [4] 3 ERd32+ERs32 → ERd32 — [4] 1 Rd8+#xx:8+C→ Rd8 — [5] 1 Rd8+Rs8+C → Rd8 — [5] 1 Rd16+1 → Rd16 — — — 1 Rd16+2 → Rd16 — — — 1 ERd32+1 → ERd32 — — — 1 ERd32+2 → ERd32 — — — 1 Rd8 decimal adjust→ Rd8 — ** 1 Rd8-Rs8→ Rd8 — 1 Operation Condition Code NormalIHNZV C Advanced No. of States* ↔↔↔ ↔↔ ↔↔

Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic SUB SUBX SUBS DEC DAS MULXU MULXS SUB.W Rs,Rd W 2 SUB.L #xx:32,ERd L 6 SUB.L ERs,ERd L 2 SUBX #xx:8,Rd B 2 SUBX Rs,Rd B 2 SUBS #1,ERd L 2 SUBS #2,ERd L 2 SUBS #4,ERd L 2 DEC.B Rd B 2 DEC.W #1,Rd W 2 DEC.W #2,Rd W 2 DEC.L #1,ERd L 2 DEC.L #2,ERd L 2 DAS Rd B 2 MULXU.B Rs,Rd B 2 MULXU.W Rs,ERd W 2 MULXS.B Rs,Rd B 4 MULXS.W Rs,ERd W 4 Rd16-Rs16→ Rd16 — [3] 1 ERd32-#xx:32→ ERd32 — [4] 3 ERd32-ERs32 → ERd32 — [4] 1 Rd8-#xx:8-C→ Rd8 — [5] 1 Rd8-Rs8-C→ Rd8 — [5] 1 Rd8-1→ Rd8 — — — 1 Rd16-1→ Rd16 — — — 1 Rd16-2→ Rd16 — — — 1 ERd32-1→ ERd32 — — — 1 ERd32-2→ ERd32 — — — 1 Rd8 decimal adjust→ Rd8 — * * —1 Rd8 ×Rs8→ Rd16 (unsigned multiplication)—————— 1 2 (unsigned multiplication) Rd8 ×Rs8→ Rd16 (signed multiplication)—— —— 1 3 (signed multiplication) Operation Condition Code NormalIHNZV C Advanced No. of States*1 ↔↔↔

Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic DIVXU DIVXS CMP NEG EXTU DIVXU.B Rs,Rd B 2 DIVXU.W Rs,ERd W 2 divxs.B Rs,Rd B 4 DIVXS.W Rs,ERd W 4 CMP.B #xx:8,Rd B 2 CMP.B Rs,Rd B 2 CMP.W #xx:16,Rd W 4 CMP.W Rs,Rd W 2 CMP.L #xx:32,ERd L 6 CMP.L ERs,ERd L 2 NEG.B Rd B 2 NEG.W Rd W 2 NEG.L ERd L 2 EXTU.W Rd W 2 EXTU.L ERd L 2 Rd16 ÷Rs8→ Rd16 (RdH: remainder,— — [6] [7] — — 12 RdL: quotient) (unsigned division) ERd32 ÷Rs16→ ERd32 (Ed: remainder,— — [6] [7] — — 20 Rd: quotient) (unsigned division) Rd16 ÷Rs8→ Rd16 (RdH: remainder,— — [8] [7] — — 13 RdL: quotient) (signed division) ERd32 ÷Rs16→ ERd32 (Ed: remainder,— — [8] [7] — — 21 Rd: quotient) (signed division) Rd8-#xx:8 — 1 Rd8-Rs8 — 1 Rd16-Rs16 — [3] 1 ERd32-#xx:32 — [4] 3 ERd32-ERs32 — [4] 1 0-Rd8→ Rd8 — 1 0-Rd16→ Rd16 — 1 0-ERd32→ ERd32 — 1 0→ (<bit 15 to 8> of Rd16) — — 0 0 — 1 0→ (<bit 31 to 16> of ERd32) — — 0 0 — 1 Operation Condition Code NormalIHNZV C Advanced No. of States*

Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic EXTS TAS MAC CLRMAC LDMAC STMAC EXTS.W Rd W 2 EXTS.L ERd L 2 TAS @ERd B 4 MAC @ERn+, @ERm+ CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC MACH,ERd STMAC MACL,ERd (<bit 15 to 8> of Rd16) (<bit 31 to 16> of ERd32) @ERd-0 → CCR set, (1)→ —— 0 — 4 (<bit 7> of @ERd) [2] Operation Condition Code NormalIHNZV C Advanced No. of States* ↔ ↔ ↔ ↔ ↔ ↔ Cannot be used in the H8S/2350 Series

(3) Logical Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic AND OR XOR NOT AND.B #xx:8,Rd B 2 AND.B Rs,Rd B 2 AND.W #xx:16,Rd W 4 AND.W Rs,Rd W 2 AND.L #xx:32,ERd L 6 AND.L ERs,ERd L 4 OR.B #xx:8,Rd B 2 OR.B Rs,Rd B 2 OR.W #xx:16,Rd W 4 OR.W Rs,Rd W 2 OR.L #xx:32,ERd L 6 OR.L ERs,ERd L 4 XOR.B #xx:8,Rd B 2 XOR.B Rs,Rd B 2 XOR.W #xx:16,Rd W 4 XOR.W Rs,Rd W 2 XOR.L #xx:32,ERd L 6 XOR.L ERs,ERd L 4 NOT.B Rd B 2 NOT.W Rd W 2 NOT.L ERd L 2 Rd16 ∧Rs16→ Rd16 — — 0 — 1 ERd32 ∧#xx:32→ ERd32 — — 0 — 3 ERd32 ∧ERs32 → ERd32 — — 0 — 2 Rd16 ∨Rs16→ Rd16 — — 0 — 1 ERd32 ∨#xx:32→ ERd32 — — 0 — 3 ERd32 ∨ERs32 → ERd32 — — 0 — 2 Rd16 ⊕ Rs16→ Rd16 — — 0 — 1 ERd32 ⊕ #xx:32→ ERd32 — — 0 — 3 ERd32 ⊕ ERs32 → ERd32 — — 0 — 2 Operation Condition Code NormalIHNZV C Advanced No. of States*

(4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic SHAL SHAR SHLL SHAL.B Rd B 2 SHAL.B #2,Rd B 2 SHAL.W Rd W 2 SHAL.W #2,Rd W 2 SHAL.L ERd L 2 SHAL.L #2,ERd L 2 SHAR.B Rd B 2 SHAR.B #2,Rd B 2 SHAR.W Rd W 2 SHAR.W #2,Rd W 2 SHAR.L ERd L 2 SHAR.L #2,ERd L 2 SHLL.B Rd B 2 SHLL.B #2,Rd B 2 SHLL.W Rd W 2 SHLL.W #2,Rd W 2 SHLL.L ERd L 2 SHLL.L #2,ERd L 2 —— 1 —— 1 —— 1 —— 1 —— 1 —— 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 Operation Condition Code NormalIHNZV C Advanced No. of States* C MSB LSB MSB LSB CMSB LSB C

Table A-1 Instruction Set (cont) (4) Shift Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic SHLR ROTXL ROTXR SHLR.B Rd B 2 SHLR.B #2,Rd B 2 SHLR.W Rd W 2 SHLR.W #2,Rd W 2 SHLR.L ERd L 2 SHLR.L #2,ERd L 2 ROTXL.B Rd B 2 ROTXL.B #2,Rd B 2 ROTXL.W Rd W 2 ROTXL.W #2,Rd W 2 ROTXL.L ERd L 2 ROTXL.L #2,ERd L 2 ROTXR.B Rd B 2 ROTXR.B #2,Rd B 2 ROTXR.W Rd W 2 ROTXR.W #2,Rd W 2 ROTXR.L ERd L 2 ROTXR.L #2,ERd L 2 —— — 0 0 1 —— — 0 0 1 —— — 0 0 1 —— — 0 0 1 —— — 0 0 1 —— — 0 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— — 0 1 Operation Condition Code NormalIHNZV C Advanced No. of States* CMSB LSB C MSB LSB CMSB LSB

—— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— 0 1 —— — 0 1 —— — 0 1 —— — 0 1 —— 0 1 —— — 0 1 1— — 0 1 Table A-1 Instruction Set (cont) (4) Shift Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic ROTL ROTR ROTL.B Rd B 2 ROTL.B #2,Rd B 2 ROTL.W Rd W 2 ROTL.W #2,Rd W 2 ROTL.L ERd L 2 ROTL.L #2,ERd L 2 ROTR.B Rd B 2 ROTR.B #2,Rd B 2 ROTR.W Rd W 2 ROTR.W #2,Rd W 2 ROTR.L ERd L 2 ROTR.L #2,ERd L 2 Operation Condition Code NormalIHNZV C Advanced No. of States* CMSB LSB C MSB LSB

(5) Bit-Manipulation Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic BSET BCLR BSET #xx:3,Rd B 2 BSET #xx:3,@ERd B 4 BSET #xx:3,@aa:8 B 4 BSET #xx:3,@aa:16 B 6 BSET #xx:3,@aa:32 B 8 BSET Rn,Rd B 2 BSET Rn,@ERd B 4 BSET Rn,@aa:8 B 4 BSET Rn,@aa:16 B 6 BSET Rn,@aa:32 B 8 BCLR #xx:3,Rd B 2 BCLR #xx:3,@ERd B 4 BCLR #xx:3,@aa:8 B 4 BCLR #xx:3,@aa:16 B 6 BCLR #xx:3,@aa:32 B 8 BCLR Rn,Rd B 2 BCLR Rn,@ERd B 4 BCLR Rn,@aa:8 B 4 BCLR Rn,@aa:16 B 6 Operation Condition Code NormalIHNZV C Advanced No. of States*

Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic BCLR BNOT BTST BCLR Rn,@aa:32 B 8 BNOT #xx:3,Rd B 2 BNOT #xx:3,@ERd B 4 BNOT #xx:3,@aa:8 B 4 BNOT #xx:3,@aa:16 B 6 BNOT #xx:3,@aa:32 B 8 BNOT Rn,Rd B 2 BNOT Rn,@ERd B 4 BNOT Rn,@aa:8 B 4 BNOT Rn,@aa:16 B 6 BNOT Rn,@aa:32 B 8 BTST #xx:3,Rd B 2 BTST #xx:3,@ERd B 4 BTST #xx:3,@aa:8 B 4 BTST #xx:3,@aa:16 B 6 [¬ (#xx:3 of @ERd)] [¬ (#xx:3 of @aa:8)] [¬ (#xx:3 of @aa:16)] [¬ (#xx:3 of @aa:32)] [¬ (Rn8 of @aa:16)] [¬ (Rn8 of @aa:32)] Operation Condition Code NormalIHNZV C Advanced No. of States* ↔↔↔↔

Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic BTST BLD BILD BST BTST #xx:3,@aa:32 B 8 BTST Rn,Rd B 2 BTST Rn,@ERd B 4 BTST Rn,@aa:8 B 4 BTST Rn,@aa:16 B 6 BTST Rn,@aa:32 B 8 BLD #xx:3,Rd B 2 BLD #xx:3,@ERd B 4 BLD #xx:3,@aa:8 B 4 BLD #xx:3,@aa:16 B 6 BLD #xx:3,@aa:32 B 8 BILD #xx:3,Rd B 2 BILD #xx:3,@ERd B 4 BILD #xx:3,@aa:8 B 4 BILD #xx:3,@aa:16 B 6 BILD #xx:3,@aa:32 B 8 BST #xx:3,Rd B 2 BST #xx:3,@ERd B 4 BST #xx:3,@aa:8 B 4 Operation Condition Code NormalIHNZV C Advanced No. of States*

Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic BST BIST BAND BIAND BOR BST #xx:3,@aa:16 B 6 BST #xx:3,@aa:32 B 8 BIST #xx:3,Rd B 2 BIST #xx:3,@ERd B 4 BIST #xx:3,@aa:8 B 4 BIST #xx:3,@aa:16 B 6 BIST #xx:3,@aa:32 B 8 BAND #xx:3,Rd B 2 BAND #xx:3,@ERd B 4 BAND #xx:3,@aa:8 B 4 BAND #xx:3,@aa:16 B 6 BAND #xx:3,@aa:32 B 8 BIAND #xx:3,Rd B 2 BIAND #xx:3,@ERd B 4 BIAND #xx:3,@aa:8 B 4 BIAND #xx:3,@aa:16 B 6 BIAND #xx:3,@aa:32 B 8 BOR #xx:3,Rd B 2 BOR #xx:3,@ERd B 4 Operation Condition Code NormalIHNZV C Advanced No. of States*

Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic BOR BIOR BXOR BIXOR BOR #xx:3,@aa:8 B 4 BOR #xx:3,@aa:16 B 6 BOR #xx:3,@aa:32 B 8 BIOR #xx:3,Rd B 2 BIOR #xx:3,@ERd B 4 BIOR #xx:3,@aa:8 B 4 BIOR #xx:3,@aa:16 B 6 BIOR #xx:3,@aa:32 B 8 BXOR #xx:3,Rd B 2 BXOR #xx:3,@ERd B 4 BXOR #xx:3,@aa:8 B 4 BXOR #xx:3,@aa:16 B 6 BXOR #xx:3,@aa:32 B 8 BIXOR #xx:3,Rd B 2 BIXOR #xx:3,@ERd B 4 BIXOR #xx:3,@aa:8 B 4 BIXOR #xx:3,@aa:16 B 6 BIXOR #xx:3,@aa:32 B 8 Operation Condition Code NormalIHNZV C Advanced No. of States*

(6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic Operation Condition Code Branching Condition NormalIHNZV C Advanced No. of States*1 BRA d:8(BT d:8) — 2 if condition is true then BRA d:16(BT d:16) — 4 PC ← PC+d BRN d:8(BF d:8) — 2 else next; BRN d:16(BF d:16) — 4 BHI d:8 — 2 BHI d:16 — 4 BLS d:8 — 2 BLS d:16 — 4 BCC d:B(BHS d:8) — 2 BCC d:16(BHS d:16) — 4 BCS d:8(BLO d:8) — 2 BCS d:16(BLO d:16) — 4 BNE d:8 — 2 BNE d:16 — 4 BEQ d:8 — 2 BEQ d:16 — 4 BVC d:8 — 2 BVC d:16 — 4

Table A-1 Instruction Set (cont) (6) Branch Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic Operation Condition Code Branching Condition NormalIHNZV C Advanced No. of States*1 BVS d:8 — 2 BVS d:16 — 4 BPL d:8 — 2 BPL d:16 — 4 BMI d:8 — 2 BMI d:16 — 4 BGE d:8 — 2 BGE d:16 — 4 BLT d:8 — 2 BLT d:16 — 4 BGT d:8 — 2 BGT d:16 — 4 BLE d:8 — 2 BLE d:16 — 4

Table A-1 Instruction Set (cont) (6) Branch Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic JMP BSR JSR RTS JMP @ERn — 2 JMP @aa:24 — 4 JMP @@aa:8 — 2 BSR d:8 — 2 BSR d:16 — 4 JSR @ERn — 2 JSR @aa:24 — 4 JSR @@aa:8 — 2 RTS — 2 Operation Condition Code NormalIHNZV C Advanced No. of States*

(7) System Control Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic TRAPA RTE SLEEP LDC TRAPA #xx:2 — RTE — SLEEP — LDC #xx:8,CCR B 2 LDC #xx:8,EXR B 4 LDC Rs,CCR B 2 LDC Rs,EXR B 2 LDC @ERs,CCR W 4 LDC @ERs,EXR W 4 LDC @(d:16,ERs),CCR W 6 LDC @(d:16,ERs),EXR W 6 LDC @(d:32,ERs),CCR W 10 LDC @(d:32,ERs),EXR W 10 LDC @ERs+,CCR W 4 LDC @ERs+,EXR W 4 LDC @aa:16,CCR W 6 LDC @aa:16,EXR W 6 LDC @aa:32,CCR W 8 LDC @aa:32,EXR W 8 EXR ← @SP+,CCR ← @SP+, 5 [9] PC ← @SP+ Transition to power-down state—————— 2 #xx:8→ CCR 1 Rs8→ CCR 1 @ERs → CCR 3 @(d:16,ERs)→ CCR 4 @(d:32,ERs)→ CCR 6 @ERs → CCR,ERs32+2 → ERs32 4 @aa:16 → CCR 4 @aa:32 → CCR 5 Operation Condition Code NormalIHNZV C Advanced No. of States* ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔

Table A-1 Instruction Set (cont) (7) System Control Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic STC ANDC ORC XORC NOP STC CCR,Rd B 2 STC EXR,Rd B 2 STC CCR,@ERd W 4 STC EXR,@ERd W 4 STC CCR,@(d:16,ERd) W 6 STC EXR,@(d:16,ERd) W 6 STC CCR,@(d:32,ERd) W 10 STC EXR,@(d:32,ERd) W 10 STC CCR,@-ERd W 4 STC EXR,@-ERd W 4 STC CCR,@aa:16 W 6 STC EXR,@aa:16 W 6 STC CCR,@aa:32 W 8 STC EXR,@aa:32 W 8 ANDC #xx:8,CCR B 2 ANDC #xx:8,EXR B 4 ORC #xx:8,CCR B 2 ORC #xx:8,EXR B 4 XORC #xx:8,CCR B 2 XORC #xx:8,EXR B 4 NOP — 2 CCR ∧#xx:8→ CCR 1 CCR ∨#xx:8→ CCR 1 CCR ⊕ #xx:8→ CCR 1 Operation Condition Code NormalIHNZV C Advanced No. of States* ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔

(8) Block Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa —Mnemonic EEPMOV Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of R4L or R4. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2350 Series. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] Set to 1 when the divisor is negative; otherwise cleared to 0. [7] Set to 1 when the divisor is zero; otherwise cleared to 0. [8] Set to 1 when the quotient is negative; otherwise cleared to 0. [9] One additional state is required for execution when EXR is valid. EEPMOV.B — 4 EEPMOV.W — 4 Repeat @ER5→ @ER6 ER5+1→ ER5 ER6+1→ ER6 R4L-1→ R4L Until R4L=0 else next; Repeat @ER5→ @ER6 ER5+1→ ER5 ER6+1→ ER6 R4-1→ R4 Until R4=0 else next; Operation Condition Code NormalIHNZV C Advanced No. of States*

A.2 Instruction Codes Table A-2 shows the instruction codes.

Table A-2 Instruction Codes ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion ADD ADDS ADDX AND ANDC BAND Bcc B B W W L L L L L B B B B W W L L B B B B B B B ers IMM erd erd erd erd erd erd erd ers IMM IMM 0 erd

0 IMM

E rd A A B B B rd E rd A C E A A rd rd rd rd rd rd rd rd 76 0 76 0 IMM IMM IMM IMM abs disp disp rs rs rs rs rs F IMM IMM abs disp disp IMM IMM abs IMM

Table A-2 Instruction Codes (cont) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion Bcc — A B C D E F A B C D E F disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp

Table A-2 Instruction Codes (cont) BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion BCLR BIAND BILD BIOR B B B B B B B B B B B B B B B B B B B B B B B B B IMM erd erd IMM erd IMM erd IMM erd IMM IMM IMM IMM IMM IMM IMM IMM D F A A D F A A C E A A C E A A C E A A rn rd rd rd rd rd rn rn rn rn abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs IMM IMM IMM IMM IMM IMM IMM IMM

Table A-2 Instruction Codes (cont) BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion BIST BIXOR BLD BNOT B B B B B B B B B B B B B B B B B B B B B B B B B IMM erd IMM erd IMM erd IMM erd erd IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM D F A A C E A A C E A A D F A A D F A A rn rd rd rd rd rd rn rn 1r n 1r n abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs

Table A-2 Instruction Codes (cont) BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion BOR BSET BSR BST BTST B B B B B B B B B B B B B B B B B B B B B B B B B B B IMM erd IMM erd erd IMM erd IMM erd erd abs abs abs disp abs abs IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM C E A A D F A A D F A A C D F A A C E A A C rn rn rd rd rd rd rd rd rn rn rn rn rn abs abs abs disp abs abs abs abs abs abs abs

Table A-2 Instruction Codes (cont) BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion BTST BXOR CLRMAC CMP DAA DAS DEC DIVXS DIVXU EEPMOV B B B B B B B B B B W W L L B B B W W L L B W B W IMM erd ers erd erd erd erd erd IMM IMM 0 erd A E A A C E A A rd C D A F F F A B B B B B B rs rs D F D D rs rs D rd rd rd rd rd rd rd rd rd rd C rn rs rs rd F F rn 0 rn 0 abs abs IMM abs abs IMM abs abs IMM Cannot be used in the H8S/2350 Series

Table A-2 Instruction Codes (cont) EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion EXTS EXTU INC JMP JSR LDC W L W L B W W L L B B B B W W W W W W W W W W ern ern erd erd erd erd ers ers ers ers ers ers ers ers A B B B B A B D E F D F D F rd rd rd rd rd rs rs F F D D B B B B abs abs abs abs IMM IMM disp disp disp disp disp disp

Table A-2 Instruction Codes (cont) LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion LDC LDM LDMAC MAC MOV W W L L L L L B B B B B B B B B B B B B B B B W W W W W ers ers ers ers erd erd erd erd ers ers ers ern+1 ern+2 ern+3 F rd C E C rd A A E C rs A A D F rs A rs rd rd rd rd rd rd rs rs rs rs rs rd rd rd rd B B D D D A A B A IMM abs abs disp abs disp abs IMM disp abs abs abs abs disp disp disp Cannot be used in the H8S/2350 Series

Table A-2 Instruction Codes (cont) MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion MOV MOVFPE MOVTPE MULXS MULXU W W W W W W W W W L L L L L L L L L L L L L L B B B W B W ers erd erd erd erd ers erd erd erd ers ers ers ers erd erd erd erd erd erd erd erd erd ers ers ers ers ers erd erd ers D B B F D B B A F A C C rs rs rd rd rd rs rs rs rs rs rd B F D B B F D B B A A rs rs rs rd B B A abs disp abs abs abs IMM disp abs disp abs disp abs abs Cannot be used in the H8S/2350 Series disp disp

Table A-2 Instruction Codes (cont) NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion NEG NOP NOT OR ORC POP PUSH ROTL B W L B W L B B W W L L B B W L W L B B W W L L erd erd erd erd erd C rd A D D B rs rs F F C D B F rd rd rd rd rd rd rd rn rn rd rd rd rd IMM IMM D D ers 0 erd ern ern F IMM IMM IMM

Table A-2 Instruction Codes (cont) ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTS SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion ROTR ROTXL ROTXR RTE RTS SHAL B B W W L L B B W W L L B B W W L L B B W W L L erd erd erd erd erd erd erd erd C D B F C D B F rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd

Table A-2 Instruction Codes (cont) SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion SHAR SHLL SHLR SLEEP STC B B W W L L B B W W L L B B W W L L B B W W W W W W W W erd erd erd erd erd erd C D B F rd rd rd rd rd rd rd rd rd rd rd rd rd rd erd erd erd erd erd erd erd erd F F D D B B A A disp disp disp disp

Table A-2 Instruction Codes (cont) STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion STC STM STMAC SUB SUBS SUBX TAS TRAPA XOR W W W W L L L L L B W W L L L L L B B B B B W W L L ers IMM erd erd erd erd erd erd erd ers ern ern ern erd B D A A B B B rd E rd A rs rs rs E rs rs F rd rd rd rd rd rd rd B B B B D D D B A A F F F C abs abs abs abs IMM IMM IMM IMM IMM IMM Cannot be used in the H8S/2350 Series

Table A-2 Instruction Codes (cont) XORC #xx:8,CCR XORC #xx:8,EXR Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc- tion XORC B B 1 0 5 IMM IMM Note: Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. Legend Address Register 32-Bit Register Register Field General Register Register Field General Register Register Field General Register 000 001 111 ER0 ER1 ER7 0000 0001 0111 1000 1001 1111 0000 0001 0111 1000 1001 1111 R0H R1H R7H R0L R1L R7L 16-Bit Register 8-Bit Register IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: The register fields specify general registers as follows. Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.)

A.3 Operation Code Map Table A-3 shows the operation code map. Instruction code 1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1. NOP BRA MULXU BSET AH Note: * Cannot be used in the H8S/2350 Series. AL A B C D E F BRN DIVXU BNOT BHI MULXU BCLR BLS DIVXU BTST STC STMAC LDC LDMAC ORC OR BCC RTS OR BOR BIOR ANDC AND BNE RTE AND XORC XOR BCS BSR XOR BXOR BIXOR BAND BIAND LDC BEQ TRAPA BST BIST BLD BILD BVC MOV BVS A BPL JMP B BMI EEPMOV C BGE BSR D BLT MOV E ADDX SUBX BGT JSR F BLE MOV.B ADD ADDX CMP SUBX OR XOR AND MOV ADD SUB MOV MOV CMP Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(3) Table A-3 Operation Code Map (1)

Instruction code 1st byte 2nd byte AH AL BH BL MOV INC ADDS DAA DEC SUBS DAS BRA MOV MOV MOV SHLL SHLR ROTXL ROTXR NOT LDM BRN ADD ADD BHI MOV CMP CMP STM NOT BLS SUB SUB SHLL SHLR ROTXL ROTXR BCC MOVFPE * OR OR INC EXTU DEC BCS XOR XOR MAC BNE AND AND INC SHLL SHLR ROTXL ROTXR EXTU DEC BEQ LDC STC SLEEP BVC MOV ADDS SHAL SHAR ROTL ROTR NEG SUBS BVS A CLRMAC BPL MOV B NEG BMI ADD MOV SUB CMP C SHAL SHAR ROTL ROTR BGE MOVTPE * D INC EXTS DEC BLT E TAS BGT F INC SHAL SHAR ROTL ROTR EXTS DEC BLE BH AH AL Table A.3(3) Table A.3(3) Table A.3(3) Table A.3(4) Table A.3(4) Table A-3 Operation Code Map (2) Note: * Cannot be used in the H8S/2350 Series.

Instruction code 1st byte 2nd byte AH AL BH BL 3rd byte 4th byte CH CL DH DL r is the register specification field. aa is the absolute address specification. Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Notes: AH AL BH BL CH CL 01C05 01D05 01F06 7Cr06 * 7Cr07 *1 7Dr06 *1 7Dr07 *1 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 7Faa7 *2 MULXS BSET BSET BSET BSET DIVXS BNOT BNOT BNOT BNOT MULXS BCLR BCLR BCLR BCLR DIVXS BTST BTST BTST BTST OR XOR AND 789AB C D EF BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST Table A-3 Operation Code Map (3)

Instruction code 1st byte 2nd byte AH AL BH BL 3rd byte 4th byte CH CL DH DL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 5th byte 6th byte EH EL FH FL Instruction code 1st byte 2nd byte AH AL BH BL 3rd byte 4th byte CH CL DH DL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. Note: * aa is the absolute address specification. 5th byte 6th byte EH EL FH FL 7th byte 8th byte GH GL HH HL 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* 6A18aaaa7* AHALBHBLCHCLDHDLEH EL 0 BSET BNOT BCLR BTST BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST 456789AB C D EF 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* 6A38aaaaaaaa7* AHALBHBL ... FHFLGH GL 0 BSET BNOT BCLR BTST BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST 456789AB C D EF Table A-3 Operation Code Map (4)

A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I · S I + J · SJ + K · SK + L · SL + M · SM + N · SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A-5: I = L = 2, J = K = M = N = 0 From table A-4: S I = 4, SL = 2 Number of states required for execution = 2 · 4 + 2 · 2 = 12 2. JSR @@30 From table A-5: I = J = K = 2, L = M = N = 0 From table A-4: S I = SJ = SK = 4 Number of states required for execution = 2 · 4 + 2 · 4 + 2 · 4 = 24

Table A-4 Number of States per Cycle Access Conditions On-Chip Supporting External Device Module 8-Bit Bus 16-Bit Bus Cycle On-Chip Memory 8-Bit Bus 16-Bit Bus 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch SI 1 4 2 4 6 + 2m 2 3 + m Branch address read SJ Stack operation S K Byte data access S L 2 2 3 + m Word data access S M 4 4 6 + 2m Internal operation SN 11 1 1 11 1 Legend m: Number of wait states inserted into external device access

Table A-5 Number of Cycles in Instruction Execution Instruction Fetch MnemonicInstruction ADD ADDS ADDX AND ANDC BAND Bcc ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N

Table A-5 Number of Cycles in Instruction Execution (cont) Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N Bcc BCLR BIAND BILD BIOR BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32

Table A-5 Number of Cycles in Instruction Execution (cont) BIST BIXOR BLD BNOT BOR BSET BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N

Table A-5 Number of Cycles in Instruction Execution (cont) BSR BST BTST BXOR CLRMAC CMP DAA DAS DEC DIVXS DIVXU BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd Normal Advanced Normal Advanced Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N Cannot be used in the H8S/2350 Series

Table A-5 Number of Cycles in Instruction Execution (cont) EEPMOV EXTS EXTU INC JMP JSR LDC LDM LDMAC EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL 2n+2 * 2n+2 *2 Normal Advanced Normal Advanced Normal Advanced Normal Advanced Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N Cannot be used in the H8S/2350 Series

Table A-5 Number of Cycles in Instruction Execution (cont) MAC MOV MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N Cannot be used in the H8S/2350 Series

Table A-5 Number of Cycles in Instruction Execution (cont) MOV MOVFPE MOVTPE MULXS MULXU NEG NOP NOT OR ORC POP PUSH ROTL ROTR MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd Can not be used in the H8S/2350 Series Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N

Table A-5 Number of Cycles in Instruction Execution (cont) ROTXL ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP Normal Advanced Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N

Table A-5 Number of Cycles in Instruction Execution (cont) STC STM STMAC SUB SUBS SUBX TAS TRAPA XOR XORC STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L (ERn-ERn+1),@-SP STM.L (ERn-ERn+2),@-SP STM.L (ERn-ERn+3),@-SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Normal Advanced Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. Instruction Fetch MnemonicInstruction Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation IJ K L M N Cannot be used in the H8S/2350 Series

A.5 Bus States During Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Instruction JMP@aa:24 R:W 2nd Internal operation 1 state R:W EA 1 2345678 End of instruction Order of execution Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B Byte-size read R:W Word-size read W:B Byte-size write W:W Word-size write :M Transfer of the bus is not performed immediately after this cycle 2nd Address of 2nd word (3rd and 4th bytes) 3rd Address of 3rd word (5th and 6th bytes) 4th Address of 4th word (7th and 8th bytes) 5th Address of 5th word (9th and 10th bytes) NEXT Address of next instruction EA Effective address VEC Vector address

Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ø Address bus RD HWR, LWR R:W 2nd Fetching 2nd byte of instruction at jump address Fetching 1nd byte of instruction at jump address Fetching 4th byte of instruction Fetching 3rd byte of instruction R:W EA High level Internal operation Figure A-1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States)

ADD.B #xx:8,Rd R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd R:W NEXT ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd R:W NEXT AND.B #xx:8,Rd R:W NEXT AND.B Rs,Rd R:W NEXT AND.W #xx:16,Rd R:W 2nd R:W NEXT AND.W Rs,Rd R:W NEXT AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT AND.L ERs,ERd R:W 2nd R:W NEXT ANDC #xx:8,CCR R:W NEXT ANDC #xx:8,EXR R:W 2nd R:W NEXT BAND #xx:3,Rd R:W NEXT BAND #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BRA d:8 (BT d:8) R:W NEXT R:W EA BRN d:8 (BF d:8) R:W NEXT R:W EA BHI d:8 R:W NEXT R:W EA BLS d:8 R:W NEXT R:W EA BCC d:8 (BHS d:8) R:W NEXT R:W EA BCS d:8 (BLO d:8) R:W NEXT R:W EA BNE d:8 R:W NEXT R:W EA BEQ d:8 R:W NEXT R:W EA BVC d:8 R:W NEXT R:W EA BVS d:8 R:W NEXT R:W EA BPL d:8 R:W NEXT R:W EA BMI d:8 R:W NEXT R:W EA BGE d:8 R:W NEXT R:W EA BLT d:8 R:W NEXT R:W EA BGT d:8 R:W NEXT R:W EA 1 2 3 4 56789 Table A-6 Instruction Execution Cycles

Table A-6 Instruction Execution Cycles (cont) BLE d:8 R:W NEXT R:W EA BRA d:16 (BT d:16) R:W 2nd Internal operation,R:W EA 1 state BRN d:16 (BF d:16) R:W 2nd Internal operation,R:W EA 1 state BHI d:16 R:W 2nd Internal operation,R:W EA 1 state BLS d:16 R:W 2nd Internal operation,R:W EA 1 state BCC d:16 (BHS d:16) R:W 2nd Internal operation,R:W EA 1 state BCS d:16 (BLO d:16) R:W 2nd Internal operation,R:W EA 1 state BNE d:16 R:W 2nd Internal operation,R:W EA 1 state BEQ d:16 R:W 2nd Internal operation,R:W EA 1 state BVC d:16 R:W 2nd Internal operation,R:W EA 1 state BVS d:16 R:W 2nd Internal operation,R:W EA 1 state BPL d:16 R:W 2nd Internal operation,R:W EA 1 state BMI d:16 R:W 2nd Internal operation,R:W EA 1 state BGE d:16 R:W 2nd Internal operation,R:W EA 1 state BLT d:16 R:W 2nd Internal operation,R:W EA 1 state BGT d:16 R:W 2nd Internal operation,R:W EA 1 state BLE d:16 R:W 2nd Internal operation,R:W EA 1 state BCLR #xx:3,Rd R:W NEXT BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA 1 2 3 4 56789

Table A-6 Instruction Execution Cycles (cont) BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BCLR Rn,Rd R:W NEXT BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BIAND #xx:3,Rd R:W NEXT BIAND #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BIAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BIAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BIAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BILD #xx:3,Rd R:W NEXT BILD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BIOR #xx:3,Rd R:W NEXT BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BIST #xx:3,Rd R:W NEXT BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BIXOR #xx:3,Rd R:W NEXT BIXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BIXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BIXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BIXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BLD #xx:3,Rd R:W NEXT BLD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BNOT #xx:3,Rd R:W NEXT 1 2 3 4 56789

Table A-6 Instruction Execution Cycles (cont) BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BNOT Rn,Rd R:W NEXT BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BNOT Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BOR #xx:3,Rd R:W NEXT BOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BSET #xx:3,Rd R:W NEXT BSET #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BSET Rn,Rd R:W NEXT BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BSR d:8 R:W NEXT R:W EA W:W stack R:W NEXT R:W EA W:W :M stack (H)W:W stack (L) BSR d:16 R:W 2nd Internal operation,R:W EA W:W stack 1 state R:W 2nd Internal operation,R:W EA W:W :M stack (H)W:W stack (L) 1 state BST #xx:3,Rd R:W NEXT BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BTST #xx:3,Rd R:W NEXT BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT 1 2 3 4 56789 Normal Advanced Normal Advanced

Table A-6 Instruction Execution Cycles (cont) 1 2 3 4 56789 BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BTST Rn,Rd R:W NEXT BTST Rn,@ERd R:W 2nd R:B EA R:W:M NEXT BTST Rn,@aa:8 R:W 2nd R:B EA R:W:M NEXT BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT BXOR #xx:3,Rd R:W NEXT BXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT CLRMAC Cannot be used in the H8S/2350 Series CMP.B #xx:8,Rd R:W NEXT CMP.B Rs,Rd R:W NEXT CMP.W #xx:16,Rd R:W 2nd R:W NEXT CMP.W Rs,Rd R:W NEXT CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT CMP.L ERs,ERd R:W NEXT DAA Rd R:W NEXT DAS Rd R:W NEXT DEC.B Rd R:W NEXT DEC.W #1/2,Rd R:W NEXT DEC.L #1/2,ERd R:W NEXT DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states DIVXU.B Rs,Rd R:W NEXT Internal operation, 11 states DIVXU.W Rs,ERd R:W NEXT Internal operation, 19 states EEPMOV.B R:W 2nd R:B EAs *1 R:B EAd*1 R:B EAs*2 W:B EAd *2 R:W NEXT EEPMOV.W R:W 2nd R:B EAs *1 R:B EAd*1 R:B EAs*2 W:B EAd *2 R:W NEXT EXTS.W Rd R:W NEXT ← Repeated n times*2 → EXTS.L ERd R:W NEXT EXTU.W Rd R:W NEXT EXTU.L ERd R:W NEXT INC.B Rd R:W NEXT

Table A-6 Instruction Execution Cycles (cont) INC.W #1/2,Rd R:W NEXT INC.L #1/2,ERd R:W NEXT JMP @ERn R:W NEXT R:W EA JMP @aa:24 R:W 2nd Internal operation,R:W EA 1 state JMP @@aa:8 Normal R:W NEXT R:W aa:8 Internal operation,R:W EA 1 state Advanced R:W NEXT R:W:M aa:8 R:W aa:8 Internal operation,R:W EA 1 state JSR @ERn Normal R:W NEXT R:W EA W:W stack Advanced R:W NEXT R:W EA W:W :M stack (H) W:W stack (L) JSR @aa:24 Normal R:W 2nd Internal operation,R:W EA W:W stack 1 state Advanced R:W 2nd Internal operation,R:W EA W:W :M stack (H) W:W stack (L) 1 state JSR @@aa:8 Normal R:W NEXT R:W aa:8 W:W stack R:W EA Advanced R:W NEXT R:W:M aa:8 R:W aa:8 W:W :M stack (H) W:W stack (L)R:W EA LDC #xx:8,CCR R:W NEXT LDC #xx:8,EXR R:W 2nd R:W NEXT LDC Rs,CCR R:W NEXT LDC Rs,EXR R:W NEXT LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA LDC @(d:16,ERs),CCR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @(d:16,ERs),EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @(d:32,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LDC @(d:32,ERs),EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LDC @ERs+,CCR R:W 2nd R:W NEXT Internal operation,R:W EA 1 state LDC @ERs+,EXR R:W 2nd R:W NEXT Internal operation,R:W EA 1 state LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA LDC @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA LDM.L @SP+, R:W 2nd R:W:M NEXT Internal operation,R:W:M stack (H)*3 R:W stack (L)*3 (ERn–ERn+1) 1 state 1 2 3 4 56789

Table A-6 Instruction Execution Cycles (cont) LDM.L @SP+,(ERn–ERn+2) R:W 2nd R:W NEXT Internal operation,R:W:M stack (H)*3 R:W stack (L)*3 1 state LDM.L @SP+,(ERn–ERn+3) R:W 2nd R:W NEXT Internal operation,R:W:M stack (H)*3 R:W stack (L)*3 1 state LDMAC ERs,MACH Cannot be used in the H8S/2350 Series LDMAC ERs,MACL MAC @ERn+,@ERm+ R:W 2nd R:W NEXT R:W EAn R:W EAm MOV.B #xx:8,Rd R:W NEXT MOV.B Rs,Rd R:W NEXT MOV.B @ERs,Rd R:W NEXT R:B EA MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA MOV.B @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA MOV.B @ERs+,Rd R:W NEXT Internal operation,R:B EA 1 state MOV.B @aa:8,Rd R:W NEXT R:B EA MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA MOV.B Rs,@ERd R:W NEXT W:B EA MOV.B Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:B EA MOV.B Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA MOV.B Rs,@–ERd R:W NEXT Internal operation,W:B EA 1 state MOV.B Rs,@aa:8 R:W NEXT W:B EA MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:B EA MOV.W #xx:16,Rd R:W 2nd R:W NEXT MOV.W Rs,Rd R:W NEXT MOV.W @ERs,Rd R:W NEXT R:W EA MOV.W @(d:16,ERs),Rd R:W 2nd R:W NEXT R:W EA MOV.W @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA MOV.W @ERs+, Rd R:W NEXT Internal operation,R:W EA 1 state MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA MOV.W Rs,@ERd R:W NEXT W:W EA 1 2 3 4 56789

Table A-6 Instruction Execution Cycles (cont) 1 2 3 4 56789 MOV.W Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:W EA MOV.W Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:E 4th R:W NEXT W:W EA MOV.W Rs,@–ERd R:W NEXT Internal operation,W:W EA 1 state MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:W EA MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT MOV.L ERs,ERd R:W NEXT MOV.L @ERs,ERd R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2 MOV.L @(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT R:W:M EA R:W EA+2 MOV.L @ERs+,ERd R:W 2nd R:W:M NEXT Internal operation,R:W:M EA R:W EA+2 1 state MOV.L @aa:16,ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @aa:32,ERd R:W 2nd R:W:M 3rd R:W 4th R:W NEXT R:W:M EA R:W EA+2 MOV.L ERs,@ERd R:W 2nd R:W:M NEXT W:W:M EA W:W EA+2 MOV.L ERs,@(d:16,ERd) R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@(d:32,ERd) R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@–ERd R:W 2nd R:W:M NEXT Internal operation,W:W:M EA W:W EA+2 1 state MOV.L ERs,@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2 MOVFPE @aa:16,Rd Cannot be used in the H8S/2350 Series MOVTPE Rs,@aa:16 MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states MULXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states MULXU.B Rs,Rd R:W NEXT Internal operation, 11 states MULXU.W Rs,ERd R:W NEXT Internal operation, 19 states NEG.B Rd R:W NEXT NEG.W Rd R:W NEXT NEG.L ERd R:W NEXT NOP R:W NEXT NOT.B Rd R:W NEXT NOT.W Rd R:W NEXT NOT.L ERd R:W NEXT OR.B #xx:8,Rd R:W NEXT OR.B Rs,Rd R:W NEXT

Table A-6 Instruction Execution Cycles (cont) OR.W #xx:16,Rd R:W 2nd R:W NEXT OR.W Rs,Rd R:W NEXT OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT OR.L ERs,ERd R:W 2nd R:W NEXT ORC #xx:8,CCR R:W NEXT ORC #xx:8,EXR R:W 2nd R:W NEXT POP.W Rn R:W NEXT Internal operation,R:W EA 1 state POP.L ERn R:W 2nd R:W:M NEXT Internal operation,R:W:M EA R:W EA+2 1 state PUSH.W Rn R:W NEXT Internal operation,W:W EA 1 state PUSH.L ERn R:W 2nd R:W:M NEXT Internal operation,W:W:M EA W:W EA+2 1 state ROTL.B Rd R:W NEXT ROTL.B #2,Rd R:W NEXT ROTL.W Rd R:W NEXT ROTL.W #2,Rd R:W NEXT ROTL.L ERd R:W NEXT ROTL.L #2,ERd R:W NEXT ROTR.B Rd R:W NEXT ROTR.B #2,Rd R:W NEXT ROTR.W Rd R:W NEXT ROTR.W #2,Rd R:W NEXT ROTR.L ERd R:W NEXT ROTR.L #2,ERd R:W NEXT ROTXL.B Rd R:W NEXT ROTXL.B #2,Rd R:W NEXT ROTXL.W Rd R:W NEXT ROTXL.W #2,Rd R:W NEXT ROTXL.L ERd R:W NEXT ROTXL.L #2,ERd R:W NEXT ROTXR.B Rd R:W NEXT ROTXR.B #2,Rd R:W NEXT ROTXR.W Rd R:W NEXT ROTXR.W #2,Rd R:W NEXT ROTXR.L ERd R:W NEXT 1 2 3 4 56789

Table A-6 Instruction Execution Cycles (cont) ROTXR.L #2,ERd R:W NEXT RTE R:W NEXT R:W stack (EXR) R:W stack (H) R:W stack (L) Internal operation,R:W *4 1 state RTS R:W NEXT R:W stack Internal operation, R:W*4 1 state R:W NEXT R:W:M stack (H) R:W stack (L) Internal operation,R:W *4 1 state SHAL.B Rd R:W NEXT SHAL.B #2,Rd R:W NEXT SHAL.W Rd R:W NEXT SHAL.W #2,Rd R:W NEXT SHAL.L ERd R:W NEXT SHAL.L #2,ERd R:W NEXT SHAR.B Rd R:W NEXT SHAR.B #2,Rd R:W NEXT SHAR.W Rd R:W NEXT SHAR.W #2,Rd R:W NEXT SHAR.L ERd R:W NEXT SHAR.L #2,ERd R:W NEXT SHLL.B Rd R:W NEXT SHLL.B #2,Rd R:W NEXT SHLL.W Rd R:W NEXT SHLL.W #2,Rd R:W NEXT SHLL.L ERd R:W NEXT SHLL.L #2,ERd R:W NEXT SHLR.B Rd R:W NEXT SHLR.B #2,Rd R:W NEXT SHLR.W Rd R:W NEXT SHLR.W #2,Rd R:W NEXT SHLR.L ERd R:W NEXT SHLR.L #2,ERd R:W NEXT SLEEP R:W NEXT Internal operation:M STC CCR,Rd R:W NEXT STC EXR,Rd R:W NEXT STC CCR,@ERd R:W 2nd R:W NEXT W:W EA STC EXR,@ERd R:W 2nd R:W NEXT W:W EA STC CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA 1 2 3 4 56789 Normal Advanced

Table A-6 Instruction Execution Cycles (cont) STC EXR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC CCR,@–ERd R:W 2nd R:W NEXT Internal operation,W:W EA 1 state STC EXR,@–ERd R:W 2nd R:W NEXT Internal operation,W:W EA 1 state STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA STM.L(ERn–ERn+1),@–SP R:W 2nd R:W:M NEXT Internal operation,W:W:M stack (H)*3 W:W stack (L)*3 1 state STM.L(ERn–ERn+2),@–SP R:W 2nd R:W:M NEXT Internal operation,W:W:M stack (H)*3 W:W stack (L)*3 1 state STM.L(ERn–ERn+3),@–SP R:W 2nd R:W:M NEXT Internal operation,W:W:M stack (H)*3 W:W stack (L)*3 1 state STMAC MACH,ERd Cannot be used in the H8S/2350 Series STMAC MACL,ERd SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd R:W NEXT SUB.W Rs,Rd R:W NEXT SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT SUB.L ERs,ERd R:W NEXT SUBS #1/2/4,ERd R:W NEXT SUBX #xx:8,Rd R:W NEXT SUBX Rs,Rd R:W NEXT TAS @ERd R:W 2nd R:W NEXT R:B:M EA W:B EA TRAPA #x:2 R:W NEXT Internal operation,W:W stack (L) W:W stack (H) W:W stack (EXR) R:W VEC Internal operation,R:W *8 1 state 1 state R:W NEXT Internal operation,W:W stack (L) W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation,R:W *8 1 state 1 state XOR.B #xx8,Rd R:W NEXT XOR.B Rs,Rd R:W NEXT XOR.W #xx:16,Rd R:W 2nd R:W NEXT XOR.W Rs,Rd R:W NEXT XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT 1 2 3 4 56789 Normal Advanced

Table A-6 Instruction Execution Cycles (cont) XOR.L ERs,ERd R:W 2nd R:W NEXT XORC #xx:8,CCR R:W NEXT XORC #xx:8,EXR R:W 2nd R:W NEXT Reset exception R:W VEC Internal operation,R:W *5 handling 1 state R:W VEC R:W VEC+2 Internal operation,R:W *5 1 state Interrupt exception R:W *6 Internal operation,W:W stack (L) W:W stack (H) W:W stack (EXR) R:W VEC Internal operation,R:W *7 handling 1 state 1 state R:W*6 Internal operation,W:W stack (L) W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation,R:W *7 1 state 1 state Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Start address after return. 5. Start address of the program. 6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Start address of the interrupt-handling routine. 1 2 3 4 56789 Normal Advanced Normal Advanced

A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m = 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution

Table A-7 Condition Code Modification Instruction H N Z V C Definition ADD H = Sm–4 · Dm–4 + Dm–4 · Rm—4 + Sm–4 · Rm—4 N = Rm V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDX H = Sm–4 · Dm–4 + Dm–4 · Rm—4 + Sm–4 · Rm—4 N = Rm V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND — 0 — N = Rm ANDC Stores the corresponding bits of the result. No flags change when the operand is EXR. BILD ———— C = Dn BIOR ———— C = C' + Dn BIXOR ———— C = C' · Dn + C’ · Dn B L D ———— C = Dn B O R ———— C = C' + Dn BTST — — — — Z = Dn BXOR ———— C = C' · Dn + C’ · Dn CLRMAC Cannot be used in the H8S/2350 Series

Table A-7 Condition Code Modification (cont) Instruction H N Z V C Definition CMP H = Sm–4 · Dm—4 + Dm—4 · Rm–4 + Sm–4 · Rm–4 N = Rm V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * * N = Rm C: decimal arithmetic carry DAS * * N = Rm C: decimal arithmetic borrow DEC — — N = Rm V = Dm · Rm DIVXS — — — N = Sm · Dm + Sm · Dm DIVXU — — — N = Sm EXTS — 0 — N = Rm INC — — N = Rm V = Dm · Rm LDC Stores the corresponding bits of the result. No flags change when the operand is EXR. LDMAC Cannnot be used in the H8S/2350 Series MAC

Table A-7 Condition Code Modification (cont) Instruction H N Z V C Definition MOV — 0 — N = Rm MOVFPE Can not be used in the H8S/2350 Series MOVTPE MULXS — — — N = R2m NEG H = Dm–4 + Rm–4 N = Rm V = Dm · Rm C = Dm + Rm NOT — 0 — N = Rm OR — 0 — N = Rm ORC Stores the corresponding bits of the result. No flags change when the operand is EXR. POP — 0 — N = Rm PUSH — 0 — N = Rm ROTL — 0 N = Rm C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift)

Table A-7 Condition Code Modification (cont) Instruction H N Z V C Definition ROTXL — 0 N = Rm C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE Stores the corresponding bits of the result. SHAL — N = Rm V = Dm · Dm–1 + Dm · Dm—1 (1-bit shift) V = Dm · Dm–1 · Dm–2 · Dm · Dm—1 · Dm—2 (2-bit shift) C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHAR — 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL — 0 N = Rm C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHLR — 0 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) STMAC Cannot be used in the H8S/2350 Series

Table A-7 Condition Code Modification (cont) Instruction H N Z V C Definition SUB H = Sm–4 · Dm—4 + Dm—4 · Rm–4 + Sm–4 · Rm–4 N = Rm V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBX H = Sm–4 · Dm—4 + Dm—4 · Rm–4 + Sm–4 · Rm–4 N = Rm V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS — 0 — N = Dm XOR — 0 — N = Rm XORC Stores the corresponding bits of the result. No flags change when the operand is EXR.

Appendix B Internal I/O Register B.1 Addresses Address (low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’F800 to H’FBFF MRA SAR SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz DTC 16/32 * bit DAR CRA CRB H’FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3 16 bit H’FE81 TMDR3 — — BFB BFA MD3 MD2 MD1 MD0 H’FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H’FE84 TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA H’FE85 TSR3 — — — TCFV TGFD TGFC TGFB TGFA H’FE86 TCNT3 H’FE87 H’FE88 TGR3A H’FE89 H’FE8A TGR3B H’FE8B H’FE8C TGR3C H’FE8D H’FE8E TGR3D H’FE8F Note: * Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise.

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU4 16 bit H’FE91 TMDR4 ————M D 3 M D 2 M D 1 M D 0 H’FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FE94 TIER4 TTGE — TCIEU TCIEV — — TGIEB TGIEA H’FE95 TSR4 TCFD — TCFU TCFV — — TGFB TGFA H’FE96 TCNT4 H’FE97 H’FE98 TGR4A H’FE99 H’FE9A TGR4B H’FE9B H’FEA0 TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU5 16 bit H’FEA1 TMDR5 ————M D 3 M D 2 M D 1 M D 0 H’FEA2 TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FEA4 TIER5 TTGE — TCIEU TCIEV — — TGIEB TGIEA H’FEA5 TSR5 TCFD — TCFU TCFV — — TGFB TGFA H’FEA6 TCNT5 H’FEA7 H’FEA8 TGR5A H’FEA9 H’FEAA TGR5B H’FEAB H’FEB0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 8 bit H’FEB1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR H’FEB2 P3DDR — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR H’FEB4 P5DDR ———— P53DDR P52DDR P51DDR P50DDR H’FEB5 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR H’FEB9 PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR H’FEBA PBDDR * PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR H’FEBB PCDDR * PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR H’FEBC PDDDR * PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR H’FEBD PEDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR H’FEBE PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR H’FEBF PGDDR — — — PG4DDRPG3DDRPG2DDRPG1DDRPG0DDR Note: * Only applies to the H8S/2351.

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FEC4 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Interrupt 8 bit H’FEC5 IPRB — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 controller H’FEC6 IPRC — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FEC7 IPRD — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FEC8 IPRE — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FEC9 IPRF — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FECA IPRG — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FECB IPRH — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FECC IPRI — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FECD IPRJ — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FECE IPRK — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H’FED0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller 8 bit H’FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 H’FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40 H’FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00 H’FED4 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMST0 H’FED5 BCRL BRLE BREQOE EAE — LCASS — WDBE WAITE H’FED6 MCR TPC BE RCDM CW2 MXC1 MXC0 RLW1 RLW0 H’FED7 DRAMCR RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0 H’FED8 RTCNT H’FED9 RTCOR H’FEE1 H’FEE2 MAR0AL H’FEE3 H’FEE4 IOAR0A H’FEE5 H’FEE6 ETCR0A H’FEE7 H’FEE9 H’FEEA MAR0BL H’FEEB H’FEEC IOAR0B H’FEED H’FEEE ETCR0B H’FEEF

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FEF1 H’FEF2 MAR1AL H’FEF3 H’FEF4 IOAR1A H’FEF5 H’FEF6 ETCR1A H’FEF7 H’FEF9 H’FEFA MAR1BL H’FEFB H’FEFC IOAR1B H’FEFD H’FEFE ETCR1B H’FEFF H’FF00 DMAWER ———— WE1B WE1A WE0B WE0A 8 bit H’FF01 DMATCR — — TEE1 TEE0 ———— H’FF02 DMACR0A DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Short address mode 16 bit DTSZ SAID SAIDE BLKDIR BLKE — — — Full address mode H’FF03 DMACR0B DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Short address mode — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Full address mode H’FF04 DMACR1A DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Short address mode DTSZ SAID SAIDE BLKDIR BLKE — — — Full address mode H’FF05 DMACR1B DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Short address mode — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Full address mode H’FF06 DMABCRH FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Short address mode FAE1 FAE0 — — DTA1 — DTA0 — Full address mode H’FF07 DMABCRL DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Short address mode DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Full address mode

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FF2C ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt 8 bit H’FF2D ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA controller H’FF2E IER IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E H’FF2F ISR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F H’FF30 to H’FF35 DTCER DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 DTC 8 bit H’FF37 DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 H’FF38 SBYCR SSBY STS2 STS1 STS0 OPE — — — Power-down mode 8 bit H’FF39 SYSCR — — INTM1 INTM0 NMIEG — — RAME MCU 8 bit H’FF3A SCKCR PSTOP ———— SCK2 SCK1 SCK0 Clock pulse generator 8 bit H’FF3B MDCR ————— MDS2 MDS1 MDS0 MCU 8 bit H’FF3C MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Power-down 8 bit H’FF3D MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 mode H’FF46 PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG 8 bit H’FF47 PMR G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV H’FF48 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 H’FF49 NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 H’FF4A PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 H’FF4B PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 H’FF4C* NDRH NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 H’FF4D* NDRL NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 H’FF4E* NDRH ———— NDR11 NDR10 NDR9 NDR8 H’FF4F* NDRL ———— NDR3 NDR2 NDR1 NDR0 Note: * If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FF50 PORT1 P17 P16 P15 P14 P13 P12 P11 P10 Port 8 bit H’FF51 PORT2 P27 P26 P25 P24 P23 P22 P21 P20 H’FF52 PORT3 — — P35 P34 P33 P32 P31 P30 H’FF53 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 H’FF54 PORT5 ————P 5 3 P 5 2 P 5 1 P 5 0 H’FF55 PORT6 P67 P66 P65 P64 P63 P62 P61 P60 H’FF59 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 H’FF5A PORTB * PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 H’FF5B PORTC * PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 H’FF5C PORTD * PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 H’FF5D PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 H’FF5E PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 H’FF5F PORTG — — — PG4 PG3 PG2 PG1 PG0 H’FF60 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR H’FF61 P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR H’FF62 P3DR — — P35DR P34DR P33DR P32DR P31DR P30DR H’FF64 P5DR ———— P53DR P52DR P51DR P50DR H’FF65 P6DR P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR H’FF69 PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR H’FF6A PBDR * PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR H’FF6B PCDR * PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR H’FF6C PDDR * PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR H’FF6D PEDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR H’FF6E PFDR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR H’FF6F PGDR — — — PG4DR PG3DR PG2DR PG1DR PG0DR H’FF70 PAPCR PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR H’FF71 PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR H’FF72 PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR H’FF73 PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR H’FF74 PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR H’FF76 P3ODR — — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR H’FF77 PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Note: * Only applies to the H8S/2351.

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FF78 H’FF79 H’FF7A SMR0 BRR0 SCR0 C/A/ GM *1 TIE CHR RIE PE TE O/E RE STOP MPIE MP TEIE CKS1 CKE1 CKS0 CKE0 SCI0, Smart card interface 0 8 bit H’FF7B TDR0 H’FF7C SSR0 TDRE RDRF ORER FER/ ERS *2 PER TEND MPB MPBT H’FF7D RDR0 H’FF7E SCMR0 ———— SDIR SINV — SMIF H’FF80 H’FF81 H’FF82 SMR1 BRR1 SCR1 C/A/ GM *1 TIE CHR RIE PE TE O/E RE STOP MPIE MP TEIE CKS1 CKE1 CKS0 CKE0 SCI1, Smart card interface 1 8 bit H’FF83 TDR1 H’FF84 SSR1 TDRE RDRF ORER FER/ ERS *2 PER TEND MPB MPBT H’FF85 RDR1 H’FF86 SCMR1 ———— SDIR SINV — SMIF H'FF90 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D converter 8 bit H'FF92 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FF94 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FF96 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FF98 ADCSR ADF ADIE ADST SCAN CKS — CH1 CH0 H'FF99 ADCR TRGS1 TRGS0 —————— H’FFA4 DADR0 D/A converter 8 bit H’FFA5 DADR1 H’FFA6 DACR DAOE1 DAOE0 DAE ————— Notes: 1. Functions as C/A for SCI use, and as GM for smart card interface use. 2. Functions as FER for SCI use, and as ERS for smart card interface use.

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FFBC (read) TCSR OVF WT/ IT TME — — CKS2 CKS1 CKS0 WDT 16 bit H’FFBD (read) TCNT H’FFBF (read) RSTCSR WOVF RSTE RSTS ————— H’FFC0 TSTR — — CST5 CST4 CST3 CST2 CST1 CST0 TPU 16 bit H’FFC1 TSYR — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 H’FFD0 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU0 16 bit H’FFD1 TMDR0 — — BFB BFA MD3 MD2 MD1 MD0 H’FFD2 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FFD3 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H’FFD4 TIER0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA H’FFD5 TSR0 — — — TCFV TGFD TGFC TGFB TGFA H’FFD6 TCNT0 H’FFD7 H’FFD8 TGR0A H’FFD9 H’FFDA TGR0B H’FFDB H’FFDC TGR0C H’FFDD H’FFDE TGR0D H’FFDF H’FFE0 TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU1 16 bit H’FFE1 TMDR1 ————M D 3 M D 2 M D 1 M D 0 H’FFE2 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FFE4 TIER1 TTGE — TCIEU TCIEV — — TGIEB TGIEA H’FFE5 TSR1 TCFD — TCFU TCFV — — TGFB TGFA H’FFE6 TCNT1 H’FFE7 H’FFE8 TGR1A H’FFE9 H’FFEA TGR1B H’FFEB

(low) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FFF0 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16 bit H’FFF1 TMDR2 ————M D 3 M D 2 M D 1 M D 0 H’FFF2 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FFF4 TIER2 TTGE — TCIEU TCIEV — — TGIEB TGIEA H’FFF5 TSR2 TCFD — TCFU TCFV — — TGFB TGFA H’FFF6 TCNT2 H’FFF7 H’FFF8 TGR2A H’FFF9 H’FFFA TGR2B H’FFFB

B.2 Functions MRA—DTC Mode Register A H'F800—H'FBFF DTC SM1 Undefined SM0 Undefined DM1 Undefined DM0 Undefined MD1 Undefined Sz Undefined MD0 Undefined DTS Undefined Bit Initial value Read/Write Source Address Mode Destination Address Mode DTC Mode Normal mode Repeat mode Block transfer mode DTC Data Transfer Size Byte-size transfer DTC Transfer Mode Select Word-size transfer Destination side is repeat area or block area Source side is repeat area or block area DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) SAR is fixed

MRB—DTC Mode Register B H'F800—H'FBFF DTC CHNE Undefined DISEL Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Initial value Read/Write DTC Chain Transfer Enable End of DTC data transfer DTC chain transfer DTC Interrupt Select Reserved Only 0 should be written to these bits After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After a data transfer ends, the CPU interrupt is enabled SAR—DTC Source Address Register H'F800—H'FBFF DTC 23Bit Initial value Read/Write 22 21 20 1 9 43210 - - - - - - - - - - - - Specifies transfer data source address Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined DAR—DTC Destination Address Register H'F800—H'FBFF DTC 23Bit Initial value Read/Write 22 21 20 1 9 43210 - - - - - - - - - - - - Specifies transfer data destination address Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined

CRA—DTC Transfer Count Register A H'F800—H'FBFF DTC 15Bit Initial value Read/Write 14 13 12 1 1 1 0 9876543210 CRAH CRAL Specifies the number of DTC data transfers Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined CRB—DTC Transfer Count Register B H'F800—H'FBFF DTC 15 14 13 12 1 1 1 0 9876543210 Specifies the number of DTC block data transfers Bit Initial value Read/Write Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined

TCR3—Timer Control Register 3 H'FE80 TPU3 CCLR2 R/W CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC0 R/W TPSC2 R/W TPSC1 R/W Bit Initial value Read/Write TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 Counter Clear Clock Edge Count at rising edge Count at falling edge Count at both edges Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input Internal clock: counts on ø/1024 Internal clock: counts on ø/256 Internal clock: counts on ø/4096 Timer Prescaler TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.

TMDR3—Timer Mode Register 3 H'FE81 TPU3 BFB R/W BFA R/W MD3 R/W MD0 R/W MD2 R/W MD1 R/W Bit Initial value Read/Write Buffer Operation B TGRB operates normally Buffer Operation A TGRA operates normally Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode Notes: 1. * : Don’t care MD3 is a reserved bit. In a write, it should always be written with 0. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. TGRA and TGRC used together for buffer operation1 TGRB and TGRD used together for buffer operation

TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 TGR3B I/O Control TGR3A is output compare register TGR3A I/O Control Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges * : Don’t care * : Don’t care IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA0 R/W IOA2 R/W IOA1 R/W Bit Initial value Read/Write TGR3A is input capture register Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA3 pin Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down TGR3B is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3B is input capture register Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCB3 pin Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down Note: 1. If bits TPSC2 to TPSC0 in TCR4 are set to B'000, and ø/1 is used as the TCNT4 count clock, this setting will be invalid and input capture will not occur.

TIOR3L—Timer I/O Control Register 3L H'FE83 TPU3 TGR3D I/O Control TGR3C is output compare register TRG3C I/O Control Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match * : Don’t care * : Don’t care Notes: Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When GRC or GRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. IOD3 R/W IOD2 R/W IOD1 R/W IOD0 R/W IOC3 R/W IOC0 R/W IOC2 R/W IOC1 R/W Bit Initial value Read/Write Initial output is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is TIOCC3 pin TGR3C is input capture register Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down TGR3D is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is TIOCD3 pin TGR3D is input capture register Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down* When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as

the TCNT4 count clock, this setting is invalid and input capture is not generated.

TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3 TTGE R/W TCIEV R/W TGIED R/W TGIEA R/W TGIEC R/W TGIEB R/W Bit Initial value Read/Write A/D conversion start request generation disabled A/D conversion start request generation enabled A/D Conversion Start Request Enable Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Overflow Interrupt Enable TGR Interrupt Enable D TGR Interrupt Enable C TGR Interrupt Enable B Interrupt requests (TGIA) by TGFA bit disabled TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit enabled Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled

TSR3—Timer Status Register 3 H'FE85 TPU3 TCFV R/(W)* TGFD R/(W)* TGFA R/(W)* TGFC R/(W)* TGFB R/(W)* Bit Initial value Read/Write Note: * Can only be written with 0 for flag clearing. 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Overflow Flag 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) 0 [Clearing condition]

When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFD after reading TGFD = 1 Input Capture/Output Compare Flag D 1 [Setting condition] 0 [Clearing condition]
When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFC after reading TGFC = 1 Input Capture/Output Compare Flag C 1 [Setting condition] 0 [Clearing condition]
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1 Input Capture/Output Compare Flag B 1 [Setting condition] 0 [Clearing condition]
When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
When 0 is written to TGFA after reading TGFA = 1 Input Capture/Output Compare Flag A 1 [Setting condition]
When TCNT=TGRA while TGRA is function- ing as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
When TCNT = TGRC while TGRC is functioning as output compare register
When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
When TCNT = TGRD while TGRD is functioning as output compare register
When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register

TCNT3—Timer Counter 3 H'FE86 TPU3 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A—Timer General Register 3A H'FE88 TPU3 TGR3B—Timer General Register 3B H'FE8A TPU3 TGR3C—Timer General Register 3C H'FE8C TPU3 TGR3D—Timer General Register 3D H'FE8E TPU3 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TCR4—Timer Control Register 4 H'FE90 TPU4 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture Counter Clear Clock Edge Count at rising edge Count at falling edge Count at both edges Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024 Counts on TCNT5 overflow/underflow Timer Prescaler CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC0 R/W TPSC2 R/W TPSC1 R/W Bit Initial value Read/Write Note: This setting is ignored when channel 4 is in phase counting mode. Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Note: This setting is ignored when channel 4 is in phase counting mode. TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*

TMDR4—Timer Mode Register 4 H'FE91 TPU4 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode Notes: * : Don’t care MD3 R/W MD0 R/W MD2 R/W MD1 R/W Bit Initial value Read/Write MD3 is a reserved bit. In a write, it should always be written with 0.

TIOR4—Timer I/O Control Register 4 H'FE92 TPU4 IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA0 R/W IOA2 R/W IOA1 R/W Bit Initial value Read/Write TGR4B is output compare register TGR4B I/O Control TGR4A I/O Control * : Don’t care TGR4A is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match * : Don’t care Initial output is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges TGR4A is input capture register Capture input source is TIOCA4 pin Input capture at generation of TGR3A compare match/input capture Capture input source is TGR3A compare match/ input capture Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges TGR4B is input capture register Capture input source is TIOCB4 pin Input capture at generation of TGR3C compare match/input capture Capture input source is TGR3C compare match/ input capture

TIER4—Timer Interrupt Enable Register 4 H'FE94 TPU4 TTGE R/W TCIEU R/W TCIEV R/W TGIEA R/W TGIEB R/W Bit Initial value Read/Write Interrupt requests (TGIA) by TGFA bit disabled TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit enabled Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable B Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Overflow Interrupt Enable Underflow Interrupt Enable Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable A/D conversion start request generation disabled A/D conversion start request generation enabled

TSR4—Timer Status Register 4 H'FE95 TPU4 TCFD R TCFU R/(W)* TCFV R/(W)* TGFA R/(W)* TGFB R/(W)* Bit Initial value Read/Write TCNT counts down TCNT counts up Count Direction Flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 Underflow Flag 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF) 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Overflow Flag 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Input Capture/Output Compare Flag B 0 [Clearing condition]

When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
When 0 is written to TGFA after reading TGFA = 1 Input Capture/Output Compare Flag A 1 [Setting conditions] Note: * Can only be written with 0 for flag clearing.
When TCNT = TGRA while TGRA is functioning as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing condition]
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1 [Setting conditions]
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register

TCNT4—Timer Counter 4 H'FE96 TPU4 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. Up/down-counter* TGR4A—Timer General Register 4A H'FE98 TPU4 TGR4B—Timer General Register 4B H'FE9A TPU4 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TCR5—Timer Control Register 5 H'FEA0 TPU5 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture Counter Clear Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/256 External clock: counts on TCLKD pin input Time Prescaler CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC0 R/W TPSC2 R/W TPSC1 R/W Bit Initial value Read/Write Note: Clock Edge Count at rising edge Count at falling edge Count at both edges This setting is ignored when channel 5 is in phase counting mode. Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Note: This setting is ignored when channel 5 is in phase counting mode. TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*

TMDR5—Timer Mode Register 5 H'FEA1 TPU5 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode Notes: MD3 is a reserved bit. In a write, it should always be written with 0. * : Don’t care MD3 R/W MD0 R/W MD2 R/W MD1 R/W Bit Initial value Read/Write

TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5 IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA0 R/W IOA2 R/W IOA1 R/W Bit Initial value Read/Write TGR5B I/O Control TGR5A is output compare register TGR5A I/O Control Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match * : Don’t care TGR5A is input capture register Initial output is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is TIOCA5 pin TGR5B is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match * : Don’t care TGR5B is input capture register Initial output is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is TIOCB5 pin

TIER5—Timer Interrupt Enable Register 5 H'FEA4 TPU5 TTGE R/W TCIEU R/W TCIEV R/W TGIEA R/W TGIEB R/W Bit Initial value Read/Write A/D conversion start request generation disabled A/D conversion start request generation enabled A/D Conversion Start Request Enable Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B Interrupt requests (TGIA) by TGFA bit disabled TGR Interrupt Enable A Overflow Interrupt Enable Interrupt requests (TGIA) by TGFA bit enabled Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled

TSR5—Timer Status Register 5 H'FEA5 TPU5 TCFD R TCFU R/(W)* TCFV R/(W)* TGFA R/(W)* TGFB R/(W)* Bit Initial value Read/Write TCNT counts down TCNT counts up Count Direction Flag Underflow Flag Overflow Flag Input Capture/Output Compare Flag B 0 [Clearing condition]

When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
When 0 is written to TGFA after reading TGFA = 1 Input Capture/Output Compare Flag A 1 [Setting conditions]
When TCNT = TGRA while TGRA is functioning as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Note: * Can only be written with 0 for flag clearing. [Clearing condition]
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1 [Setting conditions]
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF)

TCNT5—Timer Counter 5 H'FEA6 TPU5 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. Up/down-counter* TGR5A—Timer General Register 5A H'FEA8 TPU5 TGR5B—Timer General Register 5B H'FEAA TPU5 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P1DDR—Port 1 Data Direction Register H'FEB0 Port 1 P17DDR W P16DDR W P15DDR W P14DDR W P13DDR W P10DDR W P12DDR W P11DDR W Bit Initial value Read/Write Specify input or output for individual port 1 pins

P2DDR—Port 2 Data Direction Register H'FEB1 Port 2 P27DDR W P26DDR W P25DDR W P24DDR W P23DDR W P20DDR W P22DDR W P21DDR W Specify input or output for individual port 2 pins Bit Initial value Read/Write P3DDR—Port 3 Data Direction Register H'FEB2 Port 3 Undefined Undefined P35DDR W P34DDR W P33DDR W P30DDR W P32DDR W P31DDR W Specify input or output for individual port 3 pins Bit Initial value Read/Write P5DDR—Port 5 Data Direction Register H'FEB4 Port 5 Undefined Undefined Undefined Undefined P53DDR W P50DDR W P52DDR W P51DDR W Specify input or output for individual port 5 pins Bit Initial value Read/Write

P6DDR—Port 6 Data Direction Register H'FEB5 Port 6 P67DDR W P66DDR W P65DDR W P64DDR W P63DDR W P60DDR W P62DDR W P61DDR W Specify input or output for individual port 6 pins Bit Initial value Read/Write PADDR—Port A Data Direction Register H'FEB9 Port A PA7DDR W PA6DDR W PA5DDR W PA4DDR W PA3DDR W PA0DDR W PA2DDR W PA1DDR W Bit Initial value Read/Write Specify input or output for individual port A pins PBDDR—Port B Data Direction Register H'FEBA Port B [H8S/2351 Only] PB7DDR W PB6DDR W PB5DDR W PB4DDR W PB3DDR W PB0DDR W PB2DDR W PB1DDR W Specify input or output for individual port B pins Bit Initial value Read/Write

PCDDR—Port C Data Direction Register H'FEBB Port C [H8S/2351 Only] PC7DDR W PC6DDR W PC5DDR W PC4DDR W PC3DDR W PC0DDR W PC2DDR W PC1DDR W Specify input or output for individual port C pins Bit Initial value Read/Write PDDDR—Port D Data Direction Register H'FEBC Port D [H8S/2351 Only] PD7DDR W PD6DDR W PD5DDR W PD4DDR W PD3DDR W PD0DDR W PD2DDR W PD1DDR W Bit Initial value Read/Write Specify input or output for individual port D pins PEDDR—Port E Data Direction Register H'FEBD Port E PE7DDR W PE6DDR W PE5DDR W PE4DDR W PE3DDR W PE0DDR W PE2DDR W PE1DDR W Specify input or output for individual port E pins Bit Initial value Read/Write

PFDDR—Port F Data Direction Register H'FEBE Port F PF7DDR W W PF6DDR W W PF5DDR W W PF4DDR W W PF3DDR W W PF0DDR W W PF2DDR W W PF1DDR W W Specify input or output for individual port F pins Bit Modes 1, 2, 4 to 6 Initial value Read/Write Modes 3, 7 Initial value Read/Write PGDDR—Port G Data Direction Register H'FEBF Port G Undefined Undefined Undefined Undefined Undefined Undefined PG4DDR W W PG3DDR W W PG0DDR W W PG2DDR W W PG1DDR W W Specify input or output for individual port G pins Bit Modes 1, 4, 5 Initial value Read/Write Modes 2, 3, 6, 7 Initial value Read/Write

IPRA — Interrupt Priority Register A H'FEC4 Interrupt Controller IPRB — Interrupt Priority Register B H'FEC5 Interrupt Controller IPRC — Interrupt Priority Register C H'FEC6 Interrupt Controller IPRD — Interrupt Priority Register D H'FEC7 Interrupt Controller IPRE — Interrupt Priority Register E H'FEC8 Interrupt Controller IPRF — Interrupt Priority Register F H'FEC9 Interrupt Controller IPRG — Interrupt Priority Register G H'FECA Interrupt Controller IPRH — Interrupt Priority Register H H'FECB Interrupt Controller IPRI — Interrupt Priority Register I H'FECC Interrupt Controller IPRJ — Interrupt Priority Register J H'FECD Interrupt Controller IPRK — Interrupt Priority Register K H'FECE Interrupt Controller IPR6 R/W IPR5 R/W IPR4 R/W IPR0 R/W IPR2 R/W IPR1 R/W Set priority (levels 7 to 0) for interrupt sources IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Register Bits IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 WDT — * TPU channel 0 TPU channel 2 TPU channel 4 — * DMAC SCI channel 1 IRQ1 IRQ4 IRQ5 DTC Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 — * SCI channel 0 — * 6 to 4 2 to 0 Correspondence between Interrupt Sources and IPR Settings Note: * Reserved bits. These bits cannot be modified and are always read as 1. Bit Initial value Read/Write

ABWCR—Bus Width Control Register H'FED0 Bus Controller ABW7 R/W R/W ABW6 R/W R/W ABW5 R/W R/W ABW4 R/W R/W ABW3 R/W R/W ABW0 R/W R/W ABW2 R/W R/W ABW1 R/W R/W Bit Modes 1, 2, 3, 5, 7 Initial value R/W Mode 4 Initial value Read/Write Area 7 to 0 Bus Width Control Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) ASTCR—Access State Control Register H'FED1 Bus Controller AST7 R/W AST6 R/W AST5 R/W AST4 R/W AST3 R/W AST0 R/W AST2 R/W AST1 R/W Bit Initial value Read/Write Area 7 to 0 Access State Control Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n = 7 to 0)

WCRH—Wait Control Register H H'FED2 Bus Controller W71 R/W W70 R/W W61 R/W W60 R/W W51 R/W W40 R/W W50 R/W W41 R/W Bit Initial value Read/Write Area 7 Wait Control Area 6 Wait Control Area 5 Wait Control Area 4 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted

WCRL—Wait Control Register L H'FED3 Bus Controller W31 R/W W30 R/W W21 R/W W20 R/W W11 R/W W00 R/W W10 R/W W01 R/W Bit Initial value Read/Write Area 3 Wait Control Area 2 Wait Control Area 1 Wait Control Area 0 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted

BCRH—Bus Control Register H H'FED4 Bus Controller ICIS1 R/W ICIS0 R/W BRSTRM R/W BRSTS1 R/W BRSTS0 R/W RMTS0 R/W RMTS2 R/W RMTS1 R/W Bit Initial value Read/Write Idle Cycle Insert 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas Idle Cycle Insert 0 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Area 0 Burst ROM Enable Area 0 is basic bus interface Area 0 is burst ROM interface Burst Cycle Select 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Burst Cycle Select 0 Max. 4 words in burst access Max. 8 words in burst access RAM Type Select RMTS2 RMTS1 RMTS0 Area 5Area 4Area 3 Area 2 Normal space DRAM spaceNormal space DRAM spaceNormal space DRAM space Note: When areas selected in DRAM space are all 8-bit space, the PF2 pin can be used as an I/O port, BREQO, or WAIT.

BCRL—Bus Control Register L H'FED5 Bus Controller BRLE R/W BREQOE R/W R/W LCASS R/W DDS R/W WAITE R/W R/W WDBE R/W Bit Initial value Read/Write Bus Release Enable External bus release is disabled External bus release is enabled BREQO Pin Enable BREQO output disabled BREQO output enabled Reserved Only 1 should be written to this bit Reserved Only 0 should be written to this bit Write Data Buffer Enable WAIT Pin Enable Wait input by WAIT pin disabled Wait input by WAIT pin enabled Write data buffer function not used Write data buffer function used LCAS Select Write 0 to this bit when using the DRAM interface DACK Timing Select When DMAC single address transfer is performed in DRAM/PSRAM space, full access is always executed DACK signal goes low from Tr or T1 cycle Burst access is possible when DMAC single address transfer is performed in DRAM/PSRAM space DACK signal goes low from Tc1 or T2 cycle

MCR—Memory Control Register H'FED6 Bus Controller TPC R/W BE R/W RCDM R/W CW2 R/W MXC1 R/W RLW0 R/W MXC0 R/W RLW1 R/W Bit Initial value Read/Write TP Cycle Control 1-state precharge cycle is inserted 2-state precharge cycle is inserted Burst Access Enable Burst disabled (always full access) RAS/CS Down Mode DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected 2-CAS Method Select 16-bit DRAM space selected 8-bit DRAM space selected Multiplex Shift Count 8-bit shift 9-bit shift 10-bit shift Refresh Cycle Wait Control No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted For DRAM space access, access in fast page mode

DRAMCR—DRAM Control Register H'FED7 Bus Controller RFSHE R/W RCW R/W RMODE R/W CMF R/W CMIE R/W CKS0 R/W CKS2 R/W CKS1 R/W Bit Initial value Read/Write Refresh Control Refresh control is not performed Refresh control is performed RAS-CAS Wait

0 Wait state insertion in CAS-before-RAS refreshing disabled

DRAM interface: CAS-before-RAS refreshing used Self-refreshing used Compare Match Flag Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag [Clearing condition] [Setting condition] Set when RTCNT = RTCOR Compare Match Interrupt Enable Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled Refresh Counter Clock Select Count operation disabled Count uses ø/2 Count uses ø/8 Count uses ø/32 Count uses ø/128 Count uses ø/512 Count uses ø/2048 Count uses ø/4096 One wait state inserted in CAS-before-RAS refreshing RAS falls in T Rc1 cycle

RTCNT—Refresh Timer Counter H'FED8 Bus Controller R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write Internal clock count value RTCOR—Refresh Time Constant Register H'FED9 Bus Controller R/W R/W R/W R/W R/W R/W R/W R/W Sets the period for compare match operations with RTCNT Bit Initial value Read/Write MAR0AH—Memory Address Register 0AH H'FEE0 DMAC MAR0AL—Memory Address Register 0AL H'FEE2 DMAC R/W R/W R/W Bit MAR0AH Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined Bit MAR0AL Initial value Read/Write In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address

IOAR0A—I/O Address Register 0A H'FEE4 DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Bit IOAR0A Initial value Read/Write ETCR0A—Transfer Count Register 0A H'FEE6 DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined Transfer counter Sequential mode Idle mode Normal mode Transfer number storage register Transfer counter Block size storage register Block size counter Bit ETCR0A Initial value Read/Write Block transfer mode Repeat mode

MAR0BH—Memory Address Register 0BH H'FEE8 DMAC MAR0BL—Memory Address Register 0BL H'FEEA DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address Bit MAR0BH Initial value Read/Write Bit MAR0BL Initial value Read/Write IOAR0B—I/O Address Register 0B H'FEEC DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Bit IOAR0B Initial value Read/Write

ETCR0B—Transfer Count Register 0B H'FEEE DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined Transfer counter Sequential mode and idle mode Repeat mode Block transfer mode Transfer number storage register Transfer counter Block transfer counter Note: Not used in normal mode. Bit ETCR0B Initial value Read/Write MAR1AH—Memory Address Register 1AH H'FEF0 DMAC MAR1AL—Memory Address Register 1AL H'FEF2 DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address Bit MAR1AH Initial value Read/Write Bit MAR1AL Initial value Read/Write

IOAR1A—I/O Address Register 1A H'FEF4 DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Bit IOAR1A Initial value Read/Write ETCR1A—Transfer Count Register 1A H'FEF6 DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined Transfer counter Sequential mode Idle mode Normal mode Repeat mode Block transfer mode Transfer number storage register Transfer counter Block size storage register Block size counter Bit ETCR1A Initial value Read/Write

MAR1BH — Memory Address Register 1BH H'FEF8 DMAC MAR1BL — Memory Address Register 1BL H'FEFA DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address Bit MAR1BH Initial value Read/Write Bit MAR1BL Initial value Read/Write IOAR1B—I/O Address Register 1B H'FEFC DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Bit IOAR1B Initial value Read/Write ETCR1B—Transfer Count Register 1B H'FEFE DMAC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit ETCR1B Initial value Read/Write * : Undefined Transfer counter Sequential mode and idle mode Repeat mode Block transfer mode Transfer number storage register Transfer counter Block transfer counter Note: Not used in normal mode.

DMAWER—DMA Write Enable Register H'FF00 DMAC WE1B R/W WE0A R/W WE1A R/W WE0B R/W Bit DMAWER Initial value Read/Write Write Enable 1B Write Enable 1A Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled Write Enable 0A Write Enable 0B Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled

DMATCR—DMA Terminal Control Register H'FF01 DMAC TEE1 R/W TEE0 R/W Bit DMATCR Initial value Read/Write Transfer End Enable 1 Transfer End Enable 0 TEND0 pin output disabled TEND0 pin output enabled TEND1 pin output disabled TEND1 pin output enabled

DMACR0A—DMA Control Register 0A H'FF02 DMAC DMACR0B—DMA Control Register 0B H'FF03 DMAC DMACR1A—DMA Control Register 1A H'FF04 DMAC DMACR1B—DMA Control Register 1B H'FF05 DMAC DTSZ R/W SAID R/W SAIDE R/W BLKDIR R/W BLKE R/W R/W R/W R/W Byte-size transfer Word-size transfer Data Transfer Size Source Address Increment/Decrement MARA is fixed MARA is incremented after a data transfer MARA is fixed MARA is decremented after a data transfer Block Direction/Block Enable Transfer in normal mode Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area Full address mode Bit DMACRA Initial value Read/Write

Destination Address Increment/Decrement MARB is fixed MARB is incremented after a data transfer MARB is fixed MARB is decremented after a data transfer Auto-request (burst) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt Data Transfer Factor Block Transfer ModeDTF DTF DTF DTF

0 Normal Mode

Full address mode (cont) Bit DMACRB Initial value Read/Write Auto-request (cycle steal)

Activated by TPU channel 5 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by SCI channel 1 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 0 transmission complete interrupt Activated by A/D converter conversion end interrupt 1 — Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe Byte-size transfer Word-size transfer Data Transfer Size MAR is incremented after a data transfer MAR is decremented after a data transfer Data Transfer Increment/Decrement Transfer in sequential mode Transfer in repeat mode or idle mode Repeat Enable Data Transfer Direction Dual address mode: Transfer with IOAR as source address and MAR as destination address Single address mode: Transfer with DACK pin as read strobe and MAR as destination address Activated by DREQ pin falling edge input Activated by DREQ pin low-level input

DMABCRH — DMA Band Control Register H'FF06 DMAC DMABCRL — DMA Band Control Register H'FF07 DMAC FAE1 R/W FAE0 R/W R/W R/W DTA1 R/W R/W R/W DTA0 R/W Full address mode Bit DMABCRH Initial value Read/Write Short address mode Full address mode Channel 1 Full Address Enable Short address mode Full address mode Channel 0 Full Address Enable

0 Clearing of selected internal interrupt source at time of

Channel 1 Data Transfer Acknowledge

1 Clearing of selected internal interrupt source at time of

Channel 0 Data Transfer Acknowledge (Continued on next page)

0 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Channel 0 Data Transfer Master Enable Channel 1 Data Transfer Enable Data transfer disabled Data transfer enabled Channel 0 Data Transfer Master Enable Data transfer disabled Data transfer enabled Channel 0 Data Transfer Enable Channel 1 Data Transfer Interrupt Enable B Channel 0 Data Transfer Interrupt Enable A Channel 0 Data Transfer Interrupt Enable A DTME1 R/W DTE1 R/W DTME0 R/W DTE0 R/W DTIE1B R/W DTIE0A R/W DTIE1A R/W DTIE0B R/W Transfer suspended interrupt disabled Transfer suspended interrupt enabled Transfer end interrupt disabled Transfer end interrupt enabled Channel 0 Data Transfer Interrupt Enable B Transfer suspended interrupt disabled Transfer suspended interrupt enabled Transfer end interrupt disabled Transfer end interrupt enabled Data transfer enabled 0 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Full address mode (cont) (Continued on next page)

Channel 1 Full Address Enable Short address mode Full address mode Channel 0 Full Address Enable Transfer in dual address mode Transfer in single address mode Channel 1B Single Address Enable Transfer in dual address mode Transfer in single address mode Channel 0B Single Address Enable

0 Clearing of selected internal interrupt

source at time of DMA transfer is disabled Channel 1B Data Transfer Acknowledge

1 Clearing of selected internal interrupt

source at time of DMA transfer is enabled

0 Clearing of selected internal interrupt source

at time of DMA transfer is disabled Channel 1A Data Transfer Acknowledge source at time of DMA transfer is enabled at time of DMA transfer is disabled Channel 0B Data Transfer Acknowledge source at time of DMA transfer is enabled source at time of DMA transfer is disabled Channel 0A Data Transfer Acknowledge

1 Clearing of selected internal

interrupt source at time of DMA transfer is enabled (Continued on next page)

Channel 1B Data Transfer Enable Channel 1A Data Transfer Enable Channel 0B Data Transfer Enable Data transfer disabled Data transfer enabled Channel 0A Data Transfer Enable Channel 1B Data Transfer Interrupt Enable Channel 1A Data Transfer Interrupt Enable Channel 0A Data Transfer Interrupt Enable DTE1B R/W DTE1A R/W DTE0B R/W DTE0A R/W DTIE1B R/W DTIE0A R/W DTIE1A R/W DTIE0B R/W Short address mode (cont) Bit DMABCRL Initial value Read/Write Channel 0B Data Transfer Interrupt Enable Transfer end interrupt disabled Transfer end interrupt enabled Transfer end interrupt disabled Transfer end interrupt enabled Transfer end interrupt disabled Transfer end interrupt enabled Transfer end interrupt disabled Transfer end interrupt enabled Data transfer disabled Data transfer enabled Data transfer disabled Data transfer enabled Data transfer disabled Data transfer enabled

ISCRH — IRQ Sense Control Register H H'FF2C Interrupt Controller ISCRL — IRQ Sense Control Register L H'FF2D Interrupt Controller IRQ7SCB R/W IRQ7SCA R/W IRQ6SCB R/W IRQ6SCA R/W IRQ5SCB R/W IRQ4SCA R/W IRQ5SCA R/W IRQ4SCB R/W Bit Initial value Read/Write ISCRH IRQ3SCB R/W IRQ3SCA R/W IRQ2SCB R/W IRQ2SCA R/W IRQ1SCB R/W IRQ0SCA R/W IRQ1SCA R/W IRQ0SCB R/W IRQ7 to IRQ4 Sense Control IRQ3 to IRQ0 Sense Control IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input IRQnSCB IRQ nSCA Interrupt Request Generation (n = 7 to 0) Bit Initial value Read/Write ISCRL

IER—IRQ Enable Register H'FF2E Interrupt Controller IRQ7E R/W IRQ6E R/W IRQ5E R/W IRQ4E R/W IRQ3E R/W IRQ0E R/W IRQ2E R/W IRQ1E R/W IRQn Enable IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0) Bit Initial value Read/Write ISR—IRQ Status Register H'FF2F Interrupt Controller IRQ7F R/(W)* IRQ6F R/(W)* IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ0F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* Bit Initial value Read/Write Note: * Can only be written with 0 for flag clearing. Indicate the status of IRQ7 to IRQ0 interrupt requests

DTCERA to DTCERF—DTC Enable Registers H'FF30 to H'FF35 DTC DTCE7 R/W DTCE6 R/W DTCE5 R/W DTCE4 R/W DTCE3 R/W DTCE0 R/W DTCE2 R/W DTCE1 R/W DTC Activation Enable Bit Initial value Read/Write DTC activation by this interrupt is disabled [Clearing conditions]

When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended Correspondence between Interrupt Sources and DTCER Bits Register 76543 2 1 0 DTCERA IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DTCERB — ADI TGI0A TGI0B TGI0C TGI0D TGI1A TGI1B DTCERC TGI2A TGI2B TGI3A TGI3B TGI3C TGI3D TGI4A TGI4B DTCERD — — TGI5A TGI5B — — — — DTCERE DMTEND0A DMTEND0B DMTEND1A DMTEND1B RXI0 TXI0 RXI1 TXI1

DTVECR—DTC Vector Register H'FF37 DTC SWDTE R/(W)* DTVEC6 R/W DTVEC5 R/W DTVEC4 R/W DTVEC3 R/W DTVEC0 R/W DTVEC2 R/W DTVEC1 R/W A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. Note: * DTC Software Activation Enable DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions]

When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended
During data transfer due to software activation Sets vector number for DTC software activation Bit Initial value Read/Write

SBYCR—Standby Control Register H'FF38 Power-Down State SSBY R/W STS2 R/W STS1 R/W STS0 R/W OPE R/W R/W Software Standby Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction Standby Timer Select Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states Output Port Enable Reserved Only 0 should be written to this bit In software standby mode, address bus and bus control signals are high-impedance Bit Initial value Read/Write In software standby mode, address bus and bus control signals retain output state

SYSCR—System Control Register H'FF39 MCU R/W INTM1 R/W INTM0 R/W NMIEG R/W RAME R/W R/W Bit Initial value Read/Write Reserved Only 0 should be written to this bit Reserved Only 0 should be written to this bit Interrupt Control Mode Selection Interrupt control mode 0 Setting prohibited Interrupt control mode 2 Setting prohibited NMI Input Edge Select Falling edge Rising edge RAM Enable On-chip RAM disabled On-chip RAM enabled

SCKCR—System Clock Control Register H'FF3A Clock Pulse Generator PSTOP R/W R/W SCK0 R/W SCK2 R/W SCK1 R/W PSTOP Normal Operation ø output Fixed high High impedance High impedance Fixed high Fixed high ø Clock Output Control Bus Master Clock Select Bus master is in high-speed mode Medium-speed clock is ø/2 Medium-speed clock is ø/4 Medium-speed clock is ø/8 Medium-speed clock is ø/16 Medium-speed clock is ø/32 ø output Fixed high Sleep Mode Bit Initial value Read/Write Software Standby Mode Hardware Standby Mode

MDCR—Mode Control Register H'FF3B MCU MDS0 — * R MDS2 — * R MDS1 — * R Current mode pin operating mode Bit Initial value Read/Write Note: * Determined by pins MD2 to MD0 MSTPCRH — Module Stop Control Register H H'FF3C Power-Down State MSTPCRL — Module Stop Control Register L H'FF3D Power-Down State R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRH MSTPCRL Specifies module stop mode Module stop mode cleared Module stop mode set Bit Initial value Read/Write Reserved Register H'FF44 R/W Reserved Only 0 should be written to these bits Bit Initial value Read/Write

PCR—PPG Output Control Register H'FF46 PPG G3CMS1 R/W G3CMS0 R/W G2CMS1 R/W G2CMS0 R/W G1CMS1 R/W G0CMS0 R/W G1CMS0 R/W G0CMS1 R/W Output Trigger for Pulse Output Group 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 0 Bit Initial value Read/Write Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 2 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 3 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3

PMR—PPG Output Mode Register H'FF47 PPG G3INV R/W G2INV R/W G1INV R/W G0INV R/W G3NOV R/W G0NOV R/W G2NOV R/W G1NOV R/W Inverted output for pulse output group n (low-level output at pin for a 1 in PODRH) Pulse Output Group n Direct/Inverted Output Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) Pulse Output Group n Normal/Non-Overlap Operation Select n=3 to 0 n=3 to 0 Bit Initial value Read/Write Non-overlapping operation in pulse output group n (independent 1 and 0 output at compare match A or B in the selected TPU channel) Direct output for pulse output group n (high-level output at pin for a 1 in PODRH)

NDERH — Next Data Enable Registers H H'FF48 PPG NDERL — Next Data Enable Registers L H'FF49 PPG NDER15 R/W NDER14 R/W NDER13 R/W NDER12 R/W NDER11 R/W NDER8 R/W NDER10 R/W NDER9 R/W NDERH NDER7 R/W NDER6 R/W NDER5 R/W NDER4 R/W NDER3 R/W NDER0 R/W NDER2 R/W NDER1 R/W Pulse outputs PO15 to PO8 are disabled Pulse outputs PO15 to PO8 are enabled Pulse Output Enable/Disable Pulse Output Enable/Disable Bit Initial value Read/Write NDERL Bit Initial value Read/Write Pulse outputs PO7 to PO0 are disabled Pulse outputs PO7 to PO0 are enabled

PODRH — Output Data Register H H'FF4A PPG PODRL — Output Data Register L H'FF4B PPG POD15 R/(W)* POD14 R/(W)* POD13 R/(W)* POD12 R/(W)* POD11 R/(W)* POD8 R/(W)* POD10 R/(W)* POD9 R/(W)* POD7 R/(W)* POD6 R/(W)* POD5 R/(W)* POD4 R/(W)* POD3 R/(W)* POD0 R/(W)* POD2 R/(W)* POD1 R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only. Stores output data for use in pulse output Stores output data for use in pulse output PODRH Bit Initial value Read/Write PODRL Bit Initial value Read/Write

NDRH—Next Data Register H H'FF4C (FF4E) PPG NDR15 R/W NDR14 R/W NDR13 R/W NDR12 R/W NDR11 R/W NDR8 R/W NDR10 R/W NDR9 R/W (1) When pulse output group output triggers are the same (a) Address: H'FF4C (b) Address: H'FF4E NDR15 R/W NDR14 R/W NDR13 R/W NDR12 R/W (2) When pulse output group output triggers are different (a) Address: H'FF4C (b) Address: H'FF4E NDR11 R/W NDR8 R/W NDR10 R/W NDR9 R/W Bit Initial value Read/Write Bit Initial value Read/Write Bit Initial value Read/Write Bit Initial value Read/Write Stores the next data for pulse output groups 3 and 2 Stores the next data for pulse output group 3 Stores the next data for pulse output group 2

NDRL—Next Data Register L H'FF4D (FF4F) PPG (b) Address: H'FF4F (b) Address: H'FF4F NDR7 R/W NDR6 R/W NDR5 R/W NDR4 R/W NDR3 R/W NDR0 R/W NDR2 R/W NDR1 R/W NDR7 R/W NDR6 R/W NDR5 R/W NDR4 R/W NDR3 R/W NDR0 R/W NDR2 R/W NDR1 R/W Bit Initial value Read/Write Bit Initial value Read/Write Bit Initial value Read/Write (1) When pulse output group output triggers are the same (a) Address: H'FF4D (2) When pulse output group output triggers are different (a) Address: H'FF4D Bit Initial value Read/Write Stores the next data for pulse output groups 1 and 0 Stores the next data for pulse output group 1 Stores the next data for pulse output group 0

PORT1—Port 1 Register H'FF50 Port 1 P17 — * R P16 — * R P15 — * R P14 — * R P13 — * R P10 — * R P12 — * R P11 — * R Note: * Determined by the state of pins P17 to P10. State of port 1 pins Bit Initial value Read/Write PORT2—Port 2 Register H'FF51 Port 2 P27 — * R P26 — * R P25 — * R P24 — * R P23 — * R P20 — * R P22 — * R P21 — * R State of port 2 pins Note: * Determined by the state of pins P27 to P20. Bit Initial value Read/Write PORT3—Port 3 Register H'FF52 Port 3 Undefined Undefined P35 — * R P34 — * R P33 — * R P30 — * R P32 — * R P31 — * R State of port 3 pins Note: * Determined by the state of pins P35 to P30. Bit Initial value Read/Write

PORT4—Port 4 Register H'FF53 Port 4 P47 — * R P46 — * R P45 — * R P44 — * R P43 — * R P40 — * R P42 — * R P41 — * R State of port 4 pins Note: * Determined by the state of pins P47 to P40. Bit Initial value Read/Write PORT5—Port 5 Register H'FF54 Port 5 Undefined Undefined Undefined Undefined P53 — * R P50 — * R P52 — * R P51 — * R State of port 5 pins Note: * Determined by the state of pins P53 to P50. Bit Initial value Read/Write PORT6—Port 6 Register H'FF55 Port 6 P67 — * R P66 — * R P65 — * R P64 — * R P63 — * R P60 — * R P62 — * R P61 — * R State of port 6 pins Note: * Determined by the state of pins P67 to P60. Bit Initial value Read/Write

PORTA—Port A Register H'FF59 Port A PA7 — * R PA6 — * R PA5 — * R PA4 — * R PA3 — * R PA0 — * R PA2 — * R PA1 — * R State of port A pins Note: * Determined by the state of pins PA7 to PA0. Bit Initial value Read/Write PORTB—Port B Register H'FF5A Port B [H8S/2351 Only] PB7 — * R PB6 — * R PB5 — * R PB4 — * R PB3 — * R PB0 — * R PB2 — * R PB1 — * R State of port B pins Note: * Determined by the state of pins PB7 to PB0. Bit Initial value Read/Write PORTC—Port C Register H'FF5B Port C [H8S/2351 Only] PC7 — * R PC6 — * R PC5 — * R PC4 — * R PC3 — * R PC0 — * R PC2 — * R PC1 — * R State of port C pins Note: * Determined by the state of pins PC7 to PC0. Bit Initial value Read/Write

PORTD—Port D Register H'FF5C Port D [H8S/2351 Only] PD7 R PD6 R PD5 R PD4 R PD3 R PD0 R PD2 R PD1 R State of port D pins Note: * Determined by the state of pins PD7 to PD0. Bit Initial value Read/Write PORTE—Port E Register H'FF5D Port E PE7 R PE6 R PE5 R PE4 R PE3 R PE0 R PE2 R PE1 R State of port E pins Note: * Determined by the state of pins PE7 to PE0. Bit Initial value Read/Write PORTF—Port F Register H'FF5E Port F PF7 — * R PF6 — * R PF5 — * R PF4 — * R PF3 — * R PF0 — * R PF2 — * R PF1 — * R State of port F pins Note: * Determined by the state of pins PF7 to PF0. Bit Initial value Read/Write

PORTG—Port G Register H'FF5F Port G Undefined Undefined Undefined PG4 — * R PG3 — * R PG0 — * R PG2 — * R PG1 — * R State of port G pins Note: * Determined by the state of pins PG4 to PG0. Bit Initial value Read/Write P1DR—Port 1 Data Register H'FF60 Port 1 P17DR R/W P16DR R/W P15DR R/W P14DR R/W P13DR R/W P10DR R/W P12DR R/W P11DR R/W Stores output data for port 1 pins (P17 to P10) Bit Initial value Read/Write P2DR—Port 2 Data Register H'FF61 Port 2 P27DR R/W P26DR R/W P25DR R/W P24DR R/W P23DR R/W P20DR R/W P22DR R/W P21DR R/W Stores output data for port 2 pins (P27 to P20) Bit Initial value Read/Write

P3DR—Port 3 Data Register H'FF62 Port 3 Undefined Undefined P35DR R/W P34DR R/W P33DR R/W P30DR R/W P32DR R/W P31DR R/W Stores output data for port 3 pins (P35 to P30) Bit Initial value Read/Write P5DR—Port 5 Data Register H'FF64 Port 5 Undefined Undefined Undefined Undefined P53DR R/W P50DR R/W P52DR R/W P51DR R/W Stores output data for port 5 pins (P53 to P50) Bit Initial value Read/Write P6DR—Port 6 Data Register H'FF65 Port 6 P67DR R/W P66DR R/W P65DR R/W P64DR R/W P63DR R/W P60DR R/W P62DR R/W P61DR R/W Stores output data for port 6 pins (P67 to P60) Bit Initial value Read/Write

PADR—Port A Data Register H'FF69 Port A PA7DR R/W PA6DR R/W PA5DR R/W PA4DR R/W PA3DR R/W PA0DR R/W PA2DR R/W PA1DR R/W Stores output data for port A pins (PA7 to PA 0) Bit Initial value Read/Write PBDR—Port B Data Register H'FF6A Port B [H8S/2351 Only] PB7DR R/W PB6DR R/W PB5DR R/W PB4DR R/W PB3DR R/W PB0DR R/W PB2DR R/W PB1DR R/W Stores output data for port B pins (PB7 to PB0) Bit Initial value Read/Write PCDR—Port C Data Register H'FF6B Port C [H8S/2351 Only] PC7DR R/W PC6DR R/W PC5DR R/W PC4DR R/W PC3DR R/W PC0DR R/W PC2DR R/W PC1DR R/W Stores output data for port C pins (PC7 to PC0) Bit Initial value Read/Write

PDDR—Port D Data Register H'FF6C Port D [H8S/2351 Only] PD7DR R/W PD6DR R/W PD5DR R/W PD4DR R/W PD3DR R/W PD0DR R/W PD2DR R/W PD1DR R/W Stores output data for port D pins (PD7 to PD0) Bit Initial value Read/Write PEDR—Port E Data Register H'FF6D Port E PE7DR R/W PE6DR R/W PE5DR R/W PE4DR R/W PE3DR R/W PE0DR R/W PE2DR R/W PE1DR R/W Stores output data for port E pins (PE7 to PE0) Bit Initial value Read/Write PFDR—Port F Data Register H'FF6E Port F PF7DR R/W PF6DR R/W PF5DR R/W PF4DR R/W PF3DR R/W PF0DR R/W PF2DR R/W PF1DR R/W Stores output data for port F pins (PF7 to PF0) Bit Initial value Read/Write

PGDR—Port G Data Register H'FF6F Port G Undefined Undefined Undefined PG4DR R/W PG3DR R/W PG0DR R/W PG2DR R/W PG1DR R/W Stores output data for port G pins (PG4 to PG0) Bit Initial value Read/Write PAPCR—Port A MOS Pull-Up Control Register H'FF70 Port A [H8S/2351 Only] PA7PCR R/W PA6PCR R/W PA5PCR R/W PA4PCR R/W PA3PCR R/W PA0PCR R/W PA2PCR R/W PA1PCR R/W Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis Bit Initial value Read/Write PBPCR—Port B MOS Pull-Up Control Register H'FF71 Port B [H8S/2351 Only] PB7PCR R/W PB6PCR R/W PB5PCR R/W PB4PCR R/W PB3PCR R/W PB0PCR R/W PB2PCR R/W PB1PCR R/W Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis Bit Initial value Read/Write

PCPCR—Port C MOS Pull-Up Control Register H'FF72 Port C [H8S/2351 Only] PC7PCR R/W PC6PCR R/W PC5PCR R/W PC4PCR R/W PC3PCR R/W PC0PCR R/W PC2PCR R/W PC1PCR R/W Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis Bit Initial value Read/Write PDPCR—Port D MOS Pull-Up Control Register H'FF73 Port D [H8S/2351 Only] PD7PCR R/W PD6PCR R/W PD5PCR R/W PD4PCR R/W PD3PCR R/W PD0PCR R/W PD2PCR R/W PD1PCR R/W Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis Bit Initial value Read/Write PEPCR—Port E MOS Pull-Up Control Register H'FF74 Port E [H8S/2351 Only] PE7PCR R/W PE6PCR R/W PE5PCR R/W PE4PCR R/W PE3PCR R/W PE0PCR R/W PE2PCR R/W PE1PCR R/W Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis Bit Initial value Read/Write

P3ODR—Port 3 Open Drain Control Register H'FF76 Port 3 Undefined Undefined P35ODR R/W P34ODR R/W P33ODR R/W P30ODR R/W P32ODR R/W P31ODR R/W Controls the PMOS on/off status for each port 3 pin (P35 to P30) Bit Initial value Read/Write PAODR—Port A Open Drain Control Register H'FF77 Port A [H8S/2351 Only] PA7ODR R/W PA6ODR R/W PA5ODR R/W PA4ODR R/W PA3ODR R/W PA0ODR R/W PA2ODR R/W PA1ODR R/W Controls the PMOS on/off status for each port A pin (PA7 to PA0) Bit Initial value Read/Write

SMR0—Serial Mode Register 0 H'FF78 SCI0 C/A/CR R/W CHR R/W PE R/W O/E/CR R/W STOP R/W CKS0 R/W MP R/W CKS1 R/W Asynchronous mode Synchronous mode Asynchronous Mode/Synchronous Mode Select Parity bit addition and checking disabled Parity bit addition and checking enabled Parity Enable Even parity Odd parity Parity Mode ø clock ø/4 clock ø/16 clock ø/64 clock Clock Select Multiprocessor function disabled Multiprocessor format selected Multiprocessor Mode 1 stop bit 2 stop bits Stop Bit Length 8-bit data 7-bit data* Character Length Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Bit Initial value Read/Write

SMR0—Serial Mode Register 0 H'FF78 Smart Card Interface 0 GM R/W CHR R/W PE R/W O/E R/W STOP R/W CKS0 R/W MP R/W CKS1 R/W Normal smart card interface mode operation

TEND flag generated 12.5 etu after beginning of start bit
Clock output on/off control only GSM mode smart card interface mode operation
TEND flag generated 11.0 etu after beginning of start bit
Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control GSM Mode Setting prohibited Parity bit addition and checking enabled Parity Enable Even parity Odd parity Parity Mode ø clock ø/4 clock ø/16 clock ø/64 clock Clock Select Multiprocessor function disabled Setting prohibited Multiprocessor Mode Setting prohibited 2 stop bits Stop Bit Length 8-bit data Setting prohibited Character Length Bit Initial value Read/Write Note: etu (Elementary Time Unit): Interval for transfer of one bit

BRR0—Bit Rate Register 0 H'FF79 SCI0, Smart Card Interface 0 R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: See section 13.2.8, Bit Rate Register (BRR), for details. Bit Initial value Read/Write

SCR0—Serial Control Register 0 H'FF7A SCI0 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W CKE0 R/W TEIE R/W CKE1 R/W 0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port Clock Enable Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Transmit End Interrupt Enable

0 Multiprocessor interrupts disabled

[Clearing conditions]

When the MPIE bit is cleared to 0
When MPB= 1 data is received Multiprocessor Interrupt Enable Reception disabled Reception enabled Receive Enable Transmission disabled Transmission enabled Transmit Enable

0 Receive data full interrupt (RXI) request and

receive error interrupt (ERI) request disabled Receive Interrupt Enable Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Transmit Interrupt Enable Notes: Bit Initial value Read/Write Synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode Internal clock/SCK pin functions as clock output*1 Synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode External clock/SCK pin functions as clock input*2 Synchronous mode External clock/SCK pin functions as serial clock input Asynchronous mode External clock/SCK pin functions as clock input*2 Synchronous mode External clock/SCK pin functions as serial clock input 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received

1 Receive data full interrupt (RXI) request and

receive error interrupt (ERI) request enabled

SCR0—Serial Control Register 0 H'FF7A Smart Card Interface 0 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W CKE0 R/W TEIE R/W CKE1 R/W SMCR SMIF SMR C/A,GM CKE1 CKE0 See SCI specification SCK pin function Clock Enable SCR setting Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Transmit End Interrupt Enable [Clearing conditions]

When the MPIE bit is cleared to 0
When MPB= 1 data is received Multiprocessor Interrupt Enable Reception disabled Reception enabled Receive Enable Transmission disabled Transmission enabled Transmit Enable

receive error interrupt (ERI) request disabled Receive Interrupt Enable Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Transmit Interrupt Enable Bit Initial value Read/Write Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received receive error interrupt (ERI) request enabled Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin

TDR0—Transmit Data Register 0 H'FF7B SCI0, Smart Card Interface 0 R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Bit Initial value Read/Write

SSR0—Serial Status Register 0 H'FF7C SCI0 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR TDRE R/(W)* RDRF R/(W)* ORER R/(W)* FER R/(W)* PER R/(W)* MPBT R/W TEND R MPB R Note: * Can only be written with 0 for flag clearing. Transmit Data Register Empty Receive Data Register Full Overrun Error Framing Error Parity Error Transmit End [Clearing condition]

When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Bit Initial value Read/Write [Setting conditions]
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition]
When 0 is written to RDRF after reading RDRF = 1
When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition]
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR

SSR0—Serial Status Register 0 H'FF7C Smart Card Interface 0 TDRE R/(W)* RDRF R/(W)* ORER R/(W)* ERS R/(W)* PER R/(W)* MPBT R/W TEND R MPB R Note: * Can only be written with 0 for flag clearing. Transmit Data Register Empty Receive Data Register Full Overrun Error Error Signal Status Parity Error Transmit End [Clearing condition]

When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Bit Initial value Read/Write [Setting conditions]
On reset, or in standby mode or module stop mode
When the TE bit in SCR is 0 and the ERS bit is 0
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR [Clearing condition]
On reset, or in standby mode or module stop mode
When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition]
When 0 is written to RDRF after reading RDRF = 1
When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition]
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR Note: etu: Elementary Time Unit (the time taken to transmit one bit) Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.

RDR0—Receive Data Register 0 H'FF7D SCI0, Smart Card Interface 0 R R R R R R R R Bit Initial value Read/Write Stores received serial data SCMR0—Smart Card Mode Register 0 H'FF7E SCI0, Smart Card Interface 0 SDIR R/W SMIF R/W SINV R/W TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first Smart Card Data Direction TDR contents are transmitted as they are Receive data is stored in RDR as it is Smart Card Data Invert Smart Card interface function is disabled Smart Card Interface Mode Select Bit Initial value Read/Write Smart Card interface function is enabled TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first

SMR1—Serial Mode Register 1 H'FF80 SCI1 C/A/CR R/W CHR R/W PE R/W O/E/CR R/W STOP R/W CKS0 R/W MP R/W CKS1 R/W Asynchronous mode Synchronous mode Asynchronous Mode/Synchronous Mode Select Parity bit addition and checking disabled Parity bit addition and checking enabled Parity Enable Even parity Odd parity Parity Mode ø clock ø/4 clock ø/16 clock ø/64 clock Clock Select Multiprocessor function disabled Multiprocessor format selected Multiprocessor Mode 1 stop bit 2 stop bits Stop Bit Length 8-bit data 7-bit data* Character Length Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Bit Initial value Read/Write

SMR1—Serial Mode Register 1 H'FF80 Smart Card Interface 1 GM R/W CHR R/W PE R/W O/E R/W STOP R/W CKS0 R/W MP R/W CKS1 R/W Normal smart card interface mode operation

TEND flag generated 12.5 etu after beginning of start bit
Clock output on/off control only GSM mode smart card interface mode operation
TEND flag generated 11.0 etu after beginning of start bit
Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control GSM Mode Setting prohibited Parity bit addition and checking enabled Parity Enable Even parity Odd parity Parity Mode ø clock ø/4 clock ø/16 clock ø/64 clock Clock Select Multiprocessor function disabled Setting prohibited Multiprocessor Mode Setting prohibited 2 stop bits Stop Bit Length 8-bit data Setting prohibited Character Length Bit Initial value Read/Write Note: etu (Elementary Time Unit): Interval for transfer of one bit

BRR1—Bit Rate Register 1 H'FF81 SCI1, Smart Card Interface 1 R/W R/W R/W R/W R/W R/W R/W R/W Note: See section 13.2.8, Bit Rate Register (BRR), for details. Sets the serial transfer bit rate Bit Initial value Read/Write

SCR1—Serial Control Register 1 H'FF82 SCI1 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W CKE0 R/W TEIE R/W CKE1 R/W

0 Asynchronous

Internal clock/SCK pin functions as I/O port Clock Enable Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Transmit End Interrupt Enable [Clearing conditions]

When the MPIE bit is cleared to 0
When MPB= 1 data is received Multiprocessor Interrupt Enable Reception disabled Reception enabled Receive Enable Transmission disabled Transmission enabled Transmit Enable

SCR1—Serial Control Register 1 H'FF82 Smart Card Interface 1 TIE R/W RIE R/W TE R/W RE R/W MPIE R/W CKE0 R/W TEIE R/W CKE1 R/W SMCR SMIF SMR C/A,GM CKE1 CKE0 See SCI specification SCK pin function Clock Enable SCR setting Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Transmit End Interrupt Enable [Clearing conditions]

When the MPIE bit is cleared to 0
When MPB= 1 data is received Multiprocessor Interrupt Enable Reception disabled Reception enabled Receive Enable Transmission disabled Transmission enabled Transmit Enable

receive error interrupt (ERI) request disabled Receive Interrupt Enable Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Transmit Interrupt Enable Bit Initial value Read/Write Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received receive error interrupt (ERI) request enabled Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin

TDR1—Transmit Data Register 1 H'FF83 SCI1, Smart Card Interface 1 R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Bit Initial value Read/Write

SSR1—Serial Status Register 1 H'FF84 SCI1 TDRE R/(W)* RDRF R/(W)* ORER R/(W)* FER R/(W)* PER R/(W)* MPBT R/W TEND R MPB R Note: * Can only be written with 0 for flag clearing. Transmit Data Register Empty Receive Data Register Full Overrun Error Framing Error Parity Error Transmit End Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Bit Initial value Read/Write [Setting condition] When data with a 1 multiprocessor bit is received [Clearing condition]

When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition]
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition]
When 0 is written to RDRF after reading RDRF = 1
When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition]
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR

SSR1—Serial Status Register 1 H'FF84 Smart Card Interface 1 TDRE R/(W)* RDRF R/(W)* ORER R/(W)* ERS R/(W)* PER R/(W)* MPBT R/W TEND R MPB R Note: * Can only be written with 0 for flag clearing. Transmit Data Register Empty Receive Data Register Full Overrun Error Error Signal Status Parity Error Transmit End Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Bit Initial value Read/Write [Setting conditions] When data with a 1 multiprocessor bit is received [Clearing condition]

When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions]
On reset, or in standby mode or module stop mode
When the TE bit in SCR is 0 and the ERS bit is 0
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR [Clearing condition]
On reset, or in standby mode or module stop mode
When 0 is written to ERS after reading ERS =1 [Setting conditions] When the error signal is sampled at the low level [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition]
When 0 is written to RDRF after reading RDRF = 1
When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition]
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR Note: etu: Elementary Time Unit (the time taken to transmit one bit) Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.

RDR1—Receive Data Register 1 H'FF85 SCI1, Smart Card Interface 1 R R R R R R R R Stores received serial data Bit Initial value Read/Write SCMR1—Smart Card Mode Register 1 H'FF86 SCI1, Smart Card Interface 1 SDIR R/W SMIF R/W SINV R/W TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first Smart Card Data Direction

0 TDR contents are transmitted as they are

Receive data is stored in RDR as it is Smart Card Data Invert Smart Card interface function is disabled Smart Card Interface Mode Select Bit Initial value Read/Write Smart Card interface function is enabled TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first

ADDRAH — A/D Data Register AH H'FF90 A/D Converter ADDRAL — A/D Data Register AL H'FF91 A/D Converter ADDRBH — A/D Data Register BH H'FF92 A/D Converter ADDRBL — A/D Data Register BL H'FF93 A/D Converter ADDRCH — A/D Data Register CH H'FF94 A/D Converter ADDRCL — A/D Data Register CL H'FF95 A/D Converter ADDRDH — A/D Data Register DH H'FF96 A/D Converter ADDRDL — A/D Data Register DL H'FF97 A/D Converter AD9 R AD8 R AD7 R AD6 R AD5 R AD4 R AD3 R AD2 R AD1 R AD0 R R R R R R R Stores the results of A/D conversion Analog Input Channel A/D Data Register Bit Initial value Read/Write Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 ADDRA ADDRB ADDRC ADDRD

ADCSR—A/D Control/Status Register H'FF98 A/D Converter [Clearing conditions]

When 0 is written to the ADF flag after reading ADF = 1
When the DTC is activated by an ADI interrupt, and ADDR is read ADF R/(W)* ADIE R/W ADST R/W SCAN R/W CKS R/W CH0 R/W CH2 R/W CH1 R/W Note: * Can only be written with 0 for flag clearing. Conversion time= 266 states (max.) Conversion time= 134 states (max.) Group Select A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled A/D Interrupt Enable Single mode Scan mode Scan Mode A/D conversion stopped A/D Start A/D End Flag CH1 CH0 Single Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Channel Select Bit Initial value Read/Write
Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends
Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode [Setting conditions]
Single mode: When A/D conversion ends
Scan mode: When one round of conversion has been performed on all specified channels CH2 Group select Channel select AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Group Mode

ADCR—A/D Control Register H'FF99 A/D TRGS1 R/W TRGS0 R/W A/D conversion start by software is enabled A/D conversion start by TPU conversion start trigger is enabled A/D conversion start by external trigger pin (ADTRG) is enabled TRGS1TRGS1

DADR0—D/A Data Register 0 H'FFA4 D/A DADR1—D/A Data Register 1 H'FFA5 D/A R/W R/W R/W R/W R/W R/W R/W R/W Stores data for D/A conversion Bit Initial value Read/Write

DACR—D/A Control Register H'FFA6 D/A DAOE1 R/W DAOE0 R/W DAE R/W D/A Conversion Control DAOE1 DAOE0 DAE Description Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled * : Don’t care Analog output DA0 is disabled Channel 0 D/A conversion is enabled D/A Output Enable 0 Analog output DA1 is disabled Channel 1 D/A conversion is enabled D/A Output Enable 1 Bit Initial value Read/Write Analog output DA0 is enabled Analog output DA1 is enabled

TCSR—Timer Control/Status Register H'FFBC (W) H'FFBC (R) WDT OVF R/(W)* WT/ IT R/W TME R/W CKS0 R/W CKS2 R/W CKS1 R/W The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. 0 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF Overflow Flag

0 Interval timer mode: Sends the CPU an interval timer interrupt request

(WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows Timer Mode Select TCNT is initialized to H'00 and halted TCNT counts Timer Enable Clock Select CKS2 CKS1 CKS0 Clock Overflow period* (when ø = 20 MHz) ø/2 (initial value) ø/64 ø/128 ø/512 ø/2048 ø/8192 ø/32768 ø/131072 25.6µs 819.2µs 1.6ms 6.6ms 26.2ms 104.9ms 419.4ms 1.68s Note: * Can only be written with 0 for flag clearing. Note: * Bit Initial value Read/Write The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. [Setting condition] Set when TCNT overflows from H'FF to H'00 in interval timer mode

TCNT—Timer Counter H'FFBC (W) H'FFBD (R) WDT R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write RSTCSR—Reset Control/Status Register H'FFBE (W) H'FFBF (R) WDT WOVF R/(W)* RSTE R/W RSTS R/W [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF Watchdog Timer Overflow Flag Note: * Can only be written with 0 for flag clearing. The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. Reset Enable Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Reset Select Power-on reset Manual reset Bit Initial value Read/Write [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Note: * The modules H8S/2350 Series are not reset, but TCNT and TCSR in WDT are reset.

TSTR—Timer Start Register H'FFC0 TPU CST5 R/W CST4 R/W CST3 R/W CST0 R/W CST2 R/W CST1 R/W Counter Start TCNTn count operation is stopped TCNTn performs count operation Note: (n = 5 to 0) If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. Bit Initial value Read/Write TSYR—Timer Synchro Register H'FFC1 TPU SYNC5 R/W SYNC4 R/W SYNC3 R/W SYNC0 R/W SYNC2 R/W SYNC1 R/W Timer Synchronization TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) (n = 5 to 0) Notes: To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Bit Initial value Read/Write TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible

TCR0—Timer Control Register 0 H'FFD0 TPU0 CCLR2 R/W CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC0 R/W TPSC2 R/W TPSC1 R/W TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel Counter Clear 0 0 Clock Edge Count at rising edge Count at falling edge Count at both edges Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Time Prescaler Bit Initial value Read/Write Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture* TCNT cleared by TGRD compare match/input capture*2

TMDR0—Timer Mode Register 0 H'FFD1 TPU0 BFB R/W BFA R/W MD3 R/W MD0 R/W MD2 R/W MD1 R/W TGRB Buffer Operation TGRB operates normally TGRA Buffer Operation TGRA operates normally Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. * : Don’t care Bit Initial value Read/Write TGRA and TGRC used together for buffer operation TGRB and TGRD used together for buffer operation

TIOR0H—Timer I/O Control Register 0H H'FFD2 TPU0 IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA0 R/W IOA2 R/W IOA1 R/W TGR0B I/O Control TGR0A is output compare register TGR0A I/O Control Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges * : Don’t care * : Don’t care Note: *1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and ø/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Bit Initial value Read/Write Initial output is 0 output TGR0A is input capture register Output disabled Initial output is 1 output Capture input source is TIOCA0 pin Capture input source is channel 1/count clock Input capture at TCNT1 count-up/ count-down TGR0B is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR0B is input capture register Output disabled Initial output is 0 output Capture input source is TIOCB0 pin Capture input source is channel 1/count clock Input capture at TCNT1 count-up/ count-down*

TIOR0L—Timer I/O Control Register 0L H'FFD3 TPU0 TGR0D I/O Control TGR0C I/O Control * : Don’t care * : Don’t care Note: When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and ø/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. IOD3 R/W IOD2 R/W IOD1 R/W IOD0 R/W IOC3 R/W IOC0 R/W IOC2 R/W IOC1 R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Bit Initial value Read/Write TGR0C is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR0C is input capture register Output disabled Initial output is 1 output Capture input source is TIOCC0 pin Capture input source is channel 1/count clock Input capture at TCNT1 count-up/ count-down TGR0D is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR0D is input capture register Output disabled Initial output is 1 output Capture input source is TIOCD0 pin Capture input source is channel 1/count clock Input capture at TCNT1 count-up/ count-down*

TIER0—Timer Interrupt Enable Register 0 H'FFD4 TPU0 TTGE R/W TCIEV R/W TGIED R/W TGIEA R/W TGIEC R/W TGIEB R/W A/D conversion start request generation disabled A/D conversion start request generation enabled A/D Conversion Start Request Enable Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Overflow Interrupt Enable TGR Interrupt Enable D TGR Interrupt Enable C TGR Interrupt Enable B Interrupt requests (TGIA) by TGFA bit disabled TGR Interrupt Enable A Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGID) by TGFD bit disabled Bit Initial value Read/Write Interrupt requests (TGIA) by TGFA bit enabled Interrupt requests (TGIB) by TGFB bit enabled Interrupt requests (TGIC) by TGFC bit enabled Interrupt requests (TGID) by TGFD bit enabled

TSR0—Timer Status Register 0 H'FFD5 TPU0 TCFV R/(W)* TGFD R/(W)* TGFA R/(W)* TGFC R/(W)* TGFB R/(W)* Note: * Can only be written with 0 for flag clearing. Overflow Flag Input Capture/Output Compare Flag D Input Capture/Output Compare Flag C Input Capture/Output Compare Flag B 0 [Clearing condition]

When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
When 0 is written to TGFA after reading TGFA = 1 Input Capture/Output Compare Flag A Bit Initial value Read/Write [Setting conditions]
When TCNT = TGRA while TGRA is functioning as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing condition]
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1 [Setting conditions]
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing condition]
When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFC after reading TGFC = 1 [Setting conditions]
When TCNT = TGRC while TGRC is functioning as output compare register
When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Clearing condition]
When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFD after reading TGFD = 1 [Setting conditions]
When TCNT = TGRD while TGRD is functioning as output compare register
When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 )

TCNT0—Timer Counter 0 H'FFD6 TPU0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A—Timer General Register 0A H'FFD8 TPU0 TGR0B—Timer General Register 0B H'FFDA TPU0 TGR0C—Timer General Register 0C H'FFDC TPU0 TGR0D—Timer General Register 0D H'FFDE TPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write

TCR1—Timer Control Register 1 H'FFE0 TPU1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture Counter Clear Clock Edge Count at rising edge Count at falling edge Count at both edges Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on ø/256 Counts on TCNT2 overflow/underflow Time Prescaler CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC0 R/W TPSC2 R/W TPSC1 R/W Note:This setting is ignored when channel 1 is in phase counting mode. Note: * Synchronous operating setting is performed by setting the SYNC bit in TSYR to 1. Bit Initial value Read/Write Note:This setting is ignored when channel 1 is in phase counting mode. TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*

TMDR1—Timer Mode Register 1 H'FFE1 TPU1 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 1Phase counting mode 4 Mode Notes:MD3 is a reserved bit. In a write, it should always be written with 0. * : Don’t care MD3 R/W MD0 R/W MD2 R/W MD1 R/W Bit Initial value Read/Write

TIOR1—Timer I/O Control Register 1 H'FFE2 TPU1 IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA0 R/W IOA2 R/W IOA1 R/W TGR1B I/O Control TGR1A I/O Control * : Don’t care * : Don’t care Bit Initial value Read/Write TGR1A is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR1A is input capture register Output disabled Initial output is 1 output Capture input source is TIOCA1 pin Capture input source is TGR0A compare match/ input capture Input capture at generation of channel 0/TGR0A compare match/ input capture TGR1B is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR1B is input capture register Output disabled Initial output is 1 output Capture input source is TIOCB1 pin Capture input source is TGR0C compare match/ input capture Input capture at generation of TGR0B compare match/input capture

TIER1—Timer Interrupt Enable Register 1 H'FFE4 TPU1 TTGE R/W TCIEU R/W TCIEV R/W TGIEA R/W TGIEB R/W A/D conversion start request generation disabled A/D conversion start request generation enabled A/D Conversion Start Request Enable Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B Interrupt requests (TGIA) by TGFA bit disabled TGR Interrupt Enable A Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Overflow Interrupt Enable Bit Initial value Read/Write Interrupt requests (TGIA) by TGFA bit enabled Interrupt requests (TGIB) by TGFB bit enabled

TSR1—Timer Status Register 1 H'FFE5 TPU1 TCFD R TCFU R/(W)* TCFV R/(W)* TGFA R/(W)* TGFB R/(W)* TCNT counts down TCNT counts up Count Direction Flag Underflow Flag Overflow Flag Input Capture/Output Compare Flag B 0 [Clearing condition]

When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
When 0 is written to TGFA after reading TGFA = 1 Input Capture/Output Compare Flag A Note: * Can only be written with 0 for flag clearing. Bit Initial value Read/Write [Setting conditions]
When TCNT = TGRA while TGRA is functioning as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing condition]
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1 [Setting conditions]
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF)

TCNT1—Timer Counter 1 H'FFE6 TPU1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * Up/down-counter* Bit Initial value Read/Write This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A—Timer General Register 1A H'FFE8 TPU1 TGR1B—Timer General Register 1B H'FFEA TPU1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write

TCR2—Timer Control Register 2 H'FFF0 TPU2 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture Counter Clear Clock Edge Count at rising edge Count at falling edge Count at both edges Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024 Time Prescaler CCLR1 R/W CCLR0 R/W CKEG1 R/W CKEG0 R/W TPSC0 R/W TPSC2 R/W TPSC1 R/W Note: This setting is ignored when channel 2 is in phase counting mode. Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Bit Initial value Read/Write Note: This setting is ignored when channel 2 is in phase counting mode. TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*

TMDR2—Timer Mode Register 2 H'FFF1 TPU2 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode Notes: MD3 is a reserved bit. In a write, it should always be written with 0. * : Don’t care MD3 R/W MD0 R/W MD2 R/W MD1 R/W Bit Initial value Read/Write

TIOR2—Timer I/O Control Register 2 H'FFF2 TPU2 IOB3 R/W IOB2 R/W IOB1 R/W IOB0 R/W IOA3 R/W IOA0 R/W IOA2 R/W IOA1 R/W TGR2B I/O Control * : Don’t care TGR2A is output compare register TGR2A I/O Control 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges * : Don’t care Bit Initial value Read/Write Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR2A is input capture register Capture input source is TIOCA2 pin TGR2B is output compare register 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Output disabled Initial output is 0 output Output disabled Initial output is 1 output TGR2B is input capture register Capture input source is TIOCB2 pin

TIER2—Timer Interrupt Enable Register 2 H'FFF4 TPU2 TTGE R/W TCIEU R/W TCIEV R/W TGIEA R/W TGIEB R/W A/D conversion start request generation disabled A/D conversion start request generation enabled A/D Conversion Start Request Enable Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B Interrupt requests (TGIA) by TGFA bit disabled TGR Interrupt Enable A Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Overflow Interrupt Enable Bit Initial value Read/Write Interrupt requests (TGIA) by TGFA bit enabled Interrupt requests (TGIB) by TGFB bit enabled

TSR2—Timer Status Register 2 H'FFF5 TPU2 TCFD R TCFU R/(W)* TCFV R/(W)* TGFA R/(W)* TGFB R/(W)* TCNT counts down TCNT counts up Count Direction Flag Underflow Flag Overflow Flag Input Capture/Output Compare Flag B 0 [Clearing condition]

When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
When 0 is written to TGFA after reading TGFA = 1 Input Capture/Output Compare Flag A Note: * Can only be written with 0 for flag clearing. Bit Initial value Read/Write [Setting conditions]
When TCNT = TGRA while TGRA is functioning as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing condition]
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1 [Setting conditions]
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF)

TCNT2—Timer Counter 2 H'FFF6 TPU2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. Up/down-counter* Bit Initial value Read/Write TGR2A—Timer General Register 2A H'FFF8 TPU2 TGR2B—Timer General Register 2B H'FFFA TPU2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write

Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram R P1nDDR C QD Reset WDDR1 Reset WDR1 R P1nDR C QD P1n RDR1 RPOR1 Internal data bus PPG module DMA controller TPU module Pulse output enable DMA transfer acknowledge enable Pulse output DMA transfer acknowledge Output compare output/ PWM output enable Output compare output/ PWM output Input capture input WDDR1 WDR1 RDR1 RPOR1 n = 0 or 1 Note: * Priority order: Output compare output/PWM output > DMA transfer acknowledge output > pulse output > DR output Legend : Write to P1DDR : Write to P1DR : Read P1DR : Read port 1 Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11)

R P1nDDR C QD Reset WDDR1 Reset WDR1 R P1nDR C QD P1n RDR1 RPOR1 Internal data bus PPG module TPU module Pulse output enable Output compare output/ PWM output enable Output compare output/ PWM output Pulse output External clock input Input capture input WDDR1 WDR1 RDR1 RPOR1 n = 2, 3, 5, 7 Note: * Priority order: Output compare output/PWM output > pulse output > DR output : Write to P1DDR : Write to P1DR : Read P1DR : Read port 1 Legend Figure C-1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17)

R P1nDDR C QD Reset WDDR1 Reset WDR1 R P1nDR C QD P1n RDR1 RPOR1 Internal data bus PPG module TPU module Pulse output enable Output compare output/ PWM output enable Output compare output/ PWM output Pulse output Input capture input WDDR1 WDR1 RDR1 RPOR1 n = 4 or 6 Note: * Priority order: Output compare output/PWM output > pulse output > DR output : Write to P1DDR : Write to P1DR : Read P1DR : Read port 1 Legend Figure C-1 (c) Port 1 Block Diagram (Pins P14 and P16)

C.2 Port 2 Block Diagram R P2nDDR C QD Reset WDDR2 Reset WDR2 R P2nDR C QD P2n RDR2 RPOR2 Internal data bus PPG module TPU module Pulse output enable Output compare output/ PWM output enable Output compare output/ PWM output Pulse output Input capture input WDDR2 WDR2 RDR2 RPOR2 n = 0 to 7 Note: * Priority order: Output compare output/PWM output > pulse output > DR output : Write to P2DDR : Write to P2DR : Read P2DR : Read port 2 Legend Figure C-2 Port 2 Block Diagram (Pin P2n)

C.3 Port 3 Block Diagram R P3nDDR C QD Reset WDDR3 Reset WDR3 R C QD P3n RDR3 RODR3 RPOR3 Internal data bus SCI module Serial transmit enable Serial transmit data WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n = 0 or 1 Notes: 1. Output enable signal 2. Open drain control signal : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR P3nDR Reset WODR3 R C QD P3nODR Legend Figure C-3 (a) Port 3 Block Diagram (Pins P30 and P31)

R P3nDDR C QD Reset WDDR3 Reset WDR3 R C QDP3n RDR3 RODR3 RPOR3 Internal data bus SCI module Serial receive data enable Serial receive data WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n = 2 or 3 Notes: 1. Output enable signal 2. Open drain control signal : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR P3nDR Reset WODR3 R C QD P3nODR Legend Figure C-3 (b) Port 3 Block Diagram (Pins P32 and P33)

R P3nDDR C QD Reset WDDR3 Reset WDR3 R C QD P3n RDR3 RODR3 RPOR3 Internal data bus SCI module Serial clock output enable Serial clock output Serial clock input enable Serial clock input WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n = 4 or 5 Notes: 1. Priority order: Serial clock input > serial clock output > DR output 2. Output enable signal 3. Open drain control signal : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR P3nDR Reset WODR3 R C QD P3nODR Legend Figure C-3 (c) Port 3 Block Diagram (Pins P34 and P35)

C.4 Port 4 Block Diagram P4n RPOR4 Internal data bus A/D converter module Analog input RPOR4 n = 0 to 5 : Read port 4 Figure C-4 (a) Port 4 Block Diagram (Pins P40 to P45) P4n RPOR4 Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output RPOR4 n = 6 or 7 : Read port 4 Figure C-4 (b) Port 4 Block Diagram (Pins P46 and P47)

C.5 Port 5 Block Diagram R P5nDDR C QD Reset WDDR5 Reset WDR5 R C QDP5n RDR5 RPOR5 Internal data bus WDDR5 WDR5 RDR5 RPOR5 n = 0 to 2 : Write to P5DDR : Write to P5DR : Read P5DR : Read port 5 P5nDR Legend Figure C-5 (a) Port 5 Block Diagram (Pins P50 to P52)

R P53DDR C QD Reset WDDR5 Reset WDR5 R C QDP53 RDR5 RPOR5 Internal data bus A/D converter A/D converter external trigger input WDDR5 WDR5 RDR5 RPOR5 Legend : Write to P5DDR : Write to P5DR : Read P5DR : Read port 5 P53DR Figure C-5 (b) Port 5 Block Diagram (Pin P53)

C.6 Port 6 Block Diagram R P60DDR C QD Reset WDDR6 Mode 1/2*/3*/7* Mode 4/5/6* Reset WDR6 R P60DR C QDP60 RDR6 RPOR6 Internal data bus DMA controller Bus controller Chip select DMA request input WDDR6 WDR6 RDR6 RPOR6 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 Legend Figure C-6 (a) Port 6 Block Diagram (Pin P60)

R P61DDR C QD Reset WDDR6 Mode 1/2*/3*/7* Mode 4/5/6* Reset WDR6 R P61DR C QDP61 RDR6 RPOR6 Internal data bus Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end WDDR6 WDR6 RDR6 RPOR6 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 Legend Figure C-6 (b) Port 6 Block Diagram (Pin P61)

R P62DDR C QD Reset WDDR6 Reset WDR6 R P62DR C QDP62 RDR6 RPOR6 Internal data bus DMA controller DMA request input WDDR6 WDR6 RDR6 RPOR6 : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 Legend Figure C-6 (c) Port 6 Block Diagram (Pin P62)

R P63DDR C QD Reset WDDR6 Reset WDR6 R C QDP63 RDR6 RPOR6 Internal data bus DMA controller DMA transfer end enable DMA transfer end WDDR6 WDR6 RDR6 RPOR6 : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 P63DR Legend Figure C-6 (d) Port 6 Block Diagram (Pin P63)

R P6nDDR C QD Reset WDDR6 Reset WDR6 R P6nDR C QDP6n RDR6 RPOR6 Internal data bus Interrupt controller IRQ interrupt input WDDR6 WDR6 RDR6 RPOR6 n = 4 or 5 : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 Legend Figure C-6 (e) Port 6 Block Diagram (Pins P64 and P65)

R P6nDDR C QD Reset WDDR6 Mode 1/2*/3*/7* Mode 4/5/6* Reset WDR6 R P6nDR C QDP6n RDR6 RPOR6 Internal data bus Interrupt controller Bus controller Chip select IRQ interrupt input WDDR6 WDR6 RDR6 RPOR6 n = 6 or 7 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 Legend Figure C-6 (f) Port 6 Block Diagram (Pins P66 and P67)

C.7 Port A Block Diagram R PAnPCR C QD Reset WPCRA Reset WDRA R C QD PA n RDRA RODRA RPORA Internal data bus Internal address bus WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA n = 0 to 3 : Write to PADDR : Write to PADR : Write to PAODR : Write to PAPCR : Read PADR : Read port A : Read PAODR : Read PAPCR PAnDR Reset WDDRA R Mode 4/5*3 S C QD PAnDDR Reset WODRA RPCRA R C QD PAnODR Mode 1/2/3/6/7 Mode 4/5 Notes: 1. Output enable signal 2. Open drain control signal 3. Set priority Legend H8S/2351 Figure C-7 (a-1) H8S/2351 Port A Block Diagram (Pins PA0 to PA3)

R C QD PA n RDRA RPORA Internal data bus Internal address bus WDDRA WDRA RDRA RPORA n = 0 to 3 Notes: 1. Output enable signal 2. Set priority : Write to PADDR : Write to PADR : Read PADR : Read port A PAnDR Reset WDDRA R Mode 4/5*2 S C QD PAnDDR Mode 1 Mode 4/5 Legend H8S/2350 Figure C-7 (a-2) H8S/2350 Port A Block Diagram (Pins PA0 to PA3)

R PA4PCR C QD Reset WPCRA Reset WDRA R C QD PA 4 RDRA RODRA RPORA Internal data bus Internal address bus WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA : Write to PADDR : Write to PADR : Write to PAODR : Write to PAPCR : Read PADR : Read port A : Read PAODR : Read PAPCR PA4DR Reset WDDRA R Mode 4/5*3 S C QD PA4DDR Reset WODRA RPCRA R C QD PA4ODR Mode 1/2/3/6/7 Mode 4/5 Interrupt controller IRQ interrupt input Notes: 1. Output enable signal 2. Open drain control signal 3. Set priority Legend H8S/2351 Figure C-7 (b-1) H8S/2351 Port A Block Diagram (Pin PA4)

R C QD PA 4 RDRA RPORA Internal data bus Internal address bus WDDRA WDRA RDRA RPORA Notes: 1. Output enable signal 2. Set priority : Write to PADDR : Write to PADR : Read PADR : Read port A PA4DR Reset WDDRA R Mode 4/5*2 S C QD PA4DDR Mode 1 Mode 4/5 Interrupt controller IRQ interrupt input Legend H8S/2350 Figure C-7 (b-2) H8S/2350 Port A Block Diagram (Pin PA4)

R PAnPCR C QD Reset WPCRA Reset WDRA R C QD PA n RDRA RODRA RPORA Internal data bus Internal address bus WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA n = 5 to 7 : Write to PADDR : Write to PADR : Write to PAODR : Write to PAPCR : Read PADR : Read port A : Read PAODR : Read PAPCR PAnDR WDDRA C QD PAnDDR Reset WODRA RPCRA R C QD PAnODR Mode 1/2/3/6/7 Mode 4/5 Interrupt controller IRQ interrupt input Reset R Notes: 1. Output enable signal 2. Open drain control signal Legend H8S/2351 Figure C-7 (c-1) H8S/2351 Port A Block Diagram (Pins PA5 to PA7)

R C QD PA n RDRA RPORA Internal data bus Internal address bus WDDRA WDRA RDRA RPORA n = 5 to 7 Note: * Output enable signal : Write to PADDR : Write to PADR : Read PADR : Read port A PAnDR WDDRA C QD PAnDDR Mode 1 Mode 4/5 Interrupt controller IRQ interrupt input Reset R Legend H8S/2350 Figure C-7 (c-2) H8S/2350 Port A Block Diagram (Pins PA5 to PA7)

C.8 Port B Block Diagram R PBnPCR C QD Reset WPCRB Reset WDRB R C QD PB n RDRB RPORB Internal data bus Internal address bus WDDRB WDRB WPCRB RDRB RPORB RPCRB n = 0 to 7 Note: * Set priority : Write to PBDDR : Write to PBDR : Write to PBPCR : Read PBDR : Read port B : Read PBPCR PBnDR Reset WDDRB R Mode 1/4/5* S C QD PBnDDR RPCRB Mode 3/7 Mode 1/2/4/5/6 Legend H8S/2351 Figure C-8 (a) H8S/2351 Port B Block Diagram (Pin PBn)

n = 0 to 7 Mode 1/4/5 Mode 1/4/5 H8S/2350 Figure C-8 (b) H8S/2350 Port B Block Diagram (Pin PBn)

C.9 Port C Block Diagram R PCnPCR C QD Reset WPCRC Reset WDRC R C QD PC n RDRC RPORC PCnDR Reset WDDRC R Mode 1/4/5* S C QD PCnDDR RPCRC Mode 3/7 Mode 1/2/4/5/6 Internal data bus Internal address bus WDDRC WDRC WPCRC RDRC RPORC RPCRC n = 0 to 7 Note: * Set priority : Write to PCDDR : Write to PCDR : Write to PCPCR : Read PCDR : Read port C : Read PCPCR Legend H8S/2351 Figure C-9 (a) H8S/2351 Port C Block Diagram (Pin PCn)

n = 0 to 7 Mode 1/4/5 Mode 1/4/5 H8S/2350 Figure C-9 (b) H8S/2350 Port C Block Diagram (Pin PCn)

C.10 Port D Block Diagram R PDnPCR C QD Reset WPCRD Reset WDRD R C QD PD n RDRD RPORD Internal upper data bus Internal lower data bus External address upper write WDDRD WDRD WPCRD RDRD RPORD RPCRD n = 0 to 7 : Write to PDDDR : Write to PDDR : Write to PDPCR : Read PDDR : Read port D : Read PDPCR PDnDR WDDRD C QD PDnDDR RPCRD Mode 3/7 Mode 1/2/4/5/6 External address write Reset R External address upper read External address lower read External address lower write Legend H8S/2351 Figure C-10 (a) H8S/2351 Port D Block Diagram (Pin PDn)

n = 0 to 7 Mode 1/4/5 External address write External address upper read External address lower read External address lower write H8S/2350 Figure C-10 (b) H8S/2350 Port D Block Diagram (Pin PDn)

C.11 Port E Block Diagram R PEnPCR C QD Reset WPCRE Reset WDRE R C QD PE n RDRE RPORE PEnDR WDDRE C QD PEnDDR RPCRE Reset R Internal upper data bus Internal lower data bus Mode 3/7 Mode 1/2/4/5/6 External address write External address lower read WDDRE WDRE WPCRE RDRE RPORE RPCRE n = 0 to 7 : Write to PEDDR : Write to PEDR : Write to PEPCR : Read PEDR : Read port E : Read PEPCR Legend H8S/2351 Figure C-11 (a) H8S/2351 Port E Block Diagram (Pin PEn)

R C QD PE n RDRE RPORE PEnDR WDDRE C QD PEnDDR Reset R Internal upper data bus Internal lower data bus 8-bit bus mode 8-bit bus mode External address write External address lower read WDDRE WDRE RDRE RPORE n = 0 to 7 : Write to PEDDR : Write to PEDR : Read PEDR : Read port E Legend H8S/2350 Figure C-11 (b) H8S/2350 Port E Block Diagram (Pin PEn)

C.12 Port F Block Diagram R PF0DDR C QD Reset WDDRF Reset WDRF R C QDPF 0 RDRF RPORF Internal data bus Bus request input WDDRF WDRF RDRF RPORF Note: * Modes 2 and 6 only apply to the H8S/2351. : Write to PFDDR : Write to PFDR : Read PFDR : Read port F PF0DR Bus controller BRLE bit Mode 1/2*/4/5/6* Legend Figure C-12 (a) Port F Block Diagram (Pin PF0)

R PF1DDR C QD Reset WDDRF Mode 1/2*/4/5/6* Reset WDRF R PF1DR C QDPF 1 RDRF RPORF Internal data bus Bus controller BRLE output Bus request acknowledge output WDDRF WDRF RDRF RPORF Note: * Modes 2 and 6 only apply to the H8S/2351. : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Legend Figure C-12 (b) Port F Block Diagram (Pin PF1)

R PF2DDR C QD Reset WDDRF Mode 4/5/6* Mode 1/2*/4/5/6* Reset WDRF R PF2DR C QDPF 2 RDRF RPORF Internal data bus Bus request output enable Bus request output Wait input LCAS output LCAS output enable WDDRF WDRF RDRF RPORF Note: * Modes 2 and 6 only apply to the H8S/2351. : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Bus controller Wait enable Mode 1/2*/4/5/6* Legend Figure C-12 (c) Port F Block Diagram (Pin PF2)

R PF3DDR C QD Reset WDDRF Reset WDRF R PF3DR C QDPF 3 RDRF RPORF Internal data bus Bus controller LWR output WDDRF WDRF RDRF RPORF Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode H8S/2350: 8-bit bus mode : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Legend Figure C-12 (d) Port F Block Diagram (Pin PF3)

R PF4DDR C QD Reset WDDRF Reset WDRF R PF4DR C QDPF 4 RDRF RPORF Internal data bus Bus controller HWR output WDDRF WDRF RDRF RPORF Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode H8S/2350: 8-bit bus mode : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Legend Figure C-12 (e) Port F Block Diagram (Pin PF4)

R PF5DDR C QD Reset WDDRF Reset WDRF R PF5DR C QDPF 5 RDRF RPORF Internal data bus Bus controller RD output WDDRF WDRF RDRF RPORF Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode H8S/2350: 8-bit bus mode : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Legend Figure C-12 (f) Port F Block Diagram (Pin PF5)

R PF6DDR C QD Reset WDDRF Reset WDRF R PF6DR C QDPF 6 RDRF RPORF Internal data bus Bus controller AS output WDDRF WDRF RDRF RPORF Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode H8S/2350: 8-bit bus mode : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Legend Figure C-12 (g) Port F Block Diagram (Pin PF6)

R PF7DR C QDPF 7 RDRF RPORF Internal data bus ø WDDRF WDRF RDRF RPORF Notes: 1. Set priority 2. Modes 2 and 6 only apply to the H8S/2351. Reset R Mode 1/2*2/4/5/6*2 S*1 C Q PF7DDR : Write to PFDDR : Write to PFDR : Read PFDR : Read port F D Legend Figure C-12 (h) Port F Block Diagram (Pin PF7)

C.13 Port G Block Diagram R PG0DDR C QD Reset WDDRG Mode 4/5/6* Reset WDRG R PG0DR C QDPG 0 RDRG RPORG Internal data bus Bus controller CAS enable CAS output WDDRG WDRG RDRG RPORG Note: Mode 6 only applies to the H8S/2351. : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Legend Figure C-13 (a) Port G Block Diagram (Pin PG0)

R PGnDDR C QD Reset WDDRG Reset WDRG R PGnDR C QDPG n RDRG RPORG Internal data bus Bus controller Chip select WDDRG WDRG RDRG RPORG n = 1, 2, 3 Note: Modes 2, 3, 6, and 7 only apply to the H8S/2351. : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Mode 1/2*/3*/7* Mode 4/5/6* Legend Figure C-13 (b) Port G Block Diagram (Pins PG1 to PG3)

R PG4DR C QDPG 4 RDRG RPORG Internal data bus Bus controller Chip select WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Mode 3/7 Mode 1/2/4/5/6 Reset R Mode 1/4/5 Mode 2/3/6/7 S C PG4DDR QD Legend H8S/2351 Figure C-13 (c-1) H8S/2351 Port G Block Diagram (Pin PG4)

R PG4DR C QDPG 4 RDRG RPORG Internal data bus Bus controller Chip select WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Mode 1/4/5 Reset R Mode 1/4/5 S C PG4DDR QD Legend H8S/2350 Figure C-13 (c-2) H8S/2350 Port G Block Diagram (Pin PG4)

D.1 Port States in Each Mode [H8S/2351] Table D-1 I/O Port States in Each Processing State (H8S/2351) Port Name Pin Name MCU Operating Mode Power- On Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode Port 1 1 to 7 T kept T kept kept I/O port Port 2 1 to 7 T kept T kept kept I/O port Port 3 1 to 7 T kept T kept kept I/O port Port 4 1 to 7 T T T T T Input port Port 5 1 to 7 T kept T kept kept I/O port P65 to P62 1 to 7 T kept T kept kept I/O port P67/CS7 P66/CS6 P61/CS5 P60/CS4 1 to 3, 7 4 to 6 T T kept kept T T kept [DDR · OPE = 0] T [DDR · OPE = 1] H kept T I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4 Port A 1 to 3, 7 T kept T kept kept I/O port 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T Address output

6 T kept T [DDR · OPE = 0]

T [DDR · OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output Port B 1, 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T Address output 2, 6 T kept T [DDR · OPE = 0] T [DDR · OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output 3, 7 T kept T kept kept I/O port

Table D-1 I/O Port States in Each Processing State (H8S/2351) (cont) Port Name Pin Name MCU Operating Mode Power- On Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode Port C 1, 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T Address output 2, 6 T kept T [DDR · OPE = 0] T [DDR · OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output 3, 7 T kept T kept kept I/O port Port D 1, 2, 4 to 6 T T * T T T Data bus 3, 7 T kept T kept kept I/O port Port E 1, 2, 4 to 6 8 bit bus T kept T kept kept I/O port 16 bit bus TT * T T T Data bus 3, 7 T kept T kept kept I/O port PF 7/ø 1, 2, 4 to 6 Clock output [DDR = 0] T [DDR = 1] Clock output T [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output 3, 7 T kept T [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output PF 6/AS PF 5/RD PF 4/HWR PF 3/LWR 1, 2, 4 to 6 H H * T [OPE = 0] T [OPE = 1] H T AS, RD, HWR, LWR 3, 7 T kept T kept kept I/O port

Table D-1 I/O Port States in Each Processing State (H8S/2351) (cont) Port Name Pin Name MCU Operating Mode Power- On Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode PF 2/LCAS/ WAIT/ BREQO 1, 2, 4 to 6 T [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] H * T [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] kept [WAITE = 1] T [LCASE = 1, OPE = 0] T [LCASE = 1, OPE = 1] LCAS [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] T [BREQOE + WAITE + LCASE= 0] I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT [LCASE = 1] LCAS 3, 7 T kept T kept kept I/O port PF 1/BACK 1, 2, 4 to 6 T [BRLE = 0] kept [BRLE = 1] BACK T [BRLE = 0] kept [BRLE = 1] H L [BRLE = 0] I/O port [BRLE = 1] BACK 3, 7 T kept T kept kept I/O port PF 0/BREQ 1, 2, 4 to 6 T [BRLE = 0] kept [BRLE = 1] BREQ T [BRLE = 0] kept [BRLE = 1] T T [BRLE = 0] I/O port [BRLE = 1] BREQ 3, 7 T kept T kept kept I/O port PG 4/CS0 1, 4, 5 H [DDR = 0] T [DDR · OPE = 0] T [DDR = 0] 2, 6 T T [DDR = 1] H * T [DDR · OPE = 1] H Input port [DDR = 1] CS0 3, 7 T kept T kept kept I/O port PG 3/CS1 PG 2/CS2 PG 1/CS3 1 to 3, 7 4 to 6 T T kept [DDR = 0] T [DDR = 1] H * T T kept [DDR · OPE = 0] T [DDR · OPE = 1] H kept T I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3

D.2 Port States in Each Mode [H8S/2350] Table D-2 I/O Port States in Each Processing State (H8S/2350) Port Name Pin Name MCU Operating Mode Power- On Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode Port 1 1, 4, 5 T kept T kept kept I/O port Port 2 1, 4, 5 T kept T kept kept I/O port Port 3 1, 4, 5 T kept T kept kept I/O port Port 4 1, 4, 5 T T T T T Input port Port 5 1, 4, 5 T kept T kept kept I/O port P65 to P62 1, 4, 5 T kept T kept kept I/O port P67/CS7 P66/CS6 P61/CS5 P60/CS4 4, 5 T T kept kept T T kept [DDR · OPE = 0] T [DDR · OPE = 1] H kept T I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4 Port A 1 T kept T kept kept I/O port 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T Address output Port B 1, 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T Address output Port C 1, 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T Address output Port D 1, 5 T T * T T T Data bus Port E 1, 4, 5 8 bit bus T kept T kept kept I/O port 16 bit bus TT * T T T Data bus PF 7/ø 1, 4, 5 Clock output [DDR = 0] T [DDR = 1] Clock output T [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output

Table D-2 I/O Port States in Each Processing State (H8S/2350) (cont) Port Name Pin Name MCU Operating Mode Power- On Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode PF 6/AS PF 5/RD PF 4/HWR PF 3/LWR 1, 4, 5 H H * T [OPE = 0] T [OPE = 1] H T AS, RD, HWR, LWR PF 2/LCAS/ WAIT/ BREQO 1, 4, 5 T [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] H * T [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] kept [WAITE = 1] T [LCASE = 1, OPE = 0] T [LCASE = 1, OPE = 1] LCAS [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] T [BREQOE + WAITE + LCASE= 0] I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT [LCASE = 1] LCAS PF 1/BACK 1, 4, 5 T [BRLE = 0] kept [BRLE = 1] BACK T [BRLE = 0] kept [BRLE = 1] H L [BRLE = 0] I/O port [BRLE = 1] BACK PF 0/BREQ 1, 2, 4 to 6 T [BRLE = 0] kept [BRLE = 1] BREQ T [BRLE = 0] kept [BRLE = 1] T T [BRLE = 0] I/O port [BRLE = 1] BREQ PG 4/CS0 1, 4, 5 H [DDR = 0] T [DDR = 1] H * T [DDR · OPE = 0] T [DDR · OPE = 1] H T [DDR = 0] Input port [DDR = 1] CS0 PG 3/CS1 PG 2/CS2 PG 1/CS3 4, 5 T T kept [DDR = 0] T [DDR = 1] H * T T kept [DDR · OPE = 0] T [DDR · OPE = 1] H kept T I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3

Table D-2 I/O Port States in Each Processing State (H8S/2350) (cont) Port Name Pin Name MCU Operating Mode Power- On Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode PG 0/CAS 1 to 3, 7 T kept T kept kept I/O port 4 to 6 T [DRAME = 0] kept [DRAME = 1] H * T [DRAME = 0] kept [OPE = 0] T [DRAME · OPE= 1] CAS T [DRAME = 0] Input port [DRAME = 1] CAS Legend: H : High level L : Low level T : High impedance kept : Input port becomes high-impedance, output port retains state DDR : Data direction register OPE : Output port enable WAITE : Wait input enable BRLE : Bus release enable BREQOE : BREQO pin enable DRAME : DRAM space setting LCASE: DRAM space setting, CW2 = LCASS = 0 Note: * Indicates the state after completion of the executing bus cycle.

Appendix E Pin States at Power-On Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below. After reset release, power-on reset exception handling is started. Note: * “Settle” refers to the pin states in a power-on reset in each MCU operating mode. E.1 When Pins Settle from an Indeterminate State at Power-On When the NMI pin level changes from low to high after powering on, the chip goes to the power- on reset state after a high level is detected at the NMI pin. While the chip detects a low level at the NMI pin, the manual reset state is established. The pin states are indeterminate during this interval. (Ports may output an internally determined value after powering on.) The NMI setup time (t NMIS ) is necessary for the chip to detect a high level at the NMI pin. VCC STBY NMI RES φ Power-on reset tOSC1 NMI = Low → NMI = High RES = Low Manual reset Figure E-1 When Pins Settle from an Indeterminate State at Power-On

E.2 When Pins Settle from the High-Impedance State at Power-On When the STBY pin level changes from low to high after powering on, the chip goes to the power- on reset state after a high level is detected at the STBY pin. While the chip detects a low level at the STBY pin, it is in the hardware standby mode. During this interval, the pins are in the high- impedance state. After detecting a high level at the STBY pin, the chip starts oscillation. VCC STBY NMI RES φ Power-on reset tOSC1 NMI = High RES = Low T1 Confirm t1min and tNMIS . Hardware standby mode Figure E-2 When Pins Settle from the High-Impedance State at Power-On

Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY RES t2≥0nst1≥10tcyc Figure F-1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY RES tOSC tNMIRH t≥100ns NMI Figure F-2 Timing of Recovery from Hardware Standby Mode

Appendix G Product Code Lineup Table G-1 H8S/2350 Series Product Code Lineup Product Type Product Code Mark Code Package (Hitachi Package Code) H8S/2351 Mask ROM HD6432351 HD6432351TE 120-pin TFP (TFP-120) HD6432351F 128-pin FP (FP-128) H8S/2350 Mask ROM HD6412350 HD6412350TE 120-pin TFP (TFP-120) HD6412350F 128-pin FP (FP-128)

Appendix H Package Dimensions Figures H-1 and H-2 show the TFP-120 and FP-128 package dimensions of the H8S/2350 Series. 16.0 – 0.2 0.07 0.10 0.5 – 0.1 16.0 – 0.2 0.40.10 – 0.10

1.20 Max

0.17 – 0.05 0° – 8° 90 61 13 0 120 31 M0.17 – 0.05 1.0 1.001.2 0.15 – 0.04 0.15 – 0.04 Unit: mm Dimension including the plating thickness Base material dimension Figure H-1 TFP-120 Package Dimensions

0.10M 16.0 – 0.2 128 0.5 0.10 1.0 0.5 – 0.2

3.15 Max

0° – 10° 22.0 – 0.2 102 103 0.22 – 0.05 0.17 – 0.05 2.700.10+0.15 –0.10 0.75 0.75 0.20 – 0.04 0.15 – 0.04 Unit: mm Dimension including the plating thickness Base material dimension Figure H-2 FP-128 Package Dimensions

H8S/2350 Series Hardware Manual Publication Date: 1st Edition, May 1997 2nd Edition, December 1997 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.

Product Information

HD6412350 specifications and overview.

Summary

The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Description

The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Source title HD6412350 Datasheet(PDF) - Renesas Technology Corp

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