HD6412324S

H8S-2329 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 1302

Technical content

Datasheet sections

• 1.1 Overview
• 1.2 Block Diagram
• 1.3 Pin Description
• 1.3.1 Pin Arrangement
• 1.3.2 Pin Functions in Each Operating Mode
• 1.3.3 Pin Functions
• 2.1 Overview
• 2.1.1 Features
• 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
• 2.1.3 Differences from H8/300 CPU
• 2.1.4 Differences from H8/300H CPU
• 2.2 CPU Operating Modes
• 2.3 Address Space
• 2.4 Register Configuration
• 2.4.1 Overview
• 2.4.2 General Registers
• 2.4.3 Control Registers
• 2.4.4 Initial Register Values
• 2.5 Data Formats
• 2.5.1 General Register Data Formats
• 2.5.2 Memory Data Formats
• 2.6 Instruction Set
• 2.6.1 Overview
• 2.6.2 Instructions and Addressing Modes
• 2.6.3 Table of Instructions Classified by Function
• 2.6.4 Basic Instruction Formats
• 2.7 Addressing Modes and Effective Address Calculation
• 2.7.1 Addressing Mode
• 2.7.2 Effective Address Calculation
• 2.8 Processing States
• 2.8.1 Overview
• 2.8.2 Reset State
• 2.8.3 Exception-Handling State
• 2.8.4 Program Execution State

Revision Date: Sep. 27, 2007 H8S/2329 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series H8S/2329 HD64F2329B H8S/2324S HD6412324S HD64F2329E H8S/2323 HD6432323 H8S/2328 HD6432328 H8S/2322R HD6412322R HD64F2328B H8S/2321 HD6412321 H8S/2327 HD6432327 H8S/2320 HD6412320 H8S/2326 HD64F2326 Rev.6.00 REJ09B0220-0600

Rev.6.00 Sep. 27, 2007 Page ii of xxx REJ09B0220-0600 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

Rev.6.00 Sep. 27, 2007 Page iii of xxx REJ09B0220-0600 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.

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Rev.6.00 Sep. 27, 2007 Page v of xxx REJ09B0220-0600 Preface This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a 16-bit timer pulse unit (TPU), a watchdog timer (WDT), a serial communication interface (SCI), DMA controller (DMAC), a D/A converter, an A/D converter, and I/O ports as on-chip supporting modules. This LSI is suitable for use as an embedded processor for high-level control systems. Its on-chip ROM are flash memory (F-ZTAT™*) and mask ROM that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2329 Group, H8S/2328 Group in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2329 Group, H8S/2328 Group to the above audience. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set. Notes on reading this manual:

• In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual.
• In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in appendix B, Internal I/O Registers. Example: Bit order: The MSB is on the left and the LSB is on the right. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. (http://www.renesas.com/eng/)

Rev.6.00 Sep. 27, 2007 Page vi of xxx REJ09B0220-0600 H8S/2329 Group, H8S/2328 Group Manuals: Document Title Document No. H8S/2329 Group, H8S/2328 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Software Manual REJ09B0139 User’s Manuals for Development Tools: Document Title Document No. H8S, H8S/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor Compiler Package Ver.6.01 User's Manual REJ10B0161 H8S, H8S/300 Series Simulator/Debugger (for Windows) User’s Manual ADE-702-037 High-performance Embedded Workshop (for Windows 95/98 and Windows NT 4.0) User’s Manual ADE-702-201 Application Notes: Document Title Document No. H8S Series Technical Q & A Application Note REJ05B0397

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1.3.1 Pin Arrangement

Figure 1.3 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (TFP- 120: Top View)

10 Figure amended

WDTOVF (FWE )* P20/PO0/TIOCA3 Note amended Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the F- ZTAT versions. Figure 1.4 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (FP- 128B: Top View)

11 Figure amended

WDTOVF (FWE )* P20/PO0/TIOCA3 Note amended Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the F- ZTAT versions. Figure 1.7 HD64F2329B Pin Arrangement (TFP- 120: Top View)

14 Figure added

Rev.6.00 Sep. 27, 2007 Page viii of xxx REJ09B0220-0600 Item Page Revision (See Manual for Details) Figure 1.8 HD64F2329B Pin Arrangement (FP- 128B: Top View)

15 Figure added

1.3.3 Pin Functions

Table 1.3 Pin Functions

26 Table amended

0 0 1 — 1 0 Mode 2 *1

1 Mode 3 *1

1 0 0 Mode 4 *2

1 Mode 5 *2

1 Mode 7

6.3.5 Chip Select

169 Description amended

Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin and either the CS167 enable bit (CS167E) or the CS25 enable bit (CS25E). In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS0 to CS7.

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14.2.8 Bit Rate

Register (BRR) Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)

618 Table amended

φ = 25 MHz Bit Rate (bits/s) n N Error (%) 110 3 110 –0.02 150 3 80 0 . 4 7 300 2 162 –0.15 600 2 80 0 . 4 7 1200 1 162 –0.15 2400 1 80 0.47 4800 0 162 –0.15 9600 0 80 0 . 4 7 19200 0 40 –0.76 31250 0 24 1.00 38400 0 19 1.73

19.4.1 Features 740 Description amended

The flash memory can be reprogrammed minimum 100 times.

19.13.1 Features 791 Description amended

The flash memory can be reprogrammed minimum 100 times.

19.22.1 Features 849 Description amended

The flash memory can be reprogrammed minimum 100 times.

22.2.6 Flash Memory

Table 22.22 Flash Memory Characteristics

977 Table amended

Item Symbol Min Typ Max Unit Test Conditions Programming time*1 *2 *4 tP — 10 200 ms/ 128 bytes Erase time*1 *3 *6 tE — 50 1000 ms/block Rewrite times N WEC 100*7 10000*8 — Times Data hold time tDRP*9 10 — — year Programming Wait time after SWE bit setting *1 x 1 — — s Wait time after PSU bit setting*1 y 50 — — s

Rev.6.00 Sep. 27, 2007 Page x of xxx REJ09B0220-0600 Item Page Revision (See Manual for Details) Table 22.22 Flash Memory Characteristics

978 Notes added

1. The minimum number of rewrites after which all characteristics are guaranteed. (The guaranteed range is one to min. rewrites.) 8. Reference value at 25°C. (This is a general indication of the number of rewrites possible under normal conditions.) 9. The data retention characteristics within the specified range, including min. rewrites. Appendix F Package Dimensions Figure F.1 TFP-120 Package Dimensions

1267 Figure replaced

Figure F.2 FP-128B Package Dimensions

1268 Figure replaced

All trademarks and registered trademarks are the property of their respective owners.

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3.1.2 Operating Mode Selection (Mask ROM and ROMless Versions,

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7.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles,

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19.25.1 Program Mode (n = 1 for addresses H'000000 to H'03FFFF

19.25.2 Program-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and

19.25.3 Erase Mode (n = 1 for addresses H'000000 to H'03FFFF

19.25.4 Erase-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and

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22.1 Electrical Characteristics of Mask ROM Version (H8S/2328, H8S/2327, H8S/2323)

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22.2 Electrical Characteristics of F-ZTAT (H8S/2329B F-ZTAT, H8S/2329E F-ZTAT,

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Rev.6.00 Sep. 27, 2007 Page 1 of 1268 REJ09B0220-0600 Section 1 Overview

1.1 Overview

The H8S/2329 Group and H8S/2328 Group are series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip supporting functions required for system configuration include DMA controller (DMAC)*1 and data transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM and other kinds of memory. Single-power-supply flash memory (F-ZTAT™ *2) and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The features of the H8S/2329 Group is shown in table 1.1. Notes: 1. The DMAC is not supported in the H8S/2321. 2. F-ZTAT is a trademark of Renesas Technology Corp.

Rev.6.00 Sep. 27, 2007 Page 2 of 1268 REJ09B0220-0600 Table 1.1 Overview Item Specification CPU • General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

• High-speed operation suitable for realtime control ⎯ Maximum clock rate: 25 MHz ⎯ High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 40 ns (at 25-MHz operation) 16 × 16-bit register-register multiply: 800 ns (at 25-MHz operation) 32 ÷ 16-bit register-register divide: 800 ns (at 25-MHz operation)
• Instruction set suitable for high-speed operation ⎯ Sixty-five basic instructions ⎯ 8/16/32-bit move/arithmetic and logic instructions ⎯ Unsigned/signed multiply and divide instructions ⎯ Powerful bit-manipulation instructions
• CPU operating mode ⎯ Advanced mode: 16-Mbyte address space Bus controller • Address space divided into 8 areas, with bus specifications settable independently for each area
• Chip select output possible for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• Maximum 8-Mbyte DRAM * directly connectable (or use of interval timer possible)
• External bus release function DMA controller* (DMAC)
• Choice of short address mode or full address mode
• 4 channels in short address mode
• 2 channels in full address mode
• Transfer possible in repeat mode, block transfer mode, etc.
• Single address mode transfer possible
• Can be activated by internal interrupt

Rev.6.00 Sep. 27, 2007 Page 3 of 1268 REJ09B0220-0600 Item Specification Data transfer controller (DTC)

• Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC 16-bit timer-pulse unit (TPU)
• 6-channel 16-bit timer
• Pulse I/O processing capability for up to 16 pins
• Automatic 2-phase encoder count capability Programmable pulse generator (PPG)
• Maximum 16-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or inverse output setting possible 8-bit timer, 2 channels
• 8-bit up-counter (external event count capability)
• Two time constant registers
• Two-channel connection possible Watchdog timer (WDT)
• Watchdog timer or interval timer selectable Serial communication interface (SCI), 3 channels
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function A/D converter • Resolution: 10 bits
• Input: 8 channel
• High-speed conversion: 6.7 µs minimum conversion time (at 20-MHz operation)
• Single or scan mode selectable
• Sample-and-hold circuit
• A/D conversion can be activated by external trigger or timer trigger D/A converter • Resolution: 8 bits
• Output: 2 channels I/O ports • 86 input/output pins, 9 input pins

Rev.6.00 Sep. 27, 2007 Page 4 of 1268 REJ09B0220-0600 Item Specification Memory • Flash memory, mask ROM

• High-speed static RAM Product Code ROM RAM H8S/2329B, H8S/2329E *1 384 kbytes 32 kbytes H8S/2328 *2, H8S/2328B 256 kbytes 8 kbytes H8S/2327 128 kbytes 8 kbytes H8S/2326 512 kbytes 8 kbytes H8S/2324S — 32 kbytes H8S/2323 32 kbytes 8 kbytes H8S/2322R — 8 kbytes H8S/2321 — 4 kbytes H8S/2320 — 4 kbytes Notes: 1. The on-chip debug function can be used with the E10A emulator (E10A compatible version). However, some function modules and pin functions are unavailable when the on-chip debug function is in use. Refer to figures 1.7 and 1.8, Pin Arrangement. For specifications, refer to the item for the H8S/2329B F-ZTAT. 2. Mask ROM version only. Interrupt controller • 39 external interrupt pins (NMI, IRQ0 to IRQ7)
• 52 internal interrupt sources
• Eight priority levels settable Power-down state • Medium-speed mode
• Sleep mode
• Module stop mode
• Software standby mode
• Hardware standby mode
• Variable clock division ratio

Rev.6.00 Sep. 27, 2007 Page 5 of 1268 REJ09B0220-0600 Item Specification Operating modes • Eight MCU operating modes (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) External Data Bus Mode CPU Operating Mode

Description

4 Advanced Disabled 16 bits 16 bits

expansion mode 8 bits 16 bits

6 On-chip ROM enabled

7 Single-chip mode — —

10 Advanced Boot mode Enabled 8 bits 16 bits

11 — —

14 Advanced User program mode Enabled 8 bits 16 bits

15 — —

Rev.6.00 Sep. 27, 2007 Page 6 of 1268 REJ09B0220-0600 Item Specification Operating modes • Four MCU operating modes (ROMless, mask ROM versions, H8S/2329B F-ZTAT) External Data Bus Mode CPU Operating Mode 2 *1 3 *1 4 *2 Advanced On-chip ROM disabled expansion mode Disabled 16 bits 16 bits 5 *2 On-chip ROM disabled expansion mode Disabled 8 bits 16 bits

7 Single-chip mode Enabled — —

Notes: 1. Boot mode in the H8S/2329B F-ZTAT. See table 19.9, for information on H8S/2329B F-ZTAT user boot modes. See table 19.9, for information on H8S/2329B F-ZTAT user program modes. 2. The ROMless versions can use only modes 4 and 5. Clock pulse generator

• Built-in duty correction circuit

Rev.6.00 Sep. 27, 2007 Page 7 of 1268 REJ09B0220-0600 Item Specification Product lineup Condition A Condition B Operating power supply voltage 2.7 to 3.6 V 3.0 to 3.6 V Operating frequency 2 to 20 MHz 2 to 25 MHz Model HD64F2329B — O HD64F2329E * — O HD6432328 O O HD64F2328B — O HD6432327 O O HD64F2326 — O HD6412324S O O HD6432323 O O HD6412322R O O HD6412321 O O HD6412320 O O O: Products in the current lineup Note: * The on-chip debug function can be used with the E10A emulator (E10A compatible version). However, some function modules and pin functions are unavailable when the on-chip debug function is in use. Refer to figures 1.7 and 1.8, Pin Arrangement. For specifications, refer to the item for the H8S/2329B F-ZTAT. Note: * Not supported in the H8S/2321.

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1.2 Block Diagram

A PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3 /A 11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 P53/ADTRG/IRQ7/WAIT/BREQO P52/SCK2/IRQ6 P51/RxD2/IRQ5 P50/TxD2/IRQ4 P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Vref AVCC AVSS P27/PO7/TIOCB5/TMO1 P26/PO6/TIOCA5/TMO0 P25/PO5/TIOCB4/TMCI1 P24/PO4/TIOCA4/TMRI1 P23/PO3/TIOCD3/TMCI0 P22/PO2/TIOCC3/TMRI0 P21/PO1/TIOCB3 P20/PO0/TIOCA3 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 P67/CS7/IRQ3 P66/CS6/IRQ2 P65/IRQ1 P64/IRQ0 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 P60/DREQ0/CS4 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3 PG0/CAS PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/WAIT/BREQO PF1/BACK PF0/BREQ Notes: 1. The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The EMLE pin applies to the H8S/2329B F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. ROM is not supported in the ROMless versions. Clock pulse generator ROM*2 RAM WDT TPU SCI PPG MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF (FWE, EMLE)*1 NMI Bus controller H8S/2000 CPU DTCInterrupt controller Port E DMAC Internal data bus Internal address bus Port B Port C Port Port Port 4Port 2Port 1 Port Port G Port F Peripheral data bus Peripheral address bus 8-bit timer D/A converter A/D converter Figure 1.1 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Internal Block Diagram

Rev.6.00 Sep. 27, 2007 Page 9 of 1268 REJ09B0220-0600 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port D VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS Port A PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3 / A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 P53/ADTRG/IRQ7/WAIT/BREQO P52/SCK2/IRQ6 P51/RxD2/IRQ5 P50/TxD2/IRQ4 P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Vref AVCC AVSS P27/PO7/TIOCB5/TMO1 P26/PO6/TIOCA5/TMO0 P25/PO5/TIOCB4/TMCI1 P24/PO4/TIOCA4/TMRI1 P23/PO3/TIOCD3/TMCI0 P22/PO2/TIOCC3/TMRI0 P21/PO1/TIOCB3 P20/PO0/TIOCA3 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 P67/CS7/IRQ3 P66/CS6/IRQ2 P65/IRQ1 P64/IRQ0 P63 P62 P61/CS5 P60/CS4 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3 PG0 PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/WAIT/BREQO PF1/BACK PF0/BREQ Clock pulse generator RAM WDT TPU SCI PPG MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF NMI Bus controller H8S/2000 CPU DTCInterrupt controller Port E Internal data bus Internal address bus Port B Port C Port Port Port 4Port 2Port 1 Port Port G Port F Peripheral data bus Peripheral address bus 8-bit timer D/A converter A/D converter Figure 1.2 H8S/2321 Internal Block Diagram

Rev.6.00 Sep. 27, 2007 Page 10 of 1268 REJ09B0220-0600

1.3 Pin Description

PF7/φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF (FWE)* P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 6160 P60/DREQ0/CS4 VSS P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC P64/IRQ0 P65/IRQ1 P52/SCK2/IRQ6 P53/ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/DA0/AN6 P47/DA1/AN7 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 MD0 MD1 MD2 PG0/CAS PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. Figure 1.3 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (TFP-120: Top View)

Rev.6.00 Sep. 27, 2007 Page 11 of 1268 REJ09B0220-0600 PG3/CS1 PG4/CS0 VSS VSSNC VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 P53/ADTRG/IRQ7/WAIT/BREQO P52/SCK2/IRQ6 VSS VSS P51/RxD2/IRQ5 P50/TxD2/IRQ4 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/BREQO PF3/LWR PF4/HWR PF5/RD PF6/AS VCC PF7/φ VSS EXTAL XTAL V CC STBY NMI RES WDTOVF (FWE)* 0/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 VSS VSS P60/DREQ0/CS4 VSS 102 101 100 P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 MD0 MD1 MD2 PG0/CAS PG1/CS3 PG2/CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. Figure 1.4 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (FP-128B: Top View)

Rev.6.00 Sep. 27, 2007 Page 12 of 1268 REJ09B0220-0600 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1 /A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 P51/RxD2/IRQ5 P50/TxD2/IRQ4 PF0/BREQ PF1/BACK PF2/WAIT/BREQO PF3/LWR PF4/HWR PF5/RD PF6/AS VCC PF7/φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63 P62 P61/CS5 6160 P60/CS4 VSS P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC P64/IRQ0 P65/IRQ1 P52/SCK2/IRQ6 P53/ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/DA0/AN6 P47/DA1/AN7 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 MD0 MD1 MD2 PG0 PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Figure 1.5 H8S/2321 Pin Arrangement (TFP-120: Top View)

Rev.6.00 Sep. 27, 2007 Page 13 of 1268 REJ09B0220-0600 PG3/CS1 PG4/CS0 VSS VSSNC VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 P53/ADTRG/IRQ7/WAIT/BREQO P52/SCK2/IRQ6 VSS VSS P51/RxD2/IRQ5 P50/TxD2/IRQ4 PF0/BREQ PF1/BACK PF2/WAIT/BREQO PF3/LWR PF4/HWR PF5/RD PF6/AS VCC PF7/φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63 P62 P61/CS5 VSS VSS P60/CS4 VSS 102 101 100 P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 MD0 MD1 MD2 PG0 PG1/CS3 PG2/CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Figure 1.6 H8S/2321 Pin Arrangement (FP-128B: Top View)

Rev.6.00 Sep. 27, 2007 Page 14 of 1268 REJ09B0220-0600 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1 /A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 P51/RxD2/IRQ5 P50/TxD2/IRQ4 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/BREQO PF3/LWR PF4/HWR PF5/RD PF6/AS VCC PF7/φ VSS EXTAL XTAL VCC STBY NMI RES EMLE P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 6160 P60/DREQ0/CS4 VSS P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC P64/IRQ0 P65/IRQ1 P52/SCK2/IRQ6 P53/ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/DA0/AN6 P47/DA1/AN7 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 MD0 MD1 MD2 PG0/CAS PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Figure 1.7 HD64F2329B Pin Arrangement (TFP-120: Top View)

Rev.6.00 Sep. 27, 2007 Page 15 of 1268 REJ09B0220-0600 PG3/CS1 PG4/CS0 VSS VSSNC VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 P53/ADTRG/IRQ7/WAIT/BREQO P52/SCK2/IRQ6 VSS VSS P51/RxD2/IRQ5 P50/TxD2/IRQ4 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/BREQO PF3/LWR PF4/HWR PF5/RD PF6/AS VCC PF7/φ VSS EXTAL XTAL V CC STBY NMI RES EMLE 0/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63/TEND1 P62/DREQ1 P61/TEND0/CS5 VSS VSS P60/DREQ0/CS4 VSS 102 101 100 P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 MD0 MD1 MD2 PG0/CAS PG1/CS3 PG2/CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Figure 1.8 HD64F2329B Pin Arrangement (FP-128B: Top View)

Rev.6.00 Sep. 27, 2007 Page 16 of 1268 REJ09B0220-0600 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1 /A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 P51/RxD2/IRQ5 P50/TxD2/IRQ4 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/BREQO PF3/LWR PF4/HWR PF5/RD PF6/AS VCC PF7/φ VSS EXTAL XTAL V CC STBY NMI RES EMLE* 0/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63/TEND1/TDO * P62/DREQ1/TDI * P61/TEND0/CS5/TCK * 6160 P60/DREQ0/CS4/TMS * VSS P35/SCK1 P34/SCK0*/TRST* P33/RxD1 P32/RxD0* P31/TxD1 P30/TxD0* VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC P64/IRQ0 P65/IRQ1 P52/SCK2/IRQ6 P53/ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/DA0/AN6 P47/DA1/AN7 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 MD0 MD1 MD2 PG0/CAS PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Note: * If an E10A emulator is used, the TDO, TDI, TDK, TMS, and TRST pins are used exclusively for the H-UDI and the functions and function modules associated with these pins are not available. SCI channel 0 is not available. Also, the watchdog timer continues to operate during break states and, if the settings specify that an internal reset is to be performed, a reset is generated if an overflow occurs. Refer to the E10A Emulator User's Manual for E10A emulator connection examples. E10A compatible version Figure 1.9 HD64F2329E Pin Arrangement (TFP-120: Top View)

Rev.6.00 Sep. 27, 2007 Page 17 of 1268 REJ09B0220-0600 PG3/CS1 PG4/CS0 VSS NC VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 P67/CS7/IRQ3 P66/CS6/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 P53/ADTRG/IRQ7/WAIT/BREQO P52/SCK2/IRQ6 VSS VSS P51/RxD2/IRQ5 P50/TxD2/IRQ4 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/BREQO PF3/LWR PF4/HWR PF5/RD PF6/AS VCC PF7/φ VSS EXTAL XTAL V CC STBY NMI RES EMLE* 0/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3/TMRI0 P23/PO3/TIOCD3/TMCI0 P24/PO4/TIOCA4/TMRI1 P25/PO5/TIOCB4/TMCI1 P26/PO6/TIOCA5/TMO0 P27/PO7/TIOCB5/TMO1 P63/TEND1/TDO * P62/DREQ1/TDI * P61/TEND0/CS5/TCK * VSS VSS P60/DREQ0/CS4/TMS * VSS 102 101 100 P35/SCK1 P34/SCK0*/TRST* P33/RxD1 P32/RxD0* P31/TxD1 P30/TxD0* VCC PD7/D15 PD6/D14 PD5/D13 PD4/D12 VSS PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 VSS PE3/D3 PE2/D2 PE1/D1 PE0/D0 VCC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 MD0 MD1 MD2 PG0/CAS PG1/CS3 PG2/CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Note: * If an E10A emulator is used, the TDO, TDI, TDK, TMS, and TRST pins are used exclusively for the H-UDI and the functions and function modules associated with these pins are not available. SCI channel 0 is not available. Also, the watchdog timer continues to operate during break states and, if the settings specify that an internal reset is to be performed, a reset is generated if an overflow occurs. Refer to the E10A Emulator User's Manual for E10A emulator connection examples. E10A compatible version Figure 1.10 HD64F2329E Pin Arrangement (FP-128B: Top View)

Rev.6.00 Sep. 27, 2007 Page 18 of 1268 REJ09B0220-0600

1.3.2 Pin Functions in Each Operating Mode

Table 1.2 Pin Functions in Each Operating Mode Pin No. Pin Name TFP-120 FP-128B Mode 4 Mode 5*1 Mode 6 Mode 7 Flash Memory Programmer Mode 1 5 V CC V CC V CC V CC V CC 2 6 A 0 A 0 PC 0/A0 PC 0 A 0 3 7 A 1 A 1 PC 1/A1 PC 1 A 1 4 8 A 2 A 2 PC 2/A2 PC 2 A 2 5 9 A 3 A 3 PC 3/A3 PC 3 A 3 6 10 V SS V SS V SS V SS V SS 7 11 A 4 A 4 PC 4/A4 PC 4 A 4 8 12 A 5 A 5 PC 5/A5 PC 5 A 5 9 13 A 6 A 6 PC 6/A6 PC 6 A 6 10 14 A 7 A 7 PC 7/A7 PC 7 A 7 11 15 A 8 A 8 PB 0/A8 PB 0 A 8 12 16 A 9 A 9 PB 1/A9 PB 1 A 9 13 17 A 10 A 10 PB 2/A10 PB 2 A 10 14 18 A 11 A 11 PB 3/A11 PB 3 A 11 15 19 V SS V SS V SS V SS V SS 16 20 A 12 A 12 PB 4/A12 PB 4 A 12 17 21 A 13 A 13 PB 5/A13 PB 5 A 13 18 22 A 14 A 14 PB 6/A14 PB 6 A 14 19 23 A 15 A 15 PB 7/A15 PB 7 A 15 20 24 A 16 A 16 PA 0/A16 PA 0 A 16 21 25 A 17 A 17 PA 1/A17 PA 1 A 17 22 26 A 18 A 18 PA 2/A18 PA 2 A 18 23 27 A 19 A 19 PA 3/A19 PA 3 NC 24 28 V SS V SS V SS V SS V SS 25 29 A 20 A 20 PA 4/A20/IRQ4 PA 4/IRQ4 NC 26 30 PA 5/A21/IRQ5 PA 5/A21/IRQ5 PA 5/A21/IRQ5 PA 5/IRQ5 NC 27 31 PA 6/A22/IRQ6 PA 6/A22/IRQ6 PA 6/A22/IRQ6 PA 6/IRQ6 NC

Rev.6.00 Sep. 27, 2007 Page 19 of 1268 REJ09B0220-0600 Pin No. Pin Name TFP-120 FP-128B Mode 4 Mode 5 Mode 6 Mode 7 Flash Memory Programmer Mode 28 32 PA 7/A23/IRQ7 PA 7/A23/IRQ7 PA 7/A23/IRQ7 PA 7/IRQ7 NC 29 33 P6 7/IRQ3/CS7 P6 7/IRQ3/CS7 P6 7/IRQ3/CS7 P6 7/IRQ3 NC 30 34 P6 6/IRQ2/CS6 P6 6/IRQ2/CS6 P6 6/IRQ2/CS6 P6 6/IRQ2 V CC — 35 V SS V SS V SS V SS V SS — 36 V SS V SS V SS V SS V SS 31 37 P6 5/IRQ1 P6 5/IRQ1 P6 5/IRQ1 P6 5/IRQ1 V SS 32 38 P6 4/IRQ0 P6 4/IRQ0 P6 4/IRQ0 P6 4/IRQ0 V SS 33 39 V CC V CC V CC V CC V CC 34 40 PE 0/D0 PE 0/D0 PE 0/D0 PE 0 NC 35 41 PE 1/D1 PE 1/D1 PE 1/D1 PE 1 NC 36 42 PE 2/D2 PE 2/D2 PE 2/D2 PE 2 NC 37 43 PE 3/D3 PE 3/D3 PE 3/D3 PE 3 NC 38 44 V SS V SS V SS V SS V SS 39 45 PE 4/D4 PE 4/D4 PE 4/D4 PE 4 NC 40 46 PE 5/D5 PE 5/D5 PE 5/D5 PE 5 NC 41 47 PE 6/D6 PE 6/D6 PE 6/D6 PE 6 NC 42 48 PE 7/D7 PE 7/D7 PE 7/D7 PE 7 NC 43 49 D 8 D 8 D 8 PD 0 I/O 0 44 50 D 9 D 9 D 9 PD 1 I/O 1 45 51 D 10 D 10 D 10 PD 2 I/O 2 46 52 D 11 D 11 D 11 PD 3 I/O 3 47 53 V SS V SS V SS V SS V SS 48 54 D 12 D 12 D 12 PD 4 I/O 4 49 55 D 13 D 13 D 13 PD 5 I/O 5 50 56 D 14 D 14 D 14 PD 6 I/O 6 51 57 D 15 D 15 D 15 PD 7 I/O 7 52 58 V CC V CC V CC V CC V CC 53 59 P3 0/TxD0 P3 0/TxD0 P3 0/TxD0 P3 0/TxD0 NC 54 60 P3 1/TxD1 P3 1/TxD1 P3 1/TxD1 P3 1/TxD1 NC 55 61 P3 2/RxD0 P3 2/RxD0 P3 2/RxD0 P3 2/RxD0 NC

Rev.6.00 Sep. 27, 2007 Page 20 of 1268 REJ09B0220-0600 Pin No. Pin Name TFP-120 FP-128B Mode 4 Mode 5 Mode 6 Mode 7 Flash Memory Programmer Mode 56 62 P3 3/RxD1 P3 3/RxD1 P3 3/RxD1 P3 3/RxD1 NC 57 63 P3 4/SCK0 P3 4/SCK0 P3 4/SCK0 P3 4/SCK0 NC 58 64 P3 5/SCK1 P3 5/SCK1 P3 5/SCK1 P3 5/SCK1 NC 59 65 V SS V SS V SS V SS V SS 60 66 P6 0/DREQ0*2/ CS4 P60/DREQ0*2/ CS4 P60/DREQ0*2/ CS4 P60/DREQ0*2 NC — 67 V SS V SS V SS V SS V SS — 68 V SS V SS V SS V SS V SS 61 69 P6 1/TEND0*2/ CS5 P61/TEND0*2/ CS5 P61/TEND0*2/ CS5 P61/TEND0*2 NC 62 70 P6 2/DREQ1*2 P6 2/DREQ1*2 P6 2/DREQ1*2 P6 2/DREQ1*2 NC 63 71 P6 3/TEND1*2 P6 3/TEND1*2 P6 3/TEND1*2 P6 3/TEND1*2 NC 64 72 P2 7/PO7/ TIOCB5/TMO1 P27/PO7/ TIOCB5/TMO1 P27/PO7/ TIOCB5/TMO1 P27/PO7/ TIOCB5/TMO1 NC 65 73 P2 6/PO6/ TIOCA5/TMO0 P26/PO6/ TIOCA5/TMO0 P26/PO6/ TIOCA5/TMO0 P26/PO6/ TIOCA5/TMO0 NC 66 74 P2 5/PO5/ TIOCB4/TMCI1 P25/PO5/ TIOCB4/TMCI1 P25/PO5/ TIOCB4/TMCI1 P25/PO5/ TIOCB4/TMCI1 VSS 67 75 P2 4/PO4/ TIOCA4/TMRI1 P24/PO4/ TIOCA4/TMRI1 P24/PO4/ TIOCA4/TMRI1 P24/PO4/ TIOCA4/TMRI1 WE 68 76 P2 3/PO3/ TIOCD3/TMCI0 P23/PO3/ TIOCD3/TMCI0 P23/PO3/ TIOCD3/TMCI0 P23/PO3/ TIOCD3/TMCI0 CE 69 77 P2 2/PO2/ TIOCC3/TMRI0 P22/PO2/ TIOCC3/TMRI0 P22/PO2/ TIOCC3/TMRI0 P22/PO2/ TIOCC3/TMRI0 OE 70 78 P2 1/PO1/ TIOCB3 P21/PO1/ TIOCB3 P21/PO1/ TIOCB3 P21/PO1/ TIOCB3 NC 71 79 P2 0/PO0/ TIOCA3 P20/PO0/ TIOCA3 P20/PO0/ TIOCA3 P20/PO0/ TIOCA3 NC 72 80 WDTOVF (FWE, EMLE)*3 WDTOVF (FWE, EMLE)*3 WDTOVF (FWE, EMLE)*3 WDTOVF (FWE, EMLE)*3 FWE, EMLE*3 73 81 RES RES RES RES RES 74 82 NMI NMI NMI NMI V CC 75 83 STBY STBY STBY STBY V CC

Rev.6.00 Sep. 27, 2007 Page 21 of 1268 REJ09B0220-0600 Pin No. Pin Name TFP-120 FP-128B Mode 4 Mode 5 Mode 6 Mode 7 Flash Memory Programmer Mode 76 84 V CC V CC V CC V CC V CC 77 85 XTAL XTAL XTAL XTAL XTAL 78 86 EXTAL EXTAL EXTAL EXTAL EXTAL 79 87 V SS V SS V SS V SS V SS 80 88 PF 7/φ PF 7/φ PF 7/φ PF 7/φ NC 81 89 V CC V CC V CC V CC V CC 82 90 PF6/AS PF 6/AS PF 6/AS PF 6 NC 83 91 RD RD RD PF 5 NC 84 92 HWR HWR HWR PF 4 NC 85 93 PF3/LWR PF 3/LWR PF 3/LWR PF 3 NC 86 94 PF 2/LCAS*4/ WAIT/BREQO PF2/LCAS*4/ WAIT/BREQO PF2/LCAS*4/ WAIT/BREQO PF2 NC 87 95 PF 1/BACK PF 1/BACK PF 1/BACK PF 1 NC 88 96 PF 0/BREQ PF 0/BREQ PF 0/BREQ PF 0 NC 89 97 P5 0/TxD2/IRQ4 P5 0/TxD2/IRQ4 P5 0/TxD2/IRQ4 P5 0/TxD2/IRQ4 NC 90 98 P5 1/RxD2/IRQ5 P5 1/RxD2/IRQ5 P5 1/RxD2/IRQ5 P5 1/RxD2/IRQ5 V CC — 99 V SS V SS V SS V SS V SS — 100 V SS V SS V SS V SS V SS 91 101 P5 2/SCK2/ IRQ6 P52/SCK2/ IRQ6 P52/SCK2/ IRQ6 P52/SCK2/ IRQ6 NC 92 102 P5 3/ADTRG/ IRQ7/WAIT/ BREQO P53/ADTRG/ IRQ7/WAIT/ BREQO P53/ADTRG/ IRQ7/WAIT/ BREQO P53/ADTRG/ IRQ7 NC 93 103 AV CC AV CC AV CC AV CC V CC 94 104 V ref V ref V ref V ref V CC 95 105 P4 0/AN0 P4 0/AN0 P4 0/AN0 P4 0/AN0 NC 96 106 P4 1/AN1 P4 1/AN1 P4 1/AN1 P4 1/AN1 NC 97 107 P4 2/AN2 P4 2/AN2 P4 2/AN2 P4 2/AN2 NC 98 108 P4 3/AN3 P4 3/AN3 P4 3/AN3 P4 3/AN3 NC 99 109 P4 4/AN4 P4 4/AN4 P4 4/AN4 P4 4/AN4 NC 100 110 P4 5/AN5 P4 5/AN5 P4 5/AN5 P4 5/AN5 NC

Rev.6.00 Sep. 27, 2007 Page 22 of 1268 REJ09B0220-0600 Pin No. Pin Name TFP-120 FP-128B Mode 4 Mode 5 Mode 6 Mode 7 Flash Memory Programmer Mode 101 111 P4 6/AN6/DA0 P4 6/AN6/DA0 P4 6/AN6/DA0 P4 6/AN6/DA0 NC 102 112 P4 7/AN7/ DA1 P4 7/AN7/DA1 P4 7/AN7/DA1 P4 7/AN7/DA1 NC 103 113 AV SS AV SS AV SS AV SS V SS 104 114 V SS V SS V SS V SS V SS 105 115 P1 7/PO15/ TIOCB2/ TCLKD P17/PO15/ TIOCB2/ TCLKD P17/PO15/ TIOCB2/ TCLKD P17/PO15/ TIOCB2/ TCLKD NC 106 116 P1 6/PO14/ TIOCA2 P16/PO14/ TIOCA2 P16/PO14/ TIOCA2 P16/PO14/ TIOCA2 NC 107 117 P1 5/PO13/ TIOCB1/ TCLKC P15/PO13/ TIOCB1/ TCLKC P15/PO13/ TIOCB1/ TCLKC P15/PO13/ TIOCB1/ TCLKC NC 108 118 P1 4/PO12/ TIOCA1 P14/PO12/ TIOCA1 P14/PO12/ TIOCA1 P14/PO12/ TIOCA1 NC 109 119 P1 3/PO11/ TIOCD0/ TCLKB P13/PO11/ TIOCD0/ TCLKB P13/PO11/ TIOCD0/ TCLKB P13/PO11/ TIOCD0/ TCLKB NC 110 120 P1 2/PO10/ TIOCC0/ TCLKA P12/PO10/ TIOCC0/ TCLKA P12/PO10/ TIOCC0/ TCLKA P12/PO10/ TIOCC0/ TCLKA NC 111 121 P1 1/PO9/ TIOCB0/ DACK1*5 P11/PO9/ TIOCB0/ DACK1*5 P11/PO9/ TIOCB0/ DACK1*5 P11/PO9/ TIOCB0/ DACK1*5 NC 112 122 P1 0/PO8/ TIOCA0/ DACK0*6 P10/PO8/ TIOCA0/ DACK0*6 P10/PO8/ TIOCA0/ DACK0*6 P10/PO8/ TIOCA0/ DACK0*6 NC 113 123 MD 0 MD 0 MD 0 MD 0 V SS 114 124 MD 1 MD 1 MD 1 MD 1 V SS 115 125 MD 2 MD 2 MD 2 MD 2 V SS 116 126 PG 0/CAS *6 PG 0/CAS *6 PG 0/CAS *6 PG 0 NC 117 127 PG 1/CS3 PG 1/CS3 PG 1/CS3 PG 1 NC 118 128 PG 2/CS2 PG 2/CS2 PG 2/CS2 PG 2 NC 119 1 PG 3/CS1 PG 3/CS1 PG 3/CS1 PG 3 NC 120 2 PG 4/CS0 PG 4/CS0 PG 4/CS0 PG 4 NC

Rev.6.00 Sep. 27, 2007 Page 23 of 1268 REJ09B0220-0600 Pin No. Pin Name TFP-120 FP-128B Mode 4 Mode 5 Mode 6 Mode 7 Flash Memory Programmer Mode — 3 V SS V SS V SS V SS V SS — 4 V SSNC*7 V SSNC*7 V SSNC*7 V SSNC*7 NC Notes: 1. Only modes 4 and 5 are provided in the ROMless version. 2. The DREQ0, TEND0, DREQ1, and TEND1 pin functions are not supported in the H8S/2321. 3. The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The EMLE pin applies to the H8S/2329B F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. 4. The LCAS pin function is not supported in the H8S/2321. 5. The DACK1 pin function is not supported in the H8S/2321. 6. The DACK0 and CAS pin functions are not supported in the H8S/2321. 7. The V SSNC pin is connected to the VSS pin or released.

Rev.6.00 Sep. 27, 2007 Page 24 of 1268 REJ09B0220-0600 Table 1.3 Pin Functions Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Power V CC 1, 33, 52, 76, 5, 39, 58, 84, Input Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. V SS 6, 15, 24, 38, 47, 59, 79, 104 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 Input Ground: For connection to ground (0 V). All V SS pins should be connected to the system power supply (0 V). Clock XTAL 77 85 Input Connects to a crystal resonator. See section 20, Clock Pulse Generator for typical connection diagrams for a crystal resonator and external clock input. EXTAL 78 86 Input Connects to a crystal resonator. The EXTAL pin can also input an external clock. See section 20, Clock Pulse Generator for typical connection diagrams for a crystal resonator and external clock input. φ 80 88 Output System clock: Supplies the system clock to an external device.

Rev.6.00 Sep. 27, 2007 Page 25 of 1268 REJ09B0220-0600 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Operating mode control MD2 to MD0 115 to 113 125 to 123 Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD 2 to MD0 and the operating mode is shown below. These pins should not be changed while the chip is operating. H8S/2328B F-ZTAT, H8S/2326 F-ZTAT: FWE MD MD MD Operating Mode 0 0 0 1 — 1 0 — 1 — 1 0 0 Mode 4

1 Mode 5

1 0 0 0 — 1 — 1 0 Mode 10

1 Mode 11

1 0 0 — 1 — 1 0 Mode 14

1 Mode 15

Rev.6.00 Sep. 27, 2007 Page 26 of 1268 REJ09B0220-0600 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Operating mode control MD2 to MD0 115 to 113 125 to 123 Input Mask ROM and ROMless versions, H8S/2329B F-ZTAT: MD MD MD Operating Mode 0 0 1 — 1 0 Mode 2 *1 1 0 0 Mode 4 *2 Notes: 1. Applies to the H8S/2329B F-ZTAT only. 2. The ROMless versions can use only modes 4 and 5. System control RES 73 81 Input Reset input: When this pin is driven low, the chip is reset. STBY 75 83 Input Standby: When this pin is driven low, a transition is made to hardware standby mode. BREQ 88 96 Input Bus request: Used by an external bus master to issue a bus request to the chip. BREQO 86, 92 94, 102 Output Bus request output: The external bus request signal used when an internal bus master accesses external space in the external bus-released state. BACK 87 95 Output Bus request acknowledge: Indicates that the bus has been released to an external bus master.

Rev.6.00 Sep. 27, 2007 Page 27 of 1268 REJ09B0220-0600 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function System control FWE *1 72 80 Input Flash write enable: Enables/ disables flash memory programming. EMLE *2 72 80 Input Emulator enable: For connection to the power supply (0 V) Interrupts NMI 74 82 Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. IRQ7 to IRQ0 28 to 25, 29 to 32, 89 to 92 32 to 29, 33, 34, 37, 38, 97, 98, 101, 102 Input Interrupt request 7 to 0: These pins request a maskable interrupt. Address bus A 23 to 28 to 25, 23 to 16, 14 to 7, 5 to 2 32 to 29, 27 to 20, 18 to 11, 9 to 6 Output Address bus: These pins output an address. Data bus D 15 to 51 to 48, 46 to 39, 37 to 34 57 to 54, 52 to 45, 43 to 40 I/O Data bus: These pins constitute a bidirectional data bus. Bus control CS7 to CS0 29, 30, 61, 60, 117 to 120 33, 34, 69, 66, 127, 128, 1, 2 Output Chip select: Signals for selecting areas 7 to 0. AS 82 90 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. RD 83 91 Output Read: When this pin is low, it indicates that the external address space can be read. HWR 84 92 Output High write/write enable: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. The 2-CAS type DRAM write enable signal. LWR 85 93 Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled.

Rev.6.00 Sep. 27, 2007 Page 28 of 1268 REJ09B0220-0600 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Bus control CAS*4 116 126 Output Upper column address strobe/ column address strobe: The 2-CAS type DRAM upper column address strobe signal. LCAS*4 86 94 Output Lower column address strobe: The 2-CAS type DRAM lower column address strobe signal. WAIT 86, 92 94, 102 Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state access space. DMA controller (DMAC) *3 DREQ1, DREQ0 62, 60 70, 66 Input DMA request 1 and 0: These pins request DMAC activation. TEND1, TEND0 63, 61 71, 69 Output DMA transfer end 1 and 0: These pins indicate the end of DMAC data transfer. DACK1, DACK0 111, 112 121, 122 Output DMA transfer acknowledge 1 and 0: These are the DMAC single address transfer acknowledge pins. 16-bit timer pulse unit (TPU) TCLKD to TCLKA 105, 107, 109, 110 115, 117, 119, 120 Input Clock input D to A: These pins input an external clock. TIOCA 0, TIOCB0, TIOCC0, TIOCD0 112 to 109 122 to 119 I/O Input capture/output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. TIOCA 1, TIOCB1 108, 107 118, 117 I/O Input capture/output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. TIOCA 2, TIOCB2 106, 105 116, 115 I/O Input capture/output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. TIOCA 3, TIOCB3, TIOCC3, TIOCD3 71 to 68 79 to 76 I/O Input capture/output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins.

Rev.6.00 Sep. 27, 2007 Page 29 of 1268 REJ09B0220-0600 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function 16-bit timer pulse unit (TPU) TIOCA4, TIOCB4 67, 66 75, 74 I/O Input capture/output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. TIOCA 5, TIOCB5 65, 64 73, 72 I/O Input capture/output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. Programmable pulse generator (PPG) PO15 to PO0 105 to 112, 64 to 71 115 to 122, 72 to 79 Output Pulse output 15 to 0: Pulse output pins. 8-bit timer TMO 0, TMO1 65, 64 73, 72 Output Compare match output: The compare match output pins. TMCI 0, TMCI1 68, 66 76, 74 Input Counter external clock input: Input pins for the external clock input to the counter. TMRI 0, TMRI1 69, 67 77, 75 Input Counter external reset input: The counter reset input pins. Watchdog timer (WDT) WDTOVF*5 72 80 Output Watchdog timer overflow: The counter overflow signal output pin in watchdog timer mode. TxD2, TxD1, TxD0 89, 54, 97, 60, Output Transmit data (channel 0, 1, 2): Data output pins. Serial communication interface (SCI)/ smart card interface RxD RxD1, RxD0 90, 56, 98, 62, Input Receive data (channel 0, 1, 2): Data input pins. SCK 2, SCK1, SCK0 91, 58, 101, 64, 63I/O Serial clock (channel 0, 1, 2): Clock I/O pins. A/D converter AN 7 to AN0 102 to 112 to 105 Input Analog 7 to 0: Analog input pins. ADTRG 92 102 Input A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. D/A converter DA 1, DA0 102, 101 112, 111 Output Analog output: D/A converter analog output pins.

Rev.6.00 Sep. 27, 2007 Page 30 of 1268 REJ09B0220-0600 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function A/D converter and D/A converter AVCC 93 103 Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). AV SS 103 113 Input This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). V ref 94 104 Input This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). I/O ports P1 7 to P10 105 to 112 115 to 122 I/O Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). P2 7 to P20 64 to 71 72 to 79 I/O Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). P3 5 to P30 58 to 53 64 to 59 I/O Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). P4 7 to P40 102 to 112 to 105 Input Port 4: An 8-bit input port. P5 3 to P50 92 to 89 102, 101, 98, 97 I/O Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR).

Rev.6.00 Sep. 27, 2007 Page 31 of 1268 REJ09B0220-0600 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function I/O ports P6 7 to P60 29 to 32, 63 to 60 33, 34, 37, 38, 71 to 69, I/O Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR). PA 7 to PA0 28 to 25, 23 to 20 32 to 29, 27 to 24 I/O Port A: An 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). PB 7 to PB0 19 to 16, 14 to 11 23 to 20, 18 to 15 I/O Port B* 5: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). PC 7 to PC0 10 to 7, 5 to 2 14 to 11, 9 to 6 I/O Port C* 5: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). PD 7 to PD0 51 to 48, 46 to 43 57 to 54, 52 to 49 I/O Port D* 5: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). PE 7 to PE0 42 to 39, 37 to 34 48 to 45, 43 to 40 I/O Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). PF 7 to PF0 80, 82 to 88 88, 90 to 96 I/O Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). PG 4 to PG0 120 to 116 2, 1, 128 to 126 I/O Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). Notes: 1. Applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. 2. Applies to the H8S/2329B F-ZTAT only. 3. Not supported in the H8S/2321. 4. Not available in the F-ZTAT versions. 5. Cannot be used as an I/O port in the ROMless versions.

Rev.6.00 Sep. 27, 2007 Page 32 of 1268 REJ09B0220-0600

Rev.6.00 Sep. 27, 2007 Page 33 of 1268 REJ09B0220-0600 Section 2 CPU

2.1 Overview

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.

2.1.1 Features

The H8S/2000 CPU has the following features.

• Upward-compatible with H8/300 and H8/300H CPUs ⎯ Can execute H8/300 and H8/300H object programs
• General-register architecture ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-five basic instructions ⎯ 8/16/32-bit arithmetic and logic instructions ⎯ Multiply and divide instructions ⎯ Powerful bit-manipulation instructions
• Eight addressing modes ⎯ Register direct [Rn] ⎯ Register indirect [@ERn] ⎯ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] ⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] ⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ⎯ Immediate [#xx:8, #xx:16, or #xx:32] ⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)] ⎯ Memory indirect [@@aa:8]
• 16-Mbyte address space ⎯ Program: 16 Mbytes ⎯ Data: 16 Mbytes (4 Gbytes architecturally)

Rev.6.00 Sep. 27, 2007 Page 34 of 1268 REJ09B0220-0600

• High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate: 25 MHz ⎯ 8/16/32-bit register-register add/subtract: 40 ns ⎯ 8 × 8-bit register-register multiply: 480 ns ⎯ 16 ÷ 8-bit register-register divide: 480 ns ⎯ 16 × 16-bit register-register multiply: 800 ns ⎯ 32 ÷ 16-bit register-register divide: 800 ns
• CPU operating mode ⎯ Advanced mode
• Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU clock speed selection

2.1.2 Differences between H8 S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU.
• Number of execution states The number of exection states of the MULXU and MULXS instructions. Internal Operation Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 There are also differences in the address space, CCR and EXR functions, power-down state, etc., depending on the product.

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2.1.3 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

• More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit control register, have been added.
• Expanded address space ⎯ Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing ⎯ The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
• Enhanced instructions ⎯ Addressing modes of bit-manipulation instructions have been enhanced. ⎯ Signed multiply and divide instructions have been added. ⎯ Two-bit shift instructions have been added. ⎯ Instructions for saving and restoring multiple registers have been added. ⎯ A test and set instruction has been added.
• Higher speed ⎯ Basic instructions execute twice as fast.

2.1.4 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

• Additional control register ⎯ One 8-bit control register has been added.
• Enhanced instructions ⎯ Addressing modes of bit-manipulation instructions have been enhanced. ⎯ Two-bit shift instructions have been added. ⎯ Instructions for saving and restoring multiple registers have been added. ⎯ A test and set instruction has been added.
• Higher speed ⎯ Basic instructions execute twice as fast.

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2.2 CPU Operating Modes

The H8S/2329 and H8S/2328 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used.

Rev.6.00 Sep. 27, 2007 Page 37 of 1268 REJ09B0220-0600 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.1). For details of the exception vector table, see section 4, Exception Handling. H'00000000 H'00000003 H'00000004 H'0000000B H'0000000C Exception vector table Reserved Power-on reset exception vector (Reserved for system use) Reserved Exception vector 1 Reserved H'00000010 H'00000008 H'00000007 Figure 2.1 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table.

Rev.6.00 Sep. 27, 2007 Page 38 of 1268 REJ09B0220-0600 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. (a) Subroutine Branch (b) Exception Handling PC (24 bits) EXR*1 Reserved*1 *3 CCR PC (24 bits) SP SP Notes: 1. When EXR is not used it is not stored on the stack. SP when EXR is not used. Ignored when returning. (SP ) *2Reserved Figure 2.2 Stack Structure in Advanced Mode

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2.3 Address Space

Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. Advanced Mode H'00000000 H'FFFFFFFF H'00FFFFFF Data area Program area Cannot be used by the H8S/2329 and H8S/2328 Group Figure 2.3 Memory Map

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2.4 Register Configuration

2.4.1 Overview

The CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers. T ———— I2 I1 I0EXR 76543210 PC 23 0 15 07 07 0 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General Registers (Rn) and Extended Registers (En) Control Registers (CR) Legend: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* SP: PC: EXR: I2 to I0: CCR: UI: Note: * In the H8S/2329 Group and H8S/2328 Group, this bit cannot be used as an interrupt mask. ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) I UI HUNZVCCCR 76543210 Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Figure 2.4 CPU Registers

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2.4.2 General Registers

The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.5 illustrates the usage of the general registers. The usage of each register can be selected independently.  Address registers  32-bit registers  16-bit registers  8-bit registers ER registers (ER0 to ER7) E registers (extended registers) (E0 to E7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.5 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.6 shows the stack.

Rev.6.00 Sep. 27, 2007 Page 42 of 1268 REJ09B0220-0600 Free area Stack area SP (ER7) Figure 2.6 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1. Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC.

Rev.6.00 Sep. 27, 2007 Page 43 of 1268 REJ09B0220-0600 (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception- handling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2329 Group and H8S/2328 Group, this bit cannot be used as an interrupt mask bit. instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, Instruction List.

Rev.6.00 Sep. 27, 2007 Page 44 of 1268 REJ09B0220-0600 Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.

2.4.4 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.

2.5 Data Formats

The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

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2.5.1 General Register Data Formats

Figure 2.7 shows the data formats in general registers. 7 6 5 4 3 2 1 0 Don’t care Don’t care 76543210 4370 Don’t careUpper Lower LSB MSB LSB Data Type Register Number Data Format 1-bit data 1-bit data 4-bit BCD data 4-bit BCD data Byte data Byte data RnH RnL RnH RnL RnH RnL MSB Don’t care Upper Lower 4370 Don’t care Don’t care Figure 2.7 General Register Data Formats

Rev.6.00 Sep. 27, 2007 Page 46 of 1268 REJ09B0220-0600 MSB LSB 15Word data Word data Rn En LSB 1516 MSB En Rn General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Legend: ERn: En: Rn: RnH: RnL: MSB: LSB: MSB LSB Longword data ERn Data Type Register Number Data Format Figure 2.7 General Register Data Formats (cont)

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2.5.2 Memory Data Formats

Figure 2.8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. 76543210 MSB LSB MSB LSB MSB LSB Data Type Data Format 1-bit data Byte data Word data Longword data Address Address L Address L Address 2M Address 2M + 1 Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.8 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size.

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2.6 Instruction Set

2.6.1 Overview

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer MOV BWL 5 POP *1, PUSH*1 WL LDM, STM L MOVFPE, MOVTPE *3 B Arithmetic ADD, SUB, CMP, NEG BWL 19 operations ADDX, SUBX, DAA, DAS B INC, DEC BWL ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS BW EXTU, EXTS WL TAS *4 B Logic operations AND, OR, XOR, NOT BWL 4 Shift SHAL, SHAR, SHLL, SHLR, RO TL, ROTR, ROTXL, ROTXR BWL 8 Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14 Branch Bcc *2, JMP, BSR, JSR, RTS — 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9 Block data transfer EEPMOV — 1 Total: 65 Legend: B: Byte W: Word L: Longword ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2329 Group and H8S/2328 Group. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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2.6.2 Instructions and Addressing Modes

Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Function Data transfer Arithmetic operations Instruction #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Logic operations System control Block data transfer Shift Bit manipulation Branch Legend: B: Byte W: Word L: Longword Notes: 1. Cannot be used in the H8S/2329 Group and H8S/2328 Group. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. MOV BWL BWL BWL BWL BWL BWL B BWL — BWL — — — — MOVTPE DIVXU DIVXS TAS XOR LDC B B W W W W — W — W — — — — ORC, XORC

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2.6.3 Table of Instructions Classified by Function

Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd General register (destination) * Rs General register (source) * Rn General register * ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ¬ NOT (logical complement) Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Rev.6.00 Sep. 27, 2007 Page 51 of 1268 REJ09B0220-0600 Table 2.3 Instructions Cl assified by Function Type Instruction Size *1 Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2329 Group and H8S/2328 Group. MOVTPE B Cannot be used in the H8S/2329 Group and H8S/2328 Group. POP W/L @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. LDM L @SP+ → Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) → @–SP Pushes two or more general registers onto the stack.

Rev.6.00 Sep. 27, 2007 Page 52 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function Arithmetic operations ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) ADDX SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. INC DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. DAA DAS B Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder.

Rev.6.00 Sep. 27, 2007 Page 53 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function Arithmetic operations DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS B @ERd – 0, 1 → (<bit 7> of @Erd)*2 Tests memory contents, and sets the most significant bit (bit 7) to 1.

Rev.6.00 Sep. 27, 2007 Page 54 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ¬ (Rd) → (Rd) Takes the one's complement of general register contents. Shift operations SHAL SHAR B/W/L Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. SHLL SHLR B/W/L Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. ROTL ROTR B/W/L Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. ROTXL ROTXR B/W/L Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible.

Rev.6.00 Sep. 27, 2007 Page 55 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function Bit- manipulation instructions BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ¬ (<bit-No.> of <EAd>) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND BIAND B B ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR BIOR B B ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

Rev.6.00 Sep. 27, 2007 Page 56 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function Bit- manipulation instructions BXOR BIXOR B B Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD BILD B B Transfers a specified bit in a general register or memory operand to the carry flag. Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST BIST B B Transfers the carry flag value to a specified bit in a general register or memory operand. Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.

Rev.6.00 Sep. 27, 2007 Page 57 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 BCC(BHS) Carry clear (high or same) C = 0 BCS(BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨(N ⊕ V) = 0 BLE Less or equal Z ∨(N ⊕ V) = 1 JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine.

Rev.6.00 Sep. 27, 2007 Page 58 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function TRAPA — Starts trap-instruction exception handling. System control instructions RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 → PC Only increments the program counter.

Rev.6.00 Sep. 27, 2007 Page 59 of 1268 REJ09B0220-0600 Type Instruction Size *1 Function Block data transfer instruction EEPMOV.B EEPMOV.W if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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2.6.4 Basic Instruction Formats

The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.9 shows examples of instruction formats. op op rn rm NOP, RTS, etc. ADD.B Rn, Rm, etc. MOV.B @(d:16, Rn), Rm, etc. (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension rn rmop EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.9 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions.

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2.7 Addressing Modes and Eff ective Address Calculation

2.7.1 Addressing Mode

The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 Addressing Modes No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

Register indirect with pre-decrement @ERn+ @–ERn

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

(1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added.

Rev.6.00 Sep. 27, 2007 Page 62 of 1268 REJ09B0220-0600 (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:

• Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even.
• Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. Table 2.5 Absolute Address Access Ranges Absolute Address Advanced Mode Data address 8 bits (@aa:8) H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction address 24 bits (@aa:24)

Rev.6.00 Sep. 27, 2007 Page 63 of 1268 REJ09B0220-0600 (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'000000 to H'0000FF). In advanced mode the memory operand is a long word operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Advanced Mode Specified by @aa:8 Reserved Branch address Figure 2.10 Branch Address Specification in Memory Indirect Mode

Rev.6.00 Sep. 27, 2007 Page 64 of 1268 REJ09B0220-0600 If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.)

2.7.2 Effective Address Calculation

Table 2.6 indicates how effective addresses are calculated in each addressing mode.

Rev.6.00 Sep. 27, 2007 Page 65 of 1268 REJ09B0220-0600 Table 2.6 Effective Address Calculation Register indirect with post-increment or pre-decrement  Register indirect with post-increment @ERn+ No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1 Register direct (Rn)

op rm rn Operand is general register contents. Register indirect (@ERn)2 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn)  Register indirect with pre-decrement @-DERn General register contents General register contents Sign extension disp General register contents 1, 2, or 4 General register contents 1, 2, or 4 Byte Word Longword Operand Size Value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r rop op r rop disp 24 23 Don't care 24 23 Don't care 24 23 Don't care 24 23 Don't care

Rev.6.00 Sep. 27, 2007 Page 66 of 1268 REJ09B0220-0600 @aa:8 Absolute address @aa:16 @aa:32 Operand is immediate data. No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs absop op abs op IMM H'FFFF Don't care 24 23 Don't care 24 23 Don't care 24 23 Don't care Sign extension

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7 Program-counter relative

@(d:8, PC)/@(d:16, PC)  Advanced mode No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) 031 8 7 disp absH'000000 31 0 24 23 31 0 24 23 op disp op abs Sign extension PC contents Memory contents Don’t care Don’t care

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2.8 Processing States

2.8.1 Overview

The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.11 shows a diagram of the processing states. Figure 2.12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Power-down state CPU operation is stopped to conserve power.* Sleep mode Software standby mode Hardware standby mode Processing states Note: * The power-down state also includes a medium-speed mode, module stop mode etc. Figure 2.11 Processing States

Rev.6.00 Sep. 27, 2007 Page 69 of 1268 REJ09B0220-0600 End of bus request Bus request Program execution state Bus-released state Sleep mode Exception-handling state External interrupt Software standby mode RES = high Reset state STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. From any state, a transition to hardware standby mode occurs when STBY goes low. SLEEP instruction with SSBY = 0 SLEEP instruction with SSBY = 1 Interrupt request End of bus request Bus requestRequest for exception handling End of exception handling Figure 2.12 State Transitions

2.8.2 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 13, Watchdog Timer.

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2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows Trace End of instruction execution or end of exception-handling sequence*1 When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence Interrupt End of instruction execution or end of exception-handling sequence*2 When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Low Trap instruction When TRAPA instruction is executed Exception handling starts when a trap (TRAPA) instruction is executed* Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state.

Rev.6.00 Sep. 27, 2007 Page 71 of 1268 REJ09B0220-0600 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exception- handling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.13 shows the stack after exception handling ends.

Rev.6.00 Sep. 27, 2007 Page 72 of 1268 REJ09B0220-0600 (c) Interrupt control mode 0 (d) Interrupt control mode 2 CCR PC (24 bits) SP Note: * Ignored when returning. CCR PC (24 bits) SP EXR Reserved* Advanced mode Figure 2.13 Stack Structure after Exception Handling (Examples)

2.8.4 Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5 Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts. There is one other bus master in addition to the CPU: the DMA controller (DMAC) * and data transfer controller (DTC). For further details, refer to section 6, Bus Controller. Note: * The DMAC is not supported in the H8S/2321.

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2.8.6 Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 21, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained.

2.9 Basic Timing

2.9.1 Overview

The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space.

2.9.2 On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.14 shows the on-chip memory access cycle. Figure 2.15 shows the pin states.

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2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the access timing for the on-chip supporting modules. Figure 2.17 shows the pin states. Bus cycle T1 T2 Address Read data Write data Internal read signal Internal data bus Internal write signal Internal data bus Read access Write access Internal address bus φ Figure 2.16 On-Chip Supporting Module Access Cycle

Rev.6.00 Sep. 27, 2007 Page 76 of 1268 REJ09B0220-0600 Bus cycle T1 T2 UnchangedAddress bus AS RD HWR, LWR Data bus φ High High High High-impedance state Figure 2.17 Pin States during On-Chip Supporting Module Access

2.9.4 External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller.

2.10 Usage Note

2.10.1 TAS Instruction

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 77 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes

3.1 Overview

3.1.1 Operating Mode Selection (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT)

The H8S/2328B F-ZTAT and H8S/2326 F-ZTAT have eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 3.1. Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) External Data Bus MCU Operating Mode FWE MD MD MD CPU Operating Mode 4 1 0 0 Advanced Disabled 16 bits 16 bits 5 1 Expanded mode with on-chip ROM disabled 8 bits 16 bits 6 1 0 Expanded mode with on- chip ROM enabled Enabled 8 bits 16 bits 7 1 Single-chip mode — — 9 1 10 1 0 Advanced Boot mode Enabled 8 bits 16 bits 11 1 — — 13 1 14 1 0 Advanced User program mode Enabled 8 bits 16 bits 15 1 — —

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 78 of 1268 REJ09B0220-0600 The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8- bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. Modes 10, 11, 14, and 15 are boot modes and user program modes in which the flash memory can be programmed and erased. For details, see section 19, ROM. The H8S/2328B F-ZTAT and H8S/2326 F-ZTAT can only be used in modes 4 to 7, 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation.

3.1.2 Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2329B

F-ZTAT) The ROMless and mask ROM versions have four operating modes (modes 4 to 7). H8S/2329B F-ZTAT has six operating modes (modes 2 to 7). The operating mode is determined by the mode pins (MD 2 to MD0). The CPU operating mode, enabling or disabling of on-chip ROM, and the initial bus width setting can be selected as shown in table 3.2. Table 3.2 lists the MCU operating modes.

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 79 of 1268 REJ09B0220-0600 Table 3.2 MCU Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2329B F-ZTAT) External Data Bus MCU Operating Mode MD2 MD1 MD CPU Operating Mode Max. Value 2*1 1 0 3*1 1 4*2 1 0 0 Advanced Disabled 16 bits 16 bits 5*2 1 Expanded mode with on-chip ROM disabled 8 bits 16 bits 6 1 0 Expanded mode with on-chip ROM enabled Enabled 8 bits 16 bits 7 1 Single-chip mode — — Notes: 1. Boot mode in the H8S/2329B F-ZTAT. See table 19.9, for information on H8S/2329B F-ZTAT user boot modes. See table 19.9, for information on H8S/2329B F-ZTAT user program modes. 2. The ROMless versions can use only modes 4 and 5. The CPU's architecture allows for 4 Gbytes of address space, but the mask ROM and ROMless versions, and H8S/2329B F-ZTAT actually access a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8- bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The ROMless and mask ROM versions can only be used in modes 4 to 7. This means that the mode pins must be set to select one of these modes. However, note that only mode 4 or 5 can be set for the ROMless version. H8S/2329B F-ZTAT can only be used in modes 2 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation.

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 80 of 1268 REJ09B0220-0600

3.1.3 Register Configuration

The H8S/2329 Group and H8S/2328 Group have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and a system control register 2 (SYSCR2)*2 that control the operation of the chip. Table 3.3 summarizes these registers. Table 3.3 Registers Name Abbreviation R/W Initial Value Address *1 Mode control register MDCR R Undefined H'FF3B System control register SYSCR R/W H'01 H'FF39 System control register 2*2 SYSCR2 R/W H'00 H'FF42 Notes: 1. Lower 16 bits of the address. 2. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM and ROMless versions this register will return an undefined value if read, and cannot be modified.

3.2 Register Descriptions

3.2.1 Mode Control Register (MDCR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 1 0 0 0 0 — * — * — * Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2329 Group and H8S/2328 Group chip. Bit 7—Reserved: This bit is always read as 1, and cannot be modified. Bits 6 to 3—Reserved: These bits are always read as 0, and cannot be modified. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset.

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3.2.2 System Control Register (SYSCR)

Bit : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROD IRQPAS RAME Initial value : 0 0 0 0 0 0 0 1 R/W : R/W — R/W R/W R/W R/W R/W R/W Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit is always read as 0, and cannot be modified. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 Bit 4 INTM0 Interrupt Control Mode 0 0 0 Control of interrupts by I bit (Initial value) 1 — Setting prohibited 1 0 2 Control of interrupts by I2 to I0 bits and IPR 1 — Setting prohibited Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG

0 An interrupt is requested at the falling edge of NMI input (Initial value)

1 An interrupt is requested at the rising edge of NMI input

Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. Bit 2 LWROD 3 is designated as LWR output pin (Initial value)

1 PF 3 is designated as I/O port, and does not function as LWR output pin

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 82 of 1268 REJ09B0220-0600 Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports. Bit 1 IRQPAS 4 to PA7 are used for IRQ4 to IRQ7 input (Initial value)

1 P5 0 to P53 are used for IRQ4 to IRQ7 input

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Note: * R/W in the H8S/2329B F-ZTAT. SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: These bits are always read as 0, and cannot be modified. Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19, ROM.

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 83 of 1268 REJ09B0220-0600 Bit 3 FLSHE

0 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB

(Initial value)

1 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB

Bits 2 and 1—Reserved: These bits are always read as 0. Only 0 should be written to these bits. Bit 0—Reserved: In the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT, this bit is always read as 0 and should only be written with 0. In the H8S/2329B F-ZTAT, this bit is reserved and should only be written with 0.

3.3 Operating Mode Descriptions

3.3.1 Mode 1

The H8S/2329 does not support mode 1. Do not select the mode 1 setting.

3.3.2 Mode 2 (H8S/2329B F-ZTAT Only)

This is a flash memory boot mode. See section 19, ROM, for details. This is the same as advanced on-chip ROM enabled expansion mode, except when erasing and reprogramming flash memory.

3.3.3 Mode 3 (H8S/2329B F-ZTAT Only)

This is a flash memory boot mode. See section 19, ROM, for details. This is the same as advanced single-chip ROM mode, except when erasing and reprogramming flash memory.

3.3.4 Mode 4 (Expanded Mode with On-Chip ROM Disabled)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8- bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 84 of 1268 REJ09B0220-0600

3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus.

3.3.6 Mode 6 (Expanded Mode with On-Chip ROM Enabled)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B, and C function as input ports immediately after a reset. These pins can be set to output addresses by setting the corresponding bits to 1 in pin function control register 1 (PFCR1) in the case of ports A and B, or in the data direction register (DDR) for port C. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus.

3.3.7 Mode 7 (Single-Chip Mode)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input/output ports.

3.3.8 Modes 8 and 9 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)

Modes 8 and 9 are not supported and must not be set.

3.3.9 Mode 10 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)

This is a flash memory boot mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled.

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3.3.10 Mode 11 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)

This is a flash memory boot mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode.

3.3.11 Modes 12 and 13

Modes 12 and 13 are not supported and must not be set.

3.3.12 Mode 14 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)

This is a flash memory user program mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled.

3.3.13 Mode 15 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)

This is a flash memory user program mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode.

3.4 Pin Functions in Each Operating Mode

The pin functions of ports A to F vary depending on the operating mode. Table 3.4 shows their functions in each operating mode.

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 86 of 1268 REJ09B0220-0600 Table 3.4 Pin Functions in Each Mode Port Mode 2*4 Mode Mode Mode Mode Mode Mode 10* Mode 11* Mode 14* Mode 15* Port A PA 7 to PA5 P*1/A P P *1/A P *1/A P *1/A P P *1/A P P *1/A P PA 4 to PA0 A A Port B P *1/A P A A P *1/A P P *1/A P P *1/A P Port C P *1/A P A A P *1/A P P *1/A P P *1/A P Port D D P D D D P D P D P Port E P *1/D P P/D *1 P *1/D P *1/D P P *1/D P P *1/D P Port F PF 7 P *1/C P *1/C P *1/C P *1/C PF 6 P/C*1 P P/C*1 P/C *1 P/C *1 P P/C*1 P P/C*1 P PF 5 to PF4 C C C C C C PF 3 P/C *1 P/C *1 P/C *1 P/C *1 P/C *1 P/C *1 PF 2 to PF0 P*1/C P *1/C P *1/C P *1/C P *1/C P *1/C Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O Notes: 1. After reset. 2. Setting is prohibited in the ROMless versions. 3. Setting prohibited except in case of the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT. 4. Valid only in the H8S/2329B F-ZTAT.

3.5 Memory Map in Each Operating Mode

Figures 3.1 to 3.9 show memory maps for each of the operating modes. The address space is 16 Mbytes. The address space is divided into eight areas.

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 87 of 1268 REJ09B0220-0600 Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) Mode 3 Boot Mode (advanced single-chip mode) On-chip ROM On-chip ROM On-chip ROM/ reserved area*2 *5 External address space Reseved area*4 Reseved area*4 Reseved area*4 Reseved area*4 On-chip RAM*3 On-chip RAM Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'FF7400 H'FFFBFF H'FF7C00 H'FF7400 H'FF7C00 H'FFFFFF H'FFFE50 H'FFFF07 H'FFFF28 On-chip ROM/ external address space*1 H'010000 H'010000 H'07FFFF H'060000H'060000 H'080000 H'FFFC00 H'FFFFFF H'FFFF08 H'FFFF28 H'FFFE50 Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 4. Access to the reserved areas H'060000 to H'07FFFF and H'FF7400 to H'FF7BFF is prohibited. 5. Do not access a reserved area. Figure 3.1 (a) H8S/2329B Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 88 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) External address space On-chip ROM On-chip RAM*3 Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 4. Access to the reserved areas H'060000 to H'07FFFF and H'FF7400 to H'FF7BFF is prohibited. 5. Do not access a reserved area. Internal I/O registers On-chip ROM On-chip ROM/ reserved area *2 *5 External address space External address space External address space Internal I/O registers External address space Reseved area*4 Reseved area*4 Reseved area*4 Reseved area*4 Reseved area*4 Reseved area*4 On-chip RAM*3 On-chip RAM Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'000000 H'FFFC00 H'FFFFFF H'FF7400 H'FFFBFF H'FF7C00 H'FF7400 H'FF7C00 H'FF7400 H'FF7C00 H'FFFFFF H'FFFF08 H'FFFE50 H'FFFF07 H'FFFF28 H'FFFF28 On-chip ROM/ external address space*1 H'FFFE50 H'010000 H'010000 H'07FFFF H'060000H'060000H'060000 H'080000 H'080000 H'FFFC00 H'FFFFFF H'FFFF08 H'FFFF28 H'FFFE50 Figure 3.1 (b) H8S/2329B Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 89 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) External address space On-chip ROM On-chip RAM*3 Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 4. Do not access a reserved area. Internal I/O registers On-chip ROM On-chip ROM/ reserved area *2 *4 External address space External address space Internal I/O registers External address space On-chip RAM*3 On-chip RAM Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'000000 H'040000 H'FFFC00 H'FFFFFF H'FFDC00H'FFDC00H'FFDC00 H'FFFBFF H'FFFFFF H'FFFF08 H'FFFE50 H'FFFF07 H'FFFF28 H'FFFF28 On-chip ROM/ external address space*1 H'FFFE50 H'010000 H'010000 H'03FFFF H'FFFC00 H'FFFFFF H'FFFF08 H'FFFF28 H'FFFE50 Figure 3.2 (a) H8S/2328 Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 90 of 1268 REJ09B0220-0600 Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) Mode 11 Boot Mode (advanced single-chip mode) On-chip ROM Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 4. Do not access a reserved area. On-chip ROM External address space On-chip RAM*3 On-chip RAM*3 On-chip ROM/ reserved area*2 *4 Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'040000 H'03FFFF H'FFDC00 H'FFFBFF H'FFFFFF H'FFFE50 H'FFFF07 H'FFFF28 On-chip ROM/ external address space*1 H'010000 H'010000 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFFFF H'FFFF08 H'FFFF28 Figure 3.2 (b) H8S/2328 Memory Map in Each Operating Mode (F-ZTAT Only)

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 91 of 1268 REJ09B0220-0600 Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) Mode 15 User Program Mode (advanced single-chip mode) On-chip ROM Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 4. Do not access a reserved area. On-chip ROM External address space On-chip RAM*3 On-chip RAM*3 On-chip ROM/ reserved area*2 *4 Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'040000 H'03FFFF H'FFDC00 H'FFFBFF H'FFFFFF H'FFFE50 H'FFFF07 H'FFFF28 On-chip ROM/ external address space*1 H'010000 H'010000 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFFFF H'FFFF08 H'FFFF28 Figure 3.2 (c) H8S/2328 Memory Map in Each Operating Mode (F-ZTAT Only)

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 92 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) External address space On-chip ROM On-chip RAM*4 Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. External addresses when EAE = 1 in BCRL; reserved area when EAE = 0. 3. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 4. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 5. Do not access a reserved area. Internal I/O registers On-chip ROM Reserved area External address space External address space Internal I/O registers External address space On-chip RAM*4 On-chip RAM Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'000000 H'040000 H'FFFC00 H'FFFFFF H'FFDC00H'FFDC00H'FFDC00 H'FFFBFF H'FFFFFF H'FFFF08 H'FFFE50 H'FFFF07 H'FFFF28 H'FFFF28 External address space/reserved area*2 *5 External address space/on-chip ROM*1 Reserved area*5/ on-chip ROM*3 H'FFFE50 H'010000 H'010000 H'020000H'020000 H'03FFFF H'FFFC00 H'FFFFFF H'FFFF08 H'FFFF28 H'FFFE50 Figure 3.3 H8S/2327 Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 93 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) External address space On-chip ROM On-chip RAM*3 Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 4. Do not access a reserved area. Internal I/O registers On-chip ROM External address space External address space Internal I/O registers External address space On-chip RAM*3 On-chip RAM Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'000000 H'080000 H'FFFC00 H'FFFFFF H'FFDC00H'FFDC00H'FFDC00 H'FFFBFF H'FFFFFF H'FFFF08 H'FFFE50 H'FFFF07 H'FFFF28 H'FFFF28 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'FFFE50 H'010000 H'010000 H'07FFFF H'FFFC00 H'FFFFFF H'FFFF08 H'FFFF28 H'FFFE50 Figure 3.4 (a) H8S/2326 F-ZTAT Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 94 of 1268 REJ09B0220-0600 Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) Mode 11 Boot Mode (advanced single-chip mode) On-chip ROM Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 4. Do not access a reserved area. On-chip ROM External address space On-chip RAM*3 On-chip RAM*3 On-chip ROM/ reserved area*2 *4 Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'080000 H'07FFFF H'FFDC00 H'FFFBFF H'FFFFFF H'FFFE50 H'FFFF07 H'FFFF28 On-chip ROM/ external address space*1 H'010000 H'010000 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFFFF H'FFFF08 H'FFFF28 Figure 3.4 (b) H8S/2326 F-ZTAT Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 95 of 1268 REJ09B0220-0600 Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) Mode 15 User Program Mode (advanced single-chip mode) On-chip ROM Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 4. Do not access a reserved area. On-chip ROM External address space On-chip RAM*3 On-chip RAM*3 On-chip ROM/ reserved area*2 *4 Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'080000 H'07FFFF H'FFDC00 H'FFFBFF H'FFFFFF H'FFFE50 H'FFFF07 H'FFFF28 On-chip ROM/ external address space*1 H'010000 H'010000 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFFFF H'FFFF08 H'FFFF28 Figure 3.4 (c) H8S/2326 F-ZTAT Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 96 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) External address space On-chip RAM* Internal I/O registers External address space Internal I/O registers External address space H'000000 H'FFFC00 H'FFFFFF H'FF7C00 H'FFFF08 H'FFFF28 H'FFFE50 Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.5 H8S/2324S Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 97 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) External address space On-chip ROM On-chip RAM*2 Notes: 1. External addresses when EAE = 1 in BCRL; reserved area when EAE = 0. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 3. Do not access a reserved area. Internal I/O registers On-chip ROM Reserved area *3 Reserved area*3 Reserved area*3 External address space External address space Internal I/O registers External address space On-chip RAM*2 On-chip RAM Internal I/O registers External address space Internal I/O registers Internal I/O registers Internal I/O registers External address space H'000000 H'000000 H'000000 H'040000 H'FFFC00 H'FFFFFF H'FFDC00H'FFDC00H'FFDC00 H'FFFBFF H'FFFFFF H'FFFF08 H'FFFE50 H'FFFF07 H'FFFF28 H'FFFF28 External address space/reserved area*1 *3 H'FFFE50 H'010000 H'010000 H'008000 H'008000 H'03FFFF H'FFFC00 H'FFFFFF H'FFFF08 H'FFFF28 H'FFFE50 Figure 3.6 H8S/2323 Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 98 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) External address space On-chip RAM* Internal I/O registers External address space Internal I/O registers External address space H'000000 H'FFFC00 H'FFFFFF H'FFDC00 H'FFFF08 H'FFFF28 H'FFFE50 Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.7 H8S/2322R Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 99 of 1268 REJ09B0220-0600 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) External address space Reserved area On-chip RAM* Internal I/O registers External address space Internal I/O registers External address space H'000000 H'FFFC00 H'FFEC00 H'FFFFFF H'FFDC00 H'FFFF08 H'FFFF28 H'FFFE50 Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.8 H8S/2320 and H8S/2321 Memory Map in Each Operating Mode

Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 100 of 1268 REJ09B0220-0600

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 101 of 1268 REJ09B0220-0600 Section 4 Exception Handling

4.1 Overview

4.1.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Trace *1 Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Interrupt Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued*2 Low Trap instruction (TRAPA) *3 Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state.

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 102 of 1268 REJ09B0220-0600

4.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out.

4.1.3 Exception Vector Table

The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Exception sources

• Reset  Trace  Interrupts  Trap instruction External interrupts: NMI, IRQ7 to IRQ0 Internal interrupts: interrupts from on-chip supporting modules Figure 4.1 Exception Sources In modes 6 and 7, the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables the 256-kbyte (128 kbytes/384 kbytes/512 kbytes)* area comprising addresses H'000000 to H'03FFFF (to H'01FFFF/H'05FFFF/H'07FFFF) to be used. For details, see section 6.2.5, Bus Control Register L (BCRL). Note: * The amount of on-chip ROM differs depending on the product.

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 103 of 1268 REJ09B0220-0600 Table 4.2 Exception Vector Table Vector Address*1 Exception Source Vector Number Advanced Mode Reset 0 H'0000 to H'0003 Reserved 1 H'0004 to H'0007 Reserved for system use 2 H'0008 to H'000B

3 H'000C to H'000F

4 H'0010 to H'0013

Trace 5 H'0014 to H'0017 Reserved for system use 6 H'0018 to H'001B External interrupt NMI 7 H'001C to H'001F Trap instruction (4 sources) 8 H'0020 to H'0023

9 H'0024 to H'0027

10 H'0028 to H'002B

11 H'002C to H'002F

Reserved for system use 12 H'0030 to H'0033

13 H'0034 to H'0037

14 H'0038 to H'003B

15 H'003C to H'003F

External interrupt IRQ0 16 H'0040 to H'0043 IRQ1 17 H'0044 to H'0047 IRQ2 18 H'0048 to H'004B IRQ3 19 H'004C to H'004F IRQ4 20 H'0050 to H'0053 IRQ5 21 H'0054 to H'0057 IRQ6 22 H'0058 to H'005B IRQ7 23 H'005C to H'005F Internal interrupt*2 24 H'0060 to H'0063 H'016C to H'016F Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector Table.

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 104 of 1268 REJ09B0220-0600

4.2 Reset

4.2.1 Overview

A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. A reset can also be caused by watchdog timer overflow. For details see section 13, Watchdog Timer.

4.2.2 Reset Sequence

The chip enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.2 shows an example of the reset sequence.

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 105 of 1268 REJ09B0220-0600 Address bus Vector fetch Internal processing Prefetch of first program instruction (1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2), (4) Start address (contents of reset exception vector address) (5) Start address ((5) = (2), (4)) (6) First program instruction φ RES (1) (5) High (2) (4) (3) (6) RD HWR, LWR D15 to D0 Note: * 3 program wait states are inserted. Figure 4.2 Reset Sequence (Mode 4)

4.2.3 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP).

4.2.4 State of On-Chip Supporting Modules after Reset Release

After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC * and DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Note: * The DMAC is not supported in the H8S/2321.

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 106 of 1268 REJ09B0220-0600

4.3 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 Trace exception handling cannot be used. 2 1 — — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution.

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 107 of 1268 REJ09B0220-0600

4.4 Interrupts

Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer*, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC)*, and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. Note: * The refresh timer and DMAC are not supported in the H8S/2321. Interrupts External interrupts Internal interrupts NMI (1) IRQ7 to IRQ0 (8) WDT*1 (1) Refresh timer*2 *3 (1) TPU (26) 8-bit timer (6) SCI (12) DTC (1) DMAC (4) A/D converter (1) Notes: Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. When the refresh timer is used as an interval timer, it generates an interrupt request at each compare match. 3. The refresh timer and DMAC are not supported in the H8S/2321. Figure 4.3 Interrupt Sources and Number of Interrupts

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 108 of 1268 REJ09B0220-0600

4.5 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 — — — 2 1 — — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution.

4.6 Stack Status aft er Exception Handling

Figure 4.4 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR PC (24 bits) CCR PC (24 bits) Reserved* EXR (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4.4 Stack Status after Exception Handling (Advanced Modes)

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 109 of 1268 REJ09B0220-0600

4.7 Notes on Use of the Stack

When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.5 shows an example of what happens when the SP value is odd. SP Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. SP SP CCR PC R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD MOV.B R1L, @–ER7 SP set to H'FFFEFF TRAP instruction executed Data saved above SP Contents of CCR lost Figure 4.5 Operation when SP Value is Odd

Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 110 of 1268 REJ09B0220-0600

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 111 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller

5.1 Overview

5.1.1 Features

The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. This chapter assumes the maximum number of interrupt sources available in these series—nine external interrupts and 52 internal interrupts.

• Two interrupt control modes ⎯ Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR)
• Priorities settable with IPRs ⎯ Interrupt priority registers (IPRs) are provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI ⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times
• Independent vector addresses ⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine
• Nine external interrupt pins ⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI ⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0
• DTC and DMAC* control ⎯ DTC and DMAC* activation is controlled by means of interrupts Note: * The DMAC is not supported in the H8S/2321.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 112 of 1268 REJ09B0220-0600

5.1.2 Block Diagram

A block diagram of the interrupt controller is shown in figure 5.1. NMI input IRQ input Internal interrupt request SWDTEND to TEI INTM1 INTM0 NMIEG NMI input unit IRQ input unit ISR ISCR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR: IRQ status register IPR: Interrupt priority register SYSCR: System control register SYSCR Figure 5.1 Block Diagram of Interrupt Controller

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 113 of 1268 REJ09B0220-0600

5.1.3 Pin Configuration

Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 7 to 0 IRQ7 to IRQ0 Input Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected

5.1.4 Register Configuration

Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers Name Abbreviation R/W Initial Value Address *1 System control register SYSCR R/W H'01 H'FF39 IRQ sense control register H ISCRH R/W H'00 H'FF2C IRQ sense control register L ISCRL R/W H'00 H'FF2D IRQ enable register IER R/W H'00 H'FF2E IRQ status register ISR R/(W) *2 H'00 H'FF2F Interrupt priority register A IPRA R/W H'77 H'FEC4 Interrupt priority register B IPRB R/W H'77 H'FEC5 Interrupt priority register C IPRC R/W H'77 H'FEC6 Interrupt priority register D IPRD R/W H'77 H'FEC7 Interrupt priority register E IPRE R/W H'77 H'FEC8 Interrupt priority register F IPRF R/W H'77 H'FEC9 Interrupt priority register G IPRG R/W H'77 H'FECA Interrupt priority register H IPRH R/W H'77 H'FECB Interrupt priority register I IPRI R/W H'77 H'FECC Interrupt priority register J IPRJ R/W H'77 H'FECD Interrupt priority register K IPRK R/W H'77 H'FECE Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 114 of 1268 REJ09B0220-0600

5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

Bit : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROD IRQPAS RAME Initial value : 0 0 0 0 0 0 0 1 R/W : R/W — R/W R/W R/W R/W R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3, MCU Operating Modes. SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 Bit 4 INTM0 Interrupt Control Mode 0 0 0 Interrupts are controlled by I bit (Initial value) 1 — Setting prohibited 1 0 2 Interrupts are controlled by bits I2 to I0, and IPR 1 — Setting prohibited Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG

0 Interrupt request generated at falling edge of NMI input (Initial value)

1 Interrupt request generated at rising edge of NMI input

Bit 1—IRQ Input Pin Select (IRQPAS): Selects switching of the pins that can be used for input of IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports.

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5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)

Bit : 7 6 5 4 3 2 1 0 — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : 0 1 1 1 0 1 1 1 R/W : — R/W R/W R/W — R/W R/W R/W The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3—Reserved: Read-only bits, always read as 0. Table 5.3 Correspondence between In terrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ2 IRQ3 IRQ4 IRQ5 IPRC IRQ6 IRQ7 DTC IPRD Watchdog timer Refresh timer IPRE — *1 A/D converter IPRF TPU channel 0 TPU channel 1 IPRG TPU channel 2 TPU channel 3 IPRH TPU channel 4 TPU channel 5 IPRI 8-bit timer channel 0 8-bit timer channel 1 IPRJ DMAC *2 SCI channel 0 IPRK SCI channel 1 SCI channel 2 Notes: 1. Reserved bits. 2. The refresh timer and DMAC are not supported in the H8S/2321.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 116 of 1268 REJ09B0220-0600 As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU.

5.2.3 IRQ Enable Register (IER)

Bit : 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE

0 IRQn interrupts disabled (Initial value)

1 IRQn interrupts enabled

(n = 7 to 0)

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 117 of 1268 REJ09B0220-0600

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)

Bit : 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W ISCRL Bit : 7 6 5 4 3 2 1 0 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W ISCR (composed of ISCRH and ISCRL) is a 16-bit readable/writable register that selects rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. ISCR is initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0—IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB IRQ7SCA to IRQ0SCA 0 0 Interrupt request generated at IRQ7 to IRQ0 input low level (Initial value)

1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input

1 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input

1 Interrupt request generated at both falling and rising edges of

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5.2.5 IRQ Status Register (ISR)

Bit : 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value : 0 0 0 0 0 0 0 0 R/W : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 [Clearing conditions] (Initial value)

• Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
• When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high
• When IRQn interrupt exception handling is executed when falling, rising, or both- edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
• When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 1 [Setting conditions]
• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
• When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0)

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 119 of 1268 REJ09B0220-0600

5.3 Interrupt Sources

Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources).

5.3.1 External Interrupts

There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to restore the chip from software standby mode. (IRQ7 to IRQ3 can be designated for use as software standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.) NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 121 of 1268 REJ09B0220-0600

5.3.2 Internal Interrupts

There are 52 sources for internal interrupts from on-chip supporting modules.

• For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC* and DTC can be activated by a TPU, SCI, or other interrupt request. When the DMAC* or DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect. Note: * The DMAC is not supported in the H8S/2321.

5.3.3 Interrupt Exception Vector Table

Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Interrupt sources can also be used to activate the DTC and DMAC*. Priorities among modules can be set by means of IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Note: * The DMAC is not supported in the H8S/2321.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 122 of 1268 REJ09B0220-0600 Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source Origin of Interrupt Source Vector Number Vector Address* IPR Priority DTC Activa- tion DMAC* Activa- tion Power-on reset 0 H'0000 — High — — Reserved 1 H'0004 Reserved for system 2 H'0008 use 3 H'000C

4 H'0010

Trace 5 H'0014 Reserved for system use

6 H'0018

7 H'001C

8 H'0020 Trap instruction

(4 sources) 9 H'0024

10 H'0028

11 H'002C

12 H'0030

13 H'0034

14 H'0038

15 H'003C

16 H'0040 IPRA6 to

IRQ1 17 H'0044 IPRA2 to IPRA0 IRQ2 18 H'0048 IPRB6 to — IRQ3 19 H'004C IPRB4 — IRQ4 20 H'0050 IPRB2 to — IRQ5 21 H'0054 IPRB0 — IRQ6 22 H'0058 IPRC6 to — IRQ7 23 H'005C IPRC4 Low —

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 123 of 1268 REJ09B0220-0600 Interrupt Source Origin of Interrupt Source Vector Number Vector Address* IPR Priority DTC Activa- tion DMAC* Activa- tion SWDTEND (software- activated data transfer end) DTC 24 H'0060 IPRC2 to IPRC0 High WOVI (interval timer) Watchdog timer

25 H'0064 IPRD6 to

— — CMI (compare match)*3 Refresh controller

26 H'0068 IPRD2 to

— — Reserved — 27 H'006C IPRE6 to IPRE4 — — ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to IPRE0 Reserved — 29 H'0074 H'0078 H'007C — — TGI0A (TGR0A input capture/compare match) TPU channel 0

32 H'0080 IPRF6 to

TGI0B (TGR0B input capture/compare match)

33 H'0084

TGI0C (TGR0C input capture/compare match)

34 H'0088

TGI0D (TGR0D input capture/compare match)

35 H'008C

TCI0V (overflow 0) 36 H'0090 — — Reserved — 37 H'0094 — —

38 H'0098

39 H'009C Low

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 124 of 1268 REJ09B0220-0600 Interrupt Source Origin of Interrupt Source Vector Number Vector Address* IPR Priority DTC Activa- tion DMAC* Activa- tion TGI1A (TGR1A input capture/compare match) TPU channel 1 H'00A0 IPRF2 to IPRF0 High TGI1B (TGR1B input capture/compare match) H'00A4 TCI1V (overflow 1) 42 H'00A8 — — TCI1U (underflow 1) 43 H'00AC — — TGI2A (TGR2A input capture/compare match) TPU channel 2 H'00B0 IPRG6 to IPRG4 TGI2B (TGR2B input capture/compare match) H'00B4 TCI2V (overflow 2) 46 H'00B8 — — TCI2U (underflow 2) 47 H'00BC — — TGI3A (TGR3A input capture/compare match) TPU channel 3

48 H'00C0 IPRG2 to

TGI3B (TGR3B input capture/compare match)

49 H'00C4

TGI3C (TGR3C input capture/compare match) H'00C8 TGI3D (TGR3D input capture/compare match)

51 H'00CC

TCI3V (overflow 3) 52 H'00D0 — — Reserved — 53 H'00D4 H'00D8 H'00DC Low — —

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 125 of 1268 REJ09B0220-0600 Interrupt Source Origin of Interrupt Source Vector Number Vector Address* IPR Priority DTC Activa- tion DMAC* Activa- tion TGI4A (TGR4A input capture/compare match) TPU channel 4

56 H'00E0 IPRH6 to

TGI4B (TGR4B input capture/compare match)

57 H'00E4

TCI4V (overflow 4) 58 H'00E8 — — TCI4U (underflow 4) 59 H'00EC — — TGI5A (TGR5A input capture/compare match) TPU channel 5

60 H'00F0 IPRH2 to

TGI5B (TGR5B input capture/compare match)

61 H'00F4

TCI5V (overflow 5) 62 H'00F8 — — TCI5U (underflow 5) 63 H'00FC — — CMIA0 (compare match A) 8-bit timer channel 0

64 H'0100 IPRI6 to

CMIB0 (compare match B)

65 H'0104

OVI0 (overflow 0) 66 H'0108 — — Reserved — 67 H'010C — — CMIA1 (compare match A) 8-bit timer channel 1

68 H'0110 IPRI2 to

CMIB1 (compare match B)

69 H'0114

OVI1 (overflow 1) 70 H'0118 — — Reserved — 71 H'011C Low — —

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 126 of 1268 REJ09B0220-0600 Interrupt Source Origin of Interrupt Source Vector Number Vector Address* IPR Priority DTC Activa- tion DMAC* Activa- tion DEND0A (channel 0/channel 0A transfer end)* DMAC 72 H'0120 IPRJ6 to IPRJ4 High — DEND0B (channel 0B transfer end) *3

73 H'0124 —

DEND1A (channel 1/channel 1A transfer end) H'0128 DEND1B (channel 1B transfer end) *3

75 H'012C —

Reserved — 76 H'0130 H'0134 H'0138 H'013C — — ERI0 (receive error 0) 80 H'0140 IPRJ2 to — — RXI0 (reception data full 0) SCI channel 0 81 H'0144 IPRJ0 TXI0 (transmit data empty 0)

82 H'0148

TEI0 (transmit end 0) 83 H'014C — — ERI1 (receive error 1) 84 H'0150 IPRK6 to — — RXI1 (reception data full 1) SCI channel 1 85 H'0154 IPRK4 TXI1 (transmit data empty 1)

86 H'0158

TEI1 (transmit end 1) 87 H'015C — — ERI2 (receive error 2) 88 H'0160 IPRK2 to — — RXI2 (reception data full 2) SCI channel 2 89 H'0164 IPRK0 TXI2 (transmit data empty 2)

90 H'0168

TEI2 (transmit end 2) 91 H'016C Low — — Notes: 1. Lower 16 bits of the start address. 2. The DMAC is not supported in the H8S/2321. 3. Reserved in the H8S/2321.

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5.4 Interrupt Operation

5.4.1 Interrupt Control Modes and Interrupt Operation

Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I bit in the CPU’s CCR, and bits I2 to I0 in EXR. Table 5.5 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Priority Setting Registers Interrupt Mask Bits Description 0 0 0 — I Interrupt mask control is performed by the I bit. — 1 — — Setting prohibited 2 1 0 IPR I2 to I0 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. — 1 — — Setting prohibited

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 128 of 1268 REJ09B0220-0600 Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt acceptance control 8-level mask control Default priority determination Vector number Interrupt control mode 2 IPR Interrupt source I2 to I0 Interrupt control mode 0 I Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts

1 NMI interrupts

2 * All interrupts *: Don't care

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 129 of 1268 REJ09B0220-0600 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt Control Mode Selected Interrupts

0 All interrupts

2 Highest-priority-level (IPR) interrupt whose priority level is greater

than the mask level (IPR > I2 to I0) Default Priority Determination: When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode. Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Setting Interrupt Acceptance Control 8-Level Control Interrupt Control Mode INTM1 INTM0 I I2 to I0 IPR Default Priority Determination T (Trace) 0 0 0 IM X — — *2 — 2 1 0 X — *1 IM PR T Legend: : Interrupt operation control performed X: No operation (All interrupts enabled) IM: Used as interrupt mask bit PR: Sets priority —: Not used Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting.

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5.4.2 Interrupt Control Mode 0

Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 131 of 1268 REJ09B0220-0600 Program execution state Interrupt generated? NMI? IRQ0? IRQ1? TEI2? I = 0? Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0

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5.4.3 Interrupt Control Mode 2

Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 133 of 1268 REJ09B0220-0600 Yes Program execution state Interrupt generated? NMI? Level 6 interrupt? Mask level 5 or below? Level 7 interrupt? Mask level 6 or below? Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt? Mask level 0? Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 134 of 1268 REJ09B0220-0600

5.4.4 Interrupt Exception Handling Sequence

Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 135 of 1268 REJ09B0220-0600 Interrupt handling routine instruction prefetch Internal operationVector fetchStack Instruction prefetch Internal operation Interrupt acceptance Interrupt level determination Wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus φ (3) (1) (2), (4) (3) (5) (7) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4 Saved PC and saved CCR Vector address Interrupt handling routine start address (vector address contents) Interrupt handling routine start address ((13) = (10), (12)) First instruction of interrupt handling routine (6), (8) (9), (11) (10), (12) (13) (14) Figure 5.7 Interrupt Exception Handling

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 136 of 1268 REJ09B0220-0600

5.4.5 Interrupt Response Times

The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.9 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times Advanced Mode No. Item INTM1 = 0 INTM1 = 1

1 Interrupt priority determination *1 3 3

2 Number of wait states until executing

instruction ends*2 1 to (19 + 2·SI) 1 to (19 + 2·S I)

3 PC, CCR, EXR stack save 2·S K 3·S K

4 Vector fetch 2·S I 2·S I

5 Instruction fetch *3 2·S I 2·S I

6 Internal processing *4 2 2

Total (using on-chip memory) 12 to 32 13 to 33 Notes: 1. Two states in case of internal interrupt. 2. Refers to MULXS and DIVXS instructions. 3. Prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.10 Number of States in In terrupt Handling Routine Execution Object of Access External Device 8-Bit Bus 16-Bit Bus Symbol Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch S I 1 4 6 + 2m 2 3 + m Branch address read S J Stack manipulation S K Legend: m: Number of wait states in an external device access.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 137 of 1268 REJ09B0220-0600

5.5 Usage Notes

5.5.1 Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5.8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0. Internal address bus Internal write signal φ TGIEA TGFA TGI0A interrupt signal TIER0 write cycle by CPU TGI0A exception handling TIER0 address Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.

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5.5.2 Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.

5.5.3 Times when Interrupts Are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

5.5.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1

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5.6 DTC and DMAC Activation by Interrupt

5.6.1 Overview

The DTC and DMAC* can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Activation request to DMAC * 4. Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC or DMAC *, see section 8, Data Transfer Controller, and section 7, DMA Controller. Note: * The DMAC is not supported in the H8S/2321.

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5.6.2 Block Diagram

Figure 5.9 shows a block diagram of the DTC, DMAC*, and interrupt controller. Note: * The DMAC is not supported in the H8S/2321. DMAC* Selection circuit DTCER DTVECR Control logic Determination of priority CPU DTC DTC activation request vector number Clear signal CPU interrupt request vector number Select signal Interrupt request Interrupt source clear signal IRQ interrupt Note: * The DMAC is not supported in the H8S/2321. On-chip supporting module Disable signal Clear signal Clear signal Interrupt controller I, I2 to I0 SWDTE clear signal Figure 5.9 Interrupt Control for DTC and DMAC*

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5.6.3 Operation

The interrupt controller has three main functions in DTC and DMAC* control. Selection of Interrupt Source: With the DMAC*, the activation source is input directly to each channel. The activation source for each DMAC* channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is to be managed by the DMAC * can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt source constituting that DMAC* activation source is not a DTC activation source or CPU interrupt source. For interrupt sources other than interrupts managed by the DMAC*, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective priorities. With the DMAC*, the activation source is input directly to each channel. Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as a DMAC* activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5.11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC*, the DTCE bit of DTCERA to DTCERF in the DTC, and the DISEL bit of MRB in the DTC. Note: * The DMAC is not supported in the H8S/2321.

Section 5 Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 142 of 1268 REJ09B0220-0600 Table 5.11 Interrupt Source Se lection and Clearing Control Settings DMAC DTC Interrupt Source Selection/Clearing Control DTA DTCE DISEL DMAC *1 DTC CPU 0 0 * X 1 0 X 1 * * X X Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X: The relevant interrupt cannot be used. *: Don't care Note: 1. The DMAC is not supported in the H8S/2321. Usage Note: SCI and A/D converter interrupt sources are cleared when the DMAC* or DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit. Note: * The DMAC is not supported in the H8S/2321.

Rev.6.00 Sep. 27, 2007 Page 143 of 1268 REJ09B0220-0600 Section 6 Bus Controller

6.1 Overview

The chip has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC)*, and data transfer controller (DTC). Note: * The DMAC is not supported in the H8S/2321.

6.1.1 Features

The features of the bus controller are listed below.

• Manages external address space in area units ⎯ In advanced mode, manages the external space as 8 areas of 2 Mbytes ⎯ Bus specifications can be set independently for each area ⎯ DRAM*/burst ROM interfaces can be set
• Basic bus interface ⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7 ⎯ 8-bit access or 16-bit access can be selected for each area ⎯ 2-state access or 3-state access can be selected for each area ⎯ Program wait states can be inserted for each area
• DRAM interface* ⎯ DRAM interface can be set for areas 2 to 5 (in advanced mode) ⎯ Row address/column address multiplexed output (8/9/10 bits) ⎯ 2-CAS access method ⎯ Burst operation (fast page mode) ⎯ T P cycle insertion to secure RAS precharging time ⎯ Choice of CAS-before-RAS refreshing or self-refreshing
• Burst ROM interface ⎯ Burst ROM interface can be set for area 0 ⎯ Choice of 1- or 2-state burst access

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• Idle cycle insertion ⎯ An idle cycle can be inserted in case of an external read cycle between different areas ⎯ An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle
• Write buffer functions ⎯ External write cycle and internal access can be executed in parallel ⎯ DMAC* single address mode and internal access can be executed in parallel
• Bus arbitration function ⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
• Other features ⎯ Refresh counter (refresh timer)* can be used as an interval timer ⎯ External bus release function Note: * The DRAM interface, DMAC, and refresh counter are not supported in the H8S/2321.

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6.1.2 Block Diagram

Figure 6.1 shows a block diagram of the bus controller. Area decoder Bus controller ABWCR ASTCR BCRH BCRL Internal address bus CS0 to CS7 External bus control signals BREQ BACK BREQO Internal control signals Wait controller WCRH WCRL Bus mode signal DRAM controller* RTCNT RTCOR DRAMCR MCR Bus arbiter CPU bus request signal DTC bus request signal DMAC bus request signal* CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal* External DRAM signals* Note: * Not supported in the H8S/2321. WAIT Internal data bus Figure 6.1 Block Diagram of Bus Controller

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6.1.3 Pin Configuration

Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write/write enable HWR Output Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. 2-CAS DRAM write enable signal*. Low write LWR Output Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Chip select 0 CS0 Output Strobe signal indicating that area 0 is selected. Chip select 1 CS1 Output Strobe signal indicating that area 1 is selected. Chip select 2/row address strobe 2 CS2 Output Strobe signal indicating that area 2 is selected. DRAM row address strobe signal when area 2 is in DRAM space*. Chip select 3/row address strobe 3 CS3 Output Strobe signal indicating that area 3 is selected. DRAM row address strobe signal when area 3 is in DRAM space*. Chip select 4/row address strobe 4 CS4 Output Strobe signal indicating that area 4 is selected. DRAM row address strobe signal when area 4 is in DRAM space*. Chip select 5/row address strobe 5 CS5 Output Strobe signal indicating that area 5 is selected. DRAM row address strobe signal when area 5 is in DRAM space*.

Rev.6.00 Sep. 27, 2007 Page 147 of 1268 REJ09B0220-0600 Name Symbol I/O Function Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected. Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected. Upper column address strobe CAS* Output 2-CAS DRAM upper column address strobe signal. Lower column strobe LCAS* Output DRAM lower column address strobe signal. Wait WAIT Input Wait request signal when accessing external 3-state access space. Bus request BREQ Input Request signal that releases bus to external device. Bus request acknowledge BACK Output Acknowledge signal indicating that bus has been released. Bus request output BREQO Output External bus request signal used when internal bus master accesses external space when external bus is released. Note: * The DRAM interface and the CAS and LCAS pin functions are not supported in the H8S/2321.

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6.1.4 Register Configuration

Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Initial Value Name Abbreviation R/W Reset Address *1 Bus width control register ABWCR R/W H'FF/H'00 *2 H'FED0 Access state control register ASTCR R/W H'FF H'FED1 Wait control register H WCRH R/W H'FF H'FED2 Wait control register L WCRL R/W H'FF H'FED3 Bus control register H BCRH R/W H'D0 H'FED4 Bus control register L BCRL R/W H'3C H'FED5 Memory control register MCR *3 R/W H'00 H'FED6 DRAM control register DRAMCR *3 R/W H'00 H'FED7 Refresh timer counter RTCNT *3 R/W H'00 H'FED8 Refresh time constant register RTCOR *3 R/W H'FF H'FED9 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. 3. In the H8S/2321 this register is reserved and must not be accessed.

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6.2 Register Descriptions

6.2.1 Bus Width Control Register (ABWCR)

Bit : 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Mode 4 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7, * and to H'00 in mode 4. It is not initialized in software standby mode. Note: * Modes 6 and 7 are not provided in the ROMless version. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn

0 Area n is designated for 16-bit access

1 Area n is designated for 8-bit access

(n = 7 to 0)

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6.2.2 Access State Control Register (ASTCR)

Bit : 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn

0 Area n is designated for 2-state access

Wait state insertion in area n external space is disabled

1 Area n is designated for 3-state access (Initial value)

Wait state insertion in area n external space is enabled (n = 7 to 0)

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6.2.3 Wait Control Registers H and L (WCRH, WCRL)

WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. WCRH Bit : 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 Bit 6 W70 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (Initial value)

Rev.6.00 Sep. 27, 2007 Page 152 of 1268 REJ09B0220-0600 Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 Bit 4 W60 0 0 Program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 Bit 2 W50 0 0 Program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 Bit 0 W40 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (Initial value)

Rev.6.00 Sep. 27, 2007 Page 153 of 1268 REJ09B0220-0600 WCRL Bit : 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 Bit 6 W30 0 0 Program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 Bit 4 W20 0 0 Program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (Initial value)

Rev.6.00 Sep. 27, 2007 Page 154 of 1268 REJ09B0220-0600 Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 Bit 2 W10 0 0 Program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 Bit 0 W00 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (Initial value)

6.2.4 Bus Control Register H (BCRH)

Bit : 7 6 5 4 3 2 1 0 ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2 * RMTS1* RMTS0 * Initial value : 1 1 0 1 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Note: * This bit is reserved in the H8S/2321. BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 155 of 1268 REJ09B0220-0600 Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1

0 Idle cycle not inserted in case of successive external read cycles in different areas

1 Idle cycle inserted in case of successive external read cycles in different areas

(Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . Bit 6 ICIS0

0 Idle cycle not inserted in case of successive external read and external write cycles

1 Idle cycle inserted in case of successive external read and external write cycles

(Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface area. Bit 5 BRSTRM

0 Area 0 is basic bus interface area (Initial value)

1 Area 0 is burst ROM interface area

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1

0 Burst cycle comprises 1 state

1 Burst cycle comprises 2 states (Initial value)

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.

Rev.6.00 Sep. 27, 2007 Page 156 of 1268 REJ09B0220-0600 Bit 3 BRSTS0 0 Max. 4 words in burst access (Initial value) 1 Max. 8 words in burst access Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as a DRAM interface area. In the H8S/2321 these bits are reserved and should only be written with 0. Bit 2 Bit 1 Bit 0 Description RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 0 Normal space

1 Normal space DRAM space

1 0 Normal space DRAM space

1 DRAM space

1 — — — The LCAS pin is used for the LCAS signal on the 2-CAS DRAM interface. If it is wished to use BREQO output and WAIT input when using the LCAS signal, it is possible to switch to the P53 pin by means of the BREQOPS bit in PFCR2. For details, see section 9.6, Port 5 and section 9.13, Port F. Note: This note applies to the H8S/2323 only. If all areas selected as DRAM space are 8-bit space, the PF2 pin can be used as an I/O port, or as the BREQ0 or WAIT pin. However, if PF2 is used as the WAIT pin on the H8S/2323 only, normal space other than DRAM space should be designated as 16-bit bus space. The RAS down mode cannot be used in this case. Sample settings are shown below. RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 0 Normal space

1 Normal space

(16-bit bus) DRAM space (8-bit bus) 1 0 Normal space (16-bit bus) DRAM space (8-bit bus) (8-bit bus)

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6.2.5 Bus Control Register L (BCRL)

Bit : 7 6 5 4 3 2 1 0 BRLE BREQOE EAE — DDS * — WDBE * WAITE Initial value : 0 0 1 1 1 1 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Note: * This bit is reserved in the H8S/2321. BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O ports (Initial value)

1 External bus release is enabled

Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE 0 BREQO output disabled. BREQO pin can be used as I/O port (Initial value)

1 BREQO output enabled

Rev.6.00 Sep. 27, 2007 Page 158 of 1268 REJ09B0220-0600 Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*2 are to be internal addresses or external addresses. H8S/2329B, H8S/2328*3, H8S/2326 H8S/2327 H8S/2323

0 On-chip ROM Addresses H'010000 to

H'01FFFF are on-chip ROM or address H'020000 to H'03FFFF are reserved area* Reserved area*1

1 Addresses H'010000 to H'03FFFF *2 are external addresses in external expanded mode

or reserved area*1 in single-chip mode (Initial value) Notes: 1. Do not access a reserved area. 2. Addresses H'010000 to H'05FFFF in the H8S/2329B. Addresses H'010000 to H'07FFFF in the H8S/2326. 3. H8S/2328B in F-ZTAT version. Bit 4—Reserved: Only 1 should be written to this bit. Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface. In the H8S/2321 this bit is reserved and should only be written with 1. Bit 3 DDS

0 When DMAC single address transfer is performed in DRAM space, full access is

DACK signal goes low from T r or T1 cycle

1 Burst access is possible when DMAC single address transfer is performed in DRAM

DACK signal goes low from Tc1 or T2 cycle (Initial value) Bit 2—Reserved: Only 1 should be written to this bit.

Rev.6.00 Sep. 27, 2007 Page 159 of 1268 REJ09B0220-0600 Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle. In the H8S/2321 this bit is reserved and should only be written with 0. Bit 1 WDBE

0 Write data buffer function not used (Initial value)

1 Write data buffer function used

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 Wait input by WAIT pin disabled. WAIT pin can be used as I/O port (Initial value)

1 Wait input by WAIT pin enabled

6.2.6 Memory Control Register (MCR)

Bit : 7 6 5 4 3 2 1 0 TPC BE RCDM — MXC1 MXC0 RLW1 RLW0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5 are designated as DRAM interface areas. MCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed.

Rev.6.00 Sep. 27, 2007 Page 160 of 1268 REJ09B0220-0600 Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (TP) is to be used when areas 2 to 5 designated as DRAM space are accessed. Bit 7 TPC 0 1-state precharge cycle is inserted (Initial value) 1 2-state precharge cycle is inserted Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM space. DRAM space burst access is performed in fast page mode. Bit 6 BE

0 Burst disabled (always full access) (Initial value)

1 For DRAM space access, access in fast page mode

Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode). Bit 5 RCDM

0 DRAM interface: RAS up mode selected (Initial value)

1 DRAM interface: RAS down mode selected

Bit 4—Reserved: Only 0 should be written to this bit. Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM interface, these bits also select the row address to be used for comparison.

Rev.6.00 Sep. 27, 2007 Page 161 of 1268 REJ09B0220-0600 Bit 3 MXC1 Bit 2 MXC0 0 0 8-bit shift (Initial value)

• When 8-bit access space is designated: Row address A 23 to A8 used for comparison
• When 16-bit access space is designated: Row address A 23 to A9 used for comparison 1 9-bit shift
• When 8-bit access space is designated: Row address A 23 to A9 used for comparison
• When 16-bit access space is designated: Row address A 23 to A10 used for comparison 1 0 10-bit shift
• When 8-bit access space is designated: Row address A 23 to A10 used for comparison
• When 16-bit access space is designated: Row address A 23 to A11 used for comparison 1 — Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled. Bit 1 RLW1 Bit 0 RLW0

0 0 No wait state inserted (Initial value) 1 1 wait state inserted 1 0 2 wait states inserted 1 3 wait states inserted

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6.2.7 DRAM Control Register (DRAMCR)

Bit : 7 6 5 4 3 2 1 0 RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed. Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not performed, the refresh timer can be used as an interval timer. Bit 7 RFSHE

0 Refresh control is not performed (Initial value)

1 Refresh control is performed

Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before- RAS refreshing. Bit 6 RCW

0 Wait state insertion in CAS-before-RAS refreshing disabled (Initial value)

1 One wait state inserted in CAS-before-RAS refreshing

Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), selects whether or not self-refresh control is performed in software standby mode. Bit 5 RMODE

0 Self-refreshing is not performed in software standby mode (Initial value)

1 Self-refreshing is performed in software standby mode

Rev.6.00 Sep. 27, 2007 Page 163 of 1268 REJ09B0220-0600 Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 CMF 0 [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag (Initial value) 1 [Setting condition] Set when RTCNT = RTCOR Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0. Bit 3 CMIE

0 Interrupt request (CMI) by CMF flag disabled (Initial value)

1 Interrupt request (CMI) by CMF flag enabled

Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 internal clocks obtained by dividing the system clock ( φ). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 0 0 0 Count operation disabled (Initial value)

1 Count uses φ/2

1 0 Count uses φ/8

1 Count uses φ/32

1 0 0 Count uses φ/128

1 Count uses φ/512

1 0 Count uses φ/2048

1 Count uses φ/4096

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6.2.8 Refresh Timer Counter (RTCNT)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in DRAMCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed.

6.2.9 Refresh Time Constant Register (RTCOR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed.

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6.3 Overview of Bus Control

6.3.1 Area Partitioning

In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area. Area 0 (2 Mbytes) H'000000 H'FFFFFF H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) Advanced mode Figure 6.2 Overview of Area Partitioning

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6.3.2 Bus Specifications

The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM interface* and burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. Note: * The DRAM interface is not supported in the H8S/2321. Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area.

Rev.6.00 Sep. 27, 2007 Page 167 of 1268 REJ09B0220-0600 Table 6.3 Bus Specifications for Ea ch Area (Basic Bus Interface) WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWCR ABWn ASTCR ASTn Wn1 Wn0 Bus Width Access States Program Wait States 0 0 — — 16 2 0 1 0 0 3 0 1 1 1 0 2 1 3 1 0 — — 8 2 0 1 0 0 3 0 1 1 1 0 2 1 3

6.3.3 Memory Interfaces

The chip’s memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface* that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface* is designated functions as DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. Note: * The DRAM interface is not supported in the H8S/2321.

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6.3.4 Advanced Mode

The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.4, Basic Bus Interface, 6.5, DRAM Interface (Not supported in the H8S/2321), and 6.7, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM* 1, and in ROM-disabled expansion mode, all of area 0 is external space. In the ROM-enabled expansion mode, the space excluding on-chip ROM *1 is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 and 6: In external expansion mode, all of area 1 and area 6 is external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. Areas 2 to 5: In external expansion mode, all of area 2 to area 5 is external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface*2 can be selected for areas 2 to 5. With the DRAM interface*2, signals CS2 to CS5 are used as RAS signals. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. Notes: 1. Only applies to versions with ROM. 2. The DRAM interface is not supported in the H8S/2321.

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6.3.5 Chip Select Signals

The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin and either the CS167 enable bit (CS167E) or the CS25 enable bit (CS25E). In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power- on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. When areas 2 to 5 are designated as DRAM space*, outputs CS2 to CS5 are used as RAS signals. Note: * The DRAM interface is not supported in the H8S/2321. Bus cycle T1 T2 T3 Area n external addressAddress bus φ CSn Figure 6.3 CSn Signal Output Timing (n = 0 to 7)

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6.4 Basic Bus Interface

6.4.1 Overview

The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL. (See table 6.3.)

6.4.2 Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. D15 D8 D7 D0 Upper data bus Lower data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space)

Rev.6.00 Sep. 27, 2007 Page 171 of 1268 REJ09B0220-0600 16-Bit Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. D15 D8 D7 D0 Upper data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size

• Even address Byte size  Odd address Lower data bus Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space)

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6.4.3 Valid Strobes

Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4 Data Buses Used and Valid Strobes Area Access Size Read/ Write Address Valid Strobe Upper Data Bus 15 to D8) Lower Data Bus 7 to D0) Byte Read — RD Valid Invalid 8-bit access space Write — HWR Hi-Z Byte Read Even RD Valid Invalid 16-bit access space Odd Invalid Valid Write Even HWR Valid Hi-Z Odd LWR Hi-Z Valid Word Read — RD Valid Valid Write — HWR, LWR Valid Valid Notes: Hi-Z: High impedance Invalid: Input state; input value is ignored.

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6.4.4 Basic Timing

8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write Note: n = 0 to 7 High Figure 6.6 Bus Timing for 8-Bit 2-State Access Space

Rev.6.00 Sep. 27, 2007 Page 174 of 1268 REJ09B0220-0600 8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Note: n = 0 to 7 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space

Rev.6.00 Sep. 27, 2007 Page 175 of 1268 REJ09B0220-0600 16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Note: n = 0 to 7 Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)

Rev.6.00 Sep. 27, 2007 Page 176 of 1268 REJ09B0220-0600 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write Note: n = 0 to 7 High Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)

Rev.6.00 Sep. 27, 2007 Page 177 of 1268 REJ09B0220-0600 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note: n = 0 to 7 Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)

Rev.6.00 Sep. 27, 2007 Page 178 of 1268 REJ09B0220-0600 16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Note: n = 0 to 7 Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)

Rev.6.00 Sep. 27, 2007 Page 179 of 1268 REJ09B0220-0600 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write High Note: n = 0 to 7 Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)

Rev.6.00 Sep. 27, 2007 Page 180 of 1268 REJ09B0220-0600 Bus cycle T1 T2 Address bus φ CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note: n = 0 to 7 Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)

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6.4.5 Wait Control

When accessing external space, the chip can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion: Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, program wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. The WAITPS bit can be used to change the WAIT input pin from PF 2 to P53. To make this change, select the input pin with the WAITPS bit, then set the WAITE bit.

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6.5 DRAM Interface (Not suppo rted in the H8S/2321)

6.5.1 Overview

When the chip is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the chip. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode.

6.5.2 Setting DRAM Space

Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6.5 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 1 Normal space DRAM space 1 0 Normal space DRAM space

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6.5.3 Address Multiplexing

With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6 shows the relation between the settings of MXC1 and MXC0 and the shift size. Table 6.6 Address Multiplexing Settings by Bits MXC1 and MXC0 MCR Shift Address Pins MXC1 MXC0 Size A23 to A13 A12 A11 A10 A9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 0 0 8 bits A 23 to A13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A 10 A 9 A 8 1 9 bits A 23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A 11 A 10 A 9 1 0 10 bits A 23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A 12 A 11 A 10 Row address

1 Setting

— — — A 23 to A13 A12 A11 A10 A9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0

6.5.4 Data Bus

If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface. For details, see section 6.4.2, Data Size and Data Alignment.

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6.5.5 Pins Used for DRAM Interface

Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 DRAM Interface Pins Pin With DRAM Setting Name I/O Function HWR WE Write enable Output When 2-CAS system is set, write enable for DRAM space access LCAS LCAS Lower column address strobe Output Lower column address strobe for 16-bit DRAM space access CS2 RAS2 Row address strobe 2 Output Row address strobe when area 2 is designated as DRAM space CS3 RAS3 Row address strobe 3 Output Row address strobe when area 3 is designated as DRAM space CS4 RAS4 Row address strobe 4 Output Row address strobe when area 4 is designated as DRAM space CS5 RAS5 Row address strobe 5 Output Row address strobe when area 5 is designated as DRAM space CAS UCAS Upper column address strobe Output Upper column address strobe for DRAM space access WAIT WAIT Wait Input Wait request signal A12 to A0 A 12 to A0 Address pins Output Ro w address/column address multiplexed output D15 to D0 D 15 to D0 Data pins I/O Data input/output pins

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6.5.6 Basic Timing

Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle. The 4 states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle), and two Tc (column address output cycle) states, Tc1 and Tc2. Tp φ CSn (RAS) Read Write CAS, LCAS HWR (WE) D15 to D0 HWR (WE) D15 to D0 A23 to A0 Tr Tc1 Tc2 Row Column Note: n = 2 to 5 Figure 6.15 Basic Access Timing

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6.5.7 Precharge State Control

When DRAM is accessed, an RAS precharging time must be secured. With the chip, one T p state is always inserted when DRAM space is accessed. This can be changed to two T p states by setting the TPC bit in MCR to 1. Set the appropriate number of Tp cycles according to the DRAM connected and the operating frequency of the chip. Figure 6.16 shows the timing when two T p states are inserted. When the TCP bit is set to 1, two Tp states are also used for refresh cycles. Tp1 φ CSn (RAS) Read Write CAS, LCAS D15 to D0 D15 to D0 A23 to A0 Tp2 Tr Tc1 Row Column Tc2 HWR (WE) HWR (WE) Note: n = 2 to 5 Figure 6.16 Timing with 2-State Precharge Cycle

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6.5.8 Wait Control

There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings of WCRH and WCRL. Pin Wait Insertion: When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figure 6.17 shows an example of wait state insertion timing.

Rev.6.00 Sep. 27, 2007 Page 189 of 1268 REJ09B0220-0600 By program wait Tp Address bus φ CSn (RAS) CAS Data bus Read data Read CAS Write data Write WAIT* Data bus Tr Tc1 Tw Tw Tc2 By WAIT pin Notes: indicates the timing of WAIT pin sampling. n = 2 to 5 Figure 6.17 Example of Wait State Insertion Timing

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6.5.9 Byte Access Control

When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. Figure 6.18 shows the control timing in the 2-CAS system, and figure 6.19 shows an example of 2-CAS type DRAM connection. Tp φ CSn (RAS) Byte control A23 to A0 Tr Tc1 Tc2 Row CAS LCAS HWR (WE) Column Note: n = 2 to 5 Figure 6.18 2-CAS System Control Timing (Upper Byte Write Access)

Rev.6.00 Sep. 27, 2007 Page 191 of 1268 REJ09B0220-0600 Chip (Address shift size set to 9 bits) CS (RAS) 2-CAS type 4-Mbit DRAM 256-kbyte × 16-bit configuration 9-bit column address OE RAS CAS UCAS LCAS LCAS HWR (WE) WE A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 D15 to D0 Row address input: A8 to A0 Column address input: A 8 to A0 Figure 6.19 Example of 2-CAS DRAM Connection

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6.5.10 Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1. Burst Access (Fast Page Mode) Operation Timing: Figure 6.20 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC1 and MXC0 in MCR. Tp φ CSn (RAS) Read Write CAS, LCAS HWR (WE) D15 to D0 HWR (WE) D15 to D0 A23 to A0 Tr Tc1 Tc2 Row Column 1 Column 2 Tc1 Tc2 Note: n = 2 to 5 Figure 6.20 Operation Timing in Fast Page Mode The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details, see section 6.5.8, Wait Control.

Rev.6.00 Sep. 27, 2007 Page 193 of 1268 REJ09B0220-0600 RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again.

• RAS down mode To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.21 shows an example of the timing in RAS down mode. Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down mode. External space access Tp A23 to A0 φ CSn (RAS) CAS, LCAS D15 to D0 Tr Tc1 Tc2 T1 T2 DRAM accessDRAM access Tc1 Tc2 Note: n = 2 to 5 Figure 6.21 Example of Operation Timing in RAS Down Mode

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• RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.22 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level. CSn (RAS) CAS, LCAS External space access Tp A23 to A0 φ D15 to D0 Tr Tc1 Tc2 Tc1 Tc2 DRAM accessDRAM access T1 T2 Note: n = 2 to 5 Figure 6.22 Example of Operation Timing in RAS Up Mode

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6.5.11 Refresh Control

The chip is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Do not clear the CMF flag when refresh control is being performed (RFSHE = 1). RTCNT operation is shown in figure 6.23, compare match timing in figure 6.24, and CBR refresh timing in figure 6.25. Access to other normal space can be performed during the CBR refresh interval. RTCOR H'00 Refresh request RTCNT Figure 6.23 RTCNT Operation

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6.6 DMAC Single Address Mo de and DRAM Interface

(Not supported in the H8S/2321) When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, this bit selects whether or not burst access is to be performed.

6.6.1 When DDS = 1

Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low from the TC1 state in the case of the DRAM interface. Figure 6.28 shows the DACK output timing for the DRAM interface when DDS = 1. Tp φ Read Write CSn (RAS) HWR (WE) D15 to D0 HWR (WE) DACK D15 to D0 A23 to A0 Tr Tc1 Tc2 Row CAS (UCAS) LCAS (LCAS) Column Note: n = 2 to 5 Figure 6.28 DACK Output Timing when DDS = 1 (Example of DRAM Access)

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6.6.2 When DDS = 0

When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6.29 shows the DACK output timing for the DRAM interface when DDS = 0. Tp φ Read Write CSn (RAS) HWR (WE) D15 to D0 HWR (WE) DACK D15 to D0 A23 to A0 Tr Tc1 Tc2 Row CAS (UCAS) LCAS (LCAS) Column Note: n = 2 to 5 Figure 6.29 DACK Output Timing when DDS = 0 (Example of DRAM Access)

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6.7 Burst ROM Interface

6.7.1 Overview

With the chip, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access.

6.7.2 Basic Timing

The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6.30 (a) and (b). The timing shown in figure 6.30 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6.30 (b) is for the case where both these bits are cleared to 0.

Rev.6.00 Sep. 27, 2007 Page 201 of 1268 REJ09B0220-0600 Address bus φ CS0 AS Data bus T2 T3 T1 T2 T1 Full access RD Burst access Only lower address changed Read data Read data Read data Figure 6.30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)

Rev.6.00 Sep. 27, 2007 Page 202 of 1268 REJ09B0220-0600 Address bus φ CS0 AS Data bus T2 T1 T1 Full access RD Burst access Only lower address changed Read data Read data Read data Figure 6.30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)

6.7.3 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle.

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6.8 Idle Cycle

6.8.1 Operation

When the chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high- speed memory, I/O interfaces, and so on. Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6.31 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Address bus φ RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Bus cycle A Bus cycle B Long output floating time Data collision (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (ICIS1 = 1 (initial value)) Address bus φ RD Data bus T2 T3 TI T1 T2 CS (area A) CS (area B) CS (area A) CS (area B) Figure 6.31 Example of Idle Cycle Operation (1)

Rev.6.00 Sep. 27, 2007 Page 206 of 1268 REJ09B0220-0600 Usage Notes: When DRAM space* is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access*, only a Tp cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6.34. However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this case is shown in figures 6.35 (a) and (b). Note: * The DRAM interface is not supported in the H8S/2321. Address bus φ RD External read Data bus T2 T3 Tp Tr DRAM space read Tc1 Tc2 Figure 6.34 Example of DRAM Access after External Read

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6.8.2 Pin States in Idle Cycle

Table 6.8 shows the pin states in an idle cycle. Table 6.8 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 High impedance CSn*2 High *1 CAS*4 High AS High RD High HWR High LWR High DACKm*3 *4 High Notes: 1. Remains low in DRAM space RAS down mode or a refresh cycle. 2. n = 0 to 7 3. m = 0 and 1 4. The CAS and DACKm pin functions are not supported in the H8S/2321.

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6.9 Write Data Buffer Function

The chip has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6.36 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write or DMA single address mode transfer* continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. Note: * The DMAC is not supported in the H8S/2321. Internal address bus A23 to A0 External write cycle HWR, LWR T2 TW TW T3 On-chip memory read Internal I/O register read Internal read signal CSn D15 to D0 External address Internal memory External space write Internal I/O register address Note: n = 0 to 7 Figure 6.36 Example of Timing when Write Data Buffer Function is Used

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6.10 Bus Release

6.10.1 Overview

The chip can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request* is generated, it can issue a bus request off-chip. The BREQOPS bit can be used to change the BREQO output pin from PF2 to P53. Note: * The DRAM interface is not supported in the H8S/2321.

6.10.2 Operation

In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the chip. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Even if a refresh request* is generated in the external bus released state, refresh control * is deferred until the external bus master drops the bus request. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, or when a refresh request* is generated, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > Intern al bus master external access (Low)

Rev.6.00 Sep. 27, 2007 Page 211 of 1268 REJ09B0220-0600 If a refresh request* and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh * > External bus release (Low) As a refresh* and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The DRAM interface is not supported in the H8S/2321.

6.10.3 Pin States in External Bus Released State

Table 6.9 shows the pin states in the external bus released state. Table 6.9 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn*1 High impedance CAS*3 High impedance AS High impedance RD High impedance HWR High impedance LWR High impedance DACKm*2 *3 High Notes: 1. n = 0 to 7 2. m = 0 or 1 3. The CAS and DACKm pin functions are not supported in the H8S/2321.

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6.10.4 Transition Timing

Figure 6.37 shows the timing for transition to the bus released state. CPU cycleExternal bus released stateCPU cycle Address T0 T1 T2 φ Address bus Data bus AS HWR, LWR BREQ BACK High impedance Minimum 1 state BREQO* [1] [2] [3] [4] [5] [6] Note: * Output only when BREQOE is set to 1. Low level of BREQ pin is sampled at rise of T 2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. BREQO signal goes high 1.5 clocks after BACK signal goes high. High impedance High impedance High impedance RD High impedance Figure 6.37 Bus Released State Transition Timing

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6.10.5 Usage Note

Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a transition is made to sleep mode when either of these settings has been made.

6.11 Bus Arbitration

6.11.1 Overview

The chip has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC*, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. Note: * The DMAC is not supported in the H8S/2321.

6.11.2 Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC * > DTC > CPU (Low) An internal bus access by an internal bus master, external bus release, and refreshing*, can be executed in parallel. In the event of simultaneous external bus release request, refresh request*, and internal bus master external access request generation, the order of priority is as follows: (High) Refresh * > External bus release (Low) (High) External bus release > Intern al bus master external access (Low)

Rev.6.00 Sep. 27, 2007 Page 214 of 1268 REJ09B0220-0600 As a refresh* and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The DMAC and DRAM interface are not supported in the H8S/2321.

6.11.3 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC*, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows:

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred.
• If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). DMAC*: The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of a transfer. Note: * The DMAC is not supported in the H8S/2321.

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6.11.4 External Bus Release Usage Note

External bus release can be performed on completion of an external bus cycle. The RD signal and the DRAM interface* RAS and CAS signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD, RAS, and CAS signals may change from the low level to the high-impedance state. Note: * The DRAM interface is not supported in the H8S/2321.

6.12 Resets and the Bus Controller

In a reset, the chip, including the bus controller, enters the reset state at that point, and any executing bus cycle is discontinued.

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Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 217 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321)

7.1 Overview

The chip has a built-in DMA controller* (DMAC) which can carry out data transfer on up to 4 channels. Note: * The DMAC is not supported in the H8S/2321.

7.1.1 Features

The features of the DMAC are listed below.

• Choice of short address mode or full address mode Short address mode ⎯ Maximum of 4 channels can be used ⎯ Choice of dual address mode or single address mode ⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits ⎯ In single address mode, transfer source or transfer destination address only is specified as 24 bits ⎯ In single address mode, transfer can be performed in one bus cycle ⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode ⎯ Maximum of 2 channels can be used ⎯ Transfer source and transfer destination address specified as 24 bits ⎯ Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) ⎯ Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts ⎯ Serial communication interface (SCI0, SCI1) transmission data empty interrupt, reception data full interrupt ⎯ A/D converter conversion end interrupt

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 218 of 1268 REJ09B0220-0600 ⎯ External request ⎯ Auto-request

• Module stop mode can be set ⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode

7.1.2 Block Diagram

A block diagram of the DMAC is shown in figure 7.1. Internal address bus Address buffer Processor Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Control logic DMAWER DMACR1B DMACR1A DMACR0B DMACR0A DMATCR DMABCR Data buffer Internal data bus MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Legend: DMAWER: DMA write enable register DMATCR: DMA terminal control register DMABCR: DMA band control register (for all channels) DMACR: DMA control register MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Channel 0Channel 1 Channel 0AChannel 0BChannel 1AChannel 1B Module data bus Figure 7.1 Block Diagram of DMAC

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7.1.3 Overview of Functions

Tables 7.1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7.1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination Dual address mode

• Sequential mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address incremented/decremented by 1 or 2 ⎯ 1 to 65,536 transfers
• Idle mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address fixed ⎯ 1 to 65,536 transfers
• Repeat mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address incremented/ decremented by 1 or 2 ⎯ After specified number of transfers (1 to 256), initial state is restored and operation continues
• TPU channel 0 to 5 compare match/input capture A interrupt
• SCI transmit- data-empty interrupt
• SCI receive- data-full interrupt
• A/D converter conversion end interrupt
• External request 24/16 16/24
• Single address mode
• 1-byte or 1-word transfer executed for one transfer request
• Transfer in 1 bus cycle using DACK pin in place of address specifying I/O
• Specifiable for sequential, idle, and repeat modes
• External request 24/DACK DACK/24

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 220 of 1268 REJ09B0220-0600 Table 7.1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination

• Normal mode Auto-request ⎯ Transfer request retained internally ⎯ Transfers continue for the specified number of times (1 to 65,536) ⎯ Choice of burst or cycle steal transfer
• Auto-request 24 24 External request ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ 1 to 65,536 transfers
• External request
• Block transfer mode ⎯ Specified block size transfer executed for one transfer request ⎯ 1 to 65,536 transfers ⎯ Either source or destination specifiable as block area ⎯ Block size: 1 to 256 bytes or words
• TPU channel 0 to 5 compare match/input capture A interrupt
• SCI transmit- data-empty interrupt
• SCI receive- data-full interrupt
• External request
• A/D converter conversion end interrupt 24 24

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7.1.4 Pin Configuration

Table 7.2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output. With regard to the DACK pins, setting single address transfer automatically sets the corresponding port to output, functioning as a DACK pin. With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting. Table 7.2 DMAC Pins Channel Pin Name Symbol I/O Function

0 DMA request 0 DREQ0 Input DMAC channel 0 external

DMA transfer acknowledge 0 DACK0 Output DMAC channel 0 single address transfer acknowledge DMA transfer end 0 TEND0 Output DMAC channel 0 transfer end

1 DMA request 1 DREQ1 Input DMAC channel 1 external

DMA transfer acknowledge 1 DACK1 Output DMAC channel 1 single address transfer acknowledge DMA transfer end 1 TEND1 Output DMAC channel 1 transfer end

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7.1.5 Register Configuration

Table 7.3 summarizes the DMAC registers. Table 7.3 DMAC Registers Channel Name Abbreviation R/W Initial Value Address* Bus Width

0 Memory address register 0A MAR0A R/W Undefined H'FEE0 16 bits

I/O address register 0A IOAR0A R/W Undefined H'FEE4 16 bits Transfer count register 0A ETCR0A R/W Undefined H'FEE6 16 bits Memory address register 0B MAR0B R/W Undefined H'FEE8 16 bits I/O address register 0B IOAR0B R/W Undefined H'FEEC 16 bits Transfer count register 0B ETCR0B R/W Undefined H'FEEE 16 bits

1 Memory address register 1A MAR1A R/W Undefined H'FEF0 16 bits

I/O address register 1A IOAR1A R/W Undefined H'FEF4 16 bits Transfer count register 1A ETCR1A R/W Undefined H'FEF6 16 bits Memory address register 1B MAR1B R/W Undefined H'FEF8 16 bits I/O address register 1B IOAR1B R/W Undefined H'FEFC 16 bits Transfer count register 1B ETCR1B R/W Undefined H'FEFE 16 bits 0, 1 DMA write enable register DMAWER R/W H'00 H'FF00 8 bits DMA terminal control register DMATCR R/W H'00 H'FF01 8 bits DMA control register 0A DMACR0A R/W H'00 H'FF02 16 bits DMA control register 0B DMACR0B R/W H'00 H'FF03 16 bits DMA control register 1A DMACR1A R/W H'00 H'FF04 16 bits DMA control register 1B DMACR1B R/W H'00 H'FF05 16 bits DMA band control register DMABCR R/W H'0000 H'FF06 16 bits Module stop control register MSTPCR R/W H'3FFF H'FF3C 8 bits Note: * Lower 16 bits of the address.

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7.2 Register Descriptions (1 ) (Short Address Mode)

Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7.4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7.4 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) FAE0 Description

0 Short address mode specified (channels A and B operate independently)

MAR0A Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A Channel 0B MAR0B IOAR0B ETCR0B DMACR0B

1 Full address mode specified (channels A and B operate in combination)

MAR0A Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B

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7.2.1 Memory Address Registers (MAR)

Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value : 0 0 0 0 0 0 0 0 * * * * * * * * R/W : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M A R : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode.

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7.2.2 I/O Address Register (IOAR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I O A R : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode.

7.2.3 Execute Transfer Count Register (ETCR)

ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. Sequential Mode and Idle Mode Transfer Counter (ETCR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 226 of 1268 REJ09B0220-0600 In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65,536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends. Repeat Mode Transfer Number Storage (ETCRH) Bit : 15 14 13 12 11 10 9 8 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Transfer Counter (ETCRL) Bit : 7 6 5 4 3 2 1 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 227 of 1268 REJ09B0220-0600

7.2.4 DMA Control Register (DMACR)

Bit : 7 6 5 4 3 2 1 0 DTSZ DTID5 RPE DTDIR DTF3 DTF2 DTF1 DTF0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode. Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ

0 Byte-size transfer (Initial value)

1 Word-size transfer

Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. Bit 6 DTID

0 MAR is incremented after a data transfer (Initial value)

• When DTSZ = 0, MAR is incremented by 1 after a transfer
• When DTSZ = 1, MAR is incremented by 2 after a transfer

1 MAR is decremented after a data transfer

• When DTSZ = 0, MAR is decremented by 1 after a transfer
• When DTSZ = 1, MAR is decremented by 2 after a transfer

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 228 of 1268 REJ09B0220-0600 Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE DMABCR DTIE 0 0 Transfer in sequential mode (no transfer end interrupt) (Initial value)

1 Transfer in sequential mode (with transfer end interrupt)

1 0 Transfer in repeat mode (no transfer end interrupt)

1 Transfer in idle mode (with transfer end interrupt)

For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR SAE Bit 4 DTDIR 0 0 Transfer with MAR as source address and IOAR as destination address (Initial value)

1 Transfer with IOAR as source address and MAR as destination address

1 0 Transfer with MAR as source address and DACK pin as write strobe

1 Transfer with DACK pin as read strobe and MAR as destination address

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 229 of 1268 REJ09B0220-0600 Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel Channel A Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 0 0 0 0 — (Initial value)

1 Activated by A/D converter conversion end interrupt

1 0 — 1 — 1 0 0 Activated by SCI channel 0 transmit-data-empty interrupt

1 Activated by SCI channel 0 receive-data-full interrupt

1 0 Activated by SCI channel 1 transmit-data-empty interrupt

1 Activated by SCI channel 1 receive-data-full interrupt

1 0 0 0 Activated by TPU channel 0 compare match/input capture A interrupt

1 Activated by TPU channel 1 compare match/input capture

1 0 Activated by TPU channel 2 compare match/input capture A interrupt

1 Activated by TPU channel 3 compare match/input capture

1 0 0 Activated by TPU channel 4 compare match/input capture A interrupt

1 Activated by TPU channel 5 compare match/input capture

1 0 — 1 —

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 230 of 1268 REJ09B0220-0600 Channel B Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 0 0 0 0 — (Initial value) 1 0 Activated by DREQ pin falling edge input*

1 Activated by DREQ pin low-level input

1 0 0 Activated by SCI channel 0 transmit-data-empty interrupt 1 0 Activated by SCI channel 1 transmit-data-empty interrupt 1 0 0 0 Activated by TPU channel 0 compare match/input capture A interrupt 1 0 Activated by TPU channel 2 compare match/input capture A interrupt 1 0 0 Activated by TPU channel 4 compare match/input capture A interrupt 1 0 — 1 — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation.

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7.2.5 DMA Band Control Register (DMABCR)

Bit : 15 14 13 12 11 10 9 8 FAE1 FAE0 SAE1 SAE0 DT A1B DTA1A DTA0B DTA0A Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DMABCRL Bit : 7 6 5 4 3 2 1 0 DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in hardware standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B can be used as independent channels. Bit 15 FAE1

0 Short address mode (Initial value)

1 Full address mode

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 232 of 1268 REJ09B0220-0600 Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B can be used as independent channels. Bit 14 FAE0 Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. Bit 13 SAE1

0 Transfer in dual address mode (Initial value)

1 Transfer in single address mode

Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. Bit 12 SAE0 Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 233 of 1268 REJ09B0220-0600 When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting. Bit 11 DTA1B

0 Clearing of selected internal interrupt source at time of DMA transfer is disabled

(Initial value)

1 Clearing of selected internal interrupt source at time of DMA transfer is enabled

Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting. Bit 10 DTA1A (Initial value) Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting. Bit 9 DTA0B (Initial value)

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 234 of 1268 REJ09B0220-0600 Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A (Initial value) Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows:

• When initialization is performed
• When the specified number of transfers have been completed in a transfer mode other than repeat mode
• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B. Bit 7 DTE1B

0 Data transfer disabled (Initial value)

1 Data transfer enabled

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 235 of 1268 REJ09B0220-0600 Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B. Bit 5 DTE0B Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B

0 Transfer end interrupt disabled (Initial value)

1 Transfer end interrupt enabled

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 236 of 1268 REJ09B0220-0600 Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt. Bit 1 DTIE0B Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt. Bit 0 DTIE0A

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 237 of 1268 REJ09B0220-0600

7.3 Register Descriptions (2) (Full Address Mode)

Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7.4.

7.3.1 Memory Address Register (MAR)

Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value : 0 0 0 0 0 0 0 0 * * * * * * * * R/W : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode.

7.3.2 I/O Address Register (IOAR)

IOAR is not used in full address transfer.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 238 of 1268 REJ09B0220-0600

7.3.3 Execute Transfer Count Register (ETCR)

ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. Normal Mode ETCRA Transfer Counter Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 239 of 1268 REJ09B0220-0600 Block Transfer Mode ETCRA Block Size Storage (ETCRAH) Bit : 15 14 13 12 11 10 9 8 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Block Size Counter (ETCRAL) Bit : 7 6 5 4 3 2 1 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined ETCRB Block Transfer Counter Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 240 of 1268 REJ09B0220-0600

7.3.4 DMA Control Register (DMACR)

DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in hardware standby mode. DMACRA Bit : 15 14 13 12 11 10 9 8 DTSZ SAID SAIDE BLKDIR BLKE — — — Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DMACRB Bit : 7 6 5 4 3 2 1 0 — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 241 of 1268 REJ09B0220-0600 Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 14 SAID Bit 13 SAIDE 0 0 MARA is fixed (Initial value)

1 MARA is incremented after a data transfer

• When DTSZ = 0, MARA is incremented by 1 after a transfer
• When DTSZ = 1, MARA is incremented by 2 after a transfer 1 0 MARA is fixed

1 MARA is decremented after a data transfer

• When DTSZ = 0, MARA is decremented by 1 after a transfer
• When DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12—Block Direction (BLKDIR) Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR Bit 11 BLKE

0 0 Transfer in normal mode (Initial value)

1 Transfer in block transfer mode, destination side is block area

1 0 Transfer in normal mode

1 Transfer in block transfer mode, source side is block area

For operation in normal mode and block transfer mode, see section 7.5, Operation. Bits 10 to 7—Reserved: Can be read or written to. Only 0 should be written to these bits.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 242 of 1268 REJ09B0220-0600 Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 DAID Bit 5 DAIDE 0 0 MARB is fixed (Initial value)

1 MARB is incremented after a data transfer

• When DTSZ = 0, MARB is incremented by 1 after a transfer
• When DTSZ = 1, MARB is incremented by 2 after a transfer 1 0 MARB is fixed

1 MARB is decremented after a data transfer

• When DTSZ = 0, MARB is decremented by 1 after a transfer
• When DTSZ = 1, MARB is decremented by 2 after a transfer Bit 4—Reserved: Can be read or written to. Only 0 should be written to this bit. Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode.
• Normal Mode Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0

0 0 0 0 — (Initial value) 1 — 1 0 Activated by DREQ pin falling edge input 1 0 * — 1 0 Auto-request (cycle steal)

1 Auto-request (burst)

1 * * * — *: Don't care

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• Block Transfer Mode Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0

0 0 0 0 — (Initial value) 1 0 Activated by DREQ pin falling edge input* 1 0 0 Activated by SCI channel 0 transmit-data-empty interrupt 1 0 Activated by SCI channel 1 transmit-data-empty interrupt 1 0 0 0 Activated by TPU channel 0 compare match/input capture A interrupt 1 0 Activated by TPU channel 2 compare match/input capture A interrupt 1 0 0 Activated by TPU channel 4 compare match/input capture A interrupt 1 0 — 1 — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 244 of 1268 REJ09B0220-0600

7.3.5 DMA Band Control Register (DMABCR)

DMABCRH: Bit : 15 14 13 12 11 10 9 8 FAE1 FAE0 — — DTA1 — DTA0 — Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DMABCRL: Bit : 7 6 5 4 3 2 1 0 : DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in hardware standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. Bit 15 FAE1

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 245 of 1268 REJ09B0220-0600 Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 Bits 13 and 12—Reserved: Can be read or written to. Only 0 should be written to these bits. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. Bit 11 DTA1 (Initial value)

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 246 of 1268 REJ09B0220-0600 Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0 (Initial value) Bits 10 and 8—Reserved: Can be read or written to. Only 0 should be written to these bits. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows:

• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows:
• When 1 is written to DTME after DTME is read as 0 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel Bit 7 DTME1

0 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt (Initial value)

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 247 of 1268 REJ09B0220-0600 Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel Bit 5 DTME0 0 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows:

• When initialization is performed
• When the specified number of transfers have been completed
• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1. Bit 6 DTE1

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 248 of 1268 REJ09B0220-0600 Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B

0 Transfer break interrupt disabled (Initial value)

1 Transfer break interrupt enabled

Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 249 of 1268 REJ09B0220-0600 Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 250 of 1268 REJ09B0220-0600

7.4 Register Descriptions (3)

7.4.1 DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels. DTC MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMATCR DMACR0B DMACR1B DMAWER DMACR0A DMACR1A DMABCRSecond transfer area using chain transfer First transfer area Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 251 of 1268 REJ09B0220-0600 Bit : 7 6 5 4 3 2 1 0 — — — — WE1B WE1A WE0B WE0A Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — R/W R/W R/W R/W DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR, by the DTC. Bit 3 WE1B

0 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

are disabled (Initial value)

1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR, by the DTC. Bit 2 WE1A

0 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled

(Initial value)

1 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 252 of 1268 REJ09B0220-0600 Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR, by the DTC. Bit 1 WE0B

0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

are disabled (Initial value)

1 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR, by the DTC. Bit 0 WE0A

0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled

(Initial value)

1 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled

Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted.

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7.4.2 DMA Terminal Control Register (DMATCR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 6—Reserved: Read-only bits, always read as 0. Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output. Bit 5 TEE1

0 TEND1 pin output disabled (Initial value)

1 TEND1 pin output enabled

Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0

0 TEND0 pin output disabled (Initial value)

1 TEND0 pin output enabled

The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0—Reserved: Read-only bits, always read as 0.

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7.4.3 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 15—Module Stop (MSTP15): Specifies the DMAC module stop mode. Bits 15 MSTP15

0 DMAC module stop mode cleared (Initial value)

1 DMAC module stop mode set

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7.5 Operation

7.5.1 Transfer Modes

Table 7.5 lists the DMAC modes. Table 7.5 DMAC Transfer Modes Transfer Mode Transfer Source Remarks Short address mode Dual address mode (1) Sequential mode (2) Idle mode (3) Repeat mode

• TPU channel 0 to 5 compare match/input capture A interrupt
• SCI transmit-data- empty interrupt
• SCI receive-data-full interrupt
• A/D converter conversion end interrupt
• External request
• Up to 4 channels can operate independently
• External request applies to channel B only
• Single address mode applies to channel B only
• Modes (1), (2), and (3) can also be specified for single address mode (4) Single address mode Full address mode (5) Normal mode • External request
• Auto-request
• Max. 2-channel operation, combining channels A and B (6) Block transfer mode • TPU channel 0 to 5 compare match/input capture A interrupt
• SCI transmit-data- empty interrupt
• SCI receive-data-full interrupt
• A/D converter conversion end interrupt
• External request
• With auto-request, burst mode transfer or cycle steal transfer can be selected

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 256 of 1268 REJ09B0220-0600 Operation in each mode is summarized below. Sequential Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. Idle Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. Repeat Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. Single Address Mode: In response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set automatically. The transfer direction is programmable. Sequential mode, idle mode, and repeat mode can also be specified for single address mode. Normal Mode

• Auto-request By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits. ⎯ Cycle steal mode The bus is released to another bus master after each byte or word transfer. ⎯ Burst mode ⎯ The bus is held and transfer continued until the specified number of transfers have been completed.

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• External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. Block Transfer Mode: In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits.

7.5.2 Sequential Mode

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in sequential mode. Table 7.6 Register Functions in Sequential Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented/ decremented every transfer 23 0 IOAR H'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 015 ETCR Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register DTDIR: Data transfer direction bit

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7.5.3 Idle Mode

Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in idle mode. Table 7.7 Register Functions in Idle Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Fixed 23 0 IOAR H'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 015 ETCR Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register DTDIR: Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.

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7.5.4 Repeat Mode

Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in repeat mode. Table 7.8 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented/ decremented every transfer. Initial setting is restored when value reaches H'0000 23 0 IOAR H'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed ETCRH ETCRL Holds number of transfers Transfer counter Number of transfers Number of transfers Fixed Decremented every transfer. Loaded with ETCRH value when count reaches H'00 Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register DTDIR: Data transfer direction bit

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 264 of 1268 REJ09B0220-0600 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1) DTID · 2DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared.

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7.5.5 Single Address Mode

Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.9 summarizes register functions in single address mode. Table 7.9 Register Functions in Single Address Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source DACK pin Write strobe Read strobe (Set automatically by SAE bit; IOAR is invalid) Strobe for external device 015 ETCR Transfer counter Number of transfers * Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer register DTDIR: Data transfer direction bit DACK: Data transfer acknowledge Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output.

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7.5.6 Normal Mode

In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.10 summarizes register functions in normal mode. Table 7.10 Register Functions in Normal Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed 015 ETCRA Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.

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7.5.7 Block Transfer Mode

In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.11 summarizes register functions in block transfer mode. Table 7.11 Register Functions in Block Transfer Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed ETCRAH ETCRAL Holds block size Block size counter Block size Block size Fixed Decremented every transfer; ETCRH value copied when count reaches H'00 15 0 ETCRB Block transfer counter Number of block transfers Decremented every block transfer; transfer ends when count reaches H'0000 Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A ETCRB: Execute transfer count register B

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 274 of 1268 REJ09B0220-0600 MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 276 of 1268 REJ09B0220-0600 Address TB Address BB Transfer Address TA Address BA 1st block 2nd block Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Legend: Address Address Address Address Where : = L A = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL T A TB BA BB LA LB N M Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.

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7.5.8 DMAC Activation Sources

DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7.12. Table 7.12 DMAC Activation Sources Short Address Mode Full Address Mode Activation Source Channels 0A and 1A Channels 0B and 1B Normal Mode Block Transfer Mode Internal ADI X Interrupts TXI0 X RXI0 X TXI1 X RXI1 X TGI0A X TGI1A X TGI2A X TGI3A X TGI4A X TGI5A X External DREQ pin falling edge input X Requests DREQ pin low-level input X Auto-request X X X Legend: : Can be specified X : Cannot be specified Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant. If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 280 of 1268 REJ09B0220-0600 unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highest- priority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Activation by Auto-Request: Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. Single Address Mode: The DMAC can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 281 of 1268 REJ09B0220-0600 In dual address mode, transfer is performed with the source address and destination address specified separately. In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the DACK strobe, without regard to the address. Figure 7.16 shows the data bus in single address mode. External memory External device (Read) (Write) RD HWR, LWR A23 to A0 Chip D15 to D0 (high impedance) DACK Address bus Data bus Figure 7.17 Data Bus in Single Address Mode When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a read strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used. Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. On the external device side, DACK is output in synchronization with the address strobe. For details of bus cycles, see section 7.5.11, DMAC Bus Cycles (Single Address Mode). Do not specify internal space for transfer addresses in single address mode.

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7.5.9 Basic DMAC Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7.18. In this example, word- size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. φ Address bus DMAC cycle (1-word transfer) RD LWR HWR Source address Destination address CPU cycle CPU cycle T1 T2 T3T1 T2 T3T1 T2 Figure 7.18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register.

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7.5.10 DMAC Bus Cycles (Dual Address Mode)

Short Address Mode: Figure 7.19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read φ Address bus RD LWR TEND HWR Bus release Last transfer cycle DMA write DMA dead DMA read DMA write DMA read DMA write Bus release Bus release Bus release Figure 7.19 Example of Short Address Mode Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter reaches 0.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 284 of 1268 REJ09B0220-0600 Full Address Mode (Cycle Steal Mode): Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read φ Address bus RD LWR TEND HWR Bus release Last transfer cycle DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Figure 7.20 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 285 of 1268 REJ09B0220-0600 Full Address Mode (Burst Mode): Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16- bit, 2-state access space to external 16-bit, 2-state access space. DMA read φ Address bus RD LWR TEND HWR Bus release DMA write DMA dead DMA read DMA write DMA read DMA write Bus release Burst transfer Last transfer cycle Figure 7.21 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 286 of 1268 REJ09B0220-0600 Full Address Mode (Block Transfer Mode): Figure 7.22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read φ Address bus RD LWR TEND HWR Bus release Block transfer Last block transfer DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Figure 7.22 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one- state DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation.

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7.5.11 DMAC Bus Cycles (Single Address Mode)

Single Address Mode (Read): Figure 7.27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read φ Address bus DMA dead RD DACK TEND Bus release DMA read DMA read DMA read Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.27 Example of Single Address Mode (Byte Read) Transfer

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 293 of 1268 REJ09B0220-0600 Single Address Mode (Write): Figure 7.29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write φ Address bus DMA dead HWR DACK TEND Bus release LWR DMA write DMA write DMA write Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.29 Example of Single Address Mode (Byte Write) Transfer

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 297 of 1268 REJ09B0220-0600 When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends.

7.5.12 Write Data Buffer Function

DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7.33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function. φ Internal address Internal read signal HWR, LWR TEND External address DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Figure 7.33 Example of Dual Address Transfer Using Write Data Buffer Function

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 298 of 1268 REJ09B0220-0600 Figure 7.34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. φ Internal address Internal read signal RD DACK External address DMA read DMA single CPU read DMA single CPU read Figure 7.34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer.

7.5.13 DMAC Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.13 summarizes the priority order for DMAC channels. Table 7.13 DMAC Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1 Channel 1B Low

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7.5.14 Relation Between the DMAC and Extern al Bus Requests, Refresh Cycles, and the

There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used.

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7.5.15 NMI Interrupts and DMAC

When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel Set DTME bit to 1 Transfer continues [1] [2] DTE = 1 DTME = 0 Transfer ends No Yes [1] [2] Check that DTE = 1 and DTME = 0 in DMABCRL. Write 1 to the DTME bit. Figure 7.36 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt

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7.5.16 Forced Termination of DMAC Operation

If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7.37 shows the procedure for forcibly terminating DMAC operation by software. Forced termination of DMAC Clear DTE bit to 0 Forced termination [1] [1] Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Figure 7.37 Example of Procedure for Forcibly Terminating DMAC Operation

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7.5.17 Clearing Full Address Mode

Figure 7.38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. Clearing full address mode Stop the channel Initialize DMACR Clear FAE bit to 0 Initialization; operation halted [1] [2] [3] [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Figure 7.38 Example of Procedure for Clearing Full Address Mode

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7.6 Interrupts

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.14 shows the interrupt sources and their priority order. Table 7.14 Interrupt Source Priority Order Interrupt Source Interrupt Interrupt Name Short Address Mode Full Address Mode Priority Order DEND0A Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0 High DEND0B Interrupt due to end of transfer on channel 0B Interrupt due to break in transfer on channel 0 DEND1A Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1 DEND1B Interrupt due to end of transfer on channel 1B Interrupt due to break in transfer on channel 1 Low Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.14. Figure 7.39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while the DTE bit is cleared to 0. DTE/ DTME DTIE Transfer end/transfer break interrupt Figure 7.39 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0 while the DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting.

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7.7 Usage Notes

DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, MAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. (a) DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMAC transfer. Figure 7.40 shows an example of the update timing for DMAC registers in dual address transfer mode. [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2'] Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Notes: 1. In single address transfer mode, the update timing is the same as [1]. 2. The MAR operation is post-incrementing/decrementing of the DMA internal address value. [3][2] [1][1] DMA transfer cycle DMA read DMA readDMA write DMA write DMA dead DMA Internal address DMA control DMA register operation DMA last transfer cycle Transfer destination Transfer destinationTransfer source Transfer source Idle Idle IdleRead Read DeadWrite Write φ [2'] Figure 7.40 DMAC Register Update Timing

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 306 of 1268 REJ09B0220-0600 (b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.41. [2][1] Note: The lower word of MAR is the updated value after the operation in [1]. CPU longword read DMA transfer cycle MAR upper word read MAR lower word read DMA read DMA write DMA internal address DMA control DMA register operation Transfe source Transfer destination Idle φ Read Write Idle Figure 7.41 Contention between DMAC Register Update and CPU Read Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop.

• Transfer end/break interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1) Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-detected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the medium- speed clock.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 307 of 1268 REJ09B0220-0600 Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.

• Write Data Buffer Function and DMAC Register Setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access.
• Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible.
• Write Data Buffer Function and TEND Output A low level is not output at the TEND pin if the bus cycle in which a low level is to be output at the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level may not be output at the TEND pin if the write data buffer function is used when data transfer is performed between an internal I/O register and on-chip memory. If at least one of the DMAC transfer addresses is an external address, a low level is output at the TEND pin. Figure 7.42 shows an example in which a low level is not output at the TEND pin.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 308 of 1268 REJ09B0220-0600 φ Internal address Internal read signal External address HWR, LWR Internal write signal TEND Not output DMA read External write by CPU, etc. DMA write Figure 7.42 Example in Which Low Level is Not Output at TEND Pin Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. Activation Source Acceptance: At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc.

Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 309 of 1268 REJ09B0220-0600 Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is forcibly terminated, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or a forcible termination should be handled by the CPU as necessary. Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write a 1 to them.

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Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 311 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller

8.1 Overview

The chip includes a data transfer controller (DTC). The DTC can be activated for data transfer by an interrupt or software.

8.1.1 Features

The features of the DTC are:

• Transfer possible over any number of channels ⎯ Transfer information is stored in memory ⎯ One activation source can trigger a number of data transfers (chain transfer) ⎯ Chain transfer execution can be set after data transfer (when counter = 0)
• Selection of transfer modes ⎯ Normal, repeat, and block transfer modes available ⎯ Incrementing, decrementing, and fixing of source and destination addresses can be selected
• Direct specification of 16-Mbyte address space possible ⎯ 24-bit transfer source and destination addresses can be specified
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC ⎯ An interrupt request can be issued to the CPU after one data transfer ends ⎯ An interrupt request can be issued to the CPU after all the specified data transfers have ended
• Activation by software is possible
• Module stop mode can be set ⎯ The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode

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8.1.2 Block Diagram

Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Interrupt request Interrupt controller DTC Internal address bus DTC activation request Control logic Register information MRA MRB CRA CRB DAR SAR CPU interrupt request On-chip RAM Internal data bus Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR DTCERA to DTCERF DTVECR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register Figure 8.1 Block Diagram of DTC

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8.1.3 Register Configuration

Table 8.1 summarizes the DTC registers. Table 8.1 DTC Registers Name Abbreviation R/W Initial Value Address *1 DTC mode register A MRA — *2 Undefined — *3 DTC mode register B MRB — *2 Undefined — *3 DTC source address register SAR — *2 Undefined — *3 DTC destination address register DAR — *2 Undefined — *3 DTC transfer count register A CRA — *2 Undefined — *3 DTC transfer count register B CRB — *2 Undefined — *3 DTC enable registers DTCER R/W H'00 H'FF30 to H'FF35 DTC vector register DTVECR R/W H'00 H'FF37 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0.

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8.2 Register Descriptions

8.2.1 DTC Mode Register A (MRA)

Bit : 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Initial value : Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 Bit 6 SM0 0 — SAR is fixed 1 0 SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1)

1 SAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 Bit 4 DM0 0 — DAR is fixed 1 0 DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1)

1 DAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 315 of 1268 REJ09B0220-0600 Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 Bit 2 MD0

1 Repeat mode

1 — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS

0 Destination side is repeat area or block area

1 Source side is repeat area or block area

Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz

0 Byte-size transfer

8.2.2 DTC Mode Register B (MRB)

Bit : 7 6 5 4 3 2 1 0 CHNE DISEL CHNS — — — — — Initial value : Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined MRB is an 8-bit register that controls the DTC operating mode.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 316 of 1268 REJ09B0220-0600 Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. When CHNE is set to 1, the chain transfer condition can be selected with the CHNS bit. Bit 7 CHNE

0 End of DTC data transfer (activation waiting state)

1 DTC chain transfer (new register inform ation is read, then data is transferred)

Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL

0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is

0 (the DTC clears the interrupt source flag of the activating interrupt to 0)

1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the

interrupt source flag of the activating interrupt to 0) Bit 5—DTC Chain Transfer Select (CHNS): Specifies the chain transfer condition when CHNE is 1. Bit 7 CHNE Bit 5 CHNS 0 – No chain transfer (DTC data transfer end, activation waiting state entered) 1 0 DTC chain transfer 1 1 Chain transfer only when transfer counter = 0 Bits 4 to 0—Reserved: These bits have no effect on DTC operation in the chip and should always be written with 0.

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8.2.3 DTC Source Address Register (SAR)

Bit : 23 22 21 20 19 – – – 4 3 2 1 0 – – – Initial value : Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined – – – Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address.

8.2.4 DTC Destination Address Register (DAR)

Bit : 23 22 21 20 19 – – – 4 3 2 1 0 – – – Initial value : Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined – – – Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address.

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8.2.5 DTC Transfer Count Register A (CRA)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA register is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated.

8.2.6 DTC Transfer Count Register B (CRB)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined Unde- fined CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

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8.2.7 DTC Enable Registers (DTCER)

Bit : 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn

0 DTC activation by this interrupt is disabled (Initial value)

[Clearing conditions]

• When the DISEL bit is 1 and the data transfer has ended
• When the specified number of transfers have ended

1 DTC activation by this interrupt is enabled

[Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8.5, together with the vector numbers generated by the interrupt controller. For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register.

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8.2.8 DTC Vector Register (DTVECR)

Bit : 7 6 5 4 3 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/(W) R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE

0 DTC software activation is disabled (Initial value)

[Clearing conditions]

• When the DISEL bit is 0 and the specified number of transfers have not ended
• When 0 is written after a software activation data-transfer-complete interrupt is issued to the CPU

1 DTC software activation is enabled

[Holding conditions]

• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left- shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.

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8.2.9 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 14—Module Stop (MSTP14): Specifies the DTC module stop mode. Bit 14 MSTP14

0 DTC module stop mode cleared (Initial value)

1 DTC module stop mode set

8.3 Operation

8.3.1 Overview

When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. A setting can also be made to have chain transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be performed by the DTC itself.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 323 of 1268 REJ09B0220-0600 Table 8.2 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer 0 — 0 Not 0 — — — — Ends at 1st transfer 0 — 0 0 — — — — Ends at 1st transfer 0 — 1 — — — — — Interrupt request to CPU 1 0 — — 0 — 0 Not 0 Ends at 2nd transfer 0 — 0 0 Ends at 2nd transfer 0 — 1 — Interrupt request to CPU 1 1 0 Not 0 — — — — Ends at 1st transfer 1 1 — 0 0 — 0 Not 0 Ends at 2nd transfer 0 — 0 0 Ends at 2nd transfer 0 — 1 — Interrupt request to CPU 1 1 1 Not 0 — — — — Ends at 1st transfer Interrupt request to CPU The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 8.3 outlines the functions of the DTC.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 324 of 1268 REJ09B0220-0600 Table 8.3 DTC Functions Address Registers Transfer Mode Activation Source Transfer Source Transfer Destination

• Normal mode ⎯ One transfer request transfers one byte or one word ⎯ Memory addresses are incremented or decremented by 1 or 2 ⎯ Up to 65,536 transfers possible
• Repeat mode ⎯ One transfer request transfers one byte or one word ⎯ Memory addresses are incremented or decremented by 1 or 2 ⎯ After the specified number of transfers (1 to 256), the initial state resumes and operation continues
• Block transfer mode ⎯ One transfer request transfers a block of the specified size ⎯ Block size is from 1 to 256 bytes or words ⎯ Up to 65,536 transfers possible ⎯ A block area can be designated at either the source or destination
• IRQ
• TPU TGI
• 8-bit timer CMI
• SCI TXI or RXI
• A/D converter ADI
• DMAC DEND *
• Software 24 bits 24 bits Note: * The DMAC is not supported in the H8S/2321.

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8.3.2 Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 8.4 shows activation source and DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Table 8.4 Activation Sou rce and DTCER Clearance Activation Source When the DISEL Bit Is 0 and the Specified Number of Transfers Have Not Ended When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended Software activation The SWDTE bit is cleared to 0 • The SWDTE bit remains set to 1

• An interrupt is issued to the CPU Interrupt activation • The corresponding DTCER bit remains set to 1
• The activation source flag is cleared to 0
• The corresponding DTCER bit is cleared to 0
• The activation source flag remains set to 1
• A request is issued to the CPU for the activation source interrupt Figure 8.3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 326 of 1268 REJ09B0220-0600 On-chip supporting module IRQ interrupt DTVECR Selection circuitInterrupt controller CPU DTC DTCER Clear control Select Interrupt request Source flag clearance Clear Clear request Interrupt mask Figure 8.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities.

8.3.3 DTC Vector Table

Figure 8.4 shows the correspondence between DTC vector addresses and register information. Table 8.5 shows the correspondence between activation, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is a 2-byte unit. These two bytes specify the lower bits of the address in the on-chip RAM.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 327 of 1268 REJ09B0220-0600 Table 8.5 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Source Origin of Interrupt Source Vector Number Vector Address DTCE* Priority Write to DTVECR Software DTVECR H'0400+ (DTVECR [6:0]<<1) — High IRQ0 External pin 16 H'0420 DTCEA7 IRQ1 17 H'0422 DTCEA6 IRQ2 18 H'0424 DTCEA5 IRQ3 19 H'0426 DTCEA4 IRQ4 20 H'0428 DTCEA3 IRQ5 21 H'042A DTCEA2 IRQ6 22 H'042C DTCEA1 IRQ7 23 H'042E DTCEA0 ADI (A/D conversion end) A/D 28 H'0438 DTCEB6 TGI0A (GR0A compare match/ input capture) TPU channel 0

32 H'0440 DTCEB5

TGI0B (GR0B compare match/ input capture)

33 H'0442 DTCEB4

TGI0C (GR0C compare match/ input capture)

34 H'0444 DTCEB3

TGI0D (GR0D compare match/ input capture)

35 H'0446 DTCEB2

TGI1A (GR1A compare match/ input capture) TPU channel 1

40 H'0450 DTCEB1

TGI1B (GR1B compare match/ input capture)

41 H'0452 DTCEB0

TGI2A (GR2A compare match/ input capture) TPU channel 2

44 H'0458 DTCEC7

TGI2B (GR2B compare match/ input capture)

45 H'045A DTCEC6

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 328 of 1268 REJ09B0220-0600 Interrupt Source Origin of Interrupt Source Vector Number Vector Address DTCE* Priority TGI3A (GR3A compare match/ input capture) TPU channel 3

48 H'0460 DTCEC5 High

TGI3B (GR3B compare match/ input capture)

49 H'0462 DTCEC4

TGI3C (GR3C compare match/ input capture)

50 H'0464 DTCEC3

TGI3D (GR3D compare match/ input capture)

51 H'0466 DTCEC2

TGI4A (GR4A compare match/ input capture) TPU channel 4

56 H'0470 DTCEC1

TGI4B (GR4B compare match/ input capture)

57 H'0472 DTCEC0

DMTEND0A (DMAC transfer complete 0) DMAC 72 H'0490 DTCEE7 DMTEND0B (DMAC transfer complete 1

73 H'0492 DTCEE6

DMTEND1A (DMAC transfer complete 2)

74 H'0494 DTCEE5

DMTEND1B (DMAC transfer complete 3)

75 H'0496 DTCEE4

TGI5A (GR5A compare match/ input capture) TPU channel 5

60 H'0478 DTCED5

TGI5B (GR5B compare match/ input capture)

61 H'047A DTCED4

CMIA0 64 H'0480 DTCED3 CMIB0 8-bit timer channel 0 65 H'0482 DTCED2 CMIA1 68 H'0488 DTCED1 CMIB1 8-bit timer channel 1 69 H'048A DTCED0 DMTEND0A (DMAC transfer complete 0) DMAC* 2 72 H'0490 DTCEE7 DMTEND0B (DMAC transfer complete 1) DMTEND1A (DMAC transfer complete 2) DMTEND1B (DMAC transfer complete 3)

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 329 of 1268 REJ09B0220-0600 Interrupt Source Origin of Interrupt Source Vector Number Vector Address DTCE* Priority RXI0 (receive-data-full 0) 81 H'04A2 DTCEE3 High TXI0 (transmit-data-empty 0) SCI channel 0 82 H'04A4 DTCEE2 RXI1 (receive-data-full 1) 85 H'04AA DTCEE1 TXI1 (transmit-data-empty 1) SCI channel 1 86 H'04AC DTCEE0 RXI2 (receive-data-full 2) SCI 89 H'04B2 DTCEF7 TXI2 (transmit-data-empty 2) channel 2 90 H'04B4 DTCEF6 Low Notes: 1. DTCE bits with no corresponding interrupt are reserved, and should be written with 0. 2. The DMAC is not supported in the H8S/2321. Register information start address Register information Next transfer DTC vector address Figure 8.4 Correspondence between DTC Vector Address and Register Information

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8.3.4 Location of Register Information in Address Space

Figure 8.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFF800 to H'FFFBFF). Register information start address Chain transfer Register information for 2nd transfer in chain transfer MRA SAR MRB DAR CRA CRB 4 bytes Lower address CRA CRB Register information MRA 01 2 3 SAR MRB DAR Figure 8.5 Location of DTC Register Information in Address Space

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8.3.5 Normal Mode

In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8.6 lists the register information in normal mode and figure 8.6 shows the memory map in normal mode. Table 8.6 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used Transfer SAR DAR Figure 8.6 Memory Map in Normal Mode

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8.3.6 Repeat Mode

In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8.7 lists the register information in repeat mode and figure 8.7 shows the memory map in repeat mode. Table 8.7 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of transfers DTC transfer count register AL CRAL Transfer counter DTC transfer count register B CRB Not used Transfer SAR or DAR DAR or SARRepeat area Figure 8.7 Memory Map in Repeat Mode

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8.3.7 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 8.8 lists the register information in block transfer mode and figure 8.8 shows the memory map in block transfer mode. Table 8.8 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR De signates transfer source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRAL Block size counter DTC transfer count register B CRB Transfer counter

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 334 of 1268 REJ09B0220-0600 Transfer SAR or DAR DAR or SARBlock area First block Nth block Figure 8.8 Memory Map in Block Transfer Mode

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8.3.8 Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the memory map for chain transfer. Source Source Destination Destination DTC vector address Register information start address Register information CHNE = 1 Register information CHNE = 0 Figure 8.9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected.

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8.3.9 Operation Timing

Figures 8.10 to 8.12 show examples of DTC operation timing. DTC activation request DTC request Address Vector read Transfer information read Transfer information write Data transfer Read Write φ Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Read Write Read Write Data transfer Transfer information write Transfer information read Vector read φ DTC activation request DTC request Address Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 337 of 1268 REJ09B0220-0600 Read Write Read WriteAddress φ DTC activation request DTC request Data transfer Data transfer Transfer information write Transfer information write Transfer information read Transfer information read Vector read Figure 8.12 DTC Operation Timing (Example of Chain Transfer)

8.3.10 Number of DTC Execution States

Table 8.9 lists execution phases for a single DTC data transfer, and table 8.10 shows the number of states required for each execution phase. Table 8.9 DTC Execution Phases Mode Vector Read I Register Information Read/Write J Data Read K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 N: Block size (initial setting of CRAH and CRAL)

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 338 of 1268 REJ09B0220-0600 Table 8.10 Number of States Required for Each Execution Phase Access To: On- Chip RAM On- Chip ROM Internal I/O Registers External Devices Bus width 32 16 8 16 8 16 Access states 1 1 2 2 2 3 2 3 Vector read S I — 1 — — 4 6+2m 2 3+m Execution phase Register information read/write S Byte data read S K 1 1 2 2 2 3+m 2 3+m Word data read S K 1 1 4 2 4 6+2m 2 3+m Byte data write S L 1 1 2 2 2 3+m 2 3+m Word data write S L 1 1 4 2 4 6+2m 2 3+m Internal operation S M 1 The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I · S I + Σ (J · SJ + K · SK + L · SL) + M · SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

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8.3.11 Procedures for Using DTC

Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to the SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested.

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8.3.12 Examples of Use of the DTC

Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception data full (RXI) interrupt. Since the generation of a receive error during the SCI receive operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 341 of 1268 REJ09B0220-0600 Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). [1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. [2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. [3] Locate the TPU transfer register information consecutively after the NDR transfer register information. [4] Set the start address of the NDR transfer register information to the DTC vector address. [5] Set the bit corresponding to TGIA in DTCER to 1. [6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. [7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. [8] Set the CST bit in TSTR to 1, and start the TCNT count operation. [9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. [10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Wrap-up processing should be performed in the interrupt handling routine.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 342 of 1268 REJ09B0220-0600 Chain Transfer when Counter = 0: By executing a second data transfer, and performing re- setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 8.13 shows the memory map. [1] For the first transfer, set the normal mode for input data. Set fixed transfer source address (G/A, etc.), CRA = H'0000 (64k times), and CHNE = 1, CHNS = 1, and DISEL = 0. [2] Prepare the upper 8-bit addresses of the start addresses for each of the 64k transfer start addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20. [3] For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. [4] Execute the first data transfer 64k times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. [5] Next, execute the first data transfer the 64k times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. [6] Steps [4] and [5] are repeated endlessly. As repeat mode is specified for the second data transfer, an interrupt request is not sent to the CPU.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 343 of 1268 REJ09B0220-0600 First data transfer register information Second data transfer register information Chain transfer (counter = 0) Upper 8 bits of DAR Input buffer Input circuit Figure 8.13 Chain Transfer when Counter = 0 Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 344 of 1268 REJ09B0220-0600 [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps [3] and [4] and led to a different software activation. To activate this transfer, go back to step [3]. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing.

8.4 Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 345 of 1268 REJ09B0220-0600

8.5 Usage Notes

Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written to the MSTP14 bit while the DTC is operating. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DMAC Transfer End Interrupt*: When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0. Note: * The DMAC is not supported in the H8S/2321. DTCE Bit Setting: For DTCE bit setting, read/write operations must be performed using bit- manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. Chain Transfer: When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI and A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained.

Section 8 Data Transfer Controller Rev.6.00 Sep. 27, 2007 Page 346 of 1268 REJ09B0220-0600

Rev.6.00 Sep. 27, 2007 Page 347 of 1268 REJ09B0220-0600 Section 9 I/O Ports

9.1 Overview

The chip has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4). Table 9.1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. Ports A to E have a built-in MOS pull-up function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Port 3 and port A include an open drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 1 and A to F can drive a single TTL load and 50 pF capacitive load, and ports 2, 3, 5, 6, and G can drive a single TTL load and 30 pF capacitive load. Ports 1, 2, and 5 (only when used for IRQ input), and pins 6 4 to 67 and A4 to A7, are Schmitt- triggered inputs.

Rev.6.00 Sep. 27, 2007 Page 348 of 1268 REJ09B0220-0600 Table 9.1 Port Functions Port Description Pins Mode 4 *1 Mode 5 *1 Mode 6 Mode 7 Port 1 • 8-bit I/O port

• Schmitt- triggered input P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1*2 P10/PO8/TIOCA0/DACK0*2 8-bit I/O port also functioning as DMA controller output pins (DACK0 and DACK1)*2, TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) and PPG output pins (PO15 to PO8) Port 2 • 8-bit I/O port
• Schmitt- triggered input 7/PO7/TIOCB5/TMO1 P26/PO6/TIOCA5/TMO0 P25/PO5/TIOCB4/TMCI1 P24/PO4/TIOCA4/TMRI1 P23/PO3/TIOCD3/TMCI0 P22/PO2/TIOCC3/TMRI0 P21/PO1/TIOCB3 P20/PO0/TIOCA3 8-bit I/O port also functioning as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5), 8-bit timer (channels 0 and 1) I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, TMO1) and PPG output pins (PO7 to PO0) Port 3 • 6-bit I/O port
• Open-drain output capability P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 6-bit I/O port also functioning as SCI (channel 0 and 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) Port 4 • 8-bit input port P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 8-bit input port also functioning as A/D converter analog inputs (AN 7 to AN0) and D/A converter analog outputs (DA1 and DA0)

Rev.6.00 Sep. 27, 2007 Page 349 of 1268 REJ09B0220-0600 Port Description Pins Mode 4 *1 Mode 5 *1 Mode 6 Mode 7 Port 5 • 4-bit I/O port

• Schmitt- triggered input (IRQ input only) 3/ADTRG/IRQ7/WAIT/ BREQO I/O port also functioning as A/D converter input pin (ADTRG), and as interrupt input pin (IRQ7) when IRQPAS = 1, WAIT input pin when WAITE = 1, BREQOE = 0, WAITPS = 1, DDR = 0, and WAITE = 0, BREQOE = 1, BREQO output pin when BREQOPS = 1 I/O port also functioning as A/D converter input pin (ADTRG), and as inter- rupt input pin (IRQ 7) when IRQPAS = 1 P5 2/SCK2/IRQ6 P51/RxD2/IRQ5 P50/TxD2/IRQ4 I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2), and as interrupt input pins (IRQ4 to IRQ6) when IRQPAS = 1 Port 6 • 8-bit I/O port
• Schmitt- triggered input (P6 4 to P67) P67/IRQ3/CS7 P66/IRQ2/CS6 P65/IRQ1 P64/IRQ0 P63/TEND1*2 P62/DREQ1*2 P61/TEND0*2/CS5 P60/DREQ0*2/CS4 8-bit I/O port also functioning as DMA controller I/O pins (DREQ 0, TEND0, DREQ1, TEND1) *2, bus control output pins (CS4 to CS7), and interrupt input pins (IRQ0 to IRQ3) 8-bit I/O port also function- ing as inter- rupt input pins (IRQ 0 to IRQ3) Port A PA 7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ5) When DDR = 1 and A23E to A21E = 1: address output When DDR = 1 and A23E to A21E = 0: DR value output Dual function as I/O ports and interrupt input pins (IRQ 7 to IRQ4)
• 8-bit I/O port
• Built-in MOS input pull-up
• Open-drain output capability
• Schmitt- triggered input (PA4 to PA7) PA4/A20/IRQ4 I/O port also functioning as address output and interrupt input pin (IRQ4) When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ 7 to IRQ4) When DDR = 1 and A23E to A20E = 1: address output When DDR = 1 and A23E to A20E = 0: DR value output PA3/A19 to PA0/A16 Address output When DDR = 0 (after reset): input ports When DDR = 1: address output I/O ports

Rev.6.00 Sep. 27, 2007 Page 350 of 1268 REJ09B0220-0600 Port Description Pins Mode 4 *1 Mode 5 *1 Mode 6 Mode 7 Port B • 8-bit I/O port

• Built-in MOS input pull-up PB7/A15 to PB0/A8 Address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O ports Port C • 8-bit I/O port
• Built-in MOS input pull-up PC 7/A7 to PC0/A0 Address output When DDR = 0 (after reset): input port When DDR = 1: address output I/O ports Port D • 8-bit I/O port
• Built-in MOS input pull-up PD7/D15 to PD0/D8 Data bus input/output I/O ports Port E • 8-bit I/O port
• Built-in MOS input pull-up PE7/D7 to PE0/D0 In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output I/O ports Port F • 8-bit I/O port PF7/φ When DDR = 0: input port When DDR = 1 (after reset): φ output When DDR = 0 (after reset): input port When DDR = 1: φ output PF 6/AS When ASOD = 1: I/O port When ASOD = 0: AS output I/O ports PF 5/RD PF4/HWR RD, HWR output PF 3/LWR When LWROD = 1: I/O port When LWROD = 0: LWR output PF 2/LCAS*2/WAIT/BREQO When WAITE = 0 and BREQOE = 0 (after reset): I/O port When WAITE = 1, BREQOE = 0, and WAITPS = 0, DDR = 0: WAIT input When WAITE = 0, BREQOE = 1, and BREQOPS = 0: BREQO output When RMTS2 to RMTS0= B'001 to B'011, and 16-bit access space is set: LCAS output

Rev.6.00 Sep. 27, 2007 Page 351 of 1268 REJ09B0220-0600 Port Description Pins Mode 4 *1 Mode 5 *1 Mode 6 Mode 7 Port F • 8-bit I/O port PF1/BACK PF0/BREQ When BRLE = 0 (after reset): I/O port When BRLE = 1: BREQ input, BACK output I/O ports Port G • 5-bit I/O port PG4/CS0 When DDR = 0 *3: input port When DDR = 1*4: CS0 output I/O ports PG 3/CS1 When DDR = 0 (after reset): input port When CS167E = 0 and DDR = 1: output port When CS167E = 1 and DDR = 1: CS1 output PG 2/CS2 When DDR = 0 (after reset): input port When CS25E = 0 and DDR = 1: output port When CS25E = 1 and DDR = 1: CS2 output PG 1/CS3 When DDR = 0 (after reset): input port When CS25E = 0 and DDR = 1: output port When CS25E = 1 and DDR = 1: CS3 output PG 0/CAS*2 DRAM space set: CAS output Otherwise (after reset): I/O port Notes: 1. Only modes 4 and 5 are provided in the ROMless version. 2. The DACK1, DACK0, TEND1, DREQ1, TEND0, DREQ0 and LCAS are not supported in the H8S/2321. 3. After a reset in mode 6. 4. After a reset in mode 4 or 5.

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9.2 Port 1

9.2.1 Overview

Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC* output pins (DACK0 and DACK1). Port 1 pin functions are the same in all operating modes. Port 1 uses Schmitt-triggered input. Figure 9.1 shows the port 1 pin configuration. Note: * Not supported in the H8S/2321. P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input) P16 (I/O) / PO14 (output) / TIOCA2 (I/O) P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input) P14 (I/O) / PO12 (output) / TIOCA1 (I/O) P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) P11 (I/O) / PO9 (output) / TIOCB0 (I/O) / DACK1* (output) P10 (I/O) / PO8 (output) / TIOCA0 (I/O) / DACK0* (output) Port 1 Port 1 pins Note: * The DACK1 and DACK0 pin functions are not supported in the H8S/2321. Figure 9.1 Port 1 Pin Functions

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9.2.2 Register Configuration

Table 9.2 shows the port 1 register configuration. Table 9.2 Port 1 Registers Name Abbreviation R/W Initial Value Address * Port 1 data direction register P1DDR W H'00 H'FEB0 Port 1 data register P1DR R/W H'00 H'FF60 Port 1 register PORT1 R Undefined H'FF50 Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) Bit : 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 354 of 1268 REJ09B0220-0600 Port 1 Data Register (P1DR) Bit : 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P1 7 to P10). P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port 1 Register (PORT1) Bit : 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W : R R R R R R R R Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state in software standby mode.

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9.2.3 Pin Functions

Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC* output pins (DACK0 and DACK1). Port 1 pin functions are shown in table 9.3. Note: * The DMAC is not supported in the H8S/2321. Table 9.3 Port 1 Pin Functions Pin Selection Method and Pin Functions P17/PO15/ TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR. TPU Channel

2 Setting

Table Below (1) Table Below (2) P17DDR — 0 1 1 NDER15 — — 0 1 Pin function TIOCB 2 output P1 7 input P17 output PO15 output TIOCB 2 input*1 TCLKD input *2 Notes: 1. TIOCB 2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1. 2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 356 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P16/PO14/ TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and bit P16DDR. TPU Channel Table Below (1) Table Below (2) P16DDR — 0 1 1 NDER14 — — 0 1 Pin function TIOCA 2 output P1 6 input P16 output PO14 output TIOCA 2 input*1 TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000, B'01xx B'001x B'0011 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Notes: 1. TIOCA 2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1. 2. TIOCB 2 output is disabled.

Rev.6.00 Sep. 27, 2007 Page 357 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P15/PO13/ TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR. TPU Channel Table Below (1) Table Below (2) P15DDR — 0 1 1 NDER13 — — 0 1 Pin function TIOCB 1 output P1 5 input P15 output PO13 output TIOCB 1 input*1 TCLKC input *2 Notes: 1. TIOCB 1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 358 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P14/PO12/ TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR. TPU Channel Table Below (1) Table Below (2) P14DDR — 0 1 1 NDER12 — — 0 1 Pin function TIOCA 1 output P1 4 input P14 output PO12 output TIOCA 1 input*1 TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don't care Notes: 1. TIOCA 1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx. 2. TIOCB 1 output is disabled.

Rev.6.00 Sep. 27, 2007 Page 359 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P13/PO11/ TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR. TPU Channel

0 Setting

Table Below (1) Table Below (2) P13DDR — 0 1 1 NDER11 — — 0 1 Pin function TIOCD 0 output P1 3 input P13 output PO11 output TIOCD 0 input*1 TCLKB input *2 Notes: 1. TIOCD 0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. 2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to TPSC0 = B'101. TCLKB input when channels 1 and 5 are set to phase counting mode. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'110 B'110 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 360 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P12/PO10/ TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR. TPU Channel Table Below (1) Table Below (2) P12DDR — 0 1 1 NDER10 — — 0 1 Pin function TIOCC 0 output P1 2 input P12 output PO10 output TIOCC 0 input*1 TCLKA input *2 TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOC3 to IOC0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'101 B'101 Output function — Output compare output — PWM mode 1 output*3 PWM mode 2 output x: Don’t care Notes: 1. TIOCC 0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to TPSC0 = B'100. TCLKA input when channels 1 and 5 are set to phase counting mode. 3. TIOCD 0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies.

Rev.6.00 Sep. 27, 2007 Page 361 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ DACK1*2 The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER9 in NDERH, bit SAE1* 2 in DMABCRH, and bit P11DDR. SAE1 *2 0 1 TPU Channel Below (1) Table Below (2) P11DDR — 0 1 1 — NDER9 — — 0 1 — Pin function TIOCB 0 output P11 input P11 output PO9 output DACK1*2 output TIOCB 0 input*1 Notes: 1. TIOCB 0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. 2. The DMAC and the DACK1 pin function are not supported in the H8S/2321. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'010 B'010 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 362 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ DACK0*2 The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, bit SAE0* 2 in DMABCRH, and bit P10DDR. SAE0 *2 0 1 TPU Channel Below (1) Table Below (2) P10DDR — 0 1 1 — NDER8 — — 0 1 — Pin function TIOCA 0 output P10 input P10 output PO8 output DACK0*2 output TIOCA 0 input*1 TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'001 B'001 Output function — Output compare output — PWM mode 1 output*3 PWM mode 2 output x: Don’t care Notes: 1. TIOCA 0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. 2. The DMAC and the DACK0 pin function are not supported in the H8S/2321. 3. TIOCB 0 output is disabled.

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9.3 Port 2

9.3.1 Overview

Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0), TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 9.2 shows the port 2 pin configuration. P27 (I/O) / PO7 (output) / TIOCB5 (I/O) / TMO1 (output) P26 (I/O) / PO6 (output) / TIOCA5 (I/O) / TMO0 (output) P25 (I/O) / PO5 (output) / TIOCB4 (I/O) / TMCI1 (input) P24 (I/O) / PO4 (output) / TIOCA4 (I/O) / TMRI1 (input) P23 (I/O) / PO3 (output) / TIOCD3 (I/O) / TMCI0 (input) P22 (I/O) / PO2 (output) / TIOCC3 (I/O) / TMRI0 (input) P21 (I/O) / PO1 (output) / TIOCB3 (I/O) P20 (I/O) / PO0 (output) / TIOCA3 (I/O) Port 2 Port 2 pins Figure 9.2 Port 2 Pin Functions

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9.3.2 Register Configuration

Table 9.4 shows the port 2 register configuration. Table 9.4 Port 2 Registers Name Abbreviation R/W Initial Value Address * Port 2 data direction register P2DDR W H'00 H'FEB1 Port 2 data register P2DR R/W H'00 H'FF61 Port 2 register PORT2 R Undefined H'FF51 Note: * Lower 16 bits of the address. Port 2 Data Direction Register (P2DDR) Bit : 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P2DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 365 of 1268 REJ09B0220-0600 Port 2 Data Register (P2DR) Bit : 7 6 5 4 3 2 1 0 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P2 7 to P20). P2DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port 2 Register (PORT2) Bit : 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 R/W : R R R R R R R R Note: * Determined by state of pins P27 to P20. PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR. If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and P2DR are initialized. PORT2 retains its prior state in software standby mode.

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9.3.3 Pin Functions

Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 9.5. Table 9.5 Port 2 Pin Functions Pin Selection Method and Pin Functions P27/PO7/TIOCB5/ TMO1 The pin function is switched as shown below according to the combination of the TPU channel 5 setting (by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5), bit NDER7 in NDERL, bits OS3 to OS0 in TCSR1, and bit P27DDR. OS3 to OS0 All 0 Not all 0 TPU Channel

5 Setting

Below (1) Table Below (2) P27DDR — 0 1 1 — NDER7 — — 0 1 — Pin function TIOCB 5 output P27 input P27 output PO7 output TMO1 output TIOCB 5 input* Note: * TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 367 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P26/PO6/TIOCA5/ TMO0 The pin function is switched as shown below according to the combination of the TPU channel 5 setting (by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5), bit NDER6 in NDERL, bits OS3 to OS0 in TCSR0, and bit P26DDR. OS3 to OS0 All 0 Not all 0 TPU Channel Below (1) Table Below (2) P26DDR — 0 1 1 — NDER6 — — 0 1 — Pin function TIOCA 5 output P26 input P26 output PO6 output TMO0 output TIOCA 5 input*1 TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Notes: 1. TIOCA 5 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1. 2. TIOCB 5 output is disabled.

Rev.6.00 Sep. 27, 2007 Page 368 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P25/PO5/TIOCB4/ TMCI1 This pin is used as the 8-bit timer external clock input pin when an external clock is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting (by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4), bit NDER5 in NDERL, and bit P25DDR. TPU Channel

4 Setting

Table Below (1) Table Below (2) P25DDR — 0 1 1 NDER5 — — 0 1 Pin function TIOCB 4 output P2 5 input P25 output PO5 output TIOCB 4 input* TMCI 1 input Note: * TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 = B'10xx. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000, B'01xx B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 369 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P24/PO4/TIOCA4/ TMRI1 This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting (by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4), bit NDER4 in NDERL, and bit P24DDR. TPU Channel Table Below (1) Table Below (2) P24DDR — 0 1 1 NDER4 — — 0 1 Pin function TIOCA 4 output P2 4 input P24 output PO4 output TIOCA 4 input*1 TMRI 1 input TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 — — — — Other than B'01 B'01 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Notes: 1. TIOCA 4 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx. 2. TIOCB 4 output is disabled.

Rev.6.00 Sep. 27, 2007 Page 370 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P23/PO3/TIOCD3/ TMCI0 This pin is used as the 8-bit timer external clock input pin when an external clock is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER3 in NDERL, and bit P23DDR. TPU Channel

3 Setting

Table Below (1) Table Below (2) P23DDR — 0 1 1 NDER3 — — 0 1 Pin function TIOCD 3 output P2 3 input P23 output PO3 output TIOCD 3 input* TMCI 0 input Note: * TIOCD3 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000 B'0010 B'0011 IOD3 to IOD0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'110 B'110 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 371 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P22/PO2/TIOCC3/ TMRI0 This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER2 in NDERL, and bit P22DDR. TPU Channel Table Below (1) Table Below (2) P22DDR — 0 1 1 NDER2 — — 0 1 Pin function TIOCC 3 output P2 2 input P22 output PO2 output TIOCC 3 input*1 TMRI 0 input TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOC3 to IOC0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'101 B'101 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Notes: 1. TIOCC 3 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 2. TIOCD 3 output is disabled. When BFA = 1 or BFB = 1 in TMDR3, output is disabled and setting (2) applies.

Rev.6.00 Sep. 27, 2007 Page 372 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P21/PO1/TIOCB3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER1 in NDERL, and bit P21DDR. TPU Channel Table Below (1) Table Below (2) P21DDR — 0 1 1 NDER1 — — 0 1 Pin function TIOCB 3 output P2 1 input P21 output PO1 output TIOCB 3 input* Note: * TIOCB3 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. TPU Channel (2) (1) (2) (2) (1) (2) MD3 to MD0 B'0000 B'0010 B'0011 IOB3 to IOB0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 — B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'010 B'010 Output function — Output compare output — — PWM mode 2 output x: Don’t care

Rev.6.00 Sep. 27, 2007 Page 373 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P20/PO0/TIOCA3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER0 in NDERL, and bit P20DDR. TPU Channel Table Below (1) Table Below (2) P20DDR — 0 1 1 NDER0 — — 0 1 Pin function TIOCA 3 output P2 0 input P20 output PO0 output TIOCA 3 input*1 TPU Channel (2) (1) (2) (1) (1) (2) MD3 to MD0 B'0000 B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 — — — — Other than B'001 B'001 Output function — Output compare output — PWM mode 1 output*2 PWM mode 2 output x: Don’t care Notes: 1. TIOCA 3 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. 2. TIOCB 3 output is disabled.

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9.4 Port 3

9.4.1 Overview

Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are the same in all operating modes. Figure 9.3 shows the port 3 pin configuration. P35 (I/O) / SCK1 (I/O) P34 (I/O) / SCK0 (I/O) P33 (I/O) / RxD1 (input) P32 (I/O) / RxD0 (input) P31 (I/O) / TxD1 (output) P30 (I/O) / TxD0 (output) Port 3 pins Port 3 Figure 9.3 Port 3 Pin Functions

9.4.2 Register Configuration

Table 9.6 shows the port 3 register configuration. Table 9.6 Port 3 Registers Name Abbreviation R/W Initial Value *2 Address *1 Port 3 data direction register P3DDR W H'00 H'FEB2 Port 3 data register P3DR R/W H'00 H'FF62 Port 3 register PORT3 R Undefined H'FF52 Port 3 open drain control register P3ODR R/W H'00 H'FF76 Notes: 1. Lower 16 bits of the address. 2. Value of bits 5 to 0.

Rev.6.00 Sep. 27, 2007 Page 375 of 1268 REJ09B0220-0600 Port 3 Data Direction Register (P3DDR) Bit : 7 6 5 4 3 2 1 0 — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : Undefined Undefined 0 0 0 0 0 0 R/W : — — W W W W W W P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read. Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P3DDR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and P3DR specifications. Port 3 Data Register (P3DR) Bit : 7 6 5 4 3 2 1 0 — — P35DR P34DR P33DR P32DR P31DR P30DR Initial value : Undefined Undefined 0 0 0 0 0 0 R/W : — — R/W R/W R/W R/W R/W R/W P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P3 5 to P30). Bits 7 and 6 are reserved; they return an undefined value if read, and cannot be modified. P3DR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 376 of 1268 REJ09B0220-0600 Port 3 Register (PORT3) Bit : 7 6 5 4 3 2 1 0 — — P35 P34 P33 P32 P31 P30 R/W : — — R R R R R R Note: * Determined by state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; they return an undefined value if read, and cannot be modified. If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and P3DR are initialized. PORT3 retains its prior state in software standby mode. Port 3 Open Drain Control Register (P3ODR) Bit : 7 6 5 4 3 2 1 0 — — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial value : Undefined Undefined 0 0 0 0 0 0 R/W : — — R/W R/W R/W R/W R/W R/W P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; they return an undefined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

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9.4.3 Pin Functions

Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are shown in table 9.7. Table 9.7 Port 3 Pin Functions Pin Selection Method and Pin Functions P35/SCK1 The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR. CKE1 0 1 C/ A 0 1 — CKE0 0 1 — — P35DDR 0 1 — — — Pin function P3 5 input pin P35 output pin* SCK1 output pin* SCK1 output pin* SCK1 input pin Note: * When P35ODR = 1, the pin becomes an NMOS open-drain output. P34/SCK0 The pin function is switched as shown below according to the combination of bit C/A in the SCI0 SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 0 1 C/ A 0 1 — CKE0 0 1 — — P34DDR 0 1 — — — Pin function P3 4 input pin P34 output pin* SCK0 output pin* SCK0 output pin* SCK0 input pin Note: * When P34ODR = 1, the pin becomes an NMOS open-drain output.

Rev.6.00 Sep. 27, 2007 Page 378 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE 0 1 P33DDR 0 1 — Pin function P3 3 input pin P3 3 output pin* RxD 1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. P32/RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR. RE 0 1 P32DDR 0 1 — Pin function P3 2 input pin P3 2 output pin* RxD 0 input pin Note: * When P32ODR = 1, the pin becomes an NMOS open-drain output. P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in the SCI1 SCR, and bit P31DDR. TE 0 1 P31DDR 0 1 — Pin function P3 1 input pin P3 1 output pin* TxD 1 output pin Note: * When P31ODR = 1, the pin becomes an NMOS open-drain output. P30/TxD0 The pin function is switched as shown below according to the combination of bit TE in the SCI0 SCR, and bit P30DDR. TE 0 1 P30DDR 0 1 — Pin function P3 0 input pin P3 0 output pin* TxD 0 output pin Note: * When P30ODR = 1, the pin becomes an NMOS open-drain output.

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9.5 Port 4

9.5.1 Overview

Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 9.4 shows the port 4 pin configuration. P47 (input) / AN7 (input) / DA1 (output) P46 (input) / AN6 (input) / DA0 (output) P45 (input) / AN5 (input) P44 (input) / AN4 (input) P43 (input) / AN3 (input) P42 (input) / AN2 (input) P41 (input) / AN1 (input) P40 (input) / AN0 (input) Port 4 pins Port 4 Figure 9.4 Port 4 Pin Functions

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9.5.2 Register Configuration

Table 9.8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9.8 Port 4 Register Name Abbreviation R/W Initial Value Address * Port 4 register PORT4 R Undefined H'FF53 Note: * Lower 16 bits of the address. Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed. Bit : 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 R/W : R R R R R R R R Note: * Determined by state of pins P47 to P40.

9.5.3 Pin Functions

Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1).

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9.6 Port 5

9.6.1 Overview

Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2), the A/D converter input pin (ADTRG), interrupt input pins (IRQ4 to IRQ7), and bus control signal I/O pins (WAIT and BREQO). The pin functions can be switched by means of settings in PFCR2 and SYSCR. IRQ4 to IRQ7 only are Schmitt-triggered inputs. Figure 9.5 shows the port 5 pin configuration. P53 (I/O) / ADTRG (input) / IRQ7 (input) / WAIT (input) / BREQO (output) P52 (I/O) / SCK2 (I/O) / IRQ6 (input) P51 (I/O) / RxD2 (input) / IRQ5 (input) P50 (I/O) / TxD2 (output) /IRQ4 (input) Port 5 pins Pin functions in mode 7 P53 (I/O) / ADTRG (input) / IRQ7 (input) P52 (I/O) / SCK2 (I/O) / IRQ6 (input) P51 (I/O) / RxD2 (input) / IRQ5 (input) P50 (I/O) / TxD2 (output) / IRQ4 (input) Pin functions in modes 4 to 6 P53 (I/O) / ADTRG (input) / IRQ7 (input) / WAIT (input) / BREQO (output) P52 (I/O) / SCK2 (I/O) / IRQ6 (input) P51 (I/O) / RxD2 (input) / IRQ5 (input) P50 (I/O) / TxD2 (output) / IRQ4 (input) Port 5 Figure 9.5 Port 5 Pin Functions

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9.6.2 Register Configuration

Table 9.9 shows the port 5 register configuration. Table 9.9 Port 5 Registers Name Abbreviation R/W Initial Value Address *1 Port 5 data direction register P5DDR W H'0 *2 H'FEB4 Port 5 data register P5DR R/W H'0 *2 H'FF64 Port 5 register PORT5 R Undefined H'FF54 Port function control register 2 PFCR2 R/W H'30 H'FFAC System control register SYSCR R/W H'01 H'FF39 Notes: 1. Lower 16 bits of the address. 2. Value of bits 3 to 0. Port 5 Data Direction Register (P5DDR) Bit : 7 6 5 4 3 2 1 0 — — — — P53DDR P52DDR P51DDR P50DDR Initial value : Undefined Undefined Undefined Undefined 0 0 0 0 R/W : — — — — W W W W P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be read. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P5DDR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. As the SCI is initialized, the pin states are determined by the P5DDR and P5DR specifications.

Rev.6.00 Sep. 27, 2007 Page 383 of 1268 REJ09B0220-0600 Port 5 Data Register (P5DR) Bit : 7 6 5 4 3 2 1 0 — — — — P53DR P52DR P51DR P50DR Initial value : Undefined Undefined Undefined Undefined 0 0 0 0 R/W : — — — — R/W R/W R/W R/W P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P5 3 to P50). Bits 7 to 4 are reserved; they return an undefined value if read, and cannot be modified. P5DR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port 5 Register (PORT5) Bit : 7 6 5 4 3 2 1 0 — — — — P53 P52 P51 P50 Initial value : Undefined Undefined Undefined Undefined — * — * — * — * R/W : — — — — R R R R Note: * Determined by state of pins P53 to P50. PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 5 pins (P53 to P50) must always be performed on P5DR. Bits 7 to 4 are reserved; they return an undefined value if read, and cannot be modified. If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT5 contents are determined by the pin states, as P5DDR and P5DR are initialized. PORT5 retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 384 of 1268 REJ09B0220-0600 Port Function Control Register 2 (PFCR2) Bit : 7 6 5 4 3 2 1 0 WAITPS BREQOPS CS167E CS25E ASOD — — — Initial value : 0 0 1 1 0 0 0 0 R/W : R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. Set the WAITPS bit before setting the DDR bit clear to 0 and the WAITE bit in BCRL to 1. Bit 7 WAITPS

0 WAIT input is PF

2 pin (Initial value)

1 WAIT input is P53 pin

Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. Set the BREQOPS bit before setting the BREQOE bit in BCRL to 1. Bit 6 BREQOPS

0 BREQO output is PF

2 pin (Initial value)

1 BREQO output is P53 pin

Bit 5—CS167 Enable (CS167E): Enables or disables CS1, CS6, and CS7 output. For details, see section 9.7, Port 6, and section 9.14, Port G. Bit 4—CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. For details, see section 9.7, Port 6, and section 9.14, Port G. Bit 3—AS Output Disable (ASOD): Enables or disables AS output. For details, see section 9.13, Port F.

Rev.6.00 Sep. 27, 2007 Page 385 of 1268 REJ09B0220-0600 System Control Register (SYSCR) Bit : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROD IRQPAS RAME Initial value : 0 0 0 0 0 0 0 1 R/W : R/W — R/W R/W R/W R/W R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, controls the LWR pin, switches the IRQ4 to IRQ7 input pins, and selects the detected edge for NMI. SYSCR is initialized to H'01 by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select either of two interrupt control modes for the interrupt controller. For details, see section 5, Interrupt Controller. Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. For details, see section 5, Interrupt Controller. Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. For details, see section 9.13, Port F. Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ 4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports. Bit 1 IRQPAS 4 to PA7 used for IRQ4 to IRQ7 input (Initial value)

1 P5 0 to P53 used for IRQ4 to IRQ7 input

Bit 0—RAM Enable (RAME): Enables or disables on-chip RAM. For details, see section 18, RAM.

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9.6.3 Pin Functions

Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2), the A/D converter input pin (ADTRG), interrupt input pins (IRQ4 to IRQ7), and bus control signal I/O pins (WAIT and BREQO). Port 5 pin functions are shown in table 9.10. Table 9.10 Port 5 Pin Functions Pin Selection Method and Pin Functions P53/ADTRG/ IRQ7/WAIT/ BREQO The pin function is switched as shown below according to the combination of the operating mode, bits TRGS1 and TRGS0 in the A/D control register (ADCR), and bits IRQPAS, WAITE, WAITPS, BREQOE, BREQOPS, and P53DDR. Operating mode Modes 4 to 6 Mode 7 [BREQOE · BREQOPS] 0 1 — [WAITE · WAITPS] 0 1 0 1 — P53DDR 0 1 0 1 — — 0 1 Pin function P5 3 input pin P53 output pin WAIT input pin Setting pro- hibited BREQO output pin Setting pro- hibited P53 input pin P53 output pin ADTRG input pin*1 IRQ7 interrupt input pin*2 Notes: 1. ADTRG input when TRGS0 = TRGS1 = 1. 2. IRQ7 input when IRQPAS = 1. P52/SCK2/IRQ6 The pin function is switched as shown below according to the combination of bit C/A in the SCI2 SMR, bits CKE0 and CKE1 in SCR, and bits IRQPAS and P52DDR. CKE1 0 1 C/ A 0 1 — CKE0 0 1 — — P52DDR 0 1 — — — Pin function P5 2 input pin P52 output pin SCK2 output pin SCK2 output pin SCK2 input pin IRQ6 interrupt input pin* Note: * IRQ6 input when IRQPAS = 1.

Rev.6.00 Sep. 27, 2007 Page 387 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P51/RxD2/IRQ5 The pin function is switched as shown below according to the combination of bit RE in the SCI2 SCR, and bits IRQPAS and P51DDR. RE 0 1 P51DDR 0 1 — Pin function P5 1 input pin P5 1 output pin RxD 2 input pin IRQ5 interrupt input pin* Note: * IRQ5 input when IRQPAS = 1. P50/TxD2/IRQ4 The pin function is switched as shown below according to the combination of bit TE in the SCI2 SCR, and bits IRQPAS and P50DDR. TE 0 1 P50DDR 0 1 — Pin function P5 0 input pin P5 0 output pin TxD 2 output pin IRQ4 interrupt input pin* Note: * IRQ4 input when IRQPAS = 1.

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9.7 Port 6

9.7.1 Overview

Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC* I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). The functions of pins P65 to P62 are the same in all operating modes, while the functions of pins P67, P66, P61, and P60 change according to the operating mode. Switching of CS4 to CS7 output can be performed by setting PFCR2. Pins P67 to P64 are Schmitt-triggered inputs. Figure 9.6 shows the port 6 pin configuration. Note: * The DMAC is not supported in the H8S/2321. P67 / IRQ3 / CS7 P66 / IRQ2 / CS6 P65 / IRQ1 P64 / IRQ0 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 P60 / DREQ0 / CS4 Port 6 pins P67 (I/O) / IRQ3 (input) P66 (I/O) / IRQ2 (input) P65 (I/O) / IRQ1 (input) P64 (I/O) / IRQ0 (input) P63 (I/O) / TEND1* (output) P62 (I/O) / DREQ1* (input) P61 (I/O) / TEND0* (output) P60 (I/O) / DREQ0* (input) Pin functions in mode 7 P67 (I/O) / IRQ3 (input) / CS7 (output) P66 (I/O) / IRQ2 (input) / CS6 (output) P65 (I/O) / IRQ1 (input) P64 (I/O) / IRQ0 (input) P63 (I/O) / TEND1* (output) P62 (I/O) / DREQ1* (input) P61 (I/O) / TEND0* (output) / CS5 (output) P60 (I/O) / DREQ0* (input) / CS4 (output) Pin functions in modes 4 to 6 Port 6 Note: * The TEND1, DREQ1, TEND0, and DREQ0 pin functions are not supported in the H8S/2321. Figure 9.6 Port 6 Pin Functions

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9.7.2 Register Configuration

Table 9.11 shows the port 6 register configuration. Table 9.11 Port 6 Registers Name Abbreviation R/W Initial Value Address * Port 6 data direction register P6DDR W H'00 H'FEB5 Port 6 data register P6DR R/W H'00 H'FF65 Port 6 register PORT6 R Undefined H'FF55 Port function control register 2 PFCR2 R/W H'30 H'FFAC Note: * Lower 16 bits of the address. Port 6 Data Direction Register (P6DDR) Bit : 7 6 5 4 3 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P6DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 390 of 1268 REJ09B0220-0600 Port 6 Data Register (P6DR) Bit : 7 6 5 4 3 2 1 0 P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P6 7 to P60). P6DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port 6 Register (PORT6) Bit : 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 R/W : R R R R R R R R Note: * Determined by state of pins P67 to P60. PORT6 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 6 pins (P67 to P60) must always be performed on P6DR. If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT6 contents are determined by the pin states, as P6DDR and P6DR are initialized. PORT6 retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 391 of 1268 REJ09B0220-0600 Port Function Control Register 2 (PFCR2) Bit : 7 6 5 4 3 2 1 0 WAITPS BREQOPS CS167E CS25E ASOD — — — Initial value : 0 0 1 1 0 0 0 0 R/W : R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6, Port 5. Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. For details, see section 9.6, Port 5. Bit 5—CS167 Enable (CS167E): Enables or disables CS 1, CS6, and CS7 output. Clear the DDR bits to 0 before changing the CS167E bit setting. Bit 5 CS167E 1, CS6, and CS7 output disabled (can be used as I/O ports)

1 CS1, CS6, and CS7 output enabled (Initial value)

Bit 4—CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. Clear the DDR bits to 0 before changing the CS25E bit setting. Bit 4 CS25E 2, CS3, CS4, and CS5 output disabled (can be used as I/O ports)

1 CS2, CS3, CS4, and CS5 output enabled (Initial value)

Bit 3—As Output Disable (ASOD): Enables or disables AS output. For details, see section 9.13, Port F. Bits 2 to 0—Reserved: These bits are always read as 0.

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9.7.3 Pin Functions

Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1)*, and bus control output pins (CS4 to CS7). Port 6 pin functions are shown in table 9.12. Table 9.12 Port 6 Pin Functions Pin Selection Method and Pin Functions P67/IRQ3/CS7 The pin function is switched as shown below according to the combination of bits P67DDR and CS167E. Mode Modes 4 to 6 Mode 7 P67DDR 0 1 0 1 CS167E — 0 1 — — Pin function P6 7 input pin P67 output pin CS7 output pin P67 input pin P67 output pin IRQ3 interrupt input pin P66/IRQ2/CS6 The pin function is switched as shown below according to the combination of bits P66DDR and CS167E. Mode Modes 4 to 6 Mode 7 P66DDR 0 1 0 1 CS167E — 0 1 — — Pin function P6 6 input pin P66 output pin CS6 output pin P66 input pin P66 output pin IRQ2 interrupt input pin P65/IRQ1 The pin function is switched as shown below according to bit P65DDR. P65DDR 0 1 Pin function P6 5 input pin P6 5 output pin IRQ1 interrupt input pin P64/IRQ0 The pin function is switched as shown below according to bit P64DDR. P64DDR 0 1 Pin function P6 4 input pin P6 4 output pin IRQ0 interrupt input pin

Rev.6.00 Sep. 27, 2007 Page 393 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions P63/TEND1* The pin function is switched as shown below according to the combination of bit TEE1* in the DMAC DMATCR, and bit P63DDR. TEE1 * 0 1 P63DDR 0 1 — Pin function P6 3 input pin P6 3 output pin TEND1 output* P62/DREQ1* The pin function is switched as shown below according to bit P62DDR. P62DDR 0 1 Pin function P6 2 input pin P6 2 output pin DREQ1 input* P61/TEND0*/CS5 The pin function is switched as shown below according to the combination of bit TEE0* in the DMAC DMATCR, and bits P61DDR and CS25E. Mode Modes 4 to 6 Mode 7 TEE0 * 0 1 0 1 P61DDR 0 1 — 0 1 — Pin function P6 1 input pin P61 output pin CS5 output pin TEND0 output* P61 input pin P61 output pin TEND0 output* P60/DREQ0*/CS4 The pin function is switched as shown below according to the combination of bits P60DDR and CS25E. Mode Modes 4 to 6 Mode 7 P60DDR 0 1 0 1 CS25E — 0 1 — — Pin function P6 0 input pin P60 output pin CS4 output pin P60 input pin P60 output pin DREQ0 input* Note: * The DMAC and the TEND1, DREQ1, TEND0, and DREQ0 pin functions are not supported in the H8S/2321.

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9.8 Port A

9.8.1 Overview

Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and interrupt input pins (IRQ4 to IRQ7). The pin functions change according to the operating mode. IRQ4 to IRQ7 input can be switched to P50 to P53 by setting the IRQPAS bit in SYSCR to 1. The address output or port output function can be selected by means of bits A23E to A20E in PFCR1. Port A has a built-in MOS input pull-up function that can be controlled by software. Pins PA 7 to PA4 are Schmitt-triggered inputs. Figure 9.7 shows the port A pin configuration. PA7 / A23 / IRQ7 PA6 / A22 / IRQ6 PA5 / A21 / IRQ5 PA4 / A20 / IRQ4 PA3 / A19 PA2 / A18 PA1 / A17 PA0 / A16 PA7 (I/O) / A23 (output) / IRQ7 (input) PA6 (I/O) / A22 (output) / IRQ6 (input) PA5 (I/O) / A21 (output) / IRQ5 (input) PA4 (output) / A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) Port A pins Pin functions in modes 4 and 5 Pin functions in mode 6 PA7 (I/O) / IRQ7 (input) PA6 (I/O) / IRQ6 (input) PA5 (I/O) / IRQ5 (input) PA4 (I/O) / IRQ4 (input) PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O) Pin functions in mode 7 PA7 (I/O) / A23 (output) / IRQ7 (input) PA6 (I/O) / A22 (output) / IRQ6 (input) PA5 (I/O) / A21 (output) / IRQ5 (input) PA4 (I/O) / A20 (output) / IRQ4 (input) PA3 (input) / A19 (output) PA2 (input) / A18 (output) PA1 (input) / A17 (output) PA0 (input) / A16 (output) Port A Figure 9.7 Port A Pin Functions

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9.8.2 Register Configuration

Table 9.13 shows the port A register configuration. Table 9.13 Port A Registers Name Abbreviation R/W Initial Value Address * Port A data direction register PADDR W H'00 H'FEB9 Port A data register PADR R/W H'00 H'FF69 Port A register PORTA R Undefined H'FF59 Port A MOS pull-up control register PAPCR R/W H'00 H'FF70 Port A open drain control register PAODR R/W H'00 H'FF77 Port function control register 1 PFCR1 R/W H'0F H'FF45 System control register SYSCR R/W H'01 H'FF39 Note: * Lower 16 bits of the address. Port A Data Direction Register (PADDR) Bit : 7 6 5 4 3 2 1 0 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. PADDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Rev.6.00 Sep. 27, 2007 Page 396 of 1268 REJ09B0220-0600 Port A Data Register (PADR) Bit : 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA 7 to PA0). PADR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port A Register (PORTA) Bit : 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R/W : R R R R R R R R Note: * Determined by state of pins PA7 to PA0. PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA7 to PA0) must always be performed on PADR. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 397 of 1268 REJ09B0220-0600 Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 6 5 4 3 2 1 0 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. All the bits are valid in modes 6 and 7, and bits 7 to 5 are valid in modes 4 and 5. When a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PAPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port A Open Drain Control Register (PAODR) Bit : 7 6 5 4 3 2 1 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA7 to PA0). PAODR is valid only in mode 7. Do not set PAODR bits to 1 in modes 4 to 6. Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 398 of 1268 REJ09B0220-0600 Port Function Control Register 1 (PFCR1) Bit : 7 6 5 4 3 2 1 0 — — — — A23E A22E A21E A20E Initial value : 0 0 0 0 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: Only 0 should be written to these bits. Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23). This bit is valid in modes 4 to 6. Bit 3 A23E

0 DR is output when PA7DDR = 1

1 A 23 is output when PA7DDR = 1 (Initial value)

Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A22). This bit is valid in modes 4 to 6. Bit 2 A22E

0 DR is output when PA6DDR = 1

1 A 22 is output when PA6DDR = 1 (Initial value)

Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). This bit is valid in modes 4 to 6. Bit 1 A21E

0 DR is output when PA5DDR = 1

1 A 21 is output when PA5DDR = 1 (Initial value)

Rev.6.00 Sep. 27, 2007 Page 399 of 1268 REJ09B0220-0600 Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). This bit is valid in modes 4 to 6. Bit 0 A20E

0 DR is output when PA4DDR = 1

1 A 20 is output when PA4DDR = 1 (Initial value)

System Control Register (SYSCR) Bit : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROD IRQPAS RAME Initial value : 0 0 0 0 0 0 0 1 R/W : R/W — R/W R/W R/W R/W R/W R/W Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit is always read as 0, and cannot be modified. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select either of two interrupt control modes for the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 Bit 4 INTM0 Interrupt Control Mode 0 0 0 Interrupt control by I bit (Initial value) 1 — Setting prohibited 1 0 2 Interrupt control by bits I2 to I0 1 — Setting prohibited Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG

0 Interrupt requested at falling edge of NMI input (Initial value)

1 Interrupt requested at rising edge of NMI input

Rev.6.00 Sep. 27, 2007 Page 400 of 1268 REJ09B0220-0600 Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. Bit 2 LWROD 3 is designated as LWR output pin (Initial value) Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports. Bit 1 IRQPAS 4 to PA7 used for IRQ4 to IRQ7 input (Initial value) Bit 0—RAM Enable (RAME): Enables or disables on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME

0 On-chip RAM disabled

1 On-chip RAM enabled (Initial value)

9.8.3 Pin Functions

Port A pins function as address outputs, interrupt input pins (IRQ4 to IRQ7), and I/O ports. Port A pin functions are shown in table 9.14.

Rev.6.00 Sep. 27, 2007 Page 401 of 1268 REJ09B0220-0600 Table 9.14 Port A Pin Functions Pin Selection Method and Pin Functions PA7/A23/IRQ7 The pin function is switched as shown below according to the combination of the operating mode and bits A23E and PA7DDR. Operating mode Modes 4 to 6 Mode 7 A23E 0 1 — PA7DDR 0 1 0 1 0 1 Pin function PA 7 input pin PA7 output pin PA7 input pin A23 output pin PA7 input pin PA7 output pin*2 IRQ7 interrupt input pin*1 Notes: 1. IRQ7 input when IRQPAS = 0. 2. NMOS open-drain output when PA7ODR = 1. PA6/A22/IRQ6 The pin function is switched as shown below according to the combination of the operating mode and bits A22E and PA6DDR. Operating mode Modes 4 to 6 Mode 7 A22E 0 1 — PA6DDR 0 1 0 1 0 1 Pin function PA 6 input pin PA6 output pin PA6 input pin A22 output pin PA6 input pin PA6 output pin*2 IRQ6 interrupt input pin*1 Notes: 1. IRQ6 input when IRQPAS = 0. 2. NMOS open-drain output when PA6ODR = 1. PA5/A21/IRQ5 The pin function is switched as shown below according to the combination of the operating mode and bits A21E and PA5DDR. Operating mode Modes 4 to 6 Mode 7 A21E 0 1 — PA5DDR 0 1 0 1 0 1 Pin function PA 5 input pin PA5 output pin PA5 input pin A21 output pin PA5 input pin PA5 output pin*2 IRQ5 interrupt input pin*1 Notes: 1. IRQ5 input when IRQPAS = 0. 2. NMOS open-drain output when PA5ODR = 1.

Rev.6.00 Sep. 27, 2007 Page 402 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions PA4/A20/IRQ4 The pin function is switched as shown below according to the combination of the operating mode and bits A20E and PA4DDR. Operating mode Modes 4 and 5 Mode 6 Mode 7 A20E 0 1 0 1 — PA4DDR 0 1 — 0 1 0 1 0 1 Pin function Setting pro- hibited PA4 output pin A20 output pin PA4 input pin PA4 output pin PA4 input pin A20 output pin PA4 input pin PA4 output pin*2 IRQ4 interrupt input pin*1 Notes: 1. IRQ4 input when IRQPAS = 0. Note that in this state in modes 4 and 5, although the pin designation is output-only, IRQ4 input is also performed. 2. NMOS open-drain output when PA4ODR = 1. PA3/A19 PA2/A18 The pin function is switched as shown below according to the combination of the operating mode and bit PAnDDR. PA1/A17 PA0/A16 Operating mode Modes 4 and 5 Mode 6 Mode 7 PAnDDR *1 — 0 1 0 1 Pin function Am output pin*1 PAn input pin*1 Am output pin*1 PAn input pin*1 PAn output pin*1 *2 Notes: 1. n = 0 to 3, m = 16 to 19 2. PAn output is NMOS open-drain output when PAnODR = 1.

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9.8.4 MOS Input Pull-Up Function

Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA7 to PA5 in modes 4 and 5, and by all pins in modes 6 and 7. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9.15 summarizes the MOS input pull-up states. Table 9.15 MOS Input Pull-Up States (Port A) Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations 6, 7 PA 7 to PA0 Off Off On/off On/off 4, 5 PA 7 to PA5 On/off On/off PA 4 to PA0 Off Off Legend: Off: MOS input pull-up is always off. On/off: On when PADDR = 0 and PAPCR = 1; otherwise off.

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9.9 Port B

9.9.1 Overview

Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 9.8 shows the port B pin configuration. PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 PB7 (input) / A15 (output) PB6 (input) / A14 (output) PB5 (input) / A13 (output) PB4 (input) / A12 (output) PB3 (input) / A11 (output) PB2 (input) / A10 (output) PB1 (input) / A9 (output) PB0 (input) / A8 (output) Port B pins Pin functions in mode 6 Pin functions in mode 7 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Pin functions in modes 4 and 5 PB7 (I/O) PB6 (I/O) PB5 (I/O) PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O) Port B Figure 9.8 Port B Pin Functions

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9.9.2 Register Configuration

Table 9.16 shows the port B register configuration. Table 9.16 Port B Registers Name Abbreviation R/W Initial Value Address * Port B data direction register PBDDR W H'00 H'FEBA Port B data register PBDR R/W H'00 H'FF6A Port B register PORTB R Undefined H'FF5A Port B MOS pull-up control register PBPCR R/W H'00 H'FF71 Note: * Lower 16 bits of the address. Port B Data Direction Register (PBDDR) Bit : 7 6 5 4 3 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode.

• Modes 4 and 5 The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
• Mode 6 Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port.
• Mode 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port.

Rev.6.00 Sep. 27, 2007 Page 406 of 1268 REJ09B0220-0600 Port B Data Register (PBDR) Bit : 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB 7 to PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port B Register (PORTB) Bit : 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 R/W : R R R R R R R R Note: * Determined by state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 407 of 1268 REJ09B0220-0600 Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. When a PBDDR bit is cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

9.9.3 Pin Functions

Modes 4 and 5: In modes 4 and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 4 and 5 are shown in figure 9.9. A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Port B Figure 9.9 Port B Pin Functions (Modes 4 and 5)

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9.9.4 MOS Input Pull-Up Function

Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When a PBDDR bit is cleared to 0 in mode 6 or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9.17 summarizes the MOS input pull-up states. Table 9.17 MOS Input Pull-Up States (Port B) Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations 4, 5 Off Off Off Off 6, 7 On/off On/off Legend: Off: MOS input pull-up is always off. On/off: On when PBDDR = 0 and PBPCR = 1; otherwise off.

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9.10 Port C

9.10.1 Overview

Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 9.12 shows the port C pin configuration. PC7 / A7 PC6 / A6 PC5 / A5 PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 Port C PC7 (input) / A7 (output) PC6 (input) / A6 (output) PC5 (input) / A5 (output) PC4 (input) / A4 (output) PC3 (input) / A3 (output) PC2 (input) / A2 (output) PC1 (input) / A1 (output) PC0 (input) / A0 (output) Port C pins Pin functions in mode 6 Pin functions in mode 7 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Pin functions in modes 4 and 5 PC7 (I/O) PC6 (I/O) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) Figure 9.12 Port C Pin Functions

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9.10.2 Register Configuration

Table 9.18 shows the port C register configuration. Table 9.18 Port C Registers Name Abbreviation R/W Initial Value Address * Port C data direction register PCDDR W H'00 H'FEBB Port C data register PCDR R/W H'00 H'FF6B Port C register PORTC R Undefined H'FF5B Port C MOS pull-up control register PCPCR R/W H'00 H'FF72 Note: * Lower 16 bits of the address. Port C Data Direction Register (PCDDR) Bit : 7 6 5 4 3 2 1 0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode.

• Modes 4 and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
• Mode 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port.
• Mode 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port.

Rev.6.00 Sep. 27, 2007 Page 412 of 1268 REJ09B0220-0600 Port C Data Register (PCDR) Bit : 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC 7 to PC0). PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port C Register (PORTC) Bit : 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W : R R R R R R R R Note: * Determined by state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 413 of 1268 REJ09B0220-0600 Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. When a PCDDR bit is cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

9.10.3 Pin Functions

Modes 4 and 5: In modes 4 and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 4 and 5 are shown in figure 9.13. A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Port C Figure 9.13 Port C Pin Functions (Modes 4 and 5)

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9.10.4 MOS Input Pull-Up Function

Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When a PCDDR bit is cleared to 0 in mode 6 or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9.19 summarizes the MOS input pull-up states. Table 9.19 MOS Input Pull-Up States (Port C) Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations 4, 5 Off Off Off Off 6, 7 On/off On/off Legend: Off: MOS input pull-up is always off. On/off: On when PCDDR = 0 and PCPCR = 1; otherwise off.

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9.11 Port D

9.11.1 Overview

Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 9.16 shows the port D pin configuration. PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 Port D D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Port D pins Pin functions in modes 4 to 6 PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Pin functions in mode 7 Figure 9.16 Port D Pin Functions

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9.11.2 Register Configuration

Table 9.20 shows the port D register configuration. Table 9.20 Port D Registers Name Abbreviation R/W Initial Value Address * Port D data direction register PDDDR W H'00 H'FEBC Port D data register PDDR R/W H'00 H'FF6C Port D register PORTD R Undefined H'FF5C Port D MOS pull-up control register PDPCR R/W H'00 H'FF73 Note: * Lower 16 bits of the address. Port D Data Direction Register (PDDDR) Bit : 7 6 5 4 3 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

• Modes 4 to 6 The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O.
• Mode 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.

Rev.6.00 Sep. 27, 2007 Page 418 of 1268 REJ09B0220-0600 Port D Data Register (PDDR) Bit : 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD 7 to PD0). PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port D Register (PORTD) Bit : 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 R/W : R R R R R R R R Note: * Determined by state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 419 of 1268 REJ09B0220-0600 Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

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9.11.3 Pin Functions

Modes 4 to 6: In modes 4 to 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 4 to 6 are shown in figure 9.17. D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Port D Figure 9.17 Port D Pin Functions (Modes 4 to 6) Mode 7: In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Port D pin functions in mode 7 are shown in figure 9.18. PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Port D Figure 9.18 Port D Pin Functions (Mode 7)

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9.11.4 MOS Input Pull-Up Function

Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9.21 summarizes the MOS input pull-up states. Table 9.21 MOS Input Pull-Up States (Port D) Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations 4 to 6 Off Off Off Off

7 On/off On/off

Legend: Off: MOS input pull-up is always off. On/off: On when PDDDR = 0 and PDPCR = 1; otherwise off.

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9.12 Port E

9.12.1 Overview

Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 9.19 shows the port E pin configuration. PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 PE7 (I/O) / D7 (I/O) PE6 (I/O) / D6 (I/O) PE5 (I/O) / D5 (I/O) PE4 (I/O) / D4 (I/O) PE3 (I/O) / D3 (I/O) PE2 (I/O) / D2 (I/O) PE1 (I/O) / D1 (I/O) PE0 (I/O) / D0 (I/O) Port E pins Pin functions in modes 4 to 6 Pin functions in mode 7 PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Port E Figure 9.19 Port E Pin Functions

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9.12.2 Register Configuration

Table 9.22 shows the port E register configuration. Table 9.22 Port E Registers Name Abbreviation R/W Initial Value Address * Port E data direction register PEDDR W H'00 H'FEBD Port E data register PEDR R/W H'00 H'FF6D Port E register PORTE R Undefined H'FF5D Port E MOS pull-up control register PEPCR R/W H'00 H'FF74 Note: * Lower 16 bits of the address. Port E Data Direction Register (PEDDR) Bit : 7 6 5 4 3 2 1 0 PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

• Modes 4 to 6 When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
• Mode 7 Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.

Rev.6.00 Sep. 27, 2007 Page 424 of 1268 REJ09B0220-0600 Port E Data Register (PEDR) Bit : 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE 7 to PE0). PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port E Register (PORTE) Bit : 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 R/W : R R R R R R R R Note: * Determined by state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 425 of 1268 REJ09B0220-0600 Port E MOS Pull-Up Control Register (PEPCR) Bit : 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) in mode 4, 5, or 6 with 8-bit bus mode selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

9.12.3 Pin Functions

Modes 4 to 6: In modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected, port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. Port E pin functions in modes 4 to 6 are shown in figure 9.20.

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9.12.4 MOS Input Pull-Up Function

Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 4, 5, or 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9.23 summarizes the MOS input pull-up states. Table 9.23 MOS Input Pull-Up States (Port E) Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations

7 Off Off On/off On/off

Legend: Off: MOS input pull-up is always off. On/off: On when PEDDR = 0 and PEPCR = 1; otherwise off.

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9.13 Port F

9.13.1 Overview

Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins ( AS, RD, HWR, LWR, LCAS*, WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin. The AS, LWR, and BREQO output pins can be switched by means of settings in PFCR2 and SYSCR. Figure 9.22 shows the port F pin configuration. Note: * LCAS is not supported in the H8S/2321. PF7 / φ PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR PF2 / LCAS* / WAIT / BREQO PF1 / BACK PF0 / BREQ Port F Port F pins PF7 (input) / φ (output) PF6 (I/O) PF5 (I/O) PF4 (I/O) PF3 (I/O) PF2 (I/O) PF1 (I/O) PF0 (I/O) Pin functions in mode 7 PF7 (input) / φ (output) PF6 (I/O) / AS (output) RD (output) HWR (output) PF3 (I/O) / LWR (output) PF2 (I/O) / LCAS* (output) / WAIT (input) / BREQO (output) PF1 (I/O) / BACK (output) PF0 (I/O) / BREQ (input) Pin functions in modes 4 to 6 Note: * LCAS is not supported in the H8S/2321. Figure 9.22 Port F Pin Functions

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9.13.2 Register Configuration

Table 9.24 shows the port F register configuration. Table 9.24 Port F Registers Name Abbreviation R/W Initial Value Address *1 Port F data direction register PFDDR W H'80/H'00 *2 H'FEBE Port F data register PFDR R/W H'00 H'FF6E Port F register PORTF R Undefined H'FF5E Port function control register 2 PFCR2 R/W H'30 H'FFAC System control register SYSCR R/W H'01 H'FF39 Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode. Port F Data Direction Register (PFDDR) Bit : 7 6 5 4 3 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 Initial value : 1 0 0 0 0 0 0 0 R/W : W W W W W W W W Mode 7 Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Rev.6.00 Sep. 27, 2007 Page 430 of 1268 REJ09B0220-0600 Port F Data Register (PFDR) Bit : 7 6 5 4 3 2 1 0 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port F Register (PORTF) Bit : 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 R/W : R R R R R R R R Note: * Determined by state of pins PF7 to PF0. PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 431 of 1268 REJ09B0220-0600 Port Function Control Register 2 (PFCR2) Bit : 7 6 5 4 3 2 1 0 WAITPS BREQOPS CS167E CS25E ASOD — — — Initial value : 0 0 1 1 0 0 0 0 R/W : R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. Set the WAITPS bit before setting the DDR bit clear to 0 and the WAITE bit in BCRL to 1. Bit 7 WAITPS

0 WAIT input is pin PF

2 (Initial value)

1 WAIT input is pin P53

Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. Set the BREQOPS bit before setting the BREQOE bit in BCRL to 1. Bit 6 BREQOPS

0 BREQO output is pin PF

2 (Initial value)

1 BREQO output is pin P53

Bit 5—CS167 Enable (CS167E): Enables or disables CS1, CS6, and CS7 output. For details, see section 9.7, Port 6, and section 9.14, Port G. Bit 4—CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. For details, see section 9.7, Port 6, and section 9.14, Port G. Bit 3—AS Output Disable (ASOD): Enables or disables AS output. This bit is valid in modes 4 to 6. Bit 3 ASOD 6 is used as AS output pin (Initial value)

1 PF6 is designated as I/O port, and does not function as AS output pin

Rev.6.00 Sep. 27, 2007 Page 432 of 1268 REJ09B0220-0600 Bits 2 to 0—Reserved: These bits are always read as 0. System Control Register (SYSCR) Bit : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROE IRQPAS RAME Initial value : 0 0 0 0 0 0 0 1 R/W : R/W — R/W R/W R/W R/W R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, controls the LWR pin, switches the IRQ4 to IRQ7 input pins, and selects the detected edge for NMI. SYSCR is initialized to H'01 by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select either of two interrupt control modes for the interrupt controller. For details, see section 5, Interrupt Controller. Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. For details, see section 5, Interrupt Controller. Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. This bit is valid in modes 4 to 6. Bit 2 LWROD 3 is designated as LWR output pin (Initial value) Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ4 to IRQ7. For details, see section 9.6, Port 5. Bit 0—RAM Enable (RAME): Enables or disables on-chip RAM. For details, see section 18, RAM.

Rev.6.00 Sep. 27, 2007 Page 433 of 1268 REJ09B0220-0600

9.13.3 Pin Functions

Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS*, WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9.25. Note: * The LCAS is not supported in the H8S/2321. Table 9.25 Port F Pin Functions Pin Selection Method and Pin Functions PF7/φ The pin function is switched as shown below according to bit PF7DDR. PF7DDR 0 1 Pin function PF 7 input pin φ output pin PF6/AS The pin function is switched as shown below according to the operating mode, bit PF6DDR, and bit ASOD in PFCR2. Operating Mode Modes 4 to 6 Mode 7 ASOD 0 1 — PF6DDR — 0 1 0 1 Pin function AS output pin PF6 input pin PF6 output pin PF6 input pin PF6 output pin PF5/RD The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode Modes 4 to 6 Mode 7 PF5DDR — 0 1 Pin function RD output pin PF 5 input pin PF 5 output pin PF4/HWR The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode Modes 4 to 6 Mode 7 PF4DDR — 0 1 Pin function HWR output pin PF 4 input pin PF 4 output pin

Rev.6.00 Sep. 27, 2007 Page 434 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions PF3/LWR The pin function is switched as shown below according to the operating mode, bit PF3DDR, and bit LWROD in SYSCR. Operating Mode Modes 4 to 6 Mode 7 LWROD 0 1 — PF3DDR — 0 1 0 1 Pin function LWR output pin PF3 input pin PF3 output pin PF3 input pin PF3 output pin PF2/LCAS*2/WAIT/ BREQO The pin function is switched as shown below according to the combination of the operating mode, and bits RMTS2 to RMTS0* 2, BREQOE, WAITE, ABW5 to ABW2, BREQOPS, WAITPS, and PF2DDR. Operating Mode Modes 4 to 6 Mode 7 [DRAM space setting]*2 · [16-bit access setting] 0 1 — [BREQOE · BREQOPS] 0 1 — — [WAITE · WAITPS] 0 1 0 1 — — PF2DDR 0 1 0 1 — — — 0 1 Pin function PF 2 input pin PF2 output pin WAIT input pin*1 Setting pro- hibited BREQO output pin Setting pro- hibited LCAS output pin*2 PF2 input pin PF2 output pin Notes: 1. When DRAM space is designated for 8-bit access and PF2 is used as the WAIT input, this pin can be used for WAIT input when all areas selected as DRAM space are 8-bit space and normal space other than DRAM space is 16-bit space. 2. The DRAM interface and LCAS are not supported in the H8S/2321. PF1/BACK The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF1DDR. Operating Mode Modes 4 to 6 Mode 7 BRLE 0 1 — PF1DDR 0 1 — 0 1 Pin function PF1 input pin PF1 output pin BACK output pin PF1 input pin PF1 output pin

Rev.6.00 Sep. 27, 2007 Page 435 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions PF0/BREQ The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode Modes 4 to 6 Mode 7 BRLE 0 1 — PF0DDR 0 1 — 0 1 Pin function PF0 input pin PF0 output pin BREQ input pin PF0 input pin PF0 output pin

9.14 Port G

9.14.1 Overview

Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins ( CS0 to CS3, and CAS*). Enabling or disabling of CS1 to CS3 output can be changed by a setting in PFCR2. Figure 9.23 shows the port G pin configuration. Note: * CAS is not supported in the H8S/2321. PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3 PG0 / CAS* PG4 (I/O) PG3 (I/O) PG2 (I/O) PG1 (I/O) PG0 (I/O) Port G pins Pin functions in mode 7Pin functions in modes 4 to 6 PG4 (input) / CS0 (output) PG3 (I/O) / CS1 (output) PG2 (I/O) / CS2 (output) PG1 (I/O) / CS3 (output) PG0 (I/O) / CAS* (output) Port G Note: * CAS is not supported in the H8S/2321. Figure 9.23 Port G Pin Functions

Rev.6.00 Sep. 27, 2007 Page 436 of 1268 REJ09B0220-0600

9.14.2 Register Configuration

Table 9.26 shows the port G register configuration. Table 9.26 Port G Registers Name Abbreviation R/W Initial Value *2 Address *1 Port G data direction register PGDDR W H'10/H'00 *3 H'FEBF Port G data register PGDR R/W H'00 H'FF6F Port G register PORTG R Undefined H'FF5F Port function register 2 PFCR2 R/W H'30 H'FFAC Notes: 1. Lower 16 bits of the address. 2. Value of bits 4 to 0. 3. Initial value depends on the mode. Port G Data Direction Register (PGDDR) Bit : 7 6 5 4 3 2 1 0 — — — PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Modes 4 and 5 Initial value : Undefined Undefined Undefined 1 0 0 0 0 R/W : — — — W W W W W Modes 6 and 7 Initial value : Undefined Undefined Undefined 0 0 0 0 0 R/W : — — — W W W W W PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read. The PG4DDR bit is initialized by a reset, and in hardware standby mode, to 1 in modes 4 and 5, and to 0 in modes 6 and 7. PGDDR retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode.

Rev.6.00 Sep. 27, 2007 Page 437 of 1268 REJ09B0220-0600 Port G Data Register (PGDR) Bit : 7 6 5 4 3 2 1 0 — — — PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined 0 0 0 0 0 R/W : — — — R/W R/W R/W R/W R/W PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG 4 to PG0). Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port G Register (PORTG) Bit : 7 6 5 4 3 2 1 0 — — — PG4 PG 3 PG2 PG1 PG0 Initial value : Undefined Undefined Undefined — * — * — * — * — * R/W : — — — R R R R R Note: * Determined by state of pins PG4 to PG0. PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG4 to PG0) must always be performed on PGDR. Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as PGDDR and PGDR are initialized. PORTG retains its prior state in software standby mode.

Rev.6.00 Sep. 27, 2007 Page 438 of 1268 REJ09B0220-0600 Port Function Control Register 2 (PFCR2) Bit : 7 6 5 4 3 2 1 0 WAITPS BREQOPS CS167E CS25E ASOD — — — Initial value : 0 0 1 1 0 0 0 0 R/W : R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6, Port 5. Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. For details, see section 9.6, Port 5. Bit 5—CS167 Enable (CS167E): Enables or disables CS 1, CS6, and CS7 output. Change the CS167E setting only when the DDR bits are cleared to 0. Bit 5 CS167E 1, CS6, and CS7 output disabled (can be used as I/O ports) Bit 4—CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. Change the CS25E setting only when the DDR bits are cleared to 0. Bit 4 CS25E 2, CS3, CS4, and CS5 output disabled (can be used as I/O ports) Bit 3—AS Output Disable (ASOD): Enables or disables AS output. For details, see section 9.13, Port F. Bits 2 to 0—Reserved: These bits are always read as 0.

Rev.6.00 Sep. 27, 2007 Page 439 of 1268 REJ09B0220-0600

9.14.3 Pin Functions

Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS*). The pin functions are different in mode 7, and modes 4 to 6. Port G pin functions are shown in table 9.27. Note: * The CAS is not supported in the H8S/2321. Table 9.27 Port G Pin Functions Pin Selection Method and Pin Functions PG4/CS0 The pin function is switched as shown below according to the operating mode and bit PG4DDR. Operating Mode Modes 4 to 6 Mode 7 PG4DDR 0 1 0 1 Pin function PG 4 input pin CS0 output pin PG 4 input pin PG 4 output pin PG3/CS1 The pin function is switched as shown below according to the operating mode and bits PG3DDR and CS167E. Operating Mode Modes 4 to 6 Mode 7 PG3DDR 0 1 0 1 CS167E — 0 1 — — Pin function PG 3 input pin PG3 output pin CS1 output pin PG3 input pin PG3 output pin PG2/CS2 The pin function is switched as shown below according to the operating mode and bits PG2DDR and CS25E. Operating Mode Modes 4 to 6 Mode 7 PG2DDR 0 1 0 1 CS25E — 0 1 — — Pin function PG 2 input pin PG2 output pin CS2 output pin PG2 input pin PG2 output pin

Rev.6.00 Sep. 27, 2007 Page 440 of 1268 REJ09B0220-0600 Pin Selection Method and Pin Functions PG1/CS3 The pin function is switched as shown below according to the operating mode and bits PG1DDR and CS25E. Operating Mode Modes 4 to 6 Mode 7 PG1DDR 0 1 0 1 CS25E — 0 1 — — Pin function PG 1 input pin PG1 output pin CS3 output pin PG1 input pin PG1 output pin PG0/CAS* The pin function is switched as shown below according to the combination of the operating mode and bits RMTS2 to RMTS0* and PG0DDR. Operating Mode Modes 4 to 6 Mode 7 RMTS2 to RMTS0* B'000, B'100 to B'111 B'001 to B'011 PG0DDR 0 1 — 0 1 Pin function PG 0 input pin PG0 output pin CAS output pin* PG0 input pin PG0 output pin Note: * The DRAM interface and CAS are not supported in the H8S/2321.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 441 of 1268 REJ09B0220-0600 Section 10 16-Bit Timer Pulse Unit (TPU)

10.1 Overview

The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.

10.1.1 Features

• Maximum 16-pulse input/output ⎯ A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ⎯ TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel: ⎯ Waveform output at compare match: Selection of 0, 1, or toggle output ⎯ Input capture function: Selection of rising edge, falling edge, or both edge detection ⎯ Counter clear operation: Counter clearing possible by compare match or input capture ⎯ Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation ⎯ PWM mode: Any PWM output duty can be set Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3 ⎯ Input capture register double-buffering possible ⎯ Automatic rewriting of output compare register possible
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5 ⎯ Two-phase encoder pulse up/down-count possible
• Cascaded operation ⎯ Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow
• Fast access via internal 16-bit bus ⎯ Fast access is possible via a 16-bit bus interface

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 442 of 1268 REJ09B0220-0600

• 26 interrupt sources ⎯ For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ⎯ For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently
• Automatic transfer of register data ⎯ Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) or DMA controller (DMAC)* activation
• Programmable pulse generator (PPG) output trigger can be generated ⎯ Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger
• A/D converter conversion start trigger can be generated ⎯ Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger
• Module stop mode can be set ⎯ As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode Note: * The DMAC is not supported in the H8S/2321.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 443 of 1268 REJ09B0220-0600 Table 10.1 lists the functions of the TPU. Table 10.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock φ/1 φ/4 φ/16 φ/64 TCLKA TCLKB TCLKC TCLKD φ/1 φ/4 φ/16 φ/64 φ/256 TCLKA TCLKB φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKA TCLKB TCLKC φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA φ/1 φ/4 φ/16 φ/64 φ/1024 TCLKA TCLKC φ/1 φ/4 φ/16 φ/64 φ/256 TCLKA TCLKC TCLKD General registers TGR0A TGR0B TGR1A TGR1B TGR2A TGR2B TGR3A TGR3B TGR4A TGR4B TGR5A TGR5B General registers/ buffer registers TGR0C TGR0D — — TGR3C TGR3D — — I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation — — — —

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 444 of 1268 REJ09B0220-0600 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DMAC* activation TGR0A compare match or input capture TGR1A compare match or input capture TGR2A compare match or input capture TGR3A compare match or input capture TGR4A compare match or input capture TGR5A compare match or input capture DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture A/D con- version start trigger TGR0A compare match or input capture TGR1A compare match or input capture TGR2A compare match or input capture TGR3A compare match or input capture TGR4A compare match or input capture TGR5A compare match or input capture PPG trigger TGR0A/ TGR0B compare match or input capture TGR1A/ TGR1B compare match or input capture TGR2A/ TGR2B compare match or input capture TGR3A/ TGR3B compare match or input capture — — Interrupt sources 5 sources

• Compare match or input capture 0A
• Compare match or input capture 0B
• Compare match or input capture 0C
• Compare match or input capture 0D
• Overflow 4 sources
• Compare match or input capture 1A
• Compare match or input capture 1B
• Overflow
• Underflow 4 sources
• Compare match or input capture 2A
• Compare match or input capture 2B
• Overflow
• Underflow 5 sources
• Compare match or input capture 3A
• Compare match or input capture 3B
• Compare match or input capture 3C
• Compare match or input capture 3D
• Overflow 4 sources
• Compare match or input capture 4A
• Compare match or input capture 4B
• Overflow
• Underflow 4 sources
• Compare match or input capture 5A
• Compare match or input capture 5B
• Overflow
• Underflow Legend: : Possible —: Not possible Note: * The DMAC is not supported in the H8S/2321.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 445 of 1268 REJ09B0220-0600

10.1.2 Block Diagram

Figure 10.1 shows a block diagram of the TPU. Channel 3 TMDR TIORL TSR TCR TIORH TIER TGRA TCNT TGRB TGRC TGRD Channel 4 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Control logic for channels 3 to 5 TGRA TCNT TGRB TGRC Channel 1 TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 0 TMDR TSR TCR TIORH TIER Control logic for channels 0 to 2 TGRD TSYRTSTR Input/output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Clock input φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA TCLKB TCLKC TCLKD Input/output pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3: Channel 4: Channel 5: Interrupt request signals Channel 0: Channel 1: Channel 2: Internal data bus A/D conversion start request signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Channel 3: Channel 4: Channel 5: Internal clock: External clock: Channel 0: Channel 1: Channel 2: TMDR TSR TCR TIOR TIER TGRA TCNT TGRB Channel 2 Common Channel 5 Bus interface Figure 10.1 Block Diagram of TPU

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 446 of 1268 REJ09B0220-0600

10.1.3 Pin Configuration

Table 10.2 summarizes the TPU pins. Table 10.2 TPU Pins Channel Name Symbol I/O Function All Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) Clock input C TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) Clock input D TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input)

0 Input capture/out

TIOCA0 I/O TGR0A input capture input/output compare output/PWM output pin Input capture/out compare match B0 TIOCB0 I/O TGR0B input capture input/output compare output/PWM output pin Input capture/out compare match C0 TIOCC0 I/O TGR0C input capture input/output compare output/PWM output pin Input capture/out compare match D0 TIOCD0 I/O TGR0D input capture input/output compare output/PWM output pin

1 Input capture/out

TIOCA1 I/O TGR1A input capture input/output compare output/PWM output pin Input capture/out compare match B1 TIOCB1 I/O TGR1B input capture input/output compare output/PWM output pin

2 Input capture/out

TIOCA2 I/O TGR2A input capture input/output compare output/PWM output pin Input capture/out compare match B2 TIOCB2 I/O TGR2B input capture input/output compare output/PWM output pin

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 447 of 1268 REJ09B0220-0600 Channel Name Symbol I/O Function

3 Input capture/out

TIOCA3 I/O TGR3A input capture input/output compare output/PWM output pin Input capture/out compare match B3 TIOCB3 I/O TGR3B input capture input/output compare output/PWM output pin Input capture/out compare match C3 TIOCC3 I/O TGR3C input capture input/output compare output/PWM output pin Input capture/out compare match D3 TIOCD3 I/O TGR3D input capture input/output compare output/PWM output pin

4 Input capture/out

TIOCA4 I/O TGR4A input capture input/output compare output/PWM output pin Input capture/out compare match B4 TIOCB4 I/O TGR4B input capture input/output compare output/PWM output pin

5 Input capture/out

TIOCA5 I/O TGR5A input capture input/output compare output/PWM output pin Input capture/out compare match B5 TIOCB5 I/O TGR5B input capture input/output compare output/PWM output pin

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 448 of 1268 REJ09B0220-0600

10.1.4 Register Configuration

Table 10.3 summarizes the TPU registers. Table 10.3 TPU Registers Channel Name Abbreviation R/W Initial Value Address *1

0 Timer control register 0 TCR0 R/W H'00 H'FFD0

Timer mode register 0 TMDR0 R/W H'C0 H'FFD1 Timer I/O control register 0H TIOR0H R/W H'00 H'FFD2 Timer I/O control register 0L TIOR0L R/W H'00 H'FFD3 Timer interrupt enable register 0 TIER0 R/W H'40 H'FFD4 Timer status register 0 TSR0 R/(W) *2 H'C0 H'FFD5 Timer counter 0 TCNT0 R/W H'0000 H'FFD6 Timer general register 0A TGR0A R/W H'FFFF H'FFD8 Timer general register 0B TGR0B R/W H'FFFF H'FFDA Timer general register 0C TGR0C R/W H'FFFF H'FFDC Timer general register 0D TGR0D R/W H'FFFF H'FFDE

1 Timer control register 1 TCR1 R/W H'00 H'FFE0

Timer mode register 1 TMDR1 R/W H'C0 H'FFE1 Timer I/O control register 1 TIOR1 R/W H'00 H'FFE2 Timer interrupt enable register 1 TIER1 R/W H'40 H'FFE4 Timer status register 1 TSR1 R/(W) *2 H'C0 H'FFE5 Timer counter 1 TCNT1 R/W H'0000 H'FFE6 Timer general register 1A TGR1A R/W H'FFFF H'FFE8 Timer general register 1B TGR1B R/W H'FFFF H'FFEA

2 Timer control register 2 TCR2 R/W H'00 H'FFF0

Timer mode register 2 TMDR2 R/W H'C0 H'FFF1 Timer I/O control register 2 TIOR2 R/W H'00 H'FFF2 Timer interrupt enable register 2 TIER2 R/W H'40 H'FFF4 Timer status register 2 TSR2 R/(W) *2 H'C0 H'FFF5 Timer counter 2 TCNT2 R/W H'0000 H'FFF6 Timer general register 2A TGR2A R/W H'FFFF H'FFF8 Timer general register 2B TGR2B R/W H'FFFF H'FFFA

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 449 of 1268 REJ09B0220-0600 Channel Name Abbreviation R/W Initial Value Address *1

3 Timer control register 3 TCR3 R/W H'00 H'FE80

Timer mode register 3 TMDR3 R/W H'C0 H'FE81 Timer I/O control register 3H TIOR3H R/W H'00 H'FE82 Timer I/O control register 3L TIOR3L R/W H'00 H'FE83 Timer interrupt enable register 3 TIER3 R/W H'40 H'FE84 Timer status register 3 TSR3 R/(W) *2 H'C0 H'FE85 Timer counter 3 TCNT3 R/W H'0000 H'FE86 Timer general register 3A TGR3A R/W H'FFFF H'FE88 Timer general register 3B TGR3B R/W H'FFFF H'FE8A Timer general register 3C TGR3C R/W H'FFFF H'FE8C Timer general register 3D TGR3D R/W H'FFFF H'FE8E

4 Timer control register 4 TCR4 R/W H'00 H'FE90

Timer mode register 4 TMDR4 R/W H'C0 H'FE91 Timer I/O control register 4 TIOR4 R/W H'00 H'FE92 Timer interrupt enable register 4 TIER4 R/W H'40 H'FE94 Timer status register 4 TSR4 R/(W) *2 H'C0 H'FE95 Timer counter 4 TCNT4 R/W H'0000 H'FE96 Timer general register 4A TGR4A R/W H'FFFF H'FE98 Timer general register 4B TGR4B R/W H'FFFF H'FE9A

5 Timer control register 5 TCR5 R/W H'00 H'FEA0

Timer mode register 5 TMDR5 R/W H'C0 H'FEA1 Timer I/O control register 5 TIOR5 R/W H'00 H'FEA2 Timer interrupt enable register 5 TIER5 R/W H'40 H'FEA4 Timer status register 5 TSR5 R/(W) *2 H'C0 H'FEA5 Timer counter 5 TCNT5 R/W H'0000 H'FEA6 Timer general register 5A TGR5A R/W H'FFFF H'FEA8 Timer general register 5B TGR5B R/W H'FFFF H'FEAA All Timer start register TSTR R/W H'00 H'FFC0 Timer synchro register TSYR R/W H'00 H'FFC1 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 450 of 1268 REJ09B0220-0600

10.2 Register Descriptions

10.2.1 Timer Control Registers (TCR)

Channel 0: TCR0 Channel 3: TCR3 Bit : 7 6 5 4 3 2 1 0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 Bit : 7 6 5 4 3 2 1 0 — CCLR1 CCLR0 CKEG1 C KEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 R/W : — R/W R/W R/W R/W R/W R/W R/W The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset and in hardware standby mode. TCR register settings should be made only when TCNT operation is stopped.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 451 of 1268 REJ09B0220-0600 Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source. Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 0, 3 0 0 0 TCNT clearing disabled (Initial value)

1 TCNT cleared by TGRA compare match/input

1 0 TCNT cleared by TGRB compare match/input capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/ synchronous operation*1 1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture*2 1 0 TCNT cleared by TGRD compare match/input capture*2 channel performing synchronous clearing/ synchronous operation* Channel Bit 7 Reserved* Bit 6 CCLR1 Bit 5 CCLR0 1, 2, 4, 5 0 0 0 TCNT clearing disabled (Initial value) 1 0 TCNT cleared by TGRB compare match/input capture channel performing synchronous clearing/ synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 452 of 1268 REJ09B0220-0600 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Bit 4 CKEG1 Bit 3 CKEG0 0 0 Count at rising edge (Initial value)

1 Count at falling edge

1 — Count at both edges Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected. Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 10.4 shows the clock sources that can be set for each channel. Table 10.4 TPU Clock Sources Internal Clock External Clock Channel φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA TCLKB TCLKC TCLKD Overflow/ Underflow on Another Channel 0 o o o o o o o o 1 o o o o o o o o 2 o o o o o o o o 3 o o o o o o o o 4 o o o o o o o o 5 o o o o o o o o Legend: o: Setting Blank: No setting

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 453 of 1268 REJ09B0220-0600 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 0 0 0 0 Internal clock: counts on φ/1 (Initial value)

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

1 0 0 0 Internal clock: counts on φ/1 (Initial value) 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on φ/256

1 Counts on TCNT2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode. Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 2 0 0 0 Internal clock: counts on φ/1 (Initial value) 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on φ/1024

Note: This setting is ignored when channel 2 is in phase counting mode.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 454 of 1268 REJ09B0220-0600 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 3 0 0 0 Internal clock: counts on φ/1 (Initial value) 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on φ/256

1 Internal clock: counts on φ/4096

4 0 0 0 Internal clock: counts on φ/1 (Initial value) 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on φ/1024

1 Counts on TCNT5 overflow/underflow

Note: This setting is ignored when channel 4 is in phase counting mode. Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 5 0 0 0 Internal clock: counts on φ/1 (Initial value) 1 0 Internal clock: counts on φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on φ/256 Note: This setting is ignored when channel 5 is in phase counting mode.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 455 of 1268 REJ09B0220-0600

10.2.2 Timer Mode Registers (TMDR)

Channel 0: TMDR0 Channel 3: TMDR3 Bit : 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 R/W : — — R/W R/W R/W R/W R/W R/W Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 Bit : 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 R/W : — — — — R/W R/W R/W R/W The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset and in hardware standby mode. TMDR register settings should be made only when TCNT operation is stopped. Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1. Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB

0 TGRB operates normally (Initial value)

1 TGRB and TGRD used together for buffer operation

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 456 of 1268 REJ09B0220-0600 Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4 BFA

0 TGRA operates normally (Initial value)

1 TGRA and TGRC used together for buffer operation

Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3 MD3* Bit 2 MD2* Bit 1 MD1 Bit 0 MD0 0 0 0 0 Normal operation (Initial value)

1 Reserved

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 Phase counting mode 4

1 * * * — *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. For these channels, 0 should always be written to MD2.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 457 of 1268 REJ09B0220-0600

10.2.3 Timer I/O Control Registers (TIOR)

Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 Bit : 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Channel 0: TIOR0L Channel 3: TIOR3L Bit : 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR registers are initialized to H'00 by a reset and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 458 of 1268 REJ09B0220-0600 Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 0 0 0 0 0 Output disabled (Initial value) TGR0B is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge

1 Input capture at falling edge

1 * TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at both edges 1 * * Capture input source is channel 1/count clock Input capture at TCNT1 count-up/count-down* *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 459 of 1268 REJ09B0220-0600 Channel Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 0 0 0 0 0 Output disabled (Initial value) TGR0D is output compare register*2 Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR0D is input capture register* Capture input source is TIOCD0 pin Input capture at both edges 1 * * Capture input source is channel 1/count clock Input capture at TCNT1 count-up/count-down* *: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 460 of 1268 REJ09B0220-0600 Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 1 0 0 0 0 Output disabled (Initial value) TGR1B is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * Capture input source is TIOCB1 pin Input capture at both edges 1 * * TGR1B is input capture register Capture input source is TGR0C compare match/ input capture Input capture at generation of TGR0C compare match/input capture *: Don’t care Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 2 0 0 0 0 Output disabled (Initial value) TGR2B is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 * 0 0 Capture input Input capture at rising edge 1 source is Input capture at falling edge 1 * TGR2B is input capture register TIOCB2 pin Input capture at both edges *: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 461 of 1268 REJ09B0220-0600 Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 3 0 0 0 0 Output disabled (Initial value) TGR3B is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR3B is input capture register Capture input source is TIOCB3 pin Input capture at both edges 1 * * Capture input source is channel 4/count clock Input capture at TCNT4 count-up/count-down*1 *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 462 of 1268 REJ09B0220-0600 Channel Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 3 0 0 0 0 Output disabled (Initial value) TGR3D is output compare register*2 Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR3D is input capture register* Capture input source is TIOCD3 pin Input capture at both edges 1 * * Capture input source is channel 4/count clock Input capture at TCNT4 count- up/count-down* *: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 463 of 1268 REJ09B0220-0600 Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 4 0 0 0 0 Output disabled (Initial value) TGR4B is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR4B is input capture register Capture input source is TIOCB4 pin Input capture at both edges 1 * * Capture input source is TGR3C compare match/ input capture Input capture at generation of TGR3C compare match/ input capture *: Don’t care Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 5 0 0 0 0 Output disabled (Initial value) TGR5B is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 * 0 0 Input capture at rising edge 1 * TGR5B is input capture register Capture input source is TIOCB5 pin Input capture at both edges *: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 464 of 1268 REJ09B0220-0600 Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 0 0 0 0 0 Output disabled (Initial value) TGR0A is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR0A is input capture register Capture input source is TIOCA0 pin Input capture at both edges 1 * * Capture input source is channel 1/ count clock Input capture at TCNT1 count- up/count-down *: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 465 of 1268 REJ09B0220-0600 Channel Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 0 0 0 0 0 Output disabled (Initial value) TGR0C is output compare register*1 Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR0C is input capture register* Capture input source is TIOCC0 pin Input capture at both edges 1 * * Capture input source is channel 1/count clock Input capture at TCNT1 count- up/count-down *: Don’t care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 466 of 1268 REJ09B0220-0600 Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 1 0 0 0 0 Output disabled (Initial value) TGR1A is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR1A is input capture register Capture input source is TIOCA1 pin Input capture at both edges 1 * * Capture input source is TGR0A compare match/ input capture Input capture at generation of channel 0/TGR0A compare match/input capture *: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 467 of 1268 REJ09B0220-0600 Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 2 0 0 0 0 Output disabled (Initial val u TGR2A is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 * 0 0 TGR2A is Capture input Input capture at rising edge 1 input capture source is Input capture at falling edge 1 * register TIOCA2 pin Input capture at both edges *: Don’t care Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 3 0 0 0 0 Output disabled (Initial value) TGR3A is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR3A is input capture register Capture input source is TIOCA3 pin Input capture at both edges 1 * * Capture input source is channel 4/count clock Input capture at TCNT4 count- up/count-down *: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 468 of 1268 REJ09B0220-0600 Channel Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 3 0 0 0 0 Output disabled (Initial value) TGR3C is output compare register*1 Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR3C is input capture register* Capture input source is TIOCC3 pin Input capture at both edges 1 * * Capture input source is channel 4/count clock Input capture at TCNT4 count- up/count-down *: Don’t care Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 469 of 1268 REJ09B0220-0600 Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 4 0 0 0 0 Output disabled (Initial value) TGR4A is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 * TGR4A is input capture register Capture input source is TIOCA4 pin Input capture at both edges 1 * * Capture input source is TGR3A compare match/ input capture Input capture at generation of TGR3A compare match/input capture *: Don’t care Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 5 0 0 0 0 Output disabled (Initial value) TGR5A is output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 1 output at compare match Initial output is 1 output Toggle output at compare match 1 * 0 0 Input capture at rising edge 1 * TGR4A is input capture register Capture input source is TIOCA4 pin Input capture at both edges *: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 470 of 1268 REJ09B0220-0600

10.2.4 Timer Interrupt Enable Registers (TIER)

Channel 0: TIER0 Channel 3: TIER3 Bit : 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 R/W : R/W — — R/W R/W R/W R/W R/W Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit : 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 R/W : R/W — R/W R/W — — R/W R/W The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset and in hardware standby mode. Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE

0 A/D conversion start request generation disabled (Initial value)

1 A/D conversion start request generation enabled

Bit 6—Reserved: This bit cannot be modified and is always read as 1. Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU bit when the TCFU bit in TSR is set to 1 in channels 1 and 2. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 471 of 1268 REJ09B0220-0600 Bit 5 TCIEU

0 Interrupt requests (TCIU) by TCFU disabled (Initial value)

1 Interrupt requests (TCIU) by TCFU enabled

Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV bit when the TCFV bit in TSR is set to 1. Bit 4 TCIEV

0 Interrupt requests (TCIV) by TCFV disabled (Initial value)

1 Interrupt requests (TCIV) by TCFV enabled

Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGIED

0 Interrupt requests (TGID) by TGFD disabled (Initial value)

1 Interrupt requests (TGID) by TGFD enabled

Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC

0 Interrupt requests (TGIC) by TGFC disabled (Initial value)

1 Interrupt requests (TGIC) by TGFC enabled

Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 472 of 1268 REJ09B0220-0600 Bit 1 TGIEB

0 Interrupt requests (TGIB) by TGFB disabled (Initial value)

1 Interrupt requests (TGIB) by TGFB enabled

Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA

0 Interrupt requests (TGIA) by TGFA disabled (Initial value)

1 Interrupt requests (TGIA) by TGFA enabled

10.2.5 Timer Status Registers (TSR)

Channel 0: TSR0 Channel 3: TSR3 Bit : 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Note: * Only 0 can be written, to clear the flag. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit : 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Note: * Only 0 can be written, to clear the flag.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 473 of 1268 REJ09B0220-0600 The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset and in hardware standby mode. Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD

0 TCNT counts down

1 TCNT counts up (Initial value)

Bit 6—Reserved: This bit cannot be modified and is always read as 1. Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCFU 0 [Clearing condition] (Initial value) When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV 0 [Clearing condition] (Initial value) When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 474 of 1268 REJ09B0220-0600 Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD 0 [Clearing conditions] (Initial value)

• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGFC

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1 1 [Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 475 of 1268 REJ09B0220-0600 Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB 0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions]
• When TCNT = TGRB while TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
• When DMAC * is activated by TGIA interrupt while DTA bit of DMABCR in DMAC* is 1
• When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions]
• When TCNT = TGRA while TGRA is functioning as output compare register
• When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Note: * The DMAC is not supported in the H8S/2321.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 476 of 1268 REJ09B0220-0600

10.2.6 Timer Counters (TCNT)

Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up- counters. The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 477 of 1268 REJ09B0220-0600

10.2.7 Timer General Registers (TGR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA-TGRC and TGRB-TGRD.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 478 of 1268 REJ09B0220-0600

10.2.8 Timer Start Register (TSTR)

Bit : 7 6 5 4 3 2 1 0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 R/W : — — R/W R/W R/W R/W R/W R/W TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bits 7 and 6—Reserved: Must always be written with 0. Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn

0 TCNTn count operation is stopped (Initial value)

1 TCNTn performs count operation

n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 479 of 1268 REJ09B0220-0600

10.2.9 Timer Synchro Register (TSYR)

Bit : 7 6 5 4 3 2 1 0 — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value : 0 0 0 0 0 0 0 0 R/W : — — R/W R/W R/W R/W R/W R/W TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6—Reserved: Must always be written with 0. Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels *1, and synchronous clearing through counter clearing on another channel*2 are possible. Bit n SYNCn

0 TCNTn operates independently (TCNT presetting/clearing is unrelated to

other channels) (Initial value)

1 TCNTn performs synchronous operation

TCNT synchronous presetting*1/synchronous clearing*2 is possible n = 5 to 0 Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 480 of 1268 REJ09B0220-0600

10.2.10 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 13—Module Stop (MSTP13): Specifies the TPU module stop mode. Bit 13 MSTP13

0 TPU module stop mode cleared

1 TPU module stop mode set (Initial value)

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 481 of 1268 REJ09B0220-0600

10.3 Interface to Bus Master

10.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.2. Bus interface H Internal data bus L Bus master Module data busTCNTH TCNTL Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] 10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 10.3 to 10.5.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 483 of 1268 REJ09B0220-0600

10.4 Operation

10.4.1 Overview

Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation

• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR.
• When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. Cascaded Operation: The channel 1 counter (TCNT1) and channel 2 counter (TCNT2), or the channel 4 counter (TCNT4) and channel 5 counter (TCNT5), can be connected together to operate as a 32-bit counter. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up/down-counting. This can be used for two-phase encoder pulse input.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 484 of 1268 REJ09B0220-0600

10.4.2 Basic Functions

Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.

• Example of count operation setting procedure Figure 10.6 shows an example of the count operation setting procedure. Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count <Periodic counter> [1] [2] [4] [3] [5] Free-running counter Start count <Free-running counter> [5] [1] [2] [3] [4] [5] Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the TGR selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the TGR selected in [2]. Set the CST bit in TSTR to 1 to start the counter operation. Figure 10.6 Example of Counter Operation Setting Procedure

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 490 of 1268 REJ09B0220-0600

10.4.3 Synchronous Operation

In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10.14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set TCNT Synchronous presetting <Synchronous presetting> [1] [2] Synchronous clearing Select counter clearing source <Counter clearing> [3] Start count [5] Set synchronous counter clearing <Synchronous clearing> [4] Start count [5] Clearing source generation channel? No Yes [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Set synchronous operation Figure 10.14 Example of Synchronous Operation Setting Procedure

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 491 of 1268 REJ09B0220-0600 Example of Synchronous Operation: Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 10.4.6, PWM Modes. TCNT0 to TCNT2 values H'0000 TIOC0A TIOC1A Time TGR0B Synchronous clearing by TGR0B compare match TGR2A TGR1A TGR2B TGR0A TGR1B TIOC2A Figure 10.15 Example of Synchronous Operation

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 492 of 1268 REJ09B0220-0600

10.4.4 Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.5 shows the register combinations used in buffer operation. Table 10.5 Register Combinations in Buffer Operation Channel Timer General Re gister Buffer Register

0 TGR0A TGR0C

3 TGR3A TGR3C

• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.16. Buffer register Timer general register TCNTComparator Compare match signal Figure 10.16 Compare Match Buffer Operation

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 496 of 1268 REJ09B0220-0600

10.4.5 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.6 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 10.6 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT1 TCNT2 Channels 4 and 5 TCNT4 TCNT5 Example of Cascaded Operation Setting Procedure: Figure 10.21 shows an example of the setting procedure for cascaded operation. Set cascading Cascaded operation Start count <Cascaded operation> [1] [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'111 to select TCNT2 (TCNT5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 10.21 Cascaded Operation Setting Procedure

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 498 of 1268 REJ09B0220-0600 TCLKC TCNT2 FFFD TCNT1 0001 TCLKD FFFE FFFF 0000 0001 0002 0001 0000 FFFF 0000 0000 Figure 10.23 Example of Cascaded Operation (2)

10.4.6 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.

• PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2 PWM output is generated using one TGR as the period register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the period and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 499 of 1268 REJ09B0220-0600 The correspondence between PWM output pins and registers is shown in table 10.7. Table 10.7 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2

0 TGR0A TIOCA0 TIOCA0

1 TGR1A TIOCA1 TIOCA1

2 TGR2A TIOCA2 TIOCA2

3 TGR3A TIOCA3 TIOCA3

4 TGR4A TIOCA4 TIOCA4

5 TGR5A TIOCA5 TIOCA5

Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 500 of 1268 REJ09B0220-0600 Example of PWM Mode Setting Procedure: Figure 10.24 shows an example of the PWM mode setting procedure. Select counter clock PWM mode Select counter clearing source Select waveform output level <PWM mode> [1] [2] [3] Set TGR [4] Set PWM mode [5] Start count [6] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the period in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Figure 10.24 Example of PWM Mode Setting Procedure

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 501 of 1268 REJ09B0220-0600 Examples of PWM Mode Operation: Figure 10.25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the value set in TGRB as the duty. TCNT value TGRA H'0000 TIOCA Time TGRB Counter cleared by TGRA compare match Figure 10.25 Example of PWM Mode Operation (1)

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 504 of 1268 REJ09B0220-0600

10.4.7 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10.8 shows the correspondence between external clock pins and channels. Table 10.8 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 or 5 is set to phase counting mode TCLKA TCLKB When channel 2 or 4 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10.28 shows an example of the phase counting mode setting procedure. Select phase counting mode Phase counting mode Start count <Phase counting mode> [1] [2] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 10.28 Example of Phase Counting Mode Setting Procedure

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 509 of 1268 REJ09B0220-0600 Phase Counting Mode Application Example: Figure 10.33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the compare match function, and are set with the speed control period and position control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. This procedure enables accurate position/speed detection to be achieved.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 510 of 1268 REJ09B0220-0600 TCNT1 TCNT0 Channel 1 TGR1A (speed period capture) TGR0A (speed control period) TGR1B (position period capture) TGR0C (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 TCLKA TCLKB Edge detection circuit Figure 10.33 Phase Counting Mode Application Example

10.5 Interrupts

10.5.1 Interrupt Sources and Priorities

There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 511 of 1268 REJ09B0220-0600 Table 10.13 lists the TPU interrupt sources. Table 10.13 TPU Interrupts Channel Interrupt Source DMAC* Activation DTC Activation Priority

0 TGI0A TGR0A input capture/compare match Possible Possible High

TGI0B TGR0B input capture/compare match Not possible Possible TGI0C TGR0C input capture/compare match Not possible Possible TGI0D TGR0D input capture/compare match Not possible Possible TCI0V TCNT0 overflow Not possible Not possible

1 TGI1A TGR1A input capture/compare match Possible Possible

TGI1B TGR1B input capture/compare match Not possible Possible TCI1V TCNT1 overflow Not possible Not possible TCI1U TCNT1 underflow Not possible Not possible

2 TGI2A TGR2A input capture/compare match Possible Possible

TGI2B TGR2B input capture/compare match Not possible Possible TCI2V TCNT2 overflow Not possible Not possible TCI2U TCNT2 underflow Not possible Not possible

3 TGI3A TGR3A input capture/compare match Possible Possible

TGI3B TGR3B input capture/compare match Not possible Possible TGI3C TGR3C input capture/compare match Not possible Possible TGI3D TGR3D input capture/compare match Not possible Possible TCI3V TCNT3 overflow Not possible Not possible

4 TGI4A TGR4A input capture/compare match Possible Possible

TGI4B TGR4B input capture/compare match Not possible Possible TCI4V TCNT4 overflow Not possible Not possible TCI4U TCNT4 underflow Not possible Not possible

5 TGI5A TGR5A input capture/compare match Possible Possible

TGI5B TGR5B input capture/compare match Not possible Possible TCI5V TCNT5 overflow Not possible Not possible TCI5U TCNT5 underflow Not possible Not possible Low Notes: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. * The DMAC is not supported in the H8S/2321.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 512 of 1268 REJ09B0220-0600 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.

10.5.2 DTC/DMAC * Activation

DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller. A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. DMAC* Activation: The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (Not Supported in the H8S/2321). In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. Note: * The DMAC is not supported in the H8S/2321.

10.5.3 A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started.

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 513 of 1268 REJ09B0220-0600 In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.

10.6 Operation Timing

10.6.1 Input/Output Timing

TCNT Count Timing: Figure 10.34 shows TCNT count timing in internal clock operation, and figure 10.35 shows TCNT count timing in external clock operation. TCNT TCNT input clock Internal clock φ N–1 N N+1 N+2 Falling edge Rising edge Figure 10.34 Count Timing in Internal Clock Operation TCNT TCNT input clock External clock φ N–1 N N+1 N+2 Rising edge Falling edgeFalling edge Figure 10.35 Count Timing in External Clock Operation

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 517 of 1268 REJ09B0220-0600

10.6.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figure 10.42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. TGR TCNT TCNT input clock φ N N N+1 Compare match signal TGF flag TGI interrupt Figure 10.42 TGI Interrupt Timing (Compare Match)

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 518 of 1268 REJ09B0220-0600 TGF Flag Setting Timing in Case of Input Capture: Figure 10.43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. TGR TCNT Input capture signal φ N N TGF flag TGI interrupt Figure 10.43 TGI Interrupt Timing (Input Capture)

Section 10 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Sep. 27, 2007 Page 521 of 1268 REJ09B0220-0600

10.7 Usage Notes

Note that the kinds of operation and contention described below can occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.48 shows the input clock conditions in phase counting mode. Overlap Phase differ- ence Phase differ- enceOverlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 10.48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = φ (N + 1) Where f : Counter frequency φ : Operating frequency N : TGR set value

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 531 of 1268 REJ09B0220-0600 Section 11 Programmable Pulse Generator (PPG)

11.1 Overview

The chip has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate both simultaneously and independently.

11.1.1 Features

PPG features are listed below.

• 16-bit output data ⎯ Maximum 16-bit data can be output, and output can be enabled on a bit-by-bit basis
• Four output groups ⎯ Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs
• Selectable output trigger signals ⎯ Output trigger signals can be selected for each group from the compare match signals of four TPU channels
• Non-overlap mode ⎯ A non-overlap margin can be provided between pulse outputs
• Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) * ⎯ The compare match signals selected as output trigger signals can activate the DTC or DMAC for sequential output of data without CPU intervention Note: * The DMAC is not supported in the H8S/2321.
• Inverted output can be set ⎯ Inverted data can be output for each group
• Module stop mode can be set ⎯ As the initial setting, PPG operation is halted. Register access is enabled by exiting module stop mode

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 532 of 1268 REJ09B0220-0600

11.1.2 Block Diagram

Figure 11.1 shows a block diagram of the PPG. Compare match signals PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Legend: PMR: PCR: NDERH: NDERL: NDRH: NDRL: PODRH: PODRL: PPG output mode register PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Internal data bus Pulse output pins, group 3 Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 PODRHPODRL NDRH NDRL Control logic NDERH PMR NDERL PCR Figure 11.1 Block Diagram of PPG

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 533 of 1268 REJ09B0220-0600

11.1.3 Pin Configuration

Table 11.1 summarizes the PPG pins. Table 11.1 PPG Pins Name Symbol I/O Function Pulse output 0 PO0 Output Group 0 pulse output Pulse output 1 PO1 Output Pulse output 2 PO2 Output Pulse output 3 PO3 Output Pulse output 4 PO4 Output Group 1 pulse output Pulse output 5 PO5 Output Pulse output 6 PO6 Output Pulse output 7 PO7 Output Pulse output 8 PO8 Output Group 2 pulse output Pulse output 9 PO9 Output Pulse output 10 PO10 Output Pulse output 11 PO11 Output Pulse output 12 PO12 Output Group 3 pulse output Pulse output 13 PO13 Output Pulse output 14 PO14 Output Pulse output 15 PO15 Output

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 534 of 1268 REJ09B0220-0600

11.1.4 Registers

Table 11.2 summarizes the PPG registers. Table 11.2 PPG Registers Name Abbreviation R/W Initial Value Address *1 PPG output control register PCR R/W H'FF H'FF46 PPG output mode register PMR R/W H'F0 H'FF47 Next data enable register H NDERH R/W H'00 H'FF48 Next data enable register L NDERL R/W H'00 H'FF49 Output data register H PODRH R/(W) *2 H'00 H'FF4A Output data register L PODRL R/(W) *2 H'00 H'FF4B Next data register H NDRH R/W H'00 H'FF4C/ H'FF4E*3 Next data register L NDRL R/W H'00 H'FF4D/ H'FF4F*3 Port 1 data direction register P1DDR W H'00 H'FEB0 Port 2 data direction register P2DDR W H'00 H'FEB1 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Bits used for pulse output cannot be written to. 3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FF4C. When the output triggers are different, the NDRH address is H'FF4E for group 2 and H'FF4C for group 3. Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FF4D. When the output triggers are different, the NDRL address is H'FF4F for group 0 and H'FF4D for group 1.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 535 of 1268 REJ09B0220-0600

11.2 Register Descriptions

11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)

Bit : 7 6 5 4 3 2 1 0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W NDERL Bit : 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from NDR to PODR and the output value does not change. NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. NDERH Bits 7 to 0—Next Data En able 15 to 8 (NDER15 to NDER8): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8

0 Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not

transferred to POD15 to POD8) (Initial value)

1 Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred

to POD15 to POD8)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 536 of 1268 REJ09B0220-0600 NDERL Bits 7 to 0—Next Data En able 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0

0 Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not

transferred to POD7 to POD0) (Initial value)

1 Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to

POD7 to POD0)

11.2.2 Output Data Regist ers H and L (PODRH, PODRL)

Bit : 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value : 0 0 0 0 0 0 0 0 R/W : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * PODRL Bit : 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 537 of 1268 REJ09B0220-0600

11.2.3 Next Data Registers H and L (NDRH, NDRL)

NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access. NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode.

11.2.4 Notes on NDR Access

The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the same compare match event, the NDRH address is H'FF4C. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FF4E consists entirely of reserved bits that cannot be modified and are always read as 1. Address H'FF4C Bit : 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Address H'FF4E Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FF4D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FF4F consists entirely of reserved bits that cannot be modified and are always read as 1.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 538 of 1268 REJ09B0220-0600 Address H'FF4D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Address H'FF4F Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FF4C and the address of the lower 4 bits (group 2) is H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4 of address H'FF4E are reserved bits that cannot be modified and are always read as 1. Address H'FF4C Bit : 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 — — — — Initial value : 0 0 0 0 1 1 1 1 R/W : R/W R/W R/W R/W — — — — Address H'FF4E Bit : 7 6 5 4 3 2 1 0 — — — — NDR11 NDR10 NDR9 NDR8 Initial value : 1 1 1 1 0 0 0 0 R/W : — — — — R/W R/W R/W R/W If pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in NDRL (group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F. Bits 3 to 0 of address H'FF4D and bits 7 to 4 of address H'FF4F are reserved bits that cannot be modified and are always read as 1.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 539 of 1268 REJ09B0220-0600 Address H'FF4D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 — — — — Initial value : 0 0 0 0 1 1 1 1 R/W : R/W R/W R/W R/W — — — — Address H'FF4F Bit : 7 6 5 4 3 2 1 0 — — — — NDR3 NDR2 NDR1 NDR0 Initial value : 1 1 1 1 0 0 0 0 R/W : — — — — R/W R/W R/W R/W

11.2.5 PPG Output Control Register (PCR)

Bit : 7 6 5 4 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a group-by-group basis. PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match that triggers pulse output group 3 (pins PO15 to PO12). Output Trigger for Pulse Output Group 3 0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 540 of 1268 REJ09B0220-0600 Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8). Output Trigger for Pulse Output Group 2 0 0 Compare match in TPU channel 0 1 0 Compare match in TPU channel 2 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). Output Trigger for Pulse Output Group 1 0 0 Compare match in TPU channel 0 1 0 Compare match in TPU channel 2 Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match that triggers pulse output group 0 (pins PO3 to PO0). Output Trigger for Pulse Output Group 0 0 0 Compare match in TPU channel 0 1 0 Compare match in TPU channel 2

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 541 of 1268 REJ09B0220-0600

11.2.6 PPG Output Mode Register (PMR)

Bit : 7 6 5 4 3 2 1 0 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value : 1 1 1 1 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA. The output values change at compare match A and B. For details, see section 11.3.4, Non-Overlapping Pulse Output. PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output group 3 (pins PO15 to PO12). Bit 7 G3INV

0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)

(Initial value) Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output group 2 (pins PO11 to PO8). Bit 6 G2INV

0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)

(Initial value)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 542 of 1268 REJ09B0220-0600 Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). Bit 5 G1INV

0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)

(Initial value) Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output group 0 (pins PO3 to PO0). Bit 4 G0INV

0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)

(Initial value) Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse output group 3 (pins PO15 to PO12). Bit 3 G3NOV

0 Normal operation in pulse output group 3 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at

compare match A or B in the selected TPU channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse output group 2 (pins PO11 to PO8). Bit 2 G2NOV

0 Normal operation in pulse output group 2 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 543 of 1268 REJ09B0220-0600 Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). Bit 1 G1NOV

0 Normal operation in pulse output group 1 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at

compare match A or B in the selected TPU channel) Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse output group 0 (pins PO3 to PO0). Bit 0 G0NOV

0 Normal operation in pulse output group 0 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

11.2.7 Port 1 Data Di rection Register (P1DDR)

Bit : 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further information about P1DDR, see section 9, I/O Port.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 544 of 1268 REJ09B0220-0600

11.2.8 Port 2 Data Di rection Register (P2DDR)

Bit : 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1. For further information about P2DDR, see section 9, I/O Port.

11.2.9 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP11 bit in MSTPCR is set to 1, PPG operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 11—Module Stop (MSTP11): Specifies the PPG module stop mode. Bit 11 MSTP11

0 PPG module stop mode cleared

1 PPG module stop mode set (Initial value)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 545 of 1268 REJ09B0220-0600

11.3 Operation

11.3.1 Overview

PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 11.2 illustrates the PPG output operation and table 11.3 summarizes the PPG operating conditions. Output trigger signal Pulse output pin Internal data bus Normal output/inverted output C PODRQD NDER Q NDRQD DDR Q Figure 11.2 PPG Output Operation Table 11.3 PPG Operating Conditions NDER DDR Pin Function 0 0 Generic input port

1 Generic output port

1 0 Generic input port (but the PODR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the PODR bit)

1 PPG pulse output

Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. For details of non-overlapping operation, see section 11.3.4, Non- Overlapping Pulse Output.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 546 of 1268 REJ09B0220-0600

11.3.2 Output Timing

If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N+1 φ TGRA N Compare match A signal NDRH mnPODRH PO8 to PO15 n mn Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 547 of 1268 REJ09B0220-0600

11.3.3 Normal Pulse Output

Sample Setup Procedure for Normal Pulse Output: Figure 11.4 shows a sample procedure for setting up normal pulse output. Select TGR functions [1] Set TGRA value Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start count Set next pulse output data Normal PPG output No Yes TPU setup Port and PPG setup TPU setup [2] [3] [4] [5] [6] [7] [8] [9] [10] Compare match? [1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger period. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC * can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. Note:* The DMAC is not supported in the H8S/2321. Figure 11.4 Setup Procedure for Normal Pulse Output (Example)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 548 of 1268 REJ09B0220-0600 Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TCNT TGRA H'0000 NDRH 00 80 C0 40 60 20 30 10 18 08 88PODRH PO15 PO14 PO13 PO12 PO11 Time Compare match C080 C080 40 60 20 30 10 18 08 88 80 C0 40 Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output compare register and the counter will be cleared by compare match A. Set the trigger period in TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt. [2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. [3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. [4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC* is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. Note: * The DMAC is not supported in the H8S/2321.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 549 of 1268 REJ09B0220-0600

11.3.4 Non-Overlapping Pulse Output

Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11.6 shows a sample procedure for setting up non-overlapping pulse output. Select TGR functions [1] Set TGR values Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set next pulse output data Start count Set next pulse output data Compare match? No Yes TPU setup PPG setup TPU setup Non-overlapping PPG output Set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled). [2] Set the pulse output trigger period in TGRB and the non-overlap margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC * can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Note:* The DMAC is not supported in the H8S/2321. Figure 11.6 Setup Procedure for Non-Overlapping Pulse Output (Example)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 550 of 1268 REJ09B0220-0600 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11.7 shows an example in which pulse output is used for four- phase complementary non-overlapping pulse output. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non-overlap margin Figure 11.7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 551 of 1268 REJ09B0220-0600 [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. [2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. [3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. [4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC * is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. Note: * The DMAC is not supported in the H8S/2321.

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 552 of 1268 REJ09B0220-0600

11.3.5 Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11.8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11.7. TCNT value TCNT TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 11.8 Inverted Pulse Output (Example)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 553 of 1268 REJ09B0220-0600

11.3.6 Pulse Output Triggered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11.9 shows the timing of this output. φ N M N TIOC pin Input capture signal NDR PODR MNPO Figure 11.9 Pulse Output Triggered by Input Capture (Example)

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 554 of 1268 REJ09B0220-0600

11.4 Usage Notes

11.4.1 Operation of Pulse Output Pins

Pins PO0 to PO15 are also used for other supporting functions such as the TPU. When output by another supporting function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur.

11.4.2 Note on Non-Overlapping Output

During non-overlapping operation, the transfer of NDR bit values to PODR bits takes place as follows.

• NDR bits are always transferred to PODR bits at compare match A.
• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11.10 illustrates the non-overlapping pulse output operation. Compare match A Compare match B Pulse output pin Normal output/inverted output C PODRQD NDER Q NDRQD Internal data bus DDR Figure 11.10 Non-Overlapping Pulse Output

Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep. 27, 2007 Page 556 of 1268 REJ09B0220-0600

Rev.6.00 Sep. 27, 2007 Page 557 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers

12.1 Overview

The chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle.

12.1.1 Features

The features of the 8-bit timer module are listed below.

• Seleyction of four clock sources The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an external clock input (enabling use as an external event counter)
• Seleyction of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal
• Timyer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output
• Provision for cascading of two channels ⎯ Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-bit count mode) ⎯ Channel 1 can be used to count channel 0 compare matches (compare match count mode)
• Three independent interrupts Compare match A and B and overflow interrupts can be requested independently
• A/D converter conversion start trigger can be generated Channel 0 compare match A signal can be used as an A/D converter conversion start trigger
• Module stop mode can be set As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting module stop mode

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12.1.2 Block Diagram

Figure 12.1 shows a block diagram of the 8-bit timer module. External clock source Internal clock sources φ/8 φ/64 φ/8192 Clock 1 Clock 0 Compare match A1 Compare match A0 Clear 1 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals TMO0 TMRI0 Internal bus TCORA0 Comparator A0 Comparator B0 TCORB0 TCSR0 TCR0 TCORA1 Comparator A1 TCNT1 Comparator B1 TCORB1 TCSR1 TCR1 TMCI0 TMCI1 TCNT0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 TMO1 TMRI1 A/D conversion start request signal Clock select Control logic Clear 0 Figure 12.1 Block Diagram of 8-Bit Timer Module

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12.1.3 Pin Configuration

Table 12.1 summarizes the input and output pins of the 8-bit timer module. Table 12.1 Input and Output Pins of 8-Bit Timer Channel Name Symbol I/O Function

0 Timer output pin 0 TMO0 Output Outputs at compare match

Timer clock input pin 0 TMCI0 Input Inputs external clock for counter Timer reset input pin 0 TMRI0 Input Inputs external reset to counter

1 Timer output pin 1 TMO1 Output Outputs at compare match

Timer clock input pin 1 TMCI1 Input Inputs external clock for counter Timer reset input pin 1 TMRI1 Input Inputs external reset to counter

12.1.4 Register Configuration

Table 12.2 summarizes the registers of the 8-bit timer module. Table 12.2 8-Bit Timer Registers Channel Name Abbreviation R/W Initial value Address *1

0 Timer control register 0 TCR0 R/W H'00 H'FFB0

Timer control/status register 0 TCSR0 R/(W) *2 H'00 H'FFB2 Time constant register A0 TCORA0 R/W H'FF H'FFB4 Time constant register B0 TCORB0 R/W H'FF H'FFB6 Timer counter 0 TCNT0 R/W H'00 H'FFB8

1 Timer control register 1 TCR1 R/W H'00 H'FFB1

Timer control/status register 1 TCSR1 R/(W) *2 H'10 H'FFB3 Time constant register A1 TCORA1 R/W H'FF H'FFB5 Time constant register B1 TCORB1 R/W H'FF H'FFB7 Timer counter 1 TCNT1 R/W H'00 H'FFB9 All Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address 2. Only 0 can be written to bits 7 to 5, to clear these flags. Each pair of registers for channel 0 and channel 1 is a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by a word transfer instruction.

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12.2 Register Descriptions

12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 in TCR. The CPU can read or write to TCNT0 and TCNT1 at all times. TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by a word transfer instruction. TCNT0 and TCNT1 can be cleared by an external reset input or by a compare match signal. Which signal is to be used for clearing is selected by clock clear bits CCLR1 and CCLR0 in TCR. When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode.

12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORA0 and TCORA1 are 8-bit readable/writable registers. TCORA0 and TCORA1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCOR write cycle.

Rev.6.00 Sep. 27, 2007 Page 561 of 1268 REJ09B0220-0600 The timer output can be freely controlled by these compare match signals and the settings of bits OS1 and OS0 in TCSR. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode.

12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCOR write cycle. The timer output can be freely controlled by these compare match signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.

12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1)

Bit : 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at which TCNT is cleared, and enable interrupts. TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode. For details of this timing, see section 12.3, Operation.

Rev.6.00 Sep. 27, 2007 Page 562 of 1268 REJ09B0220-0600 Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. Bit 7 CMIEB

0 CMFB interrupt requests (CMIB) are disabled (Initial value)

1 CMFB interrupt requests (CMIB) are enabled

Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. Bit 6 CMIEA

0 CMFA interrupt requests (CMIA) are disabled (Initial value)

1 CMFA interrupt requests (CMIA) are enabled

Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. Bit 5 OVIE

0 OVF interrupt requests (OVI) are disabled (Initial value)

1 OVF interrupt requests (OVI) are enabled

Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by which TCNT is cleared: by compare match A or B, or by an external reset input. Bit 4 CCLR1 Bit 3 CCLR0 0 0 Clearing is disabled (Initial value)

1 Clear by compare match A

1 0 Clear by compare match B

1 Clear by rising edge of external reset input

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192. The falling edge of the selected internal clock triggers the count.

Rev.6.00 Sep. 27, 2007 Page 563 of 1268 REJ09B0220-0600 When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1. Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 0 0 0 Clock input disabled (Initial value)

1 Internal clock, counted at falling edge of φ/8

1 0 Internal clock, counted at falling edge of φ/64

1 Internal clock, counted at falling edge of φ/8192

1 0 0 For channel 0: count at TCNT1 overflow signal * For channel 1: count at TCNT0 compare match A*

1 External clock, counted at rising edge

1 0 External clock, counted at falling edge

1 External clock, counted at both rising and falling edges

Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting.

12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)

Bit : 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/(W) * R/(W) * R/(W) * R/W R/W R/W R/W R/W TCSR1 Bit : 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3 OS2 OS1 OS0 Initial value : 0 0 0 1 0 0 0 0 R/W : R/(W) * R/(W) * R/(W) * — R/W R/W R/W R/W Note: * Only 0 can be written to bits 7 to 5, to clear these flags.

Rev.6.00 Sep. 27, 2007 Page 564 of 1268 REJ09B0220-0600 TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode. Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB 0 [Clearing conditions] (Initial value)

• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
• When DTC is activated by CMIB interr upt while DISEL bit of MRB in DTC is 0 1 [Setting condition] Set when TCNT matches TCORB Bit 6—Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match. Bit 6 CMFA

0 [Clearing conditions] (Initial value)

• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
• When DTC is activated by CMIA interr upt while DISEL bit of MRB in DTC is 0 1 [Setting condition] Set when TCNT matches TCORA Bit 5—Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00). Bit 5 OVF

0 [Clearing condition] (Initial value) Cleared by reading OVF when OVF = 1, then writing 0 to OVF 1 [Setting condition] Set when TCNT overflows from H'FF to H'00

Rev.6.00 Sep. 27, 2007 Page 565 of 1268 REJ09B0220-0600 Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified. Bit 4 ADTE

0 A/D converter start requests by compare match A are disabled (Initial value)

1 A/D converter start requests by compare match A are enabled

Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare match of TCOR and TCNT. Bits OS3 and OS2 select the effect of compare match B on the output level, bits OS1 and OS0 select the effect of compare match A on the output level, and both of them can be controlled independently. Note, however, that priorities are set such that: toggle output > 1 output > 0 output. If compare matches occur simultaneously, the output changes according to the compare match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare match event occurs. Bit 3 OS3 Bit 2 OS2 0 0 No change when compare match B occurs (Initial value) 1 0 is output when compare match B occurs 1 0 1 is output when compare match B occurs

1 Output is inverted when compare match B occurs (toggle output)

0 0 No change when compare match A occurs (Initial value) 1 0 is output when compare match A occurs 1 0 1 is output when compare match A occurs

1 Output is inverted when compare match A occurs (toggle output)

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12.2.6 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 12—Module Stop (MSTP12): Specifies the 8-bit timer module stop mode. Bit 12 MSTP12 0 8-bit timer module stop mode cleared 1 8-bit timer module stop mode set (Initial value)

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12.3 Operation

12.3.1 TCNT Incrementation Timing

TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing. φ Internal clock Clock input to TCNT TCNT N–1 N N+1 Figure 12.2 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 12.3 shows the timing of incrementation at both edges of an external clock signal.

Rev.6.00 Sep. 27, 2007 Page 568 of 1268 REJ09B0220-0600 φ External clock input pin Clock input to TCNT TCNT N–1 N N+1 Figure 12.3 Count Timing for External Clock Input

12.3.2 Compare Match Timing

Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 12.4 shows this timing. φ TCNT N N+1 TCOR N Compare match signal CMF Figure 12.4 Timing of CMF Setting

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12.3.3 Timing of TCNT External Reset

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.7 shows the timing of this operation. φ Clear signal External reset input pin TCNT N H'00 N–1 Figure 12.7 Timing of Clearance by External Reset

12.3.4 Timing of Overflow Flag (OVF) Setting

The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.8 shows the timing of this operation. φ OVF Overflow signal TCNT H'FF H'00 Figure 12.8 Timing of OVF Setting

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12.3.5 Operation with Cascaded Connection

If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below. 16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.

• Setting of compare match flags ⎯ The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs. ⎯ The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs.
• Counter clear specification ⎯ If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set. ⎯ The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently.
• Pin output ⎯ Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare match conditions. ⎯ Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare match conditions. Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A’s for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Usage Note: If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore avoid using both these modes.

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12.4 Interrupts

12.4.1 Interrupt Sources and DTC Activation

There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 12.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 12.3 8-Bit Timer Interrupt Sources Channel Interrupt Source Description DTC Activation Priority

0 CMIA0 Interrupt by CMFA Possible High

CMIB0 Interrupt by CMFB Possible OVI0 Interrupt by OVF Not possible

1 CMIA1 Interrupt by CMFA Possible

CMIB1 Interrupt by CMFB Possible OVI1 Interrupt by OVF Not possible Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.

12.4.2 A/D Converter Activation

The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started.

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12.5 Sample Application

In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 12.9 Example of Pulse Output

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12.6 Usage Notes

Note that the following kinds of contention can occur in the 8-bit timer module.

12.6.1 Contention between TCNT Write and Clear

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows this operation. φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 T1 T2 TCNT write cycle by CPU Figure 12.10 Contention between TCNT Write and Clear

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12.6.2 Contention between TCNT Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.11 shows this operation. φ Address TCNT address Internal write signal TCNT input clock TCNT NM T1 T2 TCNT write cycle by CPU Counter write data Figure 12.11 Contention between TCNT Write and Increment

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12.6.3 Contention between TCOR Write and Compare Match

During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs. Figure 12.12 shows this operation. φ Address TCOR address Internal write signal TCNT TCOR NM T1 T2 TCOR write cycle by CPU TCOR write data N N+1 Compare match signal Prohibited Figure 12.12 Contention between TCOR Write and Compare Match

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12.6.4 Contention between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 12.4. Table 12.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change Low

12.6.5 Switching of Internal Clocks and TCNT Operation

TCNT may increment erroneously when the internal clock is switched over. Table 12.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 12.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. The erroneous incrementation can also happen when switching between internal and external clocks.

Rev.6.00 Sep. 27, 2007 Page 578 of 1268 REJ09B0220-0600 Table 12.5 Switching of Internal Clock and TCNT Operation No. Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation

1 Switching from

low to low* Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N+1

2 Switching from

low to high*2 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write NN + 1 N+2

3 Switching from

high to low*3 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write NN + 1 N+2

Rev.6.00 Sep. 27, 2007 Page 579 of 1268 REJ09B0220-0600 No. Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation

4 Switching from high

Notes: 1. Includes switching from low to stop, and from stop to low. 2. Includes switching from stop to high. 3. Includes switching from high to stop. 4. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.

12.6.6 Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC* or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Note: * The DMAC is not supported in the H8S/2321.

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Rev.6.00 Sep. 27, 2007 Page 581 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer

13.1 Overview

The chip has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF)* if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the chip. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.

13.1.1 Features

WDT features are listed below.

• Switchable between watchdog timer mode and interval timer mode
• WDTOVF output when in watchdog timer mode* If the counter overflows, the WDT outputs WDTOVF*. It is possible to select whether or not the entire chip is reset at the same time
• Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt
• Choice of eight counter clock sources Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions.

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13.1.2 Block Diagram

Figure 13.1 shows a block diagram of the WDT. Overflow Interrupt controlWOVI (interrupt request signal) WDTOVF*1 Internal reset signal*2 Reset control RSTCSR TCNT TSCR φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock Clock select Internal clock sources Bus interfaceModule bus Legend: TCSR: TCNT: RSTCSR: Notes: Timer control/status register Timer counter Reset control/status register Internal bus WDT 1. The WDTOVF pin function cannot be used in the F-ZTAT versions. 2. Internal reset signal generation is specified by means of a register setting. Figure 13.1 Block Diagram of WDT

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13.1.3 Pin Configuration

Table 13.1 describes the WDT output pin. Table 13.1 WDT Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF* Output Outputs counter overflow signal in watchdog timer mode Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions.

13.1.4 Register Configuration

The WDT has three registers, as summarized in table 13.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 13.2 WDT Registers Address *1 Name Abbreviation R/W Initial Value Write *2 Read Timer control/status register TCSR R/(W) *3 H'18 H'FFBC H'FFBC Timer counter TCNT R/W H'00 H'FFBC H'FFBD Reset control/status register RSTCSR R/(W) *3 H'1F H'FFBE H'FFBF Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 13.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag.

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13.2 Register Descriptions

13.2.1 Timer Counter (TCNT)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W TCNT is an 8-bit readable/writable*1 up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)*2 or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/ IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Notes: 1. TCNT is write-protected by a passwo rd to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. 2. The WDTOVF pin function cannot be used in the F-ZTAT versions.

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13.2.2 Timer Control/Status Register (TCSR)

Bit : 7 6 5 4 3 2 1 0 OVF WT/ IT TME — — CKS2 CKS1 CKS0 Initial value : 0 0 0 1 1 0 0 0 R/W : R/(W) * R/W R/W — — R/W R/W R/W Note: * Only 0 can be written, to clear the flag. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 OVF 0 [Clearing condition] (Initial value) Cleared by reading TCSR when OVF = 1*, then writing 0 to OVF 1 [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode Note: * When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read at least twice. Bit 6—Timer Mode Select (WT/ IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal*1 when TCNT overflows.

Rev.6.00 Sep. 27, 2007 Page 586 of 1268 REJ09B0220-0600 Bit 6 WT/IT

0 Interval timer: Sends the CPU an interval timer interrupt request (WOVI)

when TCNT overflows (Initial value)

1 Watchdog timer: Generates the WDTOVF signal*1 when TCNT overflows*2

Notes: 1. The WDTOVF pin function cannot be used in the F-ZTAT versions. 2. For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3, Reset Control/Status Register (RSTCSR). Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME

0 TCNT is initialized to H'00 and halted (Initial value)

1 TCNT counts

Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1. Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (φ), for input to TCNT. Overflow Period (when φ = 20 MHz)* 0 0 0 φ/2 (Initial value) 25.6 µs 1 φ/64 819.2 µs 1 0 φ/128 1.6 ms 1 φ/512 6.6 ms 1 0 0 φ/2048 26.2 ms 1 φ/8192 104.9 ms 1 0 φ/32768 419.4 ms 1 φ/131072 1.68 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs.

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13.2.3 Reset Control/Status Register (RSTCSR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 1 1 1 1 1 R/W : R/(W) * R/W R/W — — — — — Note: * Only 0 can be written, to clear the flag. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 [Clearing condition] (Initial value) Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF 1 [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer operation Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. Bit 6 RSTE

0 Reset signal is not generated if TCNT overflows * (Initial value)

1 Reset signal is generated if TCNT overflows

Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.

Rev.6.00 Sep. 27, 2007 Page 588 of 1268 REJ09B0220-0600 Bit 5—Reserved: This bit should be written with 0. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.

13.2.4 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 13.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write TCSR write Address: H'FFBC Address: H'FFBC H'5A Write data 15 8 7 0 H'A5 Write data 15 8 7 0 Figure 13.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written to by a word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 13.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE bit. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit.

Rev.6.00 Sep. 27, 2007 Page 589 of 1268 REJ09B0220-0600 H'A5 H'00 15 8 7 0 H'5A Write data 15 8 7 0 Writing 0 to WOVF bit Writing to RSTE bit Address: H'FFBE Address: H'FFBE Figure 13.3 Writing to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.

13.3 Operation

13.3.1 Operation in Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal* is output. This is shown in figure 13.4. This WDTOVF signal* can be used to reset the system. The WDTOVF signal* is output for 132 states when RSTE = 1, and for 130 states when RSTE = If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip internally is generated at the same time as the WDTOVF signal*. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions.

Rev.6.00 Sep. 27, 2007 Page 590 of 1268 REJ09B0220-0600 TCNT count H'00 Time H'FF WT/IT=1 TME=1 H'00 written to TCNT WT/IT=1 TME=1 H'00 written to TCNT132 states*2 518 states WDTOVF signal*3 Internal reset signal*1 WT/IT: TME: Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. 3. The WDTOVF pin function cannot be used in the F-ZTAT versions. Overflow WDTOVF*3 and internal reset are generated WOVF=1 Timer mode select bit Timer enable bit Legend: Figure 13.4 Operation in Watchdog Timer Mode

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13.3.2 Operation in Interval Timer Mode

To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 13.5. This function can be used to generate interrupt requests at regular intervals. TCNT count H'00 Time H'FF WT/IT=0 TME=1 WOVI Overflow Overflow Overflow Overflow Legend: WOVI: Interval timer interrupt request generation WOVI WOVI WOVI Figure 13.5 Operation in Interval Timer Mode

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13.3.3 Timing of Overflow Flag (OVF) Setting

The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 13.6. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 13.6 Timing of OVF Setting

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13.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting

The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. Figure 13.7 shows the timing in this case. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. φ TCNT Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. H'FF H'00 Overflow signal (internal signal) WOVF WDTOVF signal* Internal reset signal 132 states 518 states Figure 13.7 Timing of WOVF Setting

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13.4 Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.

13.5 Usage Notes

13.5.1 Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13.8 shows this operation. Address φ Internal write signal TCNT input clock TCNT NM T1 T2 TCNT write cycle Counter write data Figure 13.8 Contention between TCNT Write and Increment

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13.5.2 Changing Value of CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors may occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.

13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors may occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode.

13.5.4 System Reset by WDTOVF Signal*

If the WDTOVF output signal* is input to the RES pin of the chip, the chip will not be initialized correctly. Make sure that the WDTOVF signal* is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal*, use the circuit shown in figure 13.9. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Reset input Reset signal to entire system Chip RES WDTOVF* Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Figure 13.9 Circuit for System Reset by WDTOVF Signal (Example)

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13.5.5 Internal Reset in Watchdog Timer Mode

The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal* is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read RSTCSR after the WDTOVF signal* goes high, then write 0 to the WOVF flag. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 597 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI)

14.1 Overview

The chip is equipped with a serial communication interface (SCI) that can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).

14.1.1 Features

SCI features are listed below.

• Choice of asynchronous or synchronous serial communication mode Asynchronous mode ⎯ Serial data communication executed using an asynchronous system in which synchronization is achieved character by character ⎯ Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) ⎯ A multiprocessor communication function is provided that enables serial data communication with a number of processors ⎯ Choice of 12 serial data transfer formats Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 ⎯ Receive error detection: Parity, overrun, and framing errors ⎯ Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error Synchronous mode ⎯ Serial data communication synchronized with a clock ⎯ Serial data communication can be carried out with other chips that have a synchronous communication function ⎯ One serial data transfer format Data length: 8 bits ⎯ Receive error detection: Overrun errors detected

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 598 of 1268 REJ09B0220-0600

• Full-duplex communication capability ⎯ The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data
• Choice of LSB-first or MSB-first transfer ⎯ Can be selected regardless of the communication mode*1 (except in the case of asynchronous mode 7-bit data)
• Built-in baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin
• Four interrupt sources ⎯ Four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and receive error—that can issue requests independently ⎯ The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC)*2 or data transfer controller (DTC) to execute data transfer
• Module stop mode can be set ⎯ As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode Notes: 1. Descriptions in this section refer to LSB-first transfer. 2. The DMAC is not supported in the H8S/2321.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 599 of 1268 REJ09B0220-0600

14.1.2 Block Diagram

Figure 14.1 shows a block diagram of the SCI. Bus interface TDR RSR RDR Module data bus TSR SCMR SSR SCR Transmission/ reception control BRR Baud rate generator Internal data bus RxD TxD SCK Parity generation Parity check Clock External clock φ φ/4 φ/16 φ/64 TXI TEI RXI ERI SMR Legend: SCMR: Smart card mode register RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 14.1 Block Diagram of SCI

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 600 of 1268 REJ09B0220-0600

14.1.3 Pin Configuration

Table 14.1 shows the serial pins for each SCI channel. Table 14.1 SCI Pins Channel Pin Name Symbol I/O Function

0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output

Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output

1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output

Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output

2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output

Receive data pin 2 RxD2 Input SCI2 receive data input Transmit data pin 2 TxD2 Output SCI2 transmit data output

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 601 of 1268 REJ09B0220-0600

14.1.4 Register Configuration

The SCI has the internal registers shown in table 14.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 14.2 SCI Registers Channel Name Abbreviation R/W Initial Value Address *1

0 Serial mode register 0 SMR0 R/W H'00 H'FF78

Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A Transmit data register 0 TDR0 R/W H'FF H'FF7B Serial status register 0 SSR0 R/(W) *2 H'84 H'FF7C Receive data register 0 RDR0 R H'00 H'FF7D Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E

1 Serial mode register 1 SMR1 R/W H'00 H'FF80

Bit rate register 1 BRR1 R/W H'FF H'FF81 Serial control register 1 SCR1 R/W H'00 H'FF82 Transmit data register 1 TDR1 R/W H'FF H'FF83 Serial status register 1 SSR1 R/(W) *2 H'84 H'FF84 Receive data register 1 RDR1 R H'00 H'FF85 Smart card mode register 1 SCMR1 R/W H'F2 H'FF86

2 Serial mode register 2 SMR2 R/W H'00 H'FF88

Bit rate register 2 BRR2 R/W H'FF H'FF89 Serial control register 2 SCR2 R/W H'00 H'FF8A Transmit data register 2 TDR2 R/W H'FF H'FF8B Serial status register 2 SSR2 R/(W) *2 H'84 H'FF8C Receive data register 2 RDR2 R H'00 H'FF8D Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E All Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 602 of 1268 REJ09B0220-0600

14.2 Register Descriptions

14.2.1 Receive Shift Register (RSR)

Bit : 7 6 5 4 3 2 1 0 RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU.

14.2.2 Receive Data Register (RDR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode.

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14.2.3 Transmit Shift Register (TSR)

Bit : 7 6 5 4 3 2 1 0 TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU.

14.2.4 Transmit Data Register (TDR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode.

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14.2.5 Serial Mode Register (SMR)

Bit : 7 6 5 4 3 2 1 0 C/ A CHR PE O/ E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bit 7—Communication Mode (C/ A): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7 C/A

0 Asynchronous mode (Initial value)

1 Synchronous mode

Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 8-bit data (Initial value) 1 7-bit data * Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 605 of 1268 REJ09B0220-0600 Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE

0 Parity bit addition and checking disabled (Initial value)

1 Parity bit addition and checking enabled *

Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/ E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/ E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E

0 Even parity *

1 (Initial value)

1 Odd parity *2

Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 606 of 1268 REJ09B0220-0600 Bit 3 STOP 0 1 stop bit: In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 1 2 stop bits : In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function. Bit 2 MP

0 Multiprocessor function disabled (Initial value)

1 Multiprocessor format selected

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 14.2.8, Bit Rate Register (BRR). Bit 1 CKS1 Bit 0 CKS0 0 0 φ clock (Initial value) 1 φ/4 clock 1 0 φ/16 clock 1 φ/64 clock

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 607 of 1268 REJ09B0220-0600

14.2.6 Serial Control Register (SCR)

Bit : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE

0 Transmit-data-empty interrupt (TXI) requests disabled * (Initial value)

1 Transmit-data-empty interrupt (TXI) requests enabled

Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 608 of 1268 REJ09B0220-0600 Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE

0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request

disabled* (Initial value)

1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request

Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE

0 Transmission disabled *

1 (Initial value)

1 Transmission enabled *2

Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE

0 Reception disabled *

1 (Initial value)

1 Reception enabled *2

Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 609 of 1268 REJ09B0220-0600 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE

0 Multiprocessor interrupts disabled (normal reception performed) (Initial value)

[Clearing conditions]

• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received

1 Multiprocessor interrupts enabled *

Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE

0 Transmit end interrupt (TEI) request disabled * (Initial value)

1 Transmit end interrupt (TEI) request enabled *

Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of external clock operation (CKE1 = 1). Set CKE1 and CKE0 before determining the SCI operating mode with SMR.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 610 of 1268 REJ09B0220-0600 For details of clock source selection, see table 14.9. Bit 1 CKE1 Bit 0 CKE0 0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port * Synchronous mode Internal clock/SCK pin functions as serial clock output

1 Asynchronous mode Internal clock/SCK pin functions as clock output *2

Synchronous mode Internal clock/SCK pin functions as serial clock output 1 0 Asynchronous mode External clock/SCK pin functions as clock input *3 Synchronous mode External clock/SCK pin functions as serial clock input

1 Asynchronous mode External clock/SCK pin functions as clock input *3

Synchronous mode External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 611 of 1268 REJ09B0220-0600

14.2.7 Serial Status Register (SSR)

Bit : 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 R/W : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R R R/W Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode or module stop mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC * or DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] (Initial value)
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR Note: * The DMAC is not supported in the H8S/2321.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 612 of 1268 REJ09B0220-0600 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 [Clearing conditions] (Initial value)

• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC * or DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Notes: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. * The DMAC is not supported in the H8S/2321. Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER

0 [Clearing condition] (Initial value) * When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 613 of 1268 REJ09B0220-0600 Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 [Clearing condition] (Initial value) * When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 [Clearing condition] (Initial value) * When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 614 of 1268 REJ09B0220-0600 Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC * or DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] (Initial value)
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Note: * The DMAC is not supported in the H8S/2321. Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB

0 [Clearing condition] (Initial value) * When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in synchronous mode. Bit 0 MPBT

0 Data with a 0 multiprocessor bit is transmitted (Initial value)

1 Data with a 1 multiprocessor bit is transmitted

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 615 of 1268 REJ09B0220-0600

14.2.8 Bit Rate Register (BRR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 14.3 shows sample BRR settings in asynchronous mode, and table 14.4 shows sample BRR settings in synchronous mode. Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) φ = 2 MHz φ = 2.097152 MHz φ = 2.4576 MHz φ = 3 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 9600 0 6 — 0 6 –2.48 0 7 0.00 0 9 –2.34 19200 0 2 — 0 2 — 0 3 0.00 0 4 –2.34 31250 0 1 0.00 0 1 — 0 1 — 0 2 0.00 38400 0 1 — 0 1 — 0 1 0.00 — — —

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 616 of 1268 REJ09B0220-0600 φ = 3.6864 MHz φ = 4 MHz φ = 4.9152 MHz φ = 5 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 — 0 7 0.00 0 7 1.73 31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00 38400 0 2 0.00 0 2 — 0 3 0.00 0 3 1.73 φ = 6 MHz φ = 6.144 MHz φ = 7.3728 MHz φ = 8 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 — — — 0 7 0.00 38400 0 4 –2.34 0 4 0.00 0 5 0.00 — — —

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 617 of 1268 REJ09B0220-0600 φ = 9.8304 MHz φ = 10 MHz φ = 12 MHz φ = 12.288 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00 31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00 φ = 14 MHz φ = 14.7456 MHz φ = 16 MHz φ = 17.2032 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 –0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 –0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 –1.70 0 15 0.00 0 16 1.20 38400 0 10 — 0 11 0.00 0 12 0.16 0 13 0.00

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 618 of 1268 REJ09B0220-0600 φ = 18 MHz φ = 19.6608 MHz φ = 20 MHz φ = 25 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 79 –0.12 3 86 0.31 3 88 –0.25 3 110 –0.02 150 2 233 0.16 2 255 0.00 3 64 0.16 3 80 0.47 300 2 116 0.16 2 127 0.00 2 129 0.16 2 162 –0.15 600 1 233 0.16 1 255 0.00 2 64 0.16 2 80 0.47 1200 1 116 0.16 1 127 0.00 1 129 0.16 1 162 –0.15 2400 0 233 0.16 0 255 0.00 1 64 0.16 1 80 0.47 4800 0 116 0.16 0 127 0.00 0 129 0.16 0 162 –0.15 9600 0 58 –0.69 0 63 0.00 0 64 0.16 0 80 0.47 19200 0 28 1.02 0 31 0.00 0 32 –1.36 0 40 –0.76 31250 0 17 0.00 0 19 –1.70 0 19 0.00 0 24 1.00 38400 0 14 –2.34 0 15 0.00 0 15 1.73 0 19 1.73

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 619 of 1268 REJ09B0220-0600 Table 14.4 BRR Settings for Various Bit Rates (Synchronous Mode) Bit Rate φ = 2 MHz φ = 4 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz φ = 25 MHz (bits/s) n N n N n N n N n N n N n N 110 3 70 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 — — 1 k 1 124 1 249 2 124 — — 2 249 — — 3 97 2.5 k 0 199 1 99 1 199 1 249 2 99 2 124 2 155 5 k 0 99 0 199 1 99 1 124 1 199 1 249 2 77 10 k 0 49 0 99 0 199 0 249 1 99 1 124 1 155 25 k 0 19 0 39 0 79 0 99 0 159 0 199 0 249 50 k 0 9 0 19 0 39 0 49 0 79 0 99 0 124 100 k 0 4 0 9 0 19 0 24 0 39 0 49 0 62 250 k 0 1 0 3 0 7 0 9 0 15 0 19 0 24 500 k 0 0 * 0 1 0 3 0 4 0 7 0 9 — —

1 M 0 0 * 0 1 0 3 0 4 — —

2.5 M 0 0 * 0 1 — —

5 M 0 0 * — —

Note: As far as possible, the setting should be made so that the error is no more than 1%. Blank: Cannot be set. —: Can be set, but there will be a degree of error. *: Continuous transfer is not possible.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 620 of 1268 REJ09B0220-0600 The BRR setting is found from the following formulas. Asynchronous mode: N = φ 64 × 22n–1 × B × 10 6 – 1 Synchronous mode: N = φ 8 × 22n–1 × B × 10 6 – 1 Where B: Bit rate (bits/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n Clock CKS1 CKS0 0 φ 0 0 1 φ/4 0 1 2 φ/16 1 0 3 φ/64 1 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { φ × 106 – 1} × 100

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 621 of 1268 REJ09B0220-0600 Table 14.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 14.6 and 14.7 show the maximum bit rates with external clock input. Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 25 781250 0 0

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 622 of 1268 REJ09B0220-0600 Table 14.6 Maximum Bit Rate with Ext ernal Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 25 6.2500 390625

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 623 of 1268 REJ09B0220-0600 Table 14.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 25 4.1667 4166666.7

14.2.9 Smart Card Mode Register (SCMR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 0 0 1 0 R/W : — — — — R/W R/W — R/W SCMR selects LSB-first or MSB-first transfer by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first transfer can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see section 15.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 624 of 1268 REJ09B0220-0600 Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR. Bit 2 SINV

0 TDR contents are transmitted without modification (Initial value)

Receive data is stored in RDR without modification

1 TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form Bit 1—Reserved: This bit cannot be modified and is always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written to this bit. Bit 0 SMIF

0 Operates as normal SCI (smart card interface function disabled) (Initial value)

1 Smart card interface function enabled

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 625 of 1268 REJ09B0220-0600

14.2.10 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Module Stop (MSTP7): Specifies the SCI channel 2 module stop mode. Bit 7 MSTP7

0 SCI channel 2 module stop mode cleared

1 SCI channel 2 module stop mode set (Initial value)

Bit 6—Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode. Bit 6 MSTP6

0 SCI channel 1 module stop mode cleared

1 SCI channel 1 module stop mode set (Initial value)

Bit 5—Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode. Bit 5 MSTP5

0 SCI channel 0 module stop mode cleared

1 SCI channel 0 module stop mode set (Initial value)

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 626 of 1268 REJ09B0220-0600

14.3 Operation

14.3.1 Overview

The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 14.8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 14.9. Asynchronous Mode

• Data length: Choice of 7 or 8 bits
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length)
• Detection of framing, parity, and overrun errors, and breaks, during reception
• Choice of internal or external clock as SCI clock source ⎯ When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ⎯ When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) Synchronous Mode
• Transfer format: Fixed 8-bit data
• Detection of overrun errors during reception
• Choice of internal or external clock as SCI clock source ⎯ When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip ⎯ When external clock is selected: The built-in baud rate generator is not used, and the SCI operates on the input serial clock

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 627 of 1268 REJ09B0220-0600 Table 14.8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR MP PE STOP Mode Data Length Multi- processor Bit Parity Bit Stop Bit Length 0 0 0 0 0 8-bit data No No 1 bit Asynchronous mode 2 bits 1 0 Yes 1 bit 1 2 bits 1 0 0 7-bit data No 1 bit 1 2 bits 1 0 Yes 1 bit 1 2 bits 0 1 — 0 8-bit data Yes No 1 bit Asynchronous mode (multi- processor format) 7-bit data 2 bits 1 bit 2 bits 1 — — — — Synchronous mode 8-bit data No None Table 14.9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting SCI Transmit/Receive Clock Bit 7 Bit 1 Bit 0 C/A CKE1 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Internal SCI does not use SCK pin Asynchronous mode Outputs clock with same frequency as bit rate 1 0 External Inputs clock with frequency of 16 times the bit rate 1 0 0 Internal Outputs serial clock Synchronous mode External Inputs serial clock

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 628 of 1268 REJ09B0220-0600

14.3.2 Operation in Asynchronous Mode

In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSB- first order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. LSB Start bit MSB Idle state (mark state) Stop bit(s) Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none One unit of transfer data (character or frame) Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 629 of 1268 REJ09B0220-0600 Data Transfer Format Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 14.10 Serial Transfer Formats (Asynchronous Mode) PE S 8-bit data STOP S 7-bit data STOP S 8-bit data STOP STOP S 8-bit data P STOP S 7-bit data STOPP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data STOPMPB S 7-bit data STOPMPB STOP S 7-bit data STOPSTOP CHR MP STOP SMR Settings 123456789 1 0 1 1 1 2 Serial Transfer Format and Frame Length STOPS 8-bit data P STOP S 7-bit data STOPP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 630 of 1268 REJ09B0220-0600 Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 14.3. 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 Figure 14.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI initialization (asynchronous mode): Before transmitting or receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 632 of 1268 REJ09B0220-0600 Serial data transmission (asynchronous mode): Figure 14.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. No <End> [1] Yes Initialization Note: * The DMAC is not supported in the H8S/2321. Start of transmission Read TDRE flag in SSR [2] Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes No Yes Read TEND flag in SSR [3] No Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 TDRE = 1? All data transmitted? TEND = 1? Break output? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC * or DTC is activated by a transmit-data- empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Figure 14.5 Sample Serial Transmission Flowchart

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 633 of 1268 REJ09B0220-0600 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 635 of 1268 REJ09B0220-0600 Serial data reception (asynchronous mode): Figure 14.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Yes <End> [1] No Initialization Start of reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Read ORER, PER, and FER flags in SSR Error handling (Continued on next page) [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes PER ∨ FER ∨ ORER = 1? RDRF = 1? All data received? SCI initialization: The RxD pin is automatically designated as the receive data input pin. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RxD pin. SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC* or DTC is activated by an RXI interrupt and the RDR value is read. [1] [2] [3] [4] [5] Note: * The DMAC is not supported in the H8S/2321. Figure 14.7 Sample Serial Reception Flowchart

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 636 of 1268 REJ09B0220-0600 <End> [3] Error handling Parity error handling No Yes Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error handling No Yes Overrun error handling ORER = 1? FER = 1? Break? PER = 1? Clear RE bit in SCR to 0 Figure 14.7 Sample Serial Reception Flowchart (cont)

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 637 of 1268 REJ09B0220-0600 In serial reception, the SCI operates as described below. [1] The SCI monitors the communication line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 14.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 639 of 1268 REJ09B0220-0600

14.3.3 Multiprocessor Communication Function

The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a single serial communication line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 14.9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 14.10.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 640 of 1268 REJ09B0220-0600 Clock See section 14.3.2, Operation in Asynchronous Mode. Transmitting station Receiving station A (ID= 01) Receiving station B (ID= 02) Receiving station C (ID= 03) Receiving station D (ID= 04) Serial communication line Serial data ID transmission cycle= receiving station specification Data transmission cycle= Data transmission to receiving station specified by ID (MPB= 1) (MPB= 0) H'01 H'AA Legend: MPB: Multiprocessor bit Figure 14.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations Multiprocessor serial data transmission: Figure 14.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 641 of 1268 REJ09B0220-0600 No <End> [1] Yes Initialization Start of transmission Read TDRE flag in SSR [2] Write transmit data to TDR and set MPBT bit in SSR No Yes No Yes Read TEND flag in SSR [3] No Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 TDRE = 1? All data transmitted? TEND = 1? Break output? Clear TDRE flag to 0 SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC* or DTC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to TDR. Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0. [1] [2] [3] [4] Note: * The DMAC is not supported in the H8S/2321. Figure 14.10 Sample Multiprocessor Serial Transmission Flowchart

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 642 of 1268 REJ09B0220-0600 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 644 of 1268 REJ09B0220-0600 Yes <End> [1] No Initialization Start of reception No Yes [4] Clear RE bit in SCR to 0 Error handling (Continued on next page) [5]No Yes FER ∨ ORER = 1? RDRF = 1? All data received? Read MPIE bit in SCR [2] Read ORER and FER flags in SSR Read RDRF flag in SSR [3] Read receive data in RDR No Yes This station's ID? Read ORER and FER flags in SSR Yes No Read RDRF flag in SSR No Yes FER ∨ ORER = 1? Read receive data in RDR RDRF = 1? SCI initialization: The RxD pin is automatically designated as the receive data input pin. ID reception cycle: Set the MPIE bit in SCR to 1. SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [1] [2] [3] [4] [5] Figure 14.12 Sample Multiprocessor Serial Reception Flowchart

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 645 of 1268 REJ09B0220-0600 <End> Error handling Yes No Clear ORER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error handling Overrun error handling ORER = 1? FER = 1? Break? Clear RE bit in SCR to 0 [5] Figure 14.12 Sample Multiprocessor Serial Reception Flowchart (cont)

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 646 of 1268 REJ09B0220-0600 Figure 14.13 shows an example of SCI operation for multiprocessor format reception. MPIE RDR value

0 D0 D1 D7 1 1 0 D0 D1 D7 0 1

Data (ID1)Start bit MPB Stop bit Start bit Data (Data1) MPB Stop bit RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 Idle state (mark state) RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state ID1 (a) Data does not match station's ID MPIE RDR value Data (ID2)Start bit MPB Stop bit Start bit Data (Data2) MPB Stop bit RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 Idle state (mark state) RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Matches this station's ID, so reception continues, and data is received in RXI interrupt handling routine MPIE bit set to 1 again ID2 (b) Data matches station's ID Data2ID1 Figure 14.13 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 647 of 1268 REJ09B0220-0600

14.3.4 Operation in Synchronous Mode

In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.14 shows the general format for synchronous serial communication. Don't careDon't care One unit of transfer data (character or frame) Bit 0Serial data Serial clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * High except in continuous transfer Figure 14.14 Data Format in Synchronous Communication In synchronous serial communication, data on the communication line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In synchronous serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the communication line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 648 of 1268 REJ09B0220-0600 Clock Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive operations in units of one character, an external clock should be selected as the clock source. Data Transfer Operations SCI initialization (synchronous mode): Before transmitting or receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 14.15 shows a sample SCI initialization flowchart.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 649 of 1268 REJ09B0220-0600 Wait <Transfer start> Start of initialization Set data transfer format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 [2] [3] Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits as necessary Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. [4] 1-bit interval elapsed? Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the TxD or RxD pin to be used. Figure 14.15 Sample SCI Initialization Flowchart

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 650 of 1268 REJ09B0220-0600 Serial data transmission (synchronous mode): Figure 14.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. No <End> [1] Yes Initialization Start of transmission Read TDRE flag in SSR [2] Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes No Yes Read TEND flag in SSR [3] Clear TE bit in SCR to 0 TDRE = 1? All data transmitted? TEND = 1? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC* or DTC is activated by a transmit-data- empty interrupt (TXI) request and data is written to TDR. Note: * The DMAC is not supported in the H8S/2321. Figure 14.16 Sample Serial Transmission Flowchart

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 651 of 1268 REJ09B0220-0600 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 14.17 shows an example of SCI operation in transmission.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 652 of 1268 REJ09B0220-0600 Transfer direction Bit 7Serial data Serial clock 1 frame TDRE TEND Bit 0 Bit 7 Bit 0 Bit 1 Bit 7 Bit 6 Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt request generated TXI interrupt request generated TXI interrupt request generated Figure 14.17 Example of SCI Transmit Operation Serial data reception (synchronous mode): Figure 14.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 653 of 1268 REJ09B0220-0600 Yes <End> [1] No Initialization Start of reception [2] No Yes Read RDRF flag in SSR [4] [5] Clear RE bit in SCR to 0 Error processing (Continued below) [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER = 1? RDRF = 1? All data received? Read ORER flag in SSR [1] [2] [3] [4] [5] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC* or DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. <End> Error handling Overrun error handling [3] Clear ORER flag in SSR to 0 Note: * The DMAC is not supported in the H8S/2321. Figure 14.18 Sample Serial Reception Flowchart

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 655 of 1268 REJ09B0220-0600 Yes <End> [1] No Initialization Start of transmission/reception [5] Error handling [3] Read receive data in RDR, and clear RDRF flag in SSR to 0 No Yes ORER = 1? All data received? [2]Read TDRE flag in SSR No Yes TDRE = 1? Write transmit data to TDR and clear TDRE flag in SSR to 0 No Yes RDRF = 1? Read ORER flag in SSR [4]Read RDRF flag in SSR Clear TE and RE bits in SCR to 0 Notes: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE and RE bits to 0, then set both these bits to 1 simultaneously. * The DMAC is not supported in the H8S/2321. [1] [2] [3] [4] [5] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC* or DTC is activated by a transmit- data-empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC* or DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 656 of 1268 REJ09B0220-0600

14.4 SCI Interrupts

The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 14.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DMAC * or DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DMAC* or DTC. The DMAC* and DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC* or DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC* or DTC. The DMAC* and DTC cannot be activated by an ERI interrupt request. Also note that the DMAC* cannot be activated by an SCI channel 2 interrupt. Note: * The DMAC is not supported in the H8S/2321.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 657 of 1268 REJ09B0220-0600 Table 14.12 SCI Interrupt Sources Channel Interrupt Source DMAC* Activation Priority*

0 ERI Interrupt due to receive error

(ORER, FER, or PER) Not possible Not possible High RXI Interrupt due to receive data full state (RDRF) Possible Possible TXI Interrupt due to transmit data empty state (TDRE) Possible Possible TEI Interrupt due to transmission end (TEND) Not possible Not possible

1 ERI Interrupt due to receive error

(ORER, FER, or PER) Not possible Not possible RXI Interrupt due to receive data full state (RDRF) Possible Possible TXI Interrupt due to transmit data empty state (TDRE) Possible Possible TEI Interrupt due to transmission end (TEND) Not possible Not possible

2 ERI Interrupt due to receive error

(ORER, FER, or PER) Not possible Not possible RXI Interrupt due to receive data full state (RDRF) Possible Not possible TXI Interrupt due to transmit data empty state (TDRE) Possible Not possible TEI Interrupt due to transmission end (TEND) Not possible Not possible Low Notes: 1. This table shows the initial state immediate after a reset. Relative priorities among channels can be changed by the interrupt controller. 2. The DMAC is not supported in the H8S/2321. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 658 of 1268 REJ09B0220-0600

14.5 Usage Notes

The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag: The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously: If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 14.13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 14.13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF ORER FER PER Receive Data Transfer from RSR to RDR Receive Error Status 1 1 0 0 X Overrun error 0 0 1 0 Framing error 0 0 0 1 Parity error 1 1 1 0 X Overrun error + framing error 1 1 0 1 X Overrun error + parity error 0 0 1 1 Framing error + parity error 1 1 1 1 X Overrun error + framing error + parity error Notes: : Receive data is transferred from RSR to RDR. X : Receive data is not transferred from RSR to RDR.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 659 of 1268 REJ09B0220-0600 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Therefore, DDR and DR for the port corresponding to the TxD pin should first be set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the base clock. This is illustrated in figure 14.21.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 660 of 1268 REJ09B0220-0600 Internal base clock 16 clocks 8 clocks Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing 15 0 7 15 007 Figure 14.21 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by formula (1) below. M = | (0.5 – 1 N (1 + F) | × 100% ... Formula (1) Where M : Receive margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a receive margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 – 1 2 × 16 ) × 100% = 46.875% ... Formula (2) However, this is a theoretical value, and a margin of 20% to 30% should be allowed in system design.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 661 of 1268 REJ09B0220-0600 Restrictions on Use of DMAC* or DTC

• When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DMAC* or DTC. Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 14.22)
• When RDR is read by the DMAC* or DTC, be sure to set the activation source to the relevant SCI receive-data-full interrupt (RXI). Note: * The DMAC is not supported in the H8S/2321. t LSB Serial data SCK D1 D3 D4 D5D2 D6 D7 Note: When operating on an external clock, set t > 4 clocks. TDRE Figure 14.22 Example of Synchronous Transmission Using DTC

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 662 of 1268 REJ09B0220-0600 Operation in Case of Mode Transition

• Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 14.23 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 14.24 and 14.25. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode or software standby mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission.
• Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 14.26 shows a sample flowchart for mode transition during reception.

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 663 of 1268 REJ09B0220-0600 Read TEND flag in SSR TE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? No All data transmitted? TEND = 1? Yes Yes Yes <Transmission> No No [1] [3] [2] TE = 1Initialization <Start of transmission> [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [3] Includes module stop mode. Figure 14.23 Sample Flowchart for Mode Transition during Transmission

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 665 of 1268 REJ09B0220-0600 RE = 0 Transition to software standby mode, etc. Read receive data in RDR Read RDRF flag in SSR Exit from software standby mode, etc. Change operating mode? No RDRF = 1? Yes Yes <Reception> No [1] [2] RE = 1Initialization <Start of reception> [1] Receive data being received becomes invalid. [2] Includes module stop mode. Figure 14.26 Sample Flowchart for Mode Transition during Reception

Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 666 of 1268 REJ09B0220-0600

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 667 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface

15.1 Overview

The SCI supports an IC card (smart card) interface conforming to ISO/IEC 7816-3 (identification card) as a serial communication interface extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting.

15.1.1 Features

Features of the smart card interface supported by the chip is as follows.

• Asynchronous mode ⎯ Data length: 8 bits ⎯ Parity bit generation and checking ⎯ Transmission of error signal (parity error) in receive mode ⎯ Error signal detection and automatic data retransmission in transmit mode ⎯ Direct convention and inverse convention both supported
• Built-in baud rate generator allows any bit rate to be selected
• Three interrupt sources ⎯ Three interrupt sources (transmit-data-empty, receive-data-full, and transmit/receive-error) that can issue requests independently ⎯ The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC)* or data transfer controller (DTC) to execute data transfer Note: * The DMAC is not supported in the H8S/2321.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 668 of 1268 REJ09B0220-0600

15.1.2 Block Diagram

Figure 15.1 shows a block diagram of the smart card interface. Bus interface TDR RSR RDR Module data bus TSR SCMR SSR SCR Transmission/ reception control BRR Baud rate generator Internal data bus RxD TxD SCK Parity generation Parity check Clock φ φ/4 φ/16 φ/64 TXI RXI ERI SMR Legend: SCMR: Smart card mode register RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 15.1 Block Diagram of Smart Card Interface

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 669 of 1268 REJ09B0220-0600

15.1.3 Pin Configuration

Table 15.1 shows the smart card interface pin configuration. Table 15.1 Smart Card Interface Pins Channel Pin Name Symbol I/O Function Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output Receive data pin 2 RxD2 Input SCI2 receive data input Transmit data pin 2 TxD2 Output SCI2 transmit data output

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 670 of 1268 REJ09B0220-0600

15.1.4 Register Configuration

Table 15.2 shows the registers used by the smart card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface (SCI). Table 15.2 Smart Card Interface Registers Channel Name Abbreviation R/W Initial Value Address *1 Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A Transmit data register 0 TDR0 R/W H'FF H'FF7B Serial status register 0 SSR0 R/(W) *2 H'84 H'FF7C Receive data register 0 RDR0 R H'00 H'FF7D Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E Bit rate register 1 BRR1 R/W H'FF H'FF81 Serial control register 1 SCR1 R/W H'00 H'FF82 Transmit data register 1 TDR1 R/W H'FF H'FF83 Serial status register 1 SSR1 R/(W) *2 H'84 H'FF84 Receive data register 1 RDR1 R H'00 H'FF85 Smart card mode register 1 SCMR1 R/W H'F2 H'FF86 Bit rate register 2 BRR2 R/W H'FF H'FF89 Serial control register 2 SCR2 R/W H'00 H'FF8A Transmit data register 2 TDR2 R/W H'FF H'FF8B Serial status register 2 SSR2 R/(W) *2 H'84 H'FF8C Receive data register 2 RDR2 R H'00 H'FF8D Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E All Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 671 of 1268 REJ09B0220-0600

15.2 Register Descriptions

Registers added with the smart card interface and bits for which the function changes are described here.

15.2.1 Smart Card Mode Register (SCMR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 0 0 1 0 R/W : — — — — R/W R/W — R/W SCMR is an 8-bit readable/writable register that selects the smart card interface function. SCMR is initialized to H'F2 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR Receive data is stored in RDR LSB-first Receive data is stored in RDR MSB-first

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 672 of 1268 REJ09B0220-0600 Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 15.3.4, Register Settings. Bit 2 SINV

0 TDR contents are transmitted as they are (Initial value)

Receive data is stored as it is in RDR Receive data is stored in inverted form in RDR Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0 SMIF

0 Smart card interface function is disabled (Initial value)

1 Smart card interface function is enabled

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 673 of 1268 REJ09B0220-0600

15.2.2 Serial Status Register (SSR)

Bit : 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 R/W : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R R R/W Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5— Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in smart card interface mode. Bit 4 ERS

0 Indicates data received normally with no error signal (Initial value)

[Clearing conditions]

• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1

1 Indicates an error signal was sent showing detection of a parity error at the receiving

[Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 674 of 1268 REJ09B0220-0600 Bits 3 to 0— Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND Indicates transfer in progress [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC * or DTC is activated by a TXI interrupt and writes data to TDR

1 Indicates transfer complete (Initial value)

[Setting conditions]

• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Notes: etu: Elementary time unit (time for transfer of 1 bit) * The DMAC is not supported in the H8S/2321.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 675 of 1268 REJ09B0220-0600

15.2.3 Serial Mode Register (SMR)

Bit : 7 6 5 4 3 2 1 0 GM BLK PE * O/ E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Note: * The DMAC is not supported in the H8S/2321. The function of bits 7, 6, 3, and 2 of SMR changes in smart card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced, and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM

0 Normal smart card interface mode operation (Initial value)

• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output on/off control only

1 GSM mode smart card interface mode operation

• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary time unit (time for transfer of 1 bit)

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 676 of 1268 REJ09B0220-0600 Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK

• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)

1 Block transfer mode operation

• Error signal transmission/detection and automatic data retransmission not performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 3 and 2—Base Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of base clock periods in a 1-bit transfer interval on the smart card interface. Bit 3 BCP1 Bit 2 BCP0

0 0 32 clock periods (Initial value) 1 64 clock periods 1 0 372 clock periods 1 256 clock periods Bits 5, 4, 1, and 0— Operate in the same way as for the normal SCI. For details, see section 14.2.5, Serial Mode Register (SMR).

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 677 of 1268 REJ09B0220-0600

15.2.4 Serial Control Register (SCR)

Bit : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2— Operate in the same way as for the normal SCI. For details, see section 14.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as being fixed high or low. SCMR SMR SCR Setting SMIF GM CKE1 CKE0 SCK Pin Function

0 See the SCI specification

1 0 0 0 Operates as port I/O pin 1 0 0 1 Outputs clock as SCK output pin 1 1 0 0 Operates as SCK output pin, with output fixed low 1 1 0 1 Outputs clock as SCK output pin 1 1 1 0 Operates as SCK output pin, with output fixed high 1 1 1 1 Outputs clock as SCK output pin

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 678 of 1268 REJ09B0220-0600

15.3 Operation

15.3.1 Overview

The main functions of the smart card interface are as follows.

• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (1 etu in block transfer mode) (elementary time unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. (This does not apply to block transfer mode.)
• If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. (This does not apply to block transfer mode.)
• Only asynchronous communication is supported; there is no synchronous communication function.

15.3.2 Pin Connections

Figure 15.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data communication line, the chip’s TxD pin and RxD pin should both be connected to the line, as shown in the figure. The data communication line should be pulled up to the V CC power supply with a resistor. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. Chip port output is used as the reset signal. Other pins must normally be connected to the power supply or ground.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 679 of 1268 REJ09B0220-0600 TxD RxD SCK Rx (port) Chip I/O CLK RST VCC Connected equipment IC card Data line Clock line Reset line Figure 15.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 680 of 1268 REJ09B0220-0600

15.3.3 Data Format

Normal Transfer Mode: Figure 15.3 shows the smart card interface data format in the normal transfer mode. In reception in this mode, a parity check is carried out on each frame. If an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When there is no parity error Transmitting station output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When a parity error occurs Transmitting station output DE Receiving station outputLegend: Ds: Start bit D0 to D7: Data bits Dp: Parity bit DE: Error signal Figure 15.3 Smart Card Interface Data Format

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 681 of 1268 REJ09B0220-0600 The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the data in which the error occurred. Block Transfer Mode: The operation sequence in block transfer mode is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check, but does not output an error signal even if an error has occurred. Since subsequent receive operations cannot be carried out if an error occurs, the error flag must be cleared to 0 before the parity bit for the next frame is received. [5] The transmitting station proceeds to transmit the next data frame.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 682 of 1268 REJ09B0220-0600

15.3.4 Register Settings

Table 15.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 15.3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMR GM BLK 1 O/ E BCP1 BCP0 CKS1 CKS0 BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCR TIE RIE TE RE 0 0 CKE1 * CKE0 TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR TDRE RDRF ORER ERS PER TEND 0 0 RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 SCMR — — — — SDIR SINV — SMIF Notes: — : Unused bit. * The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Settings: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator, and bits BCP1 and BCP0 select the number of base clock cycles during transfer of one bit. For details, see section 15.3.5, Clock. The BLK bit is cleared to 0 when using the normal smart card interface mode, and set to 1 when using block transfer mode. BRR Setting: BRR is used to set the bit rate. See section 15.3.5, Clock, for the method of calculating the value to be set. SCR Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 14, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 683 of 1268 REJ09B0220-0600 Smart Card Mode Register (SCMR) Settings: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention).

• Direct convention (SDIR = SINV = O/E = 0) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp AZZAZZZAAZ(Z) (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the smart card.
• Inverse convention (SDIR = SINV = O/E = 1) Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp AZZAAAAAAZ(Z) (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. With the chip, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR should be set to odd parity mode (the same applies to both transmission and reception).

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 684 of 1268 REJ09B0220-0600

15.3.5 Clock

Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1, and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 15.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, the clock is output from the SCK pin. The clock frequency is determined by the bit rate and the setting of bits BCP1 and BCP0. B = φ × 10 Where: N = Value set in BRR (0 ≤ N ≤ 255) B = Bit rate (bits/s) φ = Operating frequency (MHz) n = See table 15.4 S = Number of internal clock cycles in 1-bit period set by bits BCP1 and BCP0 Table 15.4 Correspondence be tween n and CKS1, CKS0 n CKS1 CKS0 0 0 0 1 1 2 1 0 3 1 Table 15.5 Examples of Bit Rate B (bits/s) for Various BRR Settings (When n = 0 and S = 372) φ (MHz) 0 13441 14400 17473 19200 21505 24194 26882 33602 1 6720 7200 8737 9600 10753 12097 13441 16801 2 4480 4800 5824 6400 7168 8065 8961 11201 Note: Bit rates are rounded to the nearest whole number.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 685 of 1268 REJ09B0220-0600 The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N = φ S × 22n+1 × B × 10 6 – 1 Table 15.6 Examples of BRR Settings for Bit Rate B (bits/s) (When n = 0 and S = 372) φ (MHz) Bits/s N Error N Error N Error N Error N Error N Error N Error N Error N Error Table 15.7 Maximum Bit Rate at Various F requencies (Smart Card Interface Mode) (When S = 372) φ (MHz) Maximum Bit Rate (bits/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 25.00 33602 0 0 The bit rate error is given by the following formula: Error (%) = ( φ × 10 6 – 1) × 100

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 686 of 1268 REJ09B0220-0600

15.3.6 Data Transfer Operations

Initialization: Before transmitting or receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE1 and CKE0 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 687 of 1268 REJ09B0220-0600 Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 15.4 shows a flowchart for transmitting, and figure 15.5 shows the relation between a transmit operation and the internal registers. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt handling or data transfer by the DMAC* or DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag setting timing is shown in figure 15.6. If the DMAC* or DTC is activated by a TXI request, the number of bytes set in the DMAC * or DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DMAC * or DTC below. Notes: For details of operation in block transfer mode, see section 14.3.2, Operation in Asynchronous Mode. * The DMAC is not supported in the H8S/2321.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 688 of 1268 REJ09B0220-0600 Initialization No Yes Clear TE bit to 0 Start of transmission Start No No No Yes Yes Yes Yes No End Write data to TDR, and clear TDRE flag in SSR to 0 Error handling Error handling TEND = 1? All data transmitted? TEND = 1? ERS = 0? ERS = 0? Figure 15.4 Sample Transmission Flowchart

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 690 of 1268 REJ09B0220-0600 Serial Data Reception (Except Block Transfer Mode): Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 15.7 shows an example of the transmission processing flow. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Initialization Read RDR and clear RDRF flag in SSR to 0 Clear RE bit to 0 Start of reception Start Error handling No No No Yes Yes ORER = 0 and PER = 0? RDRF = 1? All data received? Yes Figure 15.7 Sample Reception Flowchart

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 691 of 1268 REJ09B0220-0600 With the above processing, interrupt handling or data transfer by the DMAC* or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated. If the DMAC* or DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DMAC* or DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DMAC* or DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Notes: For details of operation in block transfer mode, see section 14.3.2, Operation in Asynchronous Mode. * The DMAC is not supported in the H8S/2321. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output: When the GSM bit in SMR is set to 1, the clock output can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.8 shows the timing for fixing the clock output. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 692 of 1268 REJ09B0220-0600 SCK Specified pulse width SCR write (CKE0 = 0) SCR write (CKE0 = 1) Specified pulse width Figure 15.8 Timing for Fixing Clock Output Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 15.8. Note: For details of operation in block transfer mode, see section 14.4, SCI Interrupts. Table 15.8 Smart Card Mode Operating States and Interrupt Sources Operating State Flag Enable Bit Interrupt Source DTC Activation DMAC* Activation Transmit Mode Normal operation TEND TIE TXI Possible Possible Error ERS RIE ERI Not possible Not possible Receive Mode Normal operation RDRF RIE RXI Possible Possible Error PER, ORER RIE ERI Not possible Not possible Note: * The DMAC is not supported in the H8S/2321.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 693 of 1268 REJ09B0220-0600 Data Transfer Operation by DMAC* or DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC* or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC* or DTC activation source, the DMAC* or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC* or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC* is not activated. Thus, the number of bytes specified by the SCI and DMAC* are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DMAC* or DTC, it is essential to set and enable the DMAC* or DTC before carrying out SCI setting. For details of the DMAC* and DTC setting procedures, see section 7, DMA Controller*, and section 8, Data Transfer Controller. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC* or DTC activation source, the DMAC* or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC* or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC* or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Notes: For details of operation in block transfer mode, see section 14.4, SCI Interrupts. * The DMAC is not supported in the H8S/2321.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 694 of 1268 REJ09B0220-0600

15.3.7 Operation in GSM Mode

Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty.

• When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt the transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state.
• When returning to smart card interface mode from software standby mode [7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set smart card interface mode and output the clock. Signal generation is started with the normal duty. Software standbyNormal operation Normal operation Figure 15.9 Clock Halt and Restart Procedure

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 695 of 1268 REJ09B0220-0600 Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output.

15.3.8 Operation in Block Transfer Mode

Operation in block transfer mode is the same as in SCI asynchronous mode, except for the following points. For details, see section 14.3.2, Operation in Asynchronous Mode. Data Format: The data format is 8 bits with parity. There is no stop bit, but there is a guard time of 2 or more bits (1 or more bits in reception). Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. Transmit/Receive Clock: Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 15.3.5, Clock. ERS (FER) Flag: As with the normal smart card interface, the ERS flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0.

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 696 of 1268 REJ09B0220-0600

15.4 Usage Notes

The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 32, 64, 372, or 256 times the transfer rate (determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the base clock. Use of a 372-times clock is illustrated in figure 15.10. Internal base clock 372 clocks 186 clocks Receive data (RxD) Synchro- nization sampling timing D0 D1 Data sampling timing 185 371 0371185 00 Start bit Figure 15.10 Receive Data Sampling Timing in Smart Card Mode (When Using 372-Times Clock)

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 697 of 1268 REJ09B0220-0600 Thus the receive margin in asynchronous mode is given by the following formula. M =⎥ (0.5 – 1 N (1 + F)⎥ × 100% Where M: Receive margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N=372 in the above formula, the receive margin formula is as follows. When D = 0.5 and F = 0, = 49.866%

Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 700 of 1268 REJ09B0220-0600

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 701 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version)

16.1 Overview

The chip incorporates a successive-approximations type 10-bit A/D converter that allows up to eight analog input channels to be selected.

16.1.1 Features

A/D converter features are listed below

• 10-bit resolution
• Eight input channels
• Settable analog conversion voltage range ⎯ Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage
• High-speed conversion ⎯ Minimum conversion time: 6.7 µs per channel (at 20-MHz operation)
• Choice of single mode or scan mode ⎯ Single mode: Single-channel A/D conversion ⎯ Scan mode: Continuous A/D conversion on 1 to 4 channels
• Four data registers ⎯ Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three kinds of conversion start ⎯ Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin
• A/D conversion end interrupt generation ⎯ A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion ⎯ The DMA controller (DMAC)* or data transfer controller (DTC) can be activated for data transfer by an interrupt Note: * The DMAC is not supported in the H8S/2321.
• Module stop mode can be set ⎯ As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode.

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 702 of 1268 REJ09B0220-0600

16.1.2 Block Diagram

Figure 16.1 shows a block diagram of the A/D converter. Module data bus Control circuit Internal data bus 10-bit D/A converter Comparator Sample-and- hold circuit ADI interrupt signal Bus interface A D C S R A D C R A D D R D A D D R C A D D R B A D D R A AVCC Vref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG Conversion start trigger from 8-bit timer or TPU Successive approximations register Multiplexer Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 16.1 Block Diagram of A/D Converter

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 703 of 1268 REJ09B0220-0600

16.1.3 Pin Configuration

Table 16.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 16.1 A/D Converter Pins Pin Name Symbol I/O Function Analog power supply pin AV CC Input Analog block power supply Analog ground pin AV SS Input Analog block ground and A/D conversion reference voltage Reference voltage pin V ref Input A/D conversion reference voltage Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Group 1 analog inputs Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input A/D external trigger input pin ADTRG Input External trigger input for starting A/D conversion

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 704 of 1268 REJ09B0220-0600

16.1.4 Register Configuration

Table 16.2 summarizes the registers of the A/D converter. Table 16.2 A/D Converter Registers Name Abbreviation R/W Initial Value Address *1 A/D data register AH ADDRAH R H'00 H'FF90 A/D data register AL ADDRAL R H'00 H'FF91 A/D data register BH ADDRBH R H'00 H'FF92 A/D data register BL ADDRBL R H'00 H'FF93 A/D data register CH ADDRCH R H'00 H'FF94 A/D data register CL ADDRCL R H'00 H'FF95 A/D data register DH ADDRDH R H'00 H'FF96 A/D data register DL ADDRDL R H'00 H'FF97 A/D control/status register ADCSR R/(W) *2 H'00 H'FF98 A/D control register ADCR R/W H'3F H'FF99 Module stop control register MSTPCR R/W H'3FFF H'FF3C Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing.

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 705 of 1268 REJ09B0220-0600

16.2 Register Descriptions

16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R R R R R R R R R R R R R R R R There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 16.3. The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 16.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 Group 1 A/D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 706 of 1268 REJ09B0220-0600

16.2.2 A/D Control/Status Register (ADCSR)

Bit : 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/(W) * R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 [Clearing conditions] (Initial value)

• When 0 is written to the ADF flag after reading ADF = 1
• When the DMAC * or DTC is activated by an ADI interrupt and ADDR is read 1 [Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels Note: * The DMAC is not supported in the H8S/2321. Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE

0 A/D conversion end interrupt (ADI) request disabled (Initial value)

1 A/D conversion end interrupt (ADI) request enabled

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 707 of 1268 REJ09B0220-0600 Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST

0 A/D conversion stopped (Initial value)

1 • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends

• Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 16.4, Operation, for details of single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN

0 Single mode (Initial value)

1 Scan mode

Bit 3—Clock Select (CKS): Used together with the CKS1 bit in ADCR to set the A/D conversion time. Only change the conversion time while conversion is stopped (ADST = 0). ADCR3 CKS1 Bit 3 CKS 0 0 Conversion time = 530 states (max.) 1 Conversion time = 68 states (max.) 1 0 Conversion time = 266 states (max.) (Initial value) 1 Conversion time = 134 states (max.) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits are used together with the SCAN bit to select the analog input channels. Only set the input channel(s) while conversion is stopped (ADST = 0).

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 708 of 1268 REJ09B0220-0600 Group Selection Channel Selection CH2 CH1 CH0 Single Mode (SCAN = 0) Scan Mode (SCAN = 1) 0 0 0 AN0 (Initial value) AN0

1 AN1 AN0, AN1

1 AN3 AN0 to AN3

1 AN5 AN4, AN5

1 AN7 AN4 to AN7

16.2.3 A/D Control Register (ADCR)

Bit : 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — CKS1 CH3 — — Initial value : 0 0 1 1 1 1 1 1 R/W : R/W R/W — — R/W R/W — — ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 Bit 6 TRGS0 0 0 A/D conversion start by external trigger is disabled (Initial value)

1 A/D conversion start by external trigger (TPU) is enabled

1 0 A/D conversion start by external trigger (8-bit timer) is enabled

1 A/D conversion start by external trigger pin ( ADTRG) is enabled

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 709 of 1268 REJ09B0220-0600 Bits 5, 4, 1, and 0—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Clock Select 1 (CKS1): Used together with the CKS bit in ADCSR to set the A/D conversion time. See the description of the CKS bit for details. Bit 2—Channel Select 3 (CH3): Reserved. A value of 1 must be written to this bit.

16.2.4 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9—Module Stop (MSTP9): Specifies the A/D converter module stop mode. Bit 9 MSTP9

0 A/D converter module stop mode cleared

1 A/D converter module stop mode set (Initial value)

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 710 of 1268 REJ09B0220-0600

16.3 Interface to Bus Master

ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 16.2 shows the data flow for ADDR access. Bus master (H'AA) ADDRnH (H'AA) ADDRnL (H'40) Lower byte read ADDRnH (H'AA) ADDRnL (H'40) TEMP (H'40) TEMP (H'40) (n = A to D) (n = A to D) Module data bus Module data bus Bus interface Upper byte read Bus master (H'40) Bus interface Figure 16.2 ADDR Access Operation (Reading H'AA40)

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 711 of 1268 REJ09B0220-0600

16.4 Operation

The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode.

16.4.1 Single Mode (SCAN = 0)

Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software or by external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 to it after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 16.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the conversion result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated.

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 712 of 1268 REJ09B0220-0600 ADIE ADST ADF State of channel 0 (AN0) A/D conversion starts ADDRA ADDRB ADDRC ADDRD State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Note: * Vertical arrows ( ) indicate instructions executed by software. Set* Set* Clear*Clear* A/D conversion result 1 A/D conversion A/D conversion result 2 Read conversion resultRead conversion result Idle Idle Idle Idle Idle Idle A/D conversion Set* Figure 16.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 713 of 1268 REJ09B0220-0600

16.4.2 Scan Mode (SCAN = 1)

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 16.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 714 of 1268 REJ09B0220-0600 ADST ADF ADDRA ADDRB ADDRC ADDRD State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Set*

1 Clear*1

Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Clear*1 Idle Idle A/D conversion time Idle Continuous A/D conversion A/D conversion 1Idle Idle Idle Idle Idle Transfer A/D conversion 3 A/D conversion 2 A/D conversion 5 A/D conversion 4 A/D conversion result 1 A/D conversion result 2 A/D conversion result 3 A/D conversion result 4 Figure 16.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 715 of 1268 REJ09B0220-0600

16.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16.5 shows the A/D conversion timing. Table 16.4 indicates the A/D conversion time. As indicated in figure 16.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 16.4. In scan mode, the values given in table 16.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is as shown in table 16.5. (1) (2) tD tSPL tCONV φ Input sampling timing ADF Address bus Write signal Legend: (1): ADCSR write cycle (2): ADCSR address t D: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 16.5 A/D Conversion Timing

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 716 of 1268 REJ09B0220-0600 Table 16.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS = 0 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay tD 18 — 33 4 — 5 10 — 17 6 — 9 Input sampling time t A/D conversion time t CONV 515 — 530 67 — 68 259 — 266 131 — 134 Note: Values in the table are the number of states. Table 16.5 A/D Conversion Time (Scan Mode) CKS1 CKS Conversion Time (States) 0 0 512 (Fixed) 1 64 (Fixed) 1 0 256 (Fixed) 1 128 (Fixed)

16.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 16.6 shows the timing.

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 717 of 1268 REJ09B0220-0600 φ ADTRG Internal trigger signal ADST A/D conversion Figure 16.6 External Trigger Input Timing

16.5 Interrupts

The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC* can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC* in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 16.6. Note: * The DMAC is not supported in the H8S/2321. Table 16.6 A/D Converter Interrupt Source Interrupt Source Description DTC Activation DMAC Activation * ADI Interrupt due to end of conversion Possible Possible Note: * The DMAC is not supported in the H8S/2321.

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 718 of 1268 REJ09B0220-0600

16.6 Usage Notes

The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to analog input pins ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. 2. Relation between AV CC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must not be left open. 3. V ref input range The analog reference voltage input at the Vref pin should be set in the range Vref ≤ AVCC. The Vref pin should be set as Vref = VCC when the A/D converter is not used. Do not leave the Vref pin open. If conditions 1, 2, and 3 above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 16.7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 16.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 719 of 1268 REJ09B0220-0600 frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance in), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC *1 *1 Vref AN0 to AN7 AVSS Notes: Values are reference values. 2. Rin: Input impedance Rin*2 100 Ω 0.1 μF 0.01 μF10 μF Figure 16.7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: The chip’s A/D conversion precision definitions are given below.

• Resolution The number of A/D converter digital output codes
• Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 to B'0000000001. (See figure 16.9.)

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 720 of 1268 REJ09B0220-0600

• Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 to B'1111111111. (See figure 16.9.)
• Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB. (See figure 16.8.)
• Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.
• Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. 111 110 101 100 011 010 001 000 FS Quantization error Digital output Ideal A/D conversion characteristic Analog input voltage 1024 1024 1022 1024 1023 1024 Figure 16.8 A/D Conversion Precision Definitions (1)

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 721 of 1268 REJ09B0220-0600 FS Offset error Nonlinearity error Actual A/D conversion characteristic Analog input voltage Digital output Ideal A/D conversion characteristic Full-scale error Figure 16.9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: The chip’s analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k Ω or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k Ω, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. If a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted.

Section 16 A/D Converter (8 Analog Input Channel Version) Rev.6.00 Sep. 27, 2007 Page 722 of 1268 REJ09B0220-0600 Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. A/D converter equivalent circuit Chip 20 pFCin = 15 pF 10 kΩ Low-pass filter C to 0.1 µF Sensor output impedance Max. 5 kΩ Sensor input Note: Values are reference values. Figure 16.10 Example of Analog Input Circuit

Rev.6.00 Sep. 27, 2007 Page 723 of 1268 REJ09B0220-0600 Section 17 D/A Converter

17.1 Overview

The chip includes an 8-bit resolution D/A converter with from two analog signal output channels.

17.1.1 Features

D/A converter features are listed below.

• 8-bit resolution
• Two output channels
• Maximum conversion time of 10 µs (with 20 pF load)
• Output voltage of 0 V to Vref
• D/A output hold function in software standby mode
• Module stop mode can be set ⎯ As the initial setting, D/A converter operation is halted. Register access is enabled by exiting module stop mode.

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17.1.2 Block Diagram

Figure 17.1 shows a block diagram of the D/A converter. Module data bus Internal data bus Vref AVCC DA1 DA0 AVSS 8-bit D/A converter Control circuit DADR0 Bus interface DADR1 DACR Legend: DACR: D/A control register DADR0, 1: D/A data registers 0, 1 Figure 17.1 Block Diagram of D/A Converter

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17.1.3 Pin Configuration

Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration Pin Name Symbol I/O Function Analog power pin AV CC Input Analog power source Analog ground pin AV SS Input Analog ground and reference voltage Analog output pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference voltage pin V ref Input Analog reference voltage

17.1.4 Register Configuration

Table 17.2 summarizes the registers of the D/A converter. Table 17.2 D/A Converter Registers Channels Name Abbreviation R/W Initial Value Address * 0, 1 D/A data register 0 DADR0 R/W H'00 H'FFA4 D/A data register 1 DADR1 R/W H'00 H'FFA5 D/A control register 01 DACR01 R/W H'1F H'FFA6 Common Module stop control register MSTPCR R/W H'3FFF H'FF3C Note: * Lower 16 bits of the address.

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17.2 Register Descriptions

17.2.1 D/A Data Registers 0, 1 (DADR0, DADR1)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W DADR0, DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode.

17.2.2 D/A Control Registers 01 (DACR01)

Bit : 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value : 0 0 0 1 1 1 1 1 R/W : R/W R/W R/W — — — — — DACR01 is a 8-bit readable/writable register that controls the operation of the D/A converter. DACR01 is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1

0 Analog output DA1 is disabled (Initial value)

1 Channel 1 D/A conversion is enabled; analog output DA1 is enabled

Rev.6.00 Sep. 27, 2007 Page 727 of 1268 REJ09B0220-0600 Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0

0 Analog output DA0 is disabled (Initial value)

1 Channel 0 D/A conversion is enabled; analog output DA0 is enabled

Bit 5—D/A Enable (DAE): Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, channel 0 and 1 D/A conversions are controlled together. Output of conversion results is always controlled independently by the DAOE0 and DAOE1 bits. Bit 7 DAOE1 Bit 6 DAOE0 Bit 5 DAE 0 0 * Channel 0 and 1 D/A conversions disabled 1 0 Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled

1 Channel 0 and 1 D/A conversions enabled

1 0 0 Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 * Channel 0 and 1 D/A conversions enabled *: Don’t care If the chip enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear both the DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.

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17.2.3 Module Stop Control Register (MSTPCR)

Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10—Module Stop (MSTP10): Specifies the D/A converter channel 0 and 1module stop mode. Bit 10 MSTP10

0 D/A converter module stop mode cleared

1 D/A converter module stop mode set (Initial value)

17.3 Operation

The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 17.2 shows the timing of this operation. [1] Write the conversion data to DADR0.

Rev.6.00 Sep. 27, 2007 Page 729 of 1268 REJ09B0220-0600 [2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents 256 × Vref The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin. Conversion data 1 Conversion result 1High-impedance state tDCONV DADR0 write cycle DA0 DAOE0 DADR0 Address φ DACR01 write cycle Conversion data 2 Conversion result 2 tDCONV Legend: tDCONV: D/A conversion time DADR0 write cycle DACR01 write cycle Figure 17.2 Example of D/A Converter Operation

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Rev.6.00 Sep. 27, 2007 Page 731 of 1268 REJ09B0220-0600 Section 18 RAM

18.1 Overview

The H8S/2329B and H8S/2324S have 32 kbytes of on-chip high-speed static RAM, the H8S/2328 (H8S/2328B in flash memory version), H8S/2327, H8S/2326, H8S/2323, and H8S/2322R have 8 kbytes, and the H8S/2321 and H8S/2320 have 4 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR).

18.1.1 Block Diagram

Figure 18.1 shows a block diagram of 32 kbytes of on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FF7C00 H'FF7C02 H'FF7C04 H'FFFBFE H'FF7C01 H'FF7C03 H'FF7C05 H'FFFBFF Figure 18.1 Block Diagram of RAM (32 kbytes)

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18.1.2 Register Configuration

The on-chip RAM is controlled by SYSCR. Table 18.1 shows the address and initial value of SYSCR. Table 18.1 RAM Register Name Abbreviation R/W Initial Value Address * System control register SYSCR R/W H'01 H'FF39 Note: * Lower 16 bits of the address.

18.2 Register Descriptions

18.2.1 System Control Register (SYSCR)

Bit : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG LWROD IRQPAS RAME Initial value : 0 0 0 0 0 0 0 1 R/W : R/W — R/W R/W R/W R/W R/W R/W The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 5.2.1, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME

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18.3 Operation

When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. Note: The amount of on-chip RAM differs depending on the product. Refer to section 3.5, Memory Map in Each Operation Mode, for details.

18.4 Usage Note

DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0.

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Rev.6.00 Sep. 27, 2007 Page 735 of 1268 REJ09B0220-0600 Section 19 ROM

19.1 Overview

The Series has 512, 384, or 256 kbytes of on-chip flash memory, or 256, 128, or 32 kbytes of on- chip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by means of the mode pins (MD2 to MD0) and the EAE bit in BCRL. The flash memory version of the chip can be erased and programmed with a PROM programmer, as well as on-board.

19.1.1 Block Diagram

Figure 19.1 shows a block diagram of 256 kbytes of on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'03FFFE H'000001 H'000003 H'03FFFF Figure 19.1 Block Diagram of ROM (256 kbytes)

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19.1.2 Register Configuration

The operating mode of the chip is controlled by the mode pins and the BCRL register. The ROM- related registers are shown in table 19.1. Table 19.1 ROM Registers Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined H'FF3B Bus controller register BCRL R/W Undefined H'FED5 Note: * Lower 16 bits of the address.

19.2 Register Descriptions

19.2.1 Mode Control Register (MDCR)

Bit : 7 6 5 4 3 2 1 0 Initial value : 1 0 0 0 0 — * — * — * Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register used to monitor the current operating mode of the chip. Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset.

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19.2.2 Bus Control Register L (BCRL)

Bit : 7 6 5 4 3 2 1 0 BRLE BREQOE EAE — DDS — WDBE WAITE Initial value : 0 0 1 1 1 1 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL). Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*2 are to be internal addresses or external addresses. H8S/2329B, H8S/2328*3, H8S/2326 H8S/2327 H8S/2323 H'01FFFF are on-chip ROM or address H'020000 to H'03FFFF are reserved area*1 Reserved area*1 or reserved area*1 in single-chip mode (Initial value) Notes: 1. Do not access a reserved area. 2. Addresses H'010000 to H'05FFFF in the H8S/2329B. Addresses H'010000 to H'07FFFF in the H8S/2326. 3. H8S/2328B in flash memory version.

19.3 Operation

The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) and the EAE bit in BCRL. These settings are shown in tables 19.2 and 19.3.

Rev.6.00 Sep. 27, 2007 Page 738 of 1268 REJ09B0220-0600 Table 19.2 Operating Modes and ROM (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) Mode Pins BCRL Mode Operating Mode FWE MD 2 MD1 MD0 EAE On-Chip ROM 1 — 0 0 0 1 — — 2 1 0 3 1

4 Advanced expanded mode

1 0 0 — Disabled

5 Advanced expanded mode

6 Advanced expanded mode

(256 kbytes)* 1*5

1 Enabled

(64 kbytes)

7 Advanced single-chip mode 1 0 Enabled

(256 kbytes) *1*5 (64 kbytes) 8 — 1 0 0 0 — — 9 1 10 1 0 0 Enabled (256 kbytes) *2*5 Boot mode (advanced expanded mode with on-chip ROM enabled)* 3 1 Enabled (64 kbytes)

11 Boot mode (advanced

single-chip mode) 1 0 Enabled (256 kbytes) *2*5 (64 kbytes) 12 — 1 0 0 — — 13 1 14 1 0 0 Enabled (256 kbytes) *1*5 User program mode (advanced expanded mode with on-chip ROM enabled)* (64 kbytes) 15 1 0 Enabled (256 kbytes) *1*5 User program mode (advanced single-chip mode)*4 1 Enabled (64 kbytes) Notes: 1. Note that in modes 6, 7, 14, and 15, the on-chip ROM that can be used after a reset is the 64-kbyte area from H'000000 to H'00FFFF.

Rev.6.00 Sep. 27, 2007 Page 739 of 1268 REJ09B0220-0600 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 4. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. 5. The capacity of on-chip ROM in the H8S/2328B F-ZTAT is 256 kbytes. The capacity of on-chip ROM in the H8S/2326 F-ZTAT is 512 kbytes. Table 19.3 Operating Modes and ROM (H8S/2329B F-ZTAT and Mask ROM Version) Mode Pins BCRL Mode Operating Mode MD2 MD1 MD0 EAE On-Chip ROM 1 — 0 0 1 — — 2*3 1 0 3*3 1 1 0 0 — Disabled 6 1 0 0 Enabled (256 kbytes) *1*2 Advanced expanded mode with on-chip ROM enabled 1 Enabled (64 kbytes)

7 Advanced single-chip mode 1 0 Enabled (256 kbytes) *1*2

1 Enabled (64 kbytes)

Notes: 1. Note that in modes 6 and 7, the on-chip ROM that can be used after a reset is the 64- kbyte area from H'000000 to H'00FFFF. 2. The amount of on-chip RAM differs depending on the product. Refer to section 3.5, Memory Map in Each Operation Mode, for details. 3. Boot mode in the H8S/2329B F-ZTAT. See table 19.9, for information on H8S/2329B F-ZTAT user boot modes. See table 19.9, for information on H8S/2329B F-ZTAT user program modes.

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19.4 Overview of Flash Memory (H8S/2329B F-ZTAT)

19.4.1 Features

The H8S/2329B F-ZTAT has 384 kbytes of on-chip flash memory. The features of the flash memory are summarized below.

• Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode
• Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). To erase the entire flash memory, the individual blocks must be erased sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks.
• Programming/erase times The flash memory programming time is 10.0 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 µs (typ.) per byte, and the erase time is 50 ms (typ.).
• Reprogramming capability The flash memory can be reprogrammed minimum 100 times.
• On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: ⎯ Boot mode ⎯ User program mode
• Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host.
• Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time.
• Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations.

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• PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode.

19.4.2 Overview

(384 kbytes) Operating modeEBR1 Internal address bus Internal data bus (16 bits) Mode pins EBR2 SYSCR2 FLMCR2 FLMCR1 RAMER Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2: Erase block register 2 RAMER: RAM emulation register SYSCR2: System control register 2 Figure 19.2 Block Diagram of Flash Memory

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19.4.3 Flash Memory Operating Modes

Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 19.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. Boot mode On-board programming mode User program mode User mode (on-chip ROM enabled) Reset state PROM mode RES = 0 SWE = 1 SWE = 0 Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, MD1 = 0, MD2 = 0, P66 = 1, P65 = 0, P64 = 0 RES = 0 RES = 0 RES = 0 MD1 = 1, MD2 = 1 MD1 = 1, MD2 = 0 Figure 19.3 Flash Memory Mode Transitions

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19.4.4 On-Board Programming Modes

• Boot mode Flash memory Chip RAM Host Programming control program SCI Application program (old version) New application program Flash memory Chip RAM Host SCI Application program (old version) Boot program area New application program Flash memory Chip RAM Host SCI Flash memory prewrite-erase Boot program New application program Flash memory Chip Program execution state RAM Host SCI New application program Boot program Programming control program 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Programming control program Boot programBoot program Boot program area Boot program area Programming control program Figure 19.4 Boot Mode

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• User program mode Flash memory Chip RAM Host Programming/ erase control program SCIBoot program New application program Flash memory Chip RAM Host SCI New application program Flash memory Chip RAM Host SCI Flash memory erase Boot program New application program Flash memory Chip Program execution state RAM Host SCIBoot program Boot program Application program (old version) New application program 1. Initial state (1) The program that will transfer the programming/erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer Executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Programming/ erase control program Programming/ erase control program Programming/ erase control program Application program (old version) Transfer program Transfer program Transfer program Transfer program Figure 19.5 User Program Mode (Example)

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19.4.5 Flash Memory Emulation in RAM

Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Application program Execution state Flash memory Emulation block RAM SCI Overlap RAM (emulation is performed on data written in RAM) Figure 19.6 Reading Overlap RAM Data in User Mode and User Program Mode

Rev.6.00 Sep. 27, 2007 Page 746 of 1268 REJ09B0220-0600 Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Application program Flash memory RAM SCI Overlap RAM (programming data)Programming data Programming control program Execution state Figure 19.7 Writing Overlap RAM Data in User Program Mode

19.4.6 Differences between Boot Mode and User Program Mode

Table 19.4 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm.

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19.4.7 Block Configuration

The flash memory is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 Address H'5FFFF 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 32 kbytes 384 kbytes 4 kbytes × 8 Figure 19.8 Flash Memory Block Configuration

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19.4.8 Pin Configuration

The flash memory is controlled by means of the pins shown in table 19.5. Table 19.5 Flash Memory Pins Pin Name Abbreviation I/O Function Reset RES Input Reset Mode 2 MD2 Input Sets MCU operating mode Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port 64 P64 Input Sets MCU operating mode in PROM mode Port 65 P65 Input Sets MCU operating mode in PROM mode Port 66 P66 Input Sets MCU operating mode in PROM mode Transmit data TxD1 Output Serial transmit data output Receive data RxD1 Input Serial receive data input

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19.4.9 Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 19.6. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.6 Flash Memory Registers Register Name Abbreviation R/W Initial Value Address*1 Flash memory control register 1 FLMCR1 *5 R/W *3 H'80 H'FFC8 *2 Flash memory control register 2 FLMCR2 *5 R/W *3 H'00 H'FFC9 *2 Erase block register 1 EBR1 *5 R/W *3 H'00 *4 H'FFCA *2 Erase block register 2 EBR2 *5 R/W *3 H'00 *4 H'FFCB *2 System control register 2 SYSCR2 *6 R/W H'00 H'FF42 RAM emulation register RAMER R/W H'00 H'FEDB Notes: 1. Lower 16 bits of the address. 2. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. 4. If a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 6. The SYSCR2 register can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be modified.

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19.5 Register Descriptions

19.5.1 Flash Memory Control Register 1 (FLMCR1)

Bit : 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Initial value : 1 0 0 0 0 0 0 0 R/W : R R/W R/W R/W R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1, then setting the EV or PV bit. Program mode is entered by setting SWE to 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized to H'80 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writing to bits ESU, PSU, EV, and PV in FLMCR1 is enabled only when SWE = 1; writing to the E bit is enabled only when SWE = 1, and ESU = 1; and writing to the P bit is enabled only when SWE = 1, and PSU = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. These bits cannot be modified and are always read as 1 in this model. Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and erasing. This bit should be set when setting bits 5 to 0 in FLMCR1, EBR1 bits 7 to 0, and EBR2 bits 5 to 0. When SWE = 1, the flash memory can only be read in program-verify or erase-verify mode. Bit 6 SWE

0 Writes disabled (Initial value)

1 Writes enabled

Rev.6.00 Sep. 27, 2007 Page 751 of 1268 REJ09B0220-0600 Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU

0 Erase setup cleared (Initial value)

1 Erase setup

[Setting condition] When SWE = 1 Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU

0 Program setup cleared (Initial value)

1 Program setup

[Setting condition] When SWE = 1 Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV

0 Erase-verify mode cleared (Initial value)

1 Transition to erase-verify mode

[Setting condition] When SWE = 1

Rev.6.00 Sep. 27, 2007 Page 752 of 1268 REJ09B0220-0600 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV

0 Program-verify mode cleared (Initial value)

1 Transition to program-verify mode

[Setting condition] When SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E

0 Erase mode cleared (Initial value)

1 Transition to erase mode

[Setting condition] When SWE = 1, and ESU = 1 Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P

0 Program mode cleared (Initial value)

1 Transition to program mode

[Setting condition] When SWE = 1, and PSU = 1

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19.5.2 Flash Memory Control Register 2 (FLMCR2)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error- protection state. Bit 7 FLER

0 Flash memory is operating normally (Initial value)

Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode

1 An error has occurred during flash memory programming/erasing

Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.8.3, Error Protection Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0.

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19.5.3 Erase Block Register 1 (EBR1)

Bit : 7 6 5 4 3 2 1 0 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. The flash memory block configuration is shown in table 19.7.

19.5.4 Erase Block Registers 2 (EBR2)

Bit : 7 6 5 4 3 2 1 0 EBR2 — — EB13 EB12 EB11 EB10 EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 R/W : — — R/W R/W R/W R/W R/W R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). Bits 7 and 6 are reserved: they are always read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.7.

Rev.6.00 Sep. 27, 2007 Page 755 of 1268 REJ09B0220-0600 Table 19.7 Flash Memory Erase Blocks Block (Size) Address EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF EB7 (4 kbytes) H'007000 to H'007FFF EB8 (32 kbytes) H'008000 to H'00FFFF EB9 (64 kbytes) H'010000 to H'01FFFF EB10 (64 kbytes) H'020000 to H'02FFFF EB11 (64 kbytes) H'030000 to H'03FFFF EB12 (64 kbytes) H'040000 to H'04FFFF EB13 (64 kbytes) H'050000 to H'05FFFF

19.5.5 System Control Register 2 (SYSCR2)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be modified. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.

Rev.6.00 Sep. 27, 2007 Page 756 of 1268 REJ09B0220-0600 Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE (Initial value)

1 Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB

Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0. Bit 0—Reserved: This bit should not be written with 0.

19.5.6 RAM Emulation Register (RAMER)

Bit : 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — R/W R/W R/W R/W RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19.8. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.

Rev.6.00 Sep. 27, 2007 Page 757 of 1268 REJ09B0220-0600 Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS

0 Emulation not selected (Initial value)

Program/erase-protection of all flash memory blocks is disabled

1 Emulation selected

Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 19.8.) Table 19.8 Flash Memory Area Divisions RAM Area Block Name RAMS RAM2 RAM1 RAM0 H'FFDC00 to H'FFEBFF RAM area, 4 kbytes 0 * * * H'000000 to H'000FFF EB0 (4 kbytes) 1 0 0 0 H'001000 to H'001FFF EB1 (4 kbytes) 1 0 0 1 H'002000 to H'002FFF EB2 (4 kbytes) 1 0 1 0 H'003000 to H'003FFF EB3 (4 kbytes) 1 0 1 1 H'004000 to H'004FFF EB4 (4 kbytes) 1 1 0 0 H'005000 to H'005FFF EB5 (4 kbytes) 1 1 0 1 H'006000 to H'006FFF EB6 (4 kbytes) 1 1 1 0 H'007000 to H'007FFF EB7 (4 kbytes) 1 1 1 1 *: Don’t care

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19.6 On-Board Programming Modes

When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.9. For a diagram of the transitions to the various flash memory modes, see figure 19.3. Table 19.9 Setting On-Board Programming Modes Mode Pins MCU Mode CPU Operating Mode MD2 MD1 MD0 Boot mode Advanced expanded mode with on-chip ROM enabled 0 1 0 Advanced single-chip mode 1 User program mode* Advanced expanded mode with on-chip ROM enabled 1 1 0 Advanced single-chip mode 1 Note: * Normally, user mode should be used. Set the SWE bit to 1 to make a transition to user program mode before performing a program/erase/verify operation.

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19.6.1 Boot Mode

When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2329B F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in on- chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19.9, and the boot program mode execution procedure in figure 19.10. RxD1 TxD1 SCI1 Chip Flash memory Write data reception Verify data transmission Host On-chip RAM Figure 19.9 System Configuration in Boot Mode

Rev.6.00 Sep. 27, 2007 Page 760 of 1268 REJ09B0220-0600 Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n = 1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM n = N? No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n + 1 → n Figure 19.10 Boot Mode Execution Procedure

Rev.6.00 Sep. 27, 2007 Page 761 of 1268 REJ09B0220-0600 Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2329B F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps. Table 19.10 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Start bit Stop bitD0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19.11 Automatic SCI Bit Rate Adjustment Table 19.10 System Clock Frequencies for which Automatic Adjustment of H8S/2329B F-ZTAT Bit Rate is Possible Host Bit Rate System Clock Frequency for which Automatic Adjustment of H8S/2329B F-ZTAT Bit Rate is Possible 19,200 bps 16 MHz to 25 MHz 9,600 bps 8 MHz to 25 MHz On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FF7C00 to H'FF83FF is reserved for use by the boot program, as shown in figure 19.12. The area to which the programming control program is transferred is H'FF8400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required.

Rev.6.00 Sep. 27, 2007 Page 762 of 1268 REJ09B0220-0600 H'FF7C00 H'FF83FF Programming control program area (30 kbytes) H'FFFBFF Boot program area* (2 kbytes) Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19.12 RAM Areas in Boot Mode Notes on Use of Boot Mode

• When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin.
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased.
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'FF8400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).

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• The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program.
• Initial settings must also be made for the other on-chip registers.
• Boot mode can be entered by making the pin settings shown in table 19.9 and executing a reset-start.
• Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pins, and executing reset release* 1. Boot mode can also be cleared by a WDT overflow reset.
• Do not change the mode pin input levels in boot mode.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode* Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pins input must satisfy the mode programming setup time (t MDS = 200 ns) with respect to the reset release timing. 2. See section 9, I/O Ports.

19.6.2 User Program Mode

When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means supply of programming data, and storing a program/erase control program in part of the program area if necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7). In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM.

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19.7 Programming/Erasing Flash Memory

In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the instruction for programming the flash memory is executed. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.

19.7.1 Program Mode

Follow the procedure shown in the program/program-verify flowchart in figure 19.14 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (x, y, z1, z2, z3 α, ß, γ, ε, η, and θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the

Rev.6.00 Sep. 27, 2007 Page 766 of 1268 REJ09B0220-0600 elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart.

19.7.2 Program-Verify Mode

In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program- verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.14) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode in FLMCR1 to 0, and wait again for at least (θ) μs. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits.

Rev.6.00 Sep. 27, 2007 Page 767 of 1268 REJ09B0220-0600 Start End of programming End sub Set SWE bit in FLMCR1 Wait (x) μs n = 1 m = 0 Sub-routine-call See Note 7 for pulse width Note 7: Write Pulse Width Start of programming Sub-routine write pulse Set PSU bit in FLMCR1 Enable WDT Set P bit in FLMCR1 Wait (y) μs Clear P bit in FLMCR1 Wait (z1) μs or (z2) μs or (z3) μs Clear PSU bit in FLMCR1 Wait (α) μs Disable WDT Wait (β) μs Write pulse application subroutine NG NG NG NG NG NG OK OK OK OK OK Wait (γ) μs Wait (ε) μs *6 *6 *5 *6 Set PV bit in FLMCR1 H'FF dummy write to verify address Read verify data Additional program data computation Transfer additional program data to additional program data area Read data = verify data? *3Reprogram data computation Clear PV bit in FLMCR1 Clear SWE bit in FLMCR1 m = 1 128-byte data verification completed? m = 0? 6 ≥ n ? 6 ≥ n ? Increment address Programming failure OK Clear SWE bit in FLMCR1 n ≥ N? Write 128-byte data in RAM reprogram data area consecutively to flash memory Write pulse (z1) μs or (z2) μs Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. RAM Program data area (128 bytes) Reprogram data area (128 bytes) Additional program data area (128 bytes) Store 128-byte program data in program data area and reprogram data area Number of Writes (n) 13.. 998 999 1000 Write Time (z) μs z2.. Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Program Data Operation Chart Transfer reprogram data to reprogram data area n ← n + 1 Note: Use a (z3) µs write pulse for additional programming. Sequentially write 128-byte data in additional program data area in RAM to flash memory Write Pulse (z3 µs additional write pulse) Wait (θ) μs Wait (η) μs Wait (θ) μs Reprogram Data (X) Original Data (D) Verify Data (V) Comments Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed Additional Program Data Operation Chart Additional Program Data (Y) Reprogram Data (X') Verify Data (V) Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. 3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data should be provided in RAM. The contents of the reprogram data and additional program data areas are modified as programming proceeds. 5. A write pulse of (z1) or (z2) μs should be applied according to the progress of programming. See Note 7 for the pulse widths. When the additional program data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied. 6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics. Figure 19.14 Program/Program-Verify Flowchart

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19.7.3 Erase Mode

Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.15. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure.

19.7.4 Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then the ESU bit in FLMCR1 is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of ( γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase- verify sequence is not repeated more than (N) times. When verification is completed, exit erase- verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1 to 0 and wait for at least (θ) μs. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way.

Rev.6.00 Sep. 27, 2007 Page 769 of 1268 REJ09B0220-0600 End of erasing Start Set SWE bit in FLMCR1 Set ESU bit in FLMCR1 Set E bit in FLMCR1 Wait (x) μs Wait (y) μs n = 1 Set EBR1, EBR2 Enable WDT Wait (z) ms *2 Wait (α) μs *2 Wait (β) μs *2 Wait (γ) μs Set block start address to verify address Wait (ε) μs *2 Wait (η) μs Start of erase Clear E bit in FLMCR1 Clear ESU bit in FLMCR1 Set EV bit in FLMCR1 H'FF dummy write to verify address Read verify data Clear EV bit in FLMCR1 Wait (η) μs Clear EV bit in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT Halt erase Verify data = all 1? Last address of block? End of erasing of all erase blocks? Erase failure Clear SWE bit in FLMCR1 n ≥ N? NG NG NG NG OK OK OK OK n ← n + 1 Increment address Notes: 1. Prewriting (setting erase block data to all 0) is not necessary. 2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in the section 22.2.6, Flash Memory Characteristics. 3. Verify data is read in 16-bit (W) units. 4. Set only one bit in EBR1or EBR2. More than one bit cannot be set. 5. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Wait (θ) μs Wait ( θ) μs Figure 19.15 Erase/Erase-Verify Flowchart

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19.8 Flash Memory Protection

There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection.

19.8.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.11). Table 19.11 Hardware Protection Functions Item Description Program Erase Reset/standby protection

• In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered.
• In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in section 22.2.3, AC Characteristics. Yes Yes

19.8.2 Software Protection

Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode (see table 19.12).

Rev.6.00 Sep. 27, 2007 Page 771 of 1268 REJ09B0220-0600 Table 19.12 Software Protection Functions Item Description Program Erase SWE bit protection • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks.

• (Execute in on-chip RAM or external memory.) Yes Yes Block specification protection
• Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2).
• Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. — Yes Emulation protection • Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Yes Yes

19.8.3 Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows:

• When flash memory is read during programming/erasing (including a vector read or instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby) is executed during programming/erasing
• When a bus master other than the CPU (the DMAC or DTC) has control of the bus during programming/erasing

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19.9 Flash Memory Emulation in RAM

19.9.1 Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.17 shows an example of emulation of real-time flash memory programming. Start of emulation program End of emulation program Tuning OK? Yes No Set RAMER Write tuning data to overlap RAM Execute application program Clear RAMER Write to flash memory emulation block Figure 19.17 Flowchart for Flash Memory Emulation in RAM

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19.9.2 RAM Overlap

An example in which flash memory block area EB1 is overlapped is shown below. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'5FFFF Flash memory EB8 to EB13 This area can be accessed from both the RAM area and flash memory area EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FFDC00 H'FFEBFF H'FFFBFF On-chip RAM Figure 19.18 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1. Set bits RAMS, RAM2, RAM1, and RAM0 in RAMER to 1, 0, 0, 1, to overlap part of RAM onto the area (EB1) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause

Rev.6.00 Sep. 27, 2007 Page 775 of 1268 REJ09B0220-0600 a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM.

19.10 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* 1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests, including NMI, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. The NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons:

• If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly.

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19.11 Flash Memory PROM Mode

19.11.1 PROM Mode Setting

Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19.13 shows PROM mode pin settings. Table 19.13 PROM Mode Pin Settings Pin Names Settings/External Circuit Connection Mode pins: MD2, MD1, MD0 Low-level input Mode setting pins: P66, P65, P64 High-level input to P66, low-level input to P65 and P64 STBY pin High-level input (do not select hardware standby mode) RES pin Reset circuit XTAL, EXTAL pins Oscillator circuit Other pins requiring setting: P32, P25 High-level input to P32, low-level input to P25

19.11.2 Socket Adapters and Memory Map

In PROM mode, a socket adapter is connected to the chip as shown in figure 19.20. Figure 19.19 shows the on-chip ROM memory map and figure 19.20 shows the socket adapter pin assignments. H'00000000 MCU mode address PROM mode address H'0005FFFF H'00000 H'5FFFF On-chip ROM space (384 kbytes) Figure 19.19 Memory Map in PROM Mode

Rev.6.00 Sep. 27, 2007 Page 777 of 1268 REJ09B0220-0600 H8S/2329B F-ZTAT Socket Adapter (40-Pin Conversion)TFP-120 Pin Name A A10 A11 A12 A13 A14 A15 A16 A17 A18 D10 D11 D12 D13 D14 D15 CE OE WE EMLE*3 HN27C4096HG (40 Pins) Pin No. Pin Name 1, 40 11, 30 5, 6, 7 A A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 FP-128B RES XTAL EXTAL NC (OPEN) 75, 76, 81, 93, 94 47, 59, 66, 79, 103, 104, 113, 114, 115 83, 84, 89, 103, 104 100, 113, 114, 123, 124, 125 V CC VSS Reset circuit Oscillation circuit Legend: EMLE: Emulation enable I/O7 to I/O0: Data input/output A18 to A0: Address input CE: Chip enable OE: Output enable WE: Write enable Notes: 1. A reset oscillation stabilization time (t osc1) of at least 10 ms is required. 2. A 12 MHz crystal resonator should be used. 3. As the FWE pin becomes VCC in the H8S/2329B F-ZTAT, the EMLE pin is ignored in PROM mode. This figure shows pin assignments, and does not show the entire socket adapter circuit. Other pins Figure 19.20 H8S/2329B F-ZTAT Socket Adapter Pin Assignments

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19.11.3 PROM Mode Operation

Table 19.14 shows how the different operating modes are set when using PROM mode, and table 19.15 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19.14 Settings for Each Operating Mode in PROM Mode Pin Names Mode CE OE WE I/O7 to I/O0 A 18 to A0 Read L L H Data output Ain Output disable L H H Hi-Z X Command write L H L Data input Ain *2 Chip disable*1 H X X Hi-Z X Legend: H: High level L: Low level Hi-Z: High impedance X: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode.

Rev.6.00 Sep. 27, 2007 Page 779 of 1268 REJ09B0220-0600 Table 19.15 PROM Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write PA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Legend: RA: Read address PA: Program address Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n).

19.11.4 Memory Read Mode

• After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed.
• Command writes can be performed in memory read mode, just as in the command wait state.
• Once memory read mode has been entered, consecutive reads can be performed.
• After power-on, memory read mode is entered.

Rev.6.00 Sep. 27, 2007 Page 780 of 1268 REJ09B0220-0600 Table 19.16 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 Data H'00 OE WE Command write twep tceh tdh tds tf tr tnxtc Note: Data is latched at the rising edge of WE. tces Memory read mode Address stable Data Figure 19.21 Memory Read Mode Timing Waveforms after Command Write

Rev.6.00 Sep. 27, 2007 Page 781 of 1268 REJ09B0220-0600 Table 19.17 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 I/O7 to I/O0 OE WE Other mode command write tceh tds tdh tf tr tnxtc Note: Do not enable WE and OE at the same time. tces twep Memory read mode Address stable Figure 19.22 Timing Waveforms when Entering Another Mode from Memory Read Mode

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19.11.5 Auto-Program Mode

• In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed.
• A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
• The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
• Memory address transfer is executed in the second cycle (figure 19.25). Do not perform transfer later than the second cycle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming operations cannot be carried out on address blocks that have already been programmed.
• Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-program operation).
• Status polling I/O6 and I/O7 information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE.

Rev.6.00 Sep. 27, 2007 Page 784 of 1268 REJ09B0220-0600 AC Characteristics Table 19.19 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t wsts 1 — ms Status polling access time t spa — 150 ns Address setup time t as 0 — ns Address hold time t ah 60 — ns Memory write time t write 1 3000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns Address stable CE A18 to A0 I/O5 to I/O0 I/O6 I/O7 OE WE tas tah tdhtds tf tr twep twsts twrite tspa tnxtc tnxtctcehtces Programming operation end identification signal Data transfer 1 byte to 128 bytes H'40 H'00 Programming normal end identification signal Figure 19.25 Auto-Program Mode Timing Waveforms

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19.11.6 Auto-Erase Mode

• Auto-erase mode supports only total memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation).
• Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. AC Characteristics Table 19.20 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t ests 1 — ms Status polling access time t spa — 150 ns Memory erase time t erase 100 40000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns

Rev.6.00 Sep. 27, 2007 Page 786 of 1268 REJ09B0220-0600 CE A18 to A0 I/O5 to I/O0 I/O6 I/O7 OE WE tests terase tspa tdhtds tf tr twep tnxtc tnxtctcehtces Erase end identifi- cation signal Erase normal end confirmation signal H'20 H'20 H'00 Figure 19.26 Auto-Erase Mode Timing Waveforms

19.11.7 Status Read Mode

• Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
• The return code is retained until a command write for other than status read mode is performed. Table 19.21 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns OE output delay time t oe — 150 ns Disable delay time t df — 100 ns CE output delay time t ce — 150 ns WE rise time t r — 30 ns WE fall time t f — 30 ns

Rev.6.00 Sep. 27, 2007 Page 787 of 1268 REJ09B0220-0600 CE A18 to A0 I/O7 to I/O0 OE WE tdh tdftds tf tr twep tnxtc tnxtc tf tr twep tds tdh tnxtctceh tceh toe tces tces tce H'71 H'71 Note: I/O3 and I/O2 are undefined. Figure 19.27 Status Read Mode Timing Waveforms Table 19.22 Status Read Mode Return Commands Pin Name I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 Attribute Normal end identification Command error Program- ming error Erase error — — Program- ming or erase count exceeded Effective address error Initial value 0 0 0 0 0 0 0 0 Indications Normal end: 0 Abnormal end: 1 Command error: 1 Otherwise: 0 Program- ming error: 1 Otherwise: 0 Erase error: 1 Otherwise: 0 — — Count exceeded: 1 Otherwise: 0 Effective address error: 1 Otherwise: 0 Note: I/O 3 and I/O2 are undefined.

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19.11.8 Status Polling

• The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode.
• The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19.23 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End Normal End I/O 7 0 1 0 1 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0

19.11.9 PROM Mode Transition Time

Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Table 19.24 Command Wait State Transition Time Specifications Item Symbol Min Max Unit Standby release (oscillation stabilization time) tosc1 30 — ms PROM mode setup time t bmv 10 — ms VCC hold time t dwn 0 — ms VCC RES Memory read mode Command wait state Command wait state Normal/ abnormal end identification Auto-program mode Auto-erase mode tosc1 tbmv tdwn Command acceptance Figure 19.28 Oscillation Stabilization Time, PROM Mode Setup Time, and Power Supply Fall Sequence

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19.11.10 Notes on Memory Programming

• When programming addresses which have previously been programmed, carry out auto- erasing before auto-programming.
• When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be carried out on address blocks that have already been programmed.

19.12 Flash Memory Programming and Erasing Precautions

Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off: When applying or disconnecting VCC power, fix the RES pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc.

Rev.6.00 Sep. 27, 2007 Page 790 of 1268 REJ09B0220-0600 Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: When flash memory is programmed or erased, all interrupt requests, including NMI, should be disabled to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In on- board programming, perform only one programming operation on a 128-byte programming unit block. In PROM mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors.

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19.13 Overview of Flash Memory (H8S/2328B F-ZTAT)

19.13.1 Features

The H8S/2328B F-ZTAT has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below.

• Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode
• Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). To erase the entire flash memory, the individual blocks must be erased sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks.
• Programming/erase times The flash memory programming time is 10.0 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 µs (typ.) per byte, and the erase time is 50 ms (typ.).
• Reprogramming capability The flash memory can be reprogrammed minimum 100 times.
• On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: ⎯ Boot mode ⎯ User program mode
• Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host.
• Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time.
• Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations.

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• PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode.

19.13.2 Overview

(256 kbytes) Operating modeEBR1 Internal address bus Internal data bus (16 bits) FWE pin Mode pins EBR2 SYSCR2 FLMCR2 FLMCR1 RAMER Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2: Erase block register 2 RAMER: RAM emulation register SYSCR2: System control register 2 Figure 19.29 Block Diagram of Flash Memory

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19.13.3 Flash Memory Operating Modes

Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a reset- start is executed, the chip enters one of the operating modes shown in figure 19.30. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. Boot mode On-board programming mode User program mode User mode (on-chip ROM enabled) Reset state PROM mode RES = 0 FWE = 1, SWE = 1 FWE = 0 or SWE = 0 Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, MD1 = 0, MD2 = 0, P66 = 1, P65 = 0, P64 = 0 RES = 0 RES = 0 RES = 0 MD1 = 1, MD2 = 1, FWE = 0 FWE = 1, MD1 = 1, MD2 = 0 Figure 19.30 Flash Memory Mode Transitions

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19.13.4 On-Board Programming Modes

• Boot mode Flash memory Chip RAM Host Programming control program SCI Application program (old version) New application program Flash memory Chip RAM Host SCI Application program (old version) Boot program area New application program Flash memory Chip RAM Host SCI Flash memory prewrite-erase Boot program New application program Flash memory Chip Program execution state RAM Host SCI New application program Boot program Programming control program 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Programming control program Boot programBoot program Boot program area Boot program area Programming control program Figure 19.31 Boot Mode

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• User program mode Flash memory Chip Chip RAM Host Programming/ erase control program SCIBoot program New application program Flash memory RAM Host SCI New application program Flash memory RAM Host SCI Flash memory erase Boot program New application program Flash memory Program execution state RAM Host SCIBoot program Boot program FWE assessment program Application program (old version) New application program 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Programming/ erase control program Programming/ erase control program Programming/ erase control program Transfer program Application program (old version) Transfer program FWE assessment program FWE assessment program Transfer program FWE assessment program Transfer program Chip Chip Figure 19.32 User Program Mode (Example)

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19.13.5 Flash Memory Emulation in RAM

Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Application program Execution state Flash memory Emulation block RAM SCI Overlap RAM (emulation is performed on data written in RAM) Figure 19.33 Reading Overlap RAM Data in User Mode and User Program Mode

Rev.6.00 Sep. 27, 2007 Page 797 of 1268 REJ09B0220-0600 Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Application program Flash memory RAM SCI Overlap RAM (programming data)Programming data Programming control program Execution state Figure 19.34 Writing Overlap RAM Data in User Program Mode

19.13.6 Differences between Boot Mode and User Program Mode

Table 19.25 Differnces between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm.

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19.13.7 Block Configuration

On-chip 256-kbyte flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 Address H'3FFFF 4 kbytes × 8 32 kbytes 64 kbytes 256 kbytes 64 kbytes 64 kbytes Figure 19.35 Flash Memory Block Configuration

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19.13.8 Pin Configuration

The flash memory is controlled by means of the pins shown in tables 19.26. Table 19.26 Flash Memory Pins Pin Name Abbreviation I/O Function Reset RES Input Reset Flash write enable FWE Input Flash program/erase protection by hardware Mode 2 MD2 Input Sets MCU operating mode Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port 64 P64 Input Sets MCU operating mode in PROM mode Port 65 P65 Input Sets MCU operating mode in PROM mode Port 66 P66 Input Sets MCU operating mode in PROM mode Transmit data TxD1 Output Serial transmit data output Receive data RxD1 Input Serial receive data input

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19.13.9 Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 19.27. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.27 Flash Memory Registers Register Name Abbreviation R/W Initial Value Address*1 Flash memory control register 1 FLMCR1 *6 R/W *3 H'00/H'80 *4 H'FFC8 *2 Flash memory control register 2 FLMCR2 *6 R/W *3 H'00 H'FFC9 *2 Erase block register 1 EBR1 *6 R/W *3 H'00 *5 H'FFCA *2 Erase block register 2 EBR2 *6 R/W *3 H'00 *5 H'FFCB *2 System control register 2 SYSCR2 *7 R/W H'00 H'FF42 RAM emulation register RAMER R/W H'00 H'FEDB Notes: 1. Lower 16 bits of the address. 2. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in FLMCR1. 4. When a high level is input to the FWE pin, the initial value is H'80. 5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 7. The SYSCR2 register can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be modified.

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19.14 Register Descriptions

19.14.1 Flash Memory Control Register 1 (FLMCR1)

Bit : 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Initial value : 1/0 0 0 0 0 0 0 0 R/W : R R/W R/W R/W R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the EV or PV bit. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV, and PV only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE

0 When a low level is input to the FWE pin (hardware-protected state)

1 When a high level is input to the FWE pin

Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and erasing. This bit should be set when setting bits 5 to 0 in FLMCR1, EBR1 bits 7 to 0, and EBR2 bits 3 to 0. When SWE = 1, the flash memory can only be read in program-verify or erase-verify mode.

Rev.6.00 Sep. 27, 2007 Page 802 of 1268 REJ09B0220-0600 Bit 6 SWE [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU [Setting condition] When FWE = 1 and SWE = 1 Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU [Setting condition] When FWE = 1 and SWE = 1 Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV [Setting condition] When FWE = 1 and SWE = 1

Rev.6.00 Sep. 27, 2007 Page 803 of 1268 REJ09B0220-0600 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P [Setting condition] When FWE = 1, SWE = 1, and PSU = 1

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19.14.2 Flash Memory Control Register 2 (FLMCR2)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error- protection state. Bit 7 FLER Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.17.3, Error Protection Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0.

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19.14.3 Erase Block Register 1 (EBR1)

Bit : 7 6 5 4 3 2 1 0 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. The flash memory block configuration is shown in table 19.28.

19.14.4 Erase Block Registers 2 (EBR2)

Bit : 7 6 5 4 3 2 1 0 EBR2 — — — — EB11 EB10 EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — R/W R/W R/W R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). Bits 7 to 4 are reserved: they are always read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.28.

Rev.6.00 Sep. 27, 2007 Page 806 of 1268 REJ09B0220-0600 Table 19.28 Flash Memory Erase Blocks Block (Size) Address EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF EB7 (4 kbytes) H'007000 to H'007FFF EB8 (32 kbytes) H'008000 to H'00FFFF EB9 (64 kbytes) H'010000 to H'01FFFF EB10 (64 kbytes) H'020000 to H'02FFFF EB11 (64 kbytes) H'030000 to H'03FFFF

19.14.5 System Control Register 2 (SYSCR2)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be modified. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.

Rev.6.00 Sep. 27, 2007 Page 807 of 1268 REJ09B0220-0600 Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE (Initial value) Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.

19.14.6 RAM Emulation Register (RAMER)

Bit : 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — R/W R/W R/W R/W RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19.29. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.

Rev.6.00 Sep. 27, 2007 Page 808 of 1268 REJ09B0220-0600 Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS Program/erase-protection of all flash memory blocks is disabled Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM (see table 19.29). Table 19.29 Flash Memory Area Divisions RAM Area Block Name RAMS RAM2 RAM1 RAM0 H'FFDC00 to H'FFEBFF RAM area, 4 kbytes 0 * * * H'000000 to H'000FFF EB0 (4 kbytes) 1 0 0 0 H'001000 to H'001FFF EB1 (4 kbytes) 1 0 0 1 H'002000 to H'002FFF EB2 (4 kbytes) 1 0 1 0 H'003000 to H'003FFF EB3 (4 kbytes) 1 0 1 1 H'004000 to H'004FFF EB4 (4 kbytes) 1 1 0 0 H'005000 to H'005FFF EB5 (4 kbytes) 1 1 0 1 H'006000 to H'006FFF EB6 (4 kbytes) 1 1 1 0 H'007000 to H'007FFF EB7 (4 kbytes) 1 1 1 1 *: Don’t care

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19.15 On-Board Programming Modes

When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.30. For a diagram of the transitions to the various flash memory modes, see figure 19.31. Table 19.30 Setting On-Board Programming Modes Mode Pins MCU Mode CPU Operating Mode FWE MD2 MD1 MD0 Boot mode Advanced expanded mode with on-chip ROM enabled 1 0 1 0 Advanced single-chip mode 1 User program mode* Advanced expanded mode with on-chip ROM enabled 1 1 1 0 Advanced single-chip mode 1 Note: * Normally, user mode should be used. Set the FWE pin to 1 to make a transition to user program mode before performing a program/erase/verify operation.

19.15.1 Boot Mode

When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2328B F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in on- chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19.36, and the boot program mode execution procedure in figure 19.37.

Rev.6.00 Sep. 27, 2007 Page 810 of 1268 REJ09B0220-0600 RxD1 TxD1 SCI1 Chip Flash memory Write data reception Verify data transmission Host On-chip RAM Figure 19.36 System Configuration in Boot Mode

Rev.6.00 Sep. 27, 2007 Page 811 of 1268 REJ09B0220-0600 Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n = 1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM n = N? No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n + 1 → n Figure 19.37 Boot Mode Execution Procedure

Rev.6.00 Sep. 27, 2007 Page 812 of 1268 REJ09B0220-0600 Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2328B F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps. Table 19.31 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Start bit Stop bitD0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19.38 Automatic SCI Bit Rate Adjustment Table 19.31 System Clock Frequencies for which Automatic Adjustment of H8S/2328B F-ZTAT Bit Rate is Possible Host Bit Rate System Clock Frequencies for which Automatic Adjustment of H8S/2328B F-ZTAT Bit Rate is Possible 19,200 bps 16 MHz to 25 MHz 9,600 bps 8 MHz to 25 MHz

Rev.6.00 Sep. 27, 2007 Page 813 of 1268 REJ09B0220-0600 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19.39. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'FFDC00 H'FFE3FF Programming control program area (6 kbytes) H'FFFBFF Boot program area* (2 kbytes) Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19.39 RAM Areas in Boot Mode Notes on Use of Boot Mode

• When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin.
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased.
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.

Rev.6.00 Sep. 27, 2007 Page 814 of 1268 REJ09B0220-0600

• Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
• The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program.
• Initial settings must also be made for the other on-chip registers.
• Boot mode can be entered by making the pin settings shown in table 19.30 and executing a reset-start.
• Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release* 1. Boot mode can also be cleared by a WDT overflow reset.
• Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased*2.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode* Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pins and FWE pin input must satisfy the mode programming setup time (t MDS = 200 ns) with respect to the reset release timing, as shown in figures 19.56 to 19.58. 2. For further information on FWE application and disconnection, see section 19.21, Flash Memory Programming and Erasing Precautions. 3. See section 9, I/O Ports.

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19.15.2 User Program Mode

When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Figure 19.40 shows the procedure for executing the program/erase control program when transferred to on-chip RAM.

Rev.6.00 Sep. 27, 2007 Page 816 of 1268 REJ09B0220-0600 Clear FWE* FWE = high* Branch to flash memory application program Branch to program/erase control program in RAM area Execute program/erase control program (flash memory rewriting) Transfer program/erase control program to RAM MD2, MD1, MD0 = 110, 111 Reset-start Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 19.21, Flash Memory Programming and Erasing Precautions. Figure 19.40 User Program Mode Execution Procedure

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19.16 Programming/Erasing Flash Memory

In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for the on-chip ROM area by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the instruction for programming the flash memory is executed. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.

19.16.1 Program Mode

Follow the procedure shown in the program/program-verify flowchart in figure 19.42 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (x, y, z1, z2, z3, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.

Rev.6.00 Sep. 27, 2007 Page 818 of 1268 REJ09B0220-0600 Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart.

19.16.2 Program-Verify Mode

In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program- verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.41) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1 to 0, and wait again for at least (θ) μs. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits.

Rev.6.00 Sep. 27, 2007 Page 819 of 1268 REJ09B0220-0600 Start End of programming End sub Set SWE bit in FLMCR1 Wait (x) μs n = 1 m = 0 Sub-routine-call See Note 7 for pulse width Note 7: Write Pulse Width Start of programming Sub-routine write pulse Set PSU bit in FLMCR1 Enable WDT Set P bit in FLMCR1 Wait (y) μs Clear P bit in FLMCR1 Wait (z1) μs or (z2) μs or (z3) μs Clear PSU bit in FLMCR1 Wait (α) μs Disable WDT Wait (β) μs Write pulse application subroutine NG NG NG NG NG NG OK OK OK OK OK Wait (γ) μs Wait (ε) μs *6 *6 *5 *6 Set PV bit in FLMCR1 H'FF dummy write to verify address Read verify data Additional program data computation Transfer additional program data to additional program data area Read data = verify data? *3Reprogram data computation Clear PV bit in FLMCR1 Clear SWE bit in FLMCR1 m = 1 128-byte data verification completed? m = 0? 6 ≥ n ? 6 ≥ n ? Increment address Programming failure OK Clear SWE bit in FLMCR1 n ≥ N? Write 128-byte data in RAM reprogram data area consecutively to flash memory Write pulse (z1) μs or (z2) μs Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. RAM Program data area (128 bytes) Reprogram data area (128 bytes) Additional program data area (128 bytes) Store 128-byte program data in program data area and reprogram data area Number of Writes (n) 13... 998 999 1000 Write Time (z) μs z2... Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. 3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data should be provided in RAM. The contents of the reprogram data and additional program data areas are modified as programming proceeds. Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Program Data Operation Chart Transfer reprogram data to reprogram data area n ← n + 1 Note: Use a (z3) µs write pulse for additional programming. Sequentially write 128-byte data in additional program data area in RAM to flash memory Write Pulse (z3) µs additional write pulse Wait (θ) μs Wait (η) μs Wait (θ) μs 5. A write pulse of (z1) or (z2) μs should be applied according to the progress of programming. See Note 7 for the pulse widths. When the additional program data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied. 6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics. Original Data (D) Verify Data (V) Reprogram Data (X) Comments Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed Additional Program Data Operation Chart Reprogram Data (X') Verify Data (V) Additional Program Data (Y) Figure 19.41 Program/Program-Verify Flowchart

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19.16.3 Erase Mode

Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.43. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure.

19.16.4 Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then the ESU bit in FLMCR1 is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of ( γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase- verify sequence is not repeated more than (N) times. When verification is completed, exit erase- verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1 to 0 and wait for at least (θ) μs. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way.

Rev.6.00 Sep. 27, 2007 Page 821 of 1268 REJ09B0220-0600 End of erasing Start Set SWE bit in FLMCR1 Set ESU bit in FLMCR1 Set E bit in FLMCR1 Wait (x) μs Wait (y) μs n = 1 Set EBR1, EBR2 Enable WDT Wait (z) ms *2 Wait (α) μs *2 Wait (β) μs *2 Wait (γ) μs Set block start address to verify address Wait (ε) μs *2 Wait (η) μs Start of erase Clear E bit in FLMCR1 Clear ESU bit in FLMCR1 Set EV bit in FLMCR1 H'FF dummy write to verify address Read verify data Clear EV bit in FLMCR1 Wait (η) μs Clear EV bit in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT Halt erase Verify data = all 1? Last address of block? End of erasing of all erase blocks? Erase failure Clear SWE bit in FLMCR1 n ≥ N? NG NG NG NG OK OK OK OK n ← n + 1 Increment address Notes: 1. Prewriting (setting erase block data to all 0) is not necessary. 2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in the section 22.2.6, Flash Memory Characteristics. 3. Verify data is read in 16-bit (W) units. 4. Set only one bit in EBR1or EBR2. More than one bit cannot be set. 5. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Wait (θ) μs Wait ( θ) μs Figure 19.42 Erase/Erase-Verify Flowchart

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19.17 Flash Memory Protection

There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection.

19.17.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.10). Table 19.32 Hardware Protection Functions Item Description Program Erase FWE pin protection • When a low level is input to the FWE pin, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. Yes Yes Reset/standby protection

• In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered.
• In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in section 22.2.3, AC Characteristics. Yes Yes

19.17.2 Software Protection

Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode (see table 19.33).

Rev.6.00 Sep. 27, 2007 Page 823 of 1268 REJ09B0220-0600 Table 19.33 Software Protection Functions Item Description Program Erase SWE bit protection • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks

• (Execute in on-chip RAM or external memory.) Yes Yes Block specification protection
• Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2).
• Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. — Yes Emulation protection • Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Yes Yes

19.17.3 Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows:

• When flash memory is read during programming/erasing (including a vector read or instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby) is executed during programming/erasing
• When a bus master other than the CPU (the DMAC or DTC) has control of the bus during programming/erasing

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19.18 Flash Memory Emulation in RAM

19.18.1 Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.44 shows an example of emulation of real-time flash memory programming. Start of emulation program End of emulation program Tuning OK? Yes No Set RAMER Write tuning data to overlap RAM Execute application program Clear RAMER Write to flash memory emulation block Figure 19.44 Flowchart for Flash Memory Emulation in RAM

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19.18.2 RAM Overlap

An example in which flash memory block area EB1 is overlapped is shown below. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'3FFFF Flash memory EB8 to EB11 This area can be accessed from both the RAM area and flash memory area EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FFDC00 H'FFEBFF H'FFFBFF On-chip RAM Figure 19.45 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1. Set bits RAMS, RAM2, RAM1, and RAM0 in RAMER to 1, 0, 0, 1, to overlap part of RAM onto the area (EB1) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0.

Rev.6.00 Sep. 27, 2007 Page 827 of 1268 REJ09B0220-0600 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM.

19.19 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests, including NMI, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. The NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons:

• If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly.

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19.20 Flash Memory PROM Mode

19.20.1 PROM Mode Setting

Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19.34 shows PROM mode pin settings. Table 19.34 PROM Mode Pin Settings Pin Names Settings/External Circuit Connection Mode pins: MD2, MD1, MD0 Low-level input Mode setting pins: P66, P65, P64 High-level input to P66, low-level input to P65 and P64 FWE pin High-level input (in auto-program and auto-erase modes) STBY pin High-level input (do not select hardware standby mode) RES pin Reset circuit XTAL, EXTAL pins Oscillator circuit Other pins requiring setting: P32, P25 High-level input to P32, low-level input to P25

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19.20.2 Socket Adapters and Memory Map

In PROM mode, a socket adapter is connected to the chip as shown in figure 19.47. Figure 19.46 shows the on-chip ROM memory map and figure 19.47 shows the socket adapter pin assignments. H'00000000 MCU mode address PROM mode address H'0003FFFF H'00000 H'3FFFF On-chip ROM space 256 kbytes Figure 19.46 Memory Map in PROM Mode

Rev.6.00 Sep. 27, 2007 Page 830 of 1268 REJ09B0220-0600 H8S/2328B F-ZTAT Socket Adapter (40-Pin Conversion)TFP-120 Pin Name A A10 A11 A12 A13 A14 A15 A16 A17 A18 D10 D11 D12 D13 D14 D15 CE OE WE FWE HN27C4096HG (40 Pins) Pin No. Pin Name 1, 40 11, 30 5, 6, 7 A A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 FP-128B RES XTAL EXTAL NC (OPEN) 75, 76, 81, 93, 94 47, 59, 66, 79, 103, 104, 113, 114, 115 83, 84, 89, 103, 104 100, 113, 114, 123, 124, 125 V CC VSS Reset circuit Oscillation circuit Legend: FWE: Flash write enable I/O 7 to I/O0: Data input/output A18 to A0: Address input CE: Chip enable OE: Output enable WE: Write enable Notes: This figure shows pin assignments, and does not show the entire socket adapter circuit. 1. A reset oscillation stabilization time (t osc1) of at least 10 ms is required. 2. A 12 MHz crystal resonator should be used. Other pins Figure 19.47 H8S/2328B F-ZTAT Socket Adapter Pin Assignments

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19.20.3 PROM Mode Operation

Table 19.35 shows how the different operating modes are set when using PROM mode, and table 19.36 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19.35 Settings for Each Operating Mode in PROM Mode Pin Names Mode FWE CE OE WE I/O7 to I/O0 A 18 to A0 Read H or L L L H Data output Ain Output disable H or L L H H Hi-Z X Command write H or L *3 L H L Data input Ain *2 Chip disable*1 H or L H X X Hi-Z X Legend: H: High level L: Low level Hi-Z: High impedance X: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin.

Rev.6.00 Sep. 27, 2007 Page 832 of 1268 REJ09B0220-0600 Table 19.36 PROM Mode Commands Number 1st Cycle 2nd Cycle Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write PA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Legend: RA: Read address PA: Program address Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n).

19.20.4 Memory Read Mode

• After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed.
• Command writes can be performed in memory read mode, just as in the command wait state.
• Once memory read mode has been entered, consecutive reads can be performed.
• After power-on, memory read mode is entered.

Rev.6.00 Sep. 27, 2007 Page 833 of 1268 REJ09B0220-0600 Table 19.37 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 Data H'00 OE WE Command write twep tceh tdh tds tf tr tnxtc Note: Data is latched at the rising edge of WE. tces Memory read mode Address stable Data Figure 19.48 Memory Read Mode Timing Waveforms after Command Write

Rev.6.00 Sep. 27, 2007 Page 834 of 1268 REJ09B0220-0600 Table 19.38 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 I/O7 to I/O0 OE WE Other mode command write tceh tds tdh tf tr tnxtc Note: Do not enable WE and OE at the same time. tces twep Memory read mode Address stable Figure 19.49 Timing Waveforms when Entering Another Mode from Memory Read Mode

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19.20.5 Auto-Program Mode

• In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed.
• A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
• The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
• Memory address transfer is executed in the second cycle (figure 19.52). Do not perform transfer later than the second cycle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming operations cannot be carried out on address blocks that have already been programmed.
• Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-program operation).
• Status polling I/O6 and I/O7 information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE.

Rev.6.00 Sep. 27, 2007 Page 837 of 1268 REJ09B0220-0600 AC Characteristics Table 19.40 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t wsts 1 — ms Status polling access time t spa — 150 ns Address setup time t as 0 — ns Address hold time t ah 60 — ns Memory write time t write 1 3000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns Write setup time t pns 100 — ns Write end setup time t pnh 100 — ns

Rev.6.00 Sep. 27, 2007 Page 838 of 1268 REJ09B0220-0600 Address stable CE FWE A18 to A0 I/O5 to I/O0 I/O6 I/O7 OE WE tas tah tdhtds tf tr twep twsts twrite tspa tpns tpnh tnxtc tnxtctcehtces Programming operation end identification signal Data transfer 1 byte to 128 bytes H'40 H'00 Programming normal end identification signal Figure 19.52 Auto-Program Mode Timing Waveforms

19.20.6 Auto-Erase Mode

• Auto-erase mode supports only total memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto- erase operation).
• Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE.

Rev.6.00 Sep. 27, 2007 Page 839 of 1268 REJ09B0220-0600 AC Characteristics Table 19.41 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t ests 1 — ms Status polling access time t spa — 150 ns Memory erase time t erase 100 40000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns Erase setup time t ens 100 — ns Erase end setup time t enh 100 — ns CE FWE A18 to A0 I/O5 to I/O0 I/O6 I/O7 OE WE tests terase tspa tdhtds tf tr twep tens tenh tnxtc tnxtctcehtces Erase end identifi- cation signal Erase normal end confirmation signal H'20 H'20 H'00 Figure 19.53 Auto-Erase Mode Timing Waveforms

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19.20.7 Status Read Mode

• Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
• The return code is retained until a command write for other than status read mode is performed. Table 19.42 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns OE output delay time t oe — 150 ns Disable delay time t df — 100 ns CE output delay time t ce — 150 ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 I/O7 to I/O0 OE WE tdh tdftds tf tr twep tnxtc tnxtc tf tr twep tds tdh tnxtctceh tceh toe tces tces tce H'71 H'71 Note: I/O3 and I/O2 are undefined. Figure 19.54 Status Read Mode Timing Waveforms

Rev.6.00 Sep. 27, 2007 Page 841 of 1268 REJ09B0220-0600 Table 19.43 Status Read Mode Return Commands Pin Name I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 Attribute Normal end identification Command error Program- ming error Erase error — — Program- ming or erase count exceeded Effective address error Initial value 0 0 0 0 0 0 0 0 Indications Normal end: 0 Abnormal end: 1 Command error: 1 Otherwise: 0 Program- ming error: 1 Otherwise: 0 Erase error: 1 Otherwise: 0 — — Count exceeded: 1 Otherwise: 0 Effective address error: 1 Otherwise: 0 Note: I/O 3 and I/O2 are undefined.

19.20.8 Status Polling

• The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode.
• The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19.44 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End Normal End I/O 7 0 1 0 1 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0

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19.20.9 PROM Mode Transition Time

Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Table 19.45 Command Wait State Transition Time Specifications Item Symbol Min Max Unit Standby release (oscillation stabilization time) tosc1 30 — ms PROM mode setup time t bmv 10 — ms VCC hold time t dwn 0 — ms VCC RES FWE Memory read mode Command wait state Command wait state Normal/ abnormal end identification Auto-program mode Auto-erase mode tosc1 tbmv tdwn Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 19.55 Oscillation Stabilization Time, PROM Mode Setup Time, and Power Supply Fall Sequence

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19.20.10 Notes on Memory Programming

• When programming addresses which have previously been programmed, carry out auto- erasing before auto-programming.
• When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be carried out on address blocks that have already been programmed.

19.21 Flash Memory Programming and Erasing Precautions

Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off (see figures 19.56 to 19.58): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. FWE application/disconnection (see figures 19.56 to 19.58): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state.

Rev.6.00 Sep. 27, 2007 Page 844 of 1268 REJ09B0220-0600 The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory:

• Apply FWE when the VCC voltage has stabilized within its rated voltage range.
• Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time).
• In boot mode, apply and disconnect FWE during a reset.
• In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory.
• Do not apply FWE if program runaway has occurred.
• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared.

Rev.6.00 Sep. 27, 2007 Page 845 of 1268 REJ09B0220-0600 Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In on- board programming, perform only one programming operation on a 128-byte programming unit block. In PROM mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors.

Rev.6.00 Sep. 27, 2007 Page 846 of 1268 REJ09B0220-0600 Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) φ VCC FWE tOSC1 Min 0 μs Min 0 μstMDS*3 tMDS*3 MD2 to MD0*1 RES SWE bit SWE set SWE cleared Programming/ erasing possibleWait time: x Wait time: 100 μs Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 22.2.6, Flash Memory Characteristics. 3. Mode programming setup time t MDS (min) = 200 ns Figure 19.56 Power-On/Off Timing (Boot Mode)

Rev.6.00 Sep. 27, 2007 Page 847 of 1268 REJ09B0220-0600 SWE set SWE cleared φ VCC FWE tOSC1 Min 0 μs MD2 to MD0*1 RES SWE bit Programming/ erasing possibleWait time: x Wait time: 100 μs tMDS*3 Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 22.2.6, Flash Memory Characteristics. 3. Mode programming setup time t MDS (min) = 200 ns Figure 19.57 Power-On/Off Timing (User Program Mode)

Rev.6.00 Sep. 27, 2007 Page 848 of 1268 REJ09B0220-0600 Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) φ VCC FWE tOSC1 Min 0 μs tMDS tMDS tMDS*2 tRESW MD2 to MD0 RES SWE bit Mode change*1 Mode change*1 Boot mode User mode User program mode SWE set SWE cleared Programming/erasing possible Wait time: x Wait time: 100 μs Programming/erasing possible Wait time: x Wait time: 100 μs Programming/erasing possible Wait time: x Wait time: 100 μs Programming/erasing possible Wait time: x Wait time: 100 μs User mode User program mode Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time t MDS (min) of 200 ns is necessary with respect to RES clearance timing. 3. See section 22.2.6, Flash Memory Characteristics. Figure 19.58 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode)

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19.22 Overview of Flash Memory (H8S/2326 F-ZTAT)

19.22.1 Features

The H8S/2326 F-ZTAT has 512 kbytes of on-chip flash memory. The features of the flash memory are summarized below.

• Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode
• Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). To erase the entire flash memory, the individual blocks must be erased sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks.
• Programming/erase times The flash memory programming time is 10.0 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 μs (typ.) per byte, and the erase time is 50 ms (typ.).
• Reprogramming capability The flash memory can be reprogrammed minimum 100 times.
• On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: ⎯ Boot mode ⎯ User program mode
• Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host.
• Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time.
• Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations.

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• PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode.

19.22.2 Overview

(512 kbytes) Operating modeEBR1 Internal address bus Internal data bus (16 bits) FWE pin Mode pins EBR2 SYSCR2 FLMCR2 FLMCR1 RAMER Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2: Erase block register 2 RAMER: RAM emulation register SYSCR2: System control register 2 Figure 19.59 Block Diagram of Flash Memory

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19.22.3 Flash Memory Operating Modes

Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a reset- start is executed, the chip enters one of the operating modes shown in figure 19.60. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. Boot mode On-board programming mode User program mode User mode (on-chip ROM enabled) Reset state PROM mode RES = 0 FWE = 1, SWE = 1 FWE = 0 or SWE = 0 Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, MD1 = 0, MD2 = 0, P66 = 1, P65 = 0, P64 = 0 RES = 0 RES = 0 RES = 0 MD1 = 1, MD2 = 1, FWE = 0 FWE = 1, MD1 = 1, MD2 = 0 Figure 19.60 Flash Memory Mode Transitions

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19.22.4 On-Board Programming Modes

• Boot mode Flash memory Chip RAM Host Programming control program SCI Application program (old version) New application program Flash memory Chip RAM Host SCI Application program (old version) Boot program area New application program Flash memory Chip RAM Host SCI Flash memory prewrite-erase Boot program New application program Flash memory Chip Program execution state RAM Host SCI New application program Boot program Programming control program 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Programming control program Boot programBoot program Boot program area Boot program area Programming control program Figure 19.61 Boot Mode

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• User program mode Flash memory Chip Chip RAM Host Programming/ erase control program SCIBoot program New application program Flash memory RAM Host SCI New application program Flash memory RAM Host SCI Flash memory erase Boot program New application program Flash memory Program execution state RAM Host SCIBoot program Boot program FWE assessment program Application program (old version) New application program 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Programming/ erase control program Programming/ erase control program Programming/ erase control program Transfer program Application program (old version) Transfer program FWE assessment program FWE assessment program Transfer program FWE assessment program Transfer program Chip Chip Figure 19.62 User Program Mode (Example)

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19.22.5 Flash Memory Emulation in RAM

Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Application program Execution state Flash memory Emulation block RAM SCI Overlap RAM (emulation is performed on data written in RAM) Figure 19.63 Reading Overlap RAM Data in User Mode and User Program Mode

Rev.6.00 Sep. 27, 2007 Page 855 of 1268 REJ09B0220-0600 Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Application program Flash memory RAM SCI Overlap RAM (programming data)Programming data Programming control program Execution state Figure 19.64 Writing Overlap RAM Data in User Program Mode

19.22.6 Differences between Boot Mode and User Program Mode

Table 19.46 Differnces between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm.

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19.22.7 Block Configuration

On-chip 512-kbyte flash memory is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'07FFFF Address H'000000 512 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 32 kbytes 4 kbytes × 8 Figure 19.65 Flash Memory Block Configuration

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19.22.8 Pin Configuration

The flash memory is controlled by means of the pins shown in tables 19.47. Table 19.47 Flash Memory Pins Pin Name Abbreviation I/O Function Reset RES Input Reset Flash write enable FWE Input Flash program/erase protection by hardware Mode 2 MD2 Input Sets MCU operating mode Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port 64 P64 Input Sets MCU operating mode in PROM mode Port 65 P65 Input Sets MCU operating mode in PROM mode Port 66 P66 Input Sets MCU operating mode in PROM mode Transmit data TxD1 Output Serial transmit data output Receive data RxD1 Input Serial receive data input

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19.22.9 Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 19.48. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.48 Flash Memory Registers Register Name Abbreviation R/W Initial Value Address*1 Flash memory control register 1 FLMCR1 *6 R/W *3 H'00/H'80 *4 H'FFC8 *2 Flash memory control register 2 FLMCR2 *6 R/W *3 H'00 H'FFC9 *2 Erase block register 1 EBR1 *6 R/W *3 H'00 *5 H'FFCA *2 Erase block register 2 EBR2 *6 R/W *3 H'00 *5 H'FFCB *2 System control register 2 SYSCR2 *7 R/W H'00 H'FF42 RAM emulation register RAMER R/W H'00 H'FEDB Notes: 1. Lower 16 bits of the address. 2. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in FLMCR1. 4. When a high level is input to the FWE pin, the initial value is H'80. 5. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, bits EB11 to EB0 are initialized to 0, and if the SWE2 bit is not set, bits EB15 to EB12 are initialized to 0. 6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 7. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be modified.

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19.23 Register Descriptions

19.23.1 Flash Memory Control Register 1 (FLMCR1)

Bit : 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 Initial value : 1/0 0 0 0 0 0 0 0 R/W : R R/W R/W R/W R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE = 1, then setting the EV1 or PV1 bit. Program mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. The initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE1 bit in FLMCR1 are valid only when FWE = 1; writes to the ESU1, PSU1, EV1, and PV1 bits only when FWE = 1 and SWE1 = 1; writes to the E1 bit only when FWE = 1, SWE1 = 1, and ESU1 = 1; and writes to the P1 bit only when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE Bit 6—Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming and erasing for addresses H'000000 to H'03FFFF. This bit should be set when setting bits 5 to 0 in FLMCR1, EBR1 bits 7 to 0, and EBR2 bits 3 to 0. When SWE1 = 1, the flash memory can only be read in program-verify or erase-verify mode.

Rev.6.00 Sep. 27, 2007 Page 860 of 1268 REJ09B0220-0600 Bit 6 SWE1 [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 [Setting condition] When FWE = 1, SWE1 = 1 Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4 PSU1 [Setting condition] When FWE = 1, SWE1 = 1 Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 EV1 [Setting condition] When FWE = 1, SWE1 = 1

Rev.6.00 Sep. 27, 2007 Page 861 of 1268 REJ09B0220-0600 Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 [Setting condition] When FWE = 1, SWE1 = 1 Bit 1—Erase 1 (E1): Selects erase mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1 [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 Bit 0—Program 1 (P1): Selects program mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0 [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1

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19.23.2 Flash Memory Control Register 2 (FLMCR2)

Bit : 7 6 5 4 3 2 1 0 FLER SWE2 ESU2 PSU2 EV2 PV2 E2 P2 Initial value : 0 0 0 0 0 0 0 0 R/W : R R/W R/W R/W R/W R/W R/W R/W FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 when FWE = 1, then setting the EV2 or PV2 bit. Program mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 when FWE = 1, then setting the PSU2 bit, and finally setting the P2 bit. Erase mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 when FWE = 1, then setting the ESU2 bit, and finally setting the E2 bit. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE2 bit in FLMCR2 are valid only when FWE = 1; writes to the ESU2, PSU2, EV2, and PV2 bits only when FWE = 1 and SWE2 = 1; writes to the E2 bit only when FWE = 1, SWE2 = 1, and ESU2 = 1; and writes to the P2 bit only when FWE = 1, SWE2 = 1, and PSU2 = 1. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error- protection state. Bit 7 FLER Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.26.3, Error Protection

Rev.6.00 Sep. 27, 2007 Page 863 of 1268 REJ09B0220-0600 Bit 6—Software Write Enable Bit 2 (SWE2): Enables or disables flash memory programming and erasing for addresses H'040000 to H'07FFFF. This bit should be set when setting bits 5 to 0 in FLMCR2, and EBR2 bits 7 to 4. When SWE2 = 1, the flash memory can only be read in program-verify or erase-verify mode. Bit 6 SWE2 [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit 2 (ESU2): Prepares for a transition to erase mode for addresses H'040000 to H'07FFFF. Do not set the SWE2, PSU2, EV2, PV2, E2, or P2 bit at the same time. Bit 5 ESU2 [Setting condition] When FWE = 1, SWE2 = 1 Bit 4—Program Setup Bit 2 (PSU2): Prepares for a transition to program mode for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, EV2, PV2, E2, or P2 bit at the same time. Bit 4 PSU2 [Setting condition] When FWE = 1, SWE2 = 1

Rev.6.00 Sep. 27, 2007 Page 864 of 1268 REJ09B0220-0600 Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3 EV2 [Setting condition] When FWE = 1, SWE2 = 1 Bit 2—Program-Verify 2 (PV2): Selects program-verify mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, EV2, E2, or P2 bit at the same time. Bit 2 PV2 [Setting condition] When FWE = 1, SWE2 = 1 Bit 1—Erase 2 (E2): Selects erase mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, EV2, PV2, or P2 bit at the same time. Bit 1 [Setting condition] When FWE = 1, SWE2 = 1, and ESU2 = 1

Rev.6.00 Sep. 27, 2007 Page 865 of 1268 REJ09B0220-0600 Bit 0—Program 2 (P2): Selects program mode transition or clearing for H'040000 to H'07FFFF. Do not set the SWE2, PSU2, ESU2, EV2, PV2, or E2 bit at the same time. Bit 0 [Setting condition] When FWE = 1, SWE2 = 1, and PSU2 = 1

19.23.3 Erase Block Register 1 (EBR1)

Bit : 7 6 5 4 3 2 1 0 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is being input to the FWE pin, and when the SWE1 bit in FLMCR1 is not set when a high level is being input to the FWE pin. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. The flash memory block configuration is shown in table 19.49

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19.23.4 Erase Block Registers 2 (EBR2)

Bit : 7 6 5 4 3 2 1 0 EBR2 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. Bits 3 to 0 in EBR2 are initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is being input to the FWE pin, and when the SWE1 bit in FLMCR1 is not set when a high level is being input to the FWE pin. Bits 7 to 4 are initialized to 0 when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE2 bit in FLMCR2 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.49.

Rev.6.00 Sep. 27, 2007 Page 867 of 1268 REJ09B0220-0600 Table 19.49 Flash Memory Erase Blocks Block (Size) Address EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF EB7 (4 kbytes) H'007000 to H'007FFF EB8 (32 kbytes) H'008000 to H'00FFFF EB9 (64 kbytes) H'010000 to H'01FFFF EB10 (64 kbytes) H'020000 to H'02FFFF EB11 (64 kbytes) H'030000 to H'03FFFF EB12 (64 kbytes) H'040000 to H'04FFFF EB13 (64 kbytes) H'050000 to H'05FFFF EB14 (64 kbytes) H'060000 to H'06FFFF EB15 (64 kbytes) H'070000 to H'07FFFF

19.23.5 System Control Register 2 (SYSCR2)

Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be modified. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.

Rev.6.00 Sep. 27, 2007 Page 868 of 1268 REJ09B0220-0600 Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE (Initial value) Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.

19.23.6 RAM Emulation Register (RAMER)

Bit : 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — R/W R/W R/W R/W RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19.50. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.

Rev.6.00 Sep. 27, 2007 Page 869 of 1268 REJ09B0220-0600 Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS Program/erase-protection of all flash memory blocks is disabled Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM (see table 19.50). Table 19.50 Flash Memory Area Divisions RAM Area Block Name RAMS RAM2 RAM1 RAM0 H'FFDC00 to H'FFEBFF RAM area, 4 kbytes 0 * * * H'000000 to H'000FFF EB0 (4 kbytes) 1 0 0 0 H'001000 to H'001FFF EB1 (4 kbytes) 1 0 0 1 H'002000 to H'002FFF EB2 (4 kbytes) 1 0 1 0 H'003000 to H'003FFF EB3 (4 kbytes) 1 0 1 1 H'004000 to H'004FFF EB4 (4 kbytes) 1 1 0 0 H'005000 to H'005FFF EB5 (4 kbytes) 1 1 0 1 H'006000 to H'006FFF EB6 (4 kbytes) 1 1 1 0 H'007000 to H'007FFF EB7 (4 kbytes) 1 1 1 1 *: Don’t care

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19.24 On-Board Programming Modes

When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.51. For a diagram of the transitions to the various flash memory modes, see figure 19.59. Table 19.51 Setting On-Board Programming Modes Mode Pins MCU Mode CPU Operating Mode FWE MD2 MD1 MD0 Boot mode Advanced expanded mode with on-chip ROM enabled 1 0 1 0 Advanced single-chip mode 1 User program mode* Advanced expanded mode with on-chip ROM enabled 1 1 1 0 Advanced single-chip mode 1 Note: * Normally, user mode should be used. Set the FWE pin to 1 to make a transition to user program mode before performing a program/erase/verify operation.

19.24.1 Boot Mode

When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2326 F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19.66, and the boot program mode execution procedure in figure 19.67.

Rev.6.00 Sep. 27, 2007 Page 871 of 1268 REJ09B0220-0600 RxD1 TxD1 SCI1 Chip Flash memory Write data reception Verify data transmission Host On-chip RAM Figure 19.66 System Configuration in Boot Mode

Rev.6.00 Sep. 27, 2007 Page 872 of 1268 REJ09B0220-0600 Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n = 1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM n = N? No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n + 1 → n Figure 19.67 Boot Mode Execution Procedure

Rev.6.00 Sep. 27, 2007 Page 873 of 1268 REJ09B0220-0600 Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2326 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps. Table 19.52 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Start bit Stop bitD0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19.68 Automatic SCI Bit Rate Adjustment Table 19.52 System Clock Frequencies for which Automatic Adjustment of H8S/2326 F-ZTAT Bit Rate is Possible Host Bit Rate System Clock Frequency for which Automatic Adjustment of H8S/2326 F-ZTAT Bit Rate is Possible 19,200 bps 16 MHz to 25 MHz 9,600 bps 8 MHz to 25 MHz

Rev.6.00 Sep. 27, 2007 Page 874 of 1268 REJ09B0220-0600 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19.69. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'FFDC00 H'FFE3FF Programming control program area (6 kbytes) H'FFFBFF Boot program area* (2 kbytes) Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19.69 RAM Areas in Boot Mode Notes on Use of Boot Mode

• When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin.
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased.
• Interrupts cannot be used while the flash memory is being programmed or erased.

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• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
• The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. Initial settings must also be made for the other on-chip registers.
• Boot mode can be entered by making the pin settings shown in table 19.51 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pins, and executing reset release* 1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode. Do not make the FWE pin low level while a boot program is executing, or while programming or erasing flash memory *2.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode* Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Input to the mode pins and FWE pin must satisfy the mode programming setup time (tMDS = 200 ns) requirement with regard to the reset release timing, as shown in figures 19.86 to 19.88. 2. Refer to section 19.30, Flash Memory Programming and Erasing Precautions, for precautions regarding applying signals to and releasing the FWE pin. 3. See section 9, I/O Ports.

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19.24.2 User Program Mode

When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board programming of the on-chip flash memory can be carried out by providing ahead of time an on-board FWE control means to supply programming data, and storing a program/erase control program in part of the program area if necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7) and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. While the SWE1 bit is set to 1 to perform programming or erasing for the addresses H'000000 to H'03FFFF, this address area cannot be read. While the SWE2 bit is set to 1 to perform programming or erasing for the addresses H'040000 to H'07FFFF, this address area cannot be read. The control program that performs programming and erasing should be run in on-chip RAM or flash memory except for the above address areas. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Figure 19.70 shows the procedure for executing the program/erase control program when transferred to on-chip RAM.

Rev.6.00 Sep. 27, 2007 Page 877 of 1268 REJ09B0220-0600 Execute programming/erase control program (flash memory rewriting) Branch to programming/erase control program in RAM area FWE = high* Transfer programming/erase control program to RAM MD2, MD1, MD0 = 101 or 111 Reset start Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand Clear FWE* Branch to application program in flash memory Notes: Do not apply a constant high level to the FWE pin. A high level should be applied to the FWE pin only when programming or erasing flash memory. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * F or further information on FWE application and disconnection, see section 19.30, Flash Memory Programming and Erasing Precautions. Figure 19.70 Example of User Program Mode Execution Procedure

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19.25 Programming/Erasing Flash Memory

In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for addresses H'000000 to H'03FFFF by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1, and for addresses H'040000 to H'07FFFF by setting the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM, external memory, or flash memory except for the above address areas. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the instruction for programming the flash memory is executed. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 bits in FLMCR1 or setting/resetting of the SWE2, ESU2, PSU2, EV2, PV2, E2, and P2 bits in FLMCR2 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing is not performed when FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 4. Do not program addresses H' 000000 to H'03FFFF and H'040000 to H'07FFFF simultaneously. Operation is not guaranteed when programming is performed simultaneously.

19.25.1 Program Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses

H'040000 to H'07FFFF) Follow the procedure shown in the program/program-verify flowchart in figure 19.70 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (x, y, z1, z2, z3 α, ß, γ, ε, η, and θ) after bits are set or cleared in flash memory control register n (FLMCRn) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics.

Rev.6.00 Sep. 27, 2007 Page 879 of 1268 REJ09B0220-0600 Following the elapse of (x) µs or more after the SWEn bit is set to 1 in flash memory control register n (FLMCRn), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the Pn bit in FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart.

19.25.2 Program-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for

addresses H'040000 to H'07FFFF) In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the Pn bit in FLMCRn is cleared to 0, then the PSUn bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program-verify mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least ( ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.70) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode and wait for at least (η) µs, then clear the SWEn bit in FLMCRn to 0, and wait again for at least ( θ) μs. If reprogramming is necessary, set program mode again, and repeat the program/program- verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits.

Rev.6.00 Sep. 27, 2007 Page 880 of 1268 REJ09B0220-0600 Start End of programming End sub Set SWE1 (2) bit in FLMCR1 (2) Wait (x) μs n = 1 m = 0 Sub-routine-call See Note 7 for pulse width Note 7: Write Pulse Width Start of programming Sub-routine write pulse Set PSU1 (2) bit in FLMCR1 (2) Enable WDT Set P1 (2) bit in FLMCR1 (2) Wait (y) μs Clear P1 (2) bit in FLMCR1 (2) Wait (z1) μs or (z2) μs or (z3) μs Clear PSU1 (2) bit in FLMCR1 (2) Wait (α) μs Disable WDT Wait (β) μs Write pulse application subroutine NG NG NG NG NG NG OK OK OK OK OK Wait (γ) μs Wait (ε) μs *6 *6 *5 *6 Set PV1 (2) bit in FLMCR1 (2) H'FF dummy write to verify address Read verify data Additional program data computation Transfer additional program data to additional program data area Read data = verify data? *3Reprogram data computation Clear PV1 (2) bit in FLMCR1 (2) Clear SWE1 (2) bit in FLMCR1 (2) m = 1 128-byte data verification completed? m = 0? 6 ≥ n ? 6 ≥ n ? Increment address Programming failure OK Clear SWE1 (2) bit in FLMCR1 (2) n ≥ N? Write 128-byte data in RAM reprogram data area consecutively to flash memory Write pulse (z1) μs or (z2) μs Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. RAM Program data area (128 bytes) Reprogram data area (128 bytes) Additional program data area (128 bytes) Store 128-byte program data in program data area and reprogram data area Number of Writes (n) 13... 998 999 1000 Write Time (z) μs z2... Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. 3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data should be provided in RAM. The contents of the reprogram data and additional program data areas are modified as programming proceeds. Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Program Data Operation Chart Transfer reprogram data to reprogram data area n ← n + 1 Note: Use a (z3) µs write pulse for additional programming. Sequentially write 128-byte data in additional program data area in RAM to flash memory Write Pulse (z3) µs additional write pulse Wait (θ) μs Wait (η) μs Wait (θ) μs 5. A write pulse of (z1) or (z2) μs should be applied according to the progress of programming. See Note 7 for the pulse widths. When the additional program data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied. 6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics. Original Data (D) Verify Data (V) Reprogram Data (X) Comments Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed Additional Program Data Operation Chart Reprogram Data (X') Verify Data (V) Additional Program Data (Y) Figure 19.71 Program/Program-Verify Flowchart

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19.25.3 Erase Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses

H'040000 to H'07FFFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.71. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register n (FLMCRn) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWEn bit to 1 in flash memory control register n (FLMCRn). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESUn bit in FLMCRn, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the En bit in FLMCRn. The time during which the En bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure.

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19.25.4 Erase-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for

addresses H'040000 to H'07FFFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared to 0, then the ESUn bit in FLMCRn is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EVn bit in FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of ( γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase- verify sequence is not repeated more than (N) times. When verification is completed, exit erase- verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWEn bit in FLMCRn to 0 and wait for at least (θ) μs. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way.

Rev.6.00 Sep. 27, 2007 Page 883 of 1268 REJ09B0220-0600 End of erasing Start Set SWE1 (2) bit in FLMCR1 (2) Set ESU1 (2) bit in FLMCR1 (2) Set E1 (2) bit in FLMCR1 (2) Wait (x) μs Wait (y) μs n = 1 Set EBR1, EBR2 Enable WDT Wait (z) ms *2 Wait (α) μs *2 Wait (β) μs *2 Wait (γ) μs Set block start address to verify address Wait (ε) μs *2 Wait (η) μs Start of erase Clear E1 (2) bit in FLMCR1(2) Clear ESU1 (2) bit in FLMCR1 (2) Set EV1 (2) bit in FLMCR1 (2) H'FF dummy write to verify address Read verify data Clear EV1 (2) bit in FLMCR1 (2) Wait (η) μs Clear EV1 (2) bit in FLMCR1 (2) Clear SWE1 (2) bit in FLMCR1 (2) Disable WDT Halt erase Verify data = all 1? Last address of block? End of erasing of all erase blocks? Erase failure Clear SWE1 (2) bit in FLMCR1 (2) n ≥ N? NG NG NG NG OK OK OK OK n ← n + 1 Increment address Notes: 1. Prewriting (setting erase block data to all 0) is not necessary. 2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in the section 22.2.6, Flash Memory Characteristics. 3. Verify data is read in 16-bit (W) units. 4. Set only one bit in EBR1or EBR2. More than one bit cannot be set. 5. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Wait (θ) μs Wait ( θ) μs Figure 19.72 Erase/Erase-Verify Flowchart

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19.26 Flash Memory Protection

There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection.

19.26.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.53). Table 19.53 Hardware Protection Functions Item Description Program Erase FWE pin protection • When a low level is input to the FWE pin, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized and the program/erase protected state is entered. Yes Yes Reset/standby protection

• In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered.
• In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in section 22.2.3, AC Characteristics. Yes Yes

19.26.2 Software Protection

Software protection can be implemented by setting the SWE1 bit in flash memory control register 1 (FLMCR1), SWE2 bit in FLMCR2 erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in FLMCR1, or the P2 or E2 bit in FLMCR2 does not cause a transition to program mode or erase mode (see table 19.54).

Rev.6.00 Sep. 27, 2007 Page 885 of 1268 REJ09B0220-0600 Table 19.54 Software Protection Functions Item Description Program Erase SWE bit protection • Clearing the SWE1 bit to 0 in FLMCR1 sets the program/erase-protected state for area H'000000 to H'03FFFF (Execute in on-chip RAM, external memory, or addresses H'040000 to H'07FFFF)

• Clearing the SWE2 bit to 0 in FLMCR2 sets the program/erase-protected state for area H'040000 to H'07FFFF (Execute in on-chip RAM, external memory, or addresses H'000000 to H'03FFFF) Yes Yes Block specification protection
• Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2).
• Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. — Yes Emulation protection • Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Yes Yes

19.26.3 Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, P2, E1, or E2 bit. However, PV1, PV2, EV1, and EV2 bit setting is enabled, and a transition can be made to verify mode.

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19.27 Flash Memory Emulation in RAM

19.27.1 Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.74 shows an example of emulation of real-time flash memory programming. Start of emulation program End of emulation program Tuning OK? Yes No Set RAMER Write tuning data to overlap RAM Execute application program Clear RAMER Write to flash memory emulation block Figure 19.74 Flowchart for Flash Memory Emulation in RAM

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19.27.2 RAM Overlap

An example in which flash memory block area EB1 is overlapped is shown below. H'000000 H'001000 H'002000 H'030000 H'004000 H'005000 H'006000 H'007000 H'008000 H'07FFFF Flash memory EB8 to EB15 This area can be accessed from both the RAM area and flash memory area EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FFDC00 H'FFEBFF H'FFFBFF On-chip RAM Figure 19.75 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1. Set bits RAMS, RAM2, RAM1, and RAM0 in RAMER to 1, 0, 0, 1, to overlap part of RAM onto the area (EB1) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or setting

Rev.6.00 Sep. 27, 2007 Page 889 of 1268 REJ09B0220-0600 the P2 or E2 bit in FLMCR2 will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM.

19.28 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1, or the P2 or E2 bit is set in FLMCR2), and while the boot program is executing in boot mode* 1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. The NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in FLMCR1, or the P2 or E2 bit remains set in FLMCR2. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons:

• If flash memory is read while being programmed or erased (while the P1 or E1 bit is set in FLMCR1, or the P2 or E2 bit is set in FLMCR2.), correct read data will not be obtained (undetermined values will be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly.

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19.29 Flash Memory PROM Mode

19.29.1 PROM Mode Setting

Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19.55 shows PROM mode pin settings. Table 19.55 PROM Mode Pin Settings Pin Names Settings/External Circuit Connection Mode pins: MD2, MD1, MD0 Low-level input Mode setting pins: P66, P65, P64 High-level input to P66, low-level input to P65 and P64 FWE pin High-level input (in auto-program and auto-erase modes) STBY pin High-level input (do not select hardware standby mode) RES pin Reset circuit XTAL, EXTAL pins Oscillator circuit Other pins requiring setting: P32, P25 High-level input to P32, low-level input to P25

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19.29.2 Socket Adapters and Memory Map

In PROM mode, a socket adapter is connected to the chip as shown in figure 19.77. Figure 19.76 shows the on-chip ROM memory map and figure 19.77 shows the socket adapter pin assignments. H'00000000 MCU mode address PROM mode address H'0007FFFF H'00000 H'7FFFF On-chip ROM space 512 kbytes Figure 19.76 Memory Map in PROM Mode

Rev.6.00 Sep. 27, 2007 Page 892 of 1268 REJ09B0220-0600 H8S/2326 F-ZTAT Socket Adapter (40-Pin Conversion)TFP-120 Pin Name A A10 A11 A12 A13 A14 A15 A16 A17 A18 D10 D11 D12 D13 D14 D15 CE OE WE FWE HN27C4096HG (40 Pins) Pin No. Pin Name 1, 40 11, 30 5, 6, 7 A A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 FP-128B RES XTAL EXTAL NC (OPEN) 75, 76, 81, 93, 94 47, 59, 66, 79, 103, 104, 113, 114, 115 83, 84, 89, 103, 104 100, 113, 114, 123, 124, 125 V CC VSS Reset circuit Oscillation circuit Legend: FWE: Flash write enable I/O7 to I/O0: Data input/output A18 to A0: Address input CE: Chip enable OE: Output enable WE: Write enable Notes: This figure shows pin assignments, and does not show the entire socket adapter circuit. 1. A reset oscillation stabilization time (t osc1) of at least 10 ms is required. 2. A 12 MHz crystal resonator should be used. Other pins Figure 19.77 H8S/2326 F-ZTAT Socket Adapter Pin Assignments

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19.29.3 PROM Mode Operation

Table 19.56 shows how the different operating modes are set when using PROM mode, and table 19.57 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19.56 Settings for Each Operating Mode in PROM Mode Pin Names Mode FWE CE OE WE I/O7 to I/O0 A 18 to A0 Read H or L L L H Data output Ain Output disable H or L L H H Hi-Z X Command write H or L *3 L H L Data input Ain *2 Chip disable*1 H or L H X X Hi-Z X Legend: H: High level L: Low level Hi-Z: High impedance X: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin.

Rev.6.00 Sep. 27, 2007 Page 894 of 1268 REJ09B0220-0600 Table 19.57 PROM Mode Commands Number 1st Cycle 2nd Cycle Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write PA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Legend: RA: Read address PA: Program address Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n).

19.29.4 Memory Read Mode

• After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed.
• Command writes can be performed in memory read mode, just as in the command wait state.
• Once memory read mode has been entered, consecutive reads can be performed.
• After power-on, memory read mode is entered.

Rev.6.00 Sep. 27, 2007 Page 895 of 1268 REJ09B0220-0600 Table 19.58 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 Data H'00 OE WE Command write twep tceh tdh tds tf tr tnxtc Note: Data is latched at the rising edge of WE. tces Memory read mode Address stable Data Figure 19.78 Memory Read Mode Timing Waveforms after Command Write

Rev.6.00 Sep. 27, 2007 Page 896 of 1268 REJ09B0220-0600 Table 19.59 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 I/O7 to I/O0 OE WE Other mode command write tceh tds tdh tf tr tnxtc Note: Do not enable WE and OE at the same time. tces twep Memory read mode Address stable Figure 19.79 Timing Waveforms when Entering Another Mode from Memory Read Mode

Rev.6.00 Sep. 27, 2007 Page 898 of 1268 REJ09B0220-0600

19.29.5 Auto-Program Mode

• In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed.
• A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
• The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
• Memory address transfer is executed in the second cycle (figure 19.82). Do not perform transfer later than the second cycle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming operations cannot be carried out on address blocks that have already been programmed.
• Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-program operation).
• Status polling I/O6 and I/O7 information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE.

Rev.6.00 Sep. 27, 2007 Page 899 of 1268 REJ09B0220-0600 AC Characteristics Table 19.61 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t wsts 1 — ms Status polling access time t spa — 150 ns Address setup time t as 0 — ns Address hold time t ah 60 — ns Memory write time t write 1 3000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns Write setup time t pns 100 — ns Write end setup time t pnh 100 — ns

Rev.6.00 Sep. 27, 2007 Page 900 of 1268 REJ09B0220-0600 Address stable CE FWE A18 to A0 I/O5 to I/O0 I/O6 I/O7 OE WE tas tah tdhtds tf tr twep twsts twrite tspa tpns tpnh tnxtc tnxtctcehtces Programming operation end identification signal Data transfer 1 byte to 128 bytes H'40 H'00 Programming normal end identification signal Figure 19.82 Auto-Program Mode Timing Waveforms

19.29.6 Auto-Erase Mode

• Auto-erase mode supports only total memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation).
• Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE.

Rev.6.00 Sep. 27, 2007 Page 901 of 1268 REJ09B0220-0600 AC Characteristics Table 19.62 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t ests 1 — ms Status polling access time t spa — 150 ns Memory erase time t erase 100 40000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns Erase setup time t ens 100 — ns Erase end setup time t enh 100 — ns

Rev.6.00 Sep. 27, 2007 Page 902 of 1268 REJ09B0220-0600 CE FWE A18 to A0 I/O5 to I/O0 I/O6 I/O7 OE WE tests terase tspa tdhtds tf tr twep tens tenh tnxtc tnxtctcehtces Erase end identifi- cation signal Erase normal end confirmation signal H'20 H'20 H'00 Figure 19.83 Auto-Erase Mode Timing Waveforms

19.29.7 Status Read Mode

• Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
• The return code is retained until a command write for other than status read mode is performed.

Rev.6.00 Sep. 27, 2007 Page 903 of 1268 REJ09B0220-0600 Table 19.63 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns OE output delay time t oe — 150 ns Disable delay time t df — 100 ns CE output delay time t ce — 150 ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A18 to A0 I/O7 to I/O0 OE WE tdh tdftds tf tr twep tnxtc tnxtc tf tr twep tds tdh tnxtctceh tceh toe tces tces tce H'71 H'71 Note: I/O3 and I/O2 are undefined. Figure 19.84 Status Read Mode Timing Waveforms

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