HD-6409 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Converter or Repeater Mode
  • Independent Manchester Encoder and Decoder Operation
  • Static to One Megabit/sec Data Rate Guaranteed
  • Low Bit Error Rate
  • Digital PLL Clock Recovery
  • On Chip Oscillator
  • Low Operating Power: 50mW Typical at +5V
  • Available in 20 Lead Dual-In-Line and 20 Pad LCC Package

Description

The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low power device manufactured using self-aligned sil- icon gate technology. The device is intended for use in serial data communication, and can be operated in either of two modes. In the converter mode, the MED converts Non return-to-Zero code (NRZ) into Manchester code and decodes Manchester code into Nonreturn-to-Zero code. For serial data communication, Manchester code does not have some of the deficiencies inherent in Nonreturn-to-Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high degree of noise immunity. Because the MED converts the most commonly used code (NRZ) to Manchester code, the advantages of using Manchester code are easily realized in a serial data link. In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This mini- mizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of 1MHz requires only 50mW of power. Manchester code is used in magnetic tape recording and in fiber optic communication, and generally is used where data accuracy is imperative. Because it frames blocks of data, the HD-6409 easily interfaces to protocol controllers. Pinouts HD-6409 (CERDIP, PDIP, SOIC) TOP VIEW HD-6409 (CLCC) TOP VIEW

Ordering Information

PKG. NO. PDIP -40 oC to +85oC HD3-6409-9 E20.3 SOIC -40 oC to +85oC HD9P6409-9 M20.3 CERDIP -40 oC to +85oC HD1-6409-9 F20.3 DESC -55 oC to 125oC 5962-9088801MRA F20.3 CLCC -40 oC to +85oC HD4-6409-9 J20.A DESC -55 oC to 125oC 5962-9088801M2A J20.A 1BZI BOI UDI SD/CDS SDO SRST DCLK NVM RST GND VCC BZO SS ECLK BOO CTS MS OX IX CO SD/CDS SDO SRST NVM DCLK UDI BOI BZI VCC BOO RST GND CO IX OX BZO SS ECLK CTS MS 10 11 12 139 321 2 0 1 9 File Number 2951.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

NUMBER TYPE SYMBOL NAME DESCRIPTION 1 I BZl Bipolar Zero Input Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. 2 I BOl Bipolar One Input Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. 3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for data input, UDI must be held low.

4 I/O SD/CDS Serial Data/Com-

In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern.

5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder

clock (DCLK). SDO is forced low when RST is low. 6O SRST SerialReset In the converter mode, SRST followsRST. In the repeater mode, whenRST goes low,SRST goes low and remains low afterRST goes high.SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. 7O NVM Non validManchester A low onNVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low onRST, and remains low afterRST goes high until valid sync pulse followed by two valid Manchester bits is received.

8 O DCLK Decoder Clock The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchro-

nously output received NRZ data (SDO). 9I RST Reset In the converter mode, a low on RST forces SDO, DCLK,NVM, and SRST low. A high onRST enables SDO and DCLK, and forcesSRST high.NVM remains low afterRST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode,RST has the same ef- fect on SDO, DCLK andNVM as in the converter mode. WhenRST goes low, SRST goes low and remains low afterRST goes high.SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received.

10 I GND Ground Ground

11 O C

O Clock Output Buffered output of clock input IX. May be used as clock signal for other peripherals. 12 I I X Clock Input I X is the input for an external clock or, if the internal oscillator is used, IX and OX are used for the connection of the crystal. 13 O O X Clock Drive If the internal oscillator is used, OX and IX are used for the connection of the crys- tal.

14 I MS Mode Select MS must be held low for operation in the converter mode, and high for operation

in the repeater mode.

15 I CTS Clear to Send In the converter mode, a high disables the encoder, forcing outputsBOO, BZO high

and ECLK low. A high to low transition ofCTS initiates transmission of a Command sync pulse. A low onCTS enablesBOO, BZO, and ECLK. In the repeater mode, the function ofCTS is identical to that of the converter mode with the exception that a transition ofCTS does not initiate a synchronization sequence.

16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data

to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop. HD-6409

data to the MED at pin SD/CDS. CTS. Manchester data out is inverted. with incoming data for its clocking. pattern. A data sync is a logically inverted command sync.

17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a

low sets the data rate at 1/16 times the clock frequency.

18 O BZO BipolarZeroOutput BZO and its logical complementBOO are the Manchester data outputs of the en-

coder. The inactive state for these outputs is in the high state. 19 O BOO BipolarOne Out See pin 18. 20) to GND (pin-10) is recommended. FIGURE 1. ENCODER OPERATION

FIGURE 7. MANCHESTER ENCODER UART

Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical) θJA θJC Maximum Junction Temperature ( Lead Tips Only for Surface Mount Packages) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions NOTES: 1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by±2 I X clock cycles (16X mode) or±6 IX clock cycles (32X mode). 3. The maximum zero crossing tolerance is±2 IX clock cycles (16X mode) or±6 IX clock cycles (32 mode) from the nominal. SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS VIH Logical “1” Input Voltage 70% V CC -V V CC = 4.5V VIL Logical “0” Input Voltage - 20% V CC VV CC = 4.5V VIHR Logic “1” Input Voltage (Reset) V CC -0.5 - V V CC = 5.5V VILR Logic “0” Input Voltage (Reset) - GND +0.5 V V CC = 4.5V VIHC Logical “1” Input Voltage (Clock) VCC -0.5 - V V CC = 5.5V VILC Logical “0” Input Voltage (Clock) - GND +0.5 V V CC = 4.5V II Input Leakage Current (Except IX) -1.0 +1.0 µAV IN = VCC or GND, VCC = 5.5V II Input Leakage Current (IX) -20 +20 µAV IN = VCC or GND, VCC = 5.5V IO I/O Leakage Current -10 +10 µAV OUT = VCC or GND, VCC = 5.5V VOH Output HIGH Voltage (All Except OX)V CC -0.4 - V I OH = -2.0mA, VCC = 4.5V (Note 2) VOL Output LOW Voltage (All Except OX) - 0.4 V I OL = +2.0mA, VCC = 4.5V (Note 2) ICCSB Standby Power Supply Current - 100 µAV IN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current - 18.0 mA f = 16.0MHz, V IN = VCC or GND VCC = 5.5V, CL = 50pF FT Functional Test - - - (Note 1) NOTES: 1. Tested as follows: f = 16MHz, VIH = 70% VCC , VIL = 20% VCC , VOH ≥ VCC /2, and VOL ≤ VCC /2, VCC = 4.5V and 5.5V. 2. Interchanging of force and sense conditions is permitted Capacitance TA = +25oC, Frequency = 1MHz SYMBOL PARAMETER TYP UNITS TEST CONDITIONS C IN Input Capacitance 10 pF All measurements are referenced to device GND C OUT Output Capacitance 12 pF HD-6409

SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS fC Clock Frequency - 16 MHz - tC Clock Period 1/f C - sec - t1 Bipolar Pulse Width t C +10 - ns - t3 One-Zero Overlap - t C -10 ns - tCH Clock High Time 20 - ns f = 16.0MHz tCL Clock Low Time 20 - ns f = 16.0MHz tCE1 Serial Data Setup Time 120 - ns - tCE2 Serial Data Hold Time 0 - ns - tCD2 DCLK to SDO,NVM - 40 ns - tR2 ECLK toBZO - 40 ns - tr Output Rise Time (All except Clock) - 50 ns From 1.0V to 3.5V, C L = 50pF, Note 2 tf Output Fall Time (All except Clock) - 50 ns From 3.5V to 1.0V, C L = 50pF, Note 2 tr Clock Output Rise Time - 11 ns From 1.0V to 3.5V, C L = 20pF, Note 2 tf Clock Output Fall Time - 11 ns From 3.5V to 1.0V, C L = 20pF, Note 2 tCE3 ECLK toBZO, BOO 0.5 1.0 DBP Notes 2, 3 tCE4 CTS Low toBZO, BOO Enabled 0.5 1.5 DBP Notes 2, 3 tCE5 CTS Low to ECLK Enabled 10.5 11.5 DBP Notes 2, 3 tCE6 CTS High to ECLK Disabled - 1.0 DBP Notes 2, 3 tCE7 CTS High toBZO, BOO Disabled 1.5 2.5 DBP Notes 2, 3 tCD1 UDI to SDO,NVM 2.5 3.0 DBP Notes 2, 3 tCD3 RST Low to CDLK, SDO,NVM Low 0.5 1.5 DBP Notes 2, 3 tCD4 RST High to DCLK, Enabled 0.5 1.5 DBP Notes 2, 3 tR1 UDI toBZO, BOO 0.5 1.0 DBP Notes 2, 3 tR3 UDI to SDO,NVM 2.5 3.0 DBP Notes 2, 3 NOTES: 1. AC testing as follows: f = 4.0MHz, VIH = 70% VCC , VIL = 20% VCC , Speed Select = 16X, VOH ≥ VCC /2, VOL ≤ VCC /2, VCC = 4.5V and 5.5V. Input rise and fall times driven at 1ns/V, Output load = 50pF . 2. Guaranteed via characteristics at initial device design and after major process and/or design changes, not tested. 3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. HD-6409

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FIGURE 17. REPEATER TIMING FIGURE 18. TEST LOAD CIRCUIT