Microcontroller

HD63B01Y0F

Hitachi Semiconductor

CMOS MCU(MICROCOMPUTER UNIT)

Manufacturer: Hitachi Semiconductor

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HD6301Y0,HDG63A01Y0, HD63B01Y0,HD63C01Y0 CMOS MCU (Microcomputer Unit) The HD6301Y0 is a CMOS 8-bit single-chip microcomputer unianch aatas'a' CPO compte wa ihe Chios bat | HDS3OI¥OP:HDSGAOTYOR. microcomputer HD6301V, 16k bytes of ROM, 256 bytes of RAM, . 53 parallel I/O pins, Serial Communication Interface (SCI) and two timers. : m= FEATURES mY} © Instruction Set Compatible with the HD6301V1 ! © 16k Bytes of ROM, 256 Bytes of RAM © 53 Parallel 1/0 Pins (48 /O Pins, 5 Output Pins) © Parallel Handshake Interface (Port 6) ' © Darlington Transistor Drive (Port 2, 6) bi © 16-Bit Programmable Timer (DP-64S) Input Capture Register x 1 Ce eee oo rcerster 2 HD6301YOF,HD63A01YOF, © 8-Bt Reloadebie Timer HD63B01YOF,HD63CO1YOF External Event Counter Square Wave Generation © Serial Communication Interface (SCI a Asynchronous Mode (8 Transmit Formats, Hardware Parity) a ed Clocked Synchronous Mode al EX © Memory Ready ~ eS

3 Kinds of Memory Ready SIMS

© Halt Lar ® Error Detection (Address Error, Op-code Error! © Interrupt — External 3, Internal 7 (FP-64) © Operation Mode Mode 1; Expanded Mode HD6301YOH, HD63A01YOH, internal ROM Inhibited) HD63B01Y0H, HD63C01YOH Mode 2; Expanded Mode {internal ROM Valid) Mode 3; Single Chip Mode © Maximum 65K Bytes Address Space © Low Power Dissipation Mode Sleep Mode Standby Mode (Hardware Standby, Software Standby) © Minimum Instruction Execution Time — 0.5us (f = 2MHz) © Wide Range of Operation Vee=3 to 5.5V (f=0.1 to 0.5MHz) f=0.1 to 1.0MHz : HD6301YO Vec=5V+10% 4 {=0.1 to 1.5MHz : HD63A01YO “ f=0.1 to 2.0MHz : HD63B01Y0 (FP-64A) £=0.1 to 3.0MHz: HD63CO1YO HD6301YOCP, HD63A01YOCP, HD63B01YOCP,HD63C01YOCP ll PROGRAM DEVELOPMENT SUPPORT TOOLS © Cross assembler and C compiler software for IBM PCs and compatibles © Incircuit emulator for use with BM PCs and compatibles (CP-68) | @HITACHI | 128 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 @ PIN ARRANGEMENT @ HD6301Y0P, HD63A01 YOP, HD63B01 YOP, @ HD6301Y0F, HD63A01YOF, HD63B01Y0F, HD63C01YOP HD63C01YOF Ves Of Kae Eessifs.ececz XxTAL TIP io SEREEREPFFIAEE EXTAL Gy} ka), way [3 Pio Meo [2] EP, re EBPs: Pn con 8 pare Pa Ee] oe _ Pu ilar Ba Pao rel Elen oral Fie, Pn Oy Fe ese Poel Fars, Pn CH cote Pa fl Fars. Po Ga] fe. Pc Ea Pas es Bl fairs Pa EA Po ‘= 3] Pars Ly Eqrs Ps Gal [alps ae Ere na ee of ars: Po Co vss | ars Po Cal Fi) Peo ss HAP. Per Oe) fa) Pe a= Br FEREEEEEEREEE raked Ege. fiiisesidiiie re z Es i (Top View) Pw Ed Fo) Pao Poe Fares Pa Bara Pea Ea Pe Pebd Eau Pub Bg Pa Pes Bo Bay Poo Pu] Eg Pe Po Be Fa Vec (Top View) © HD6301YOCP, HD63A01 YOCP, HD63B01Y0CP, @ HD6301YOH, HD63A01YOH, HD63B01Y0H, HD63C01YOCP HD63C01Y0H Zz =Be zz, ffkEsyo errei ge ZR BSSee so eeeseas Bsskisewv2ece2ds ZGRSSSoF.8 fF FESS SSIEVaS1 co ace ese) Es sles SISIGIEIEIEIEIBIEIBIEIEIGIGIEIE Po O] B) Pe P20 10] (20) Pa at ra| i Pe Pay (1) [59 Pas Pa: fal faa) Pa P22 [i] [58] Pao r. cl a P, Ps] [SAPs a fe) Pa Pull] [5 Pae Po C3) [=] Fa» Pas 3) [55 Pay Pa [3 [35] Per P20 [1g] Sa) nc Pe CI [42] Fie Por 2] [53] Pro Pr Co] [sa] Pas nc [18] [54] Pis Px Co [40] Fie Pso [9] [Si] Piz Pa Bl fsa) Pi Per 0) (50) P13 Pn Ol faa Pe Pea fal 19) Pie Pes Oi] on Pas 2] paris Ps» Bal [2] Pos Pu Bd [aA Pie Pw Gd one Pos 2d {4g} Pir Pos Gs] (a) Ves: Pos Bal 3) vss P. bal tia) Pa, Per Bal [44] Pao

7 EEEEEEEEEEEEEEETS

SERRESEEEEEEAIREGE] Se FF Fi FF Pts isis se Sere ses ae ees egaaE Peers ss F2siddddda (Top View) (Top View) @ HITACHI : Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 © (415) 589-8300 129

a HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 = BLOCK DIAGRAM oc Bie 2 “wot SsHB ae Vss —> n =] 3 3 Prttin ) cs li il im a zz Pse mis} hss oe AG iiitmeas Prix) HH Fla; le 5 Hi! Pf Pall Sle 2 Pr/TR rtm © 15 |. Cf LT 4 [pe errea Pa(Touts) THY | & Pa(Tcin) HY Fi] Paa/De l HL UL ral o Pax/D2 E P33/D: men fe = Pl Pas/Ds L, a Par/D> [se FE [is] Pio/Ao Pii/Ay i - Pu/A. L] S Praha

3 Pis/As

Pso(IROs — Py — Pre/Ae Poi (IRQz ) « Fo 3 Pir/A> aM) «(8 | Fy , Psa HALT) < Pao/Ae PssiOS i ale Par/Aro Pos rm [| ele Pas/Ars Por mean Suaxt ad PalArz AR g pea Peo PualAve Per o|8 Poa zel|o & XS Pes ole Pes. FIs RAM ROM Poe 256Bytes 16kBytes, Por | @HITACHI | 130 Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 i I

—.). eee HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 = ABSOLUTE MAXIMUM RATINGS tem Symbol Unit Supply Voltage Vec —03~+7.0 v Input Voltage Vin =0.3~Vec +0.3 Vv Storage Temperature Tag —55~+150 °C (NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field. But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the normal ‘operation, we recommend Vig, Vout: Vg = (Vin OF Vout) = Vee: @ ELECTRICAL CHARACTERISTICS © DC CHARACTERISTICS (Vcc = 5.0V + 10%, Vgg = OV, Ty = -20 ~ +75°C, unless otherwise noted.) RES, STBY [ Vec-08 [= | Input “High” Voltage EXTAL Vt [ Vecxo7 | — | 484} ov AMR BY Three State 1234 ose Ton = — 200A Vv Output “High” Voltage Von OH ian [24 T= [= | Darlington Drive - Vin = OV, f = 1MHz, Sinouant | WonOpwaten [yw | a0 080 ok | Sleeping (f= imi) [= 18 [30 [ma | “Sleeping (f=2mHz"*) | [3.0 [60 | ma Current Dissipation | Sleeping (F=3wHa"y P= a8 [80 ma Operating f= iMH2"*) [= [70 | 10.0 [ma lee Operating t=1.5MHz") | — [108 | 150 | ma |_ Operating (f= 2MH2"") [= [44.0 [20.0 [ma | “Operating (f= 3MH2"*) [=| 21.0 [0.0 [mA * Vermin = Vee — 1.0V, Vy max = 0.8V (All output terminals are at no load) Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typ. or max. values about Current Dissipations at X MHz operation are decided according to the following formula typ. value (f = X MHz) = typ. value (f = 1MHz) x x max. value (f = X MHz) = max. value (f = 1MHz) x X (both the sleeping and operating) *SCLK 0.6 (-20°C~0°C) @ HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 ¢ (415) 589-8300 131

a © AC CHARACTERISTICS (Vcc = 5.0V + 10%, Vgg = OV, Ta = -20 ~ +75°C, unless otherwise noted.) BUS TIMING ws “ [sr | clon frsx"Pow faa a Tw [omc [ow [me mm Tw [| _ Cyclo Time [ett — | [ose [ = [to [os [= | [oan] = [vo | Enable Fall Time r-[- fs[-|-l/#[-|-le]- |- [= [= Enable Pulse Width “High” Level [aso | — [| — [eo {= | - [eo] -|- [wo] -|- | Enablo Pulse Width “Low” Level" Faso |— | oo [- [= [wm[-|-]w[-]- [es Address, RW Delay Time” [0 | [= [— [ao | [= [oe | = [= Proof | = [fs Data Delay Time [we | toow_| [== [ooo | == [ve [= [= Jeo | = | = Ym | FB, WRaAccressHoigTime” | tae _| fw [-{[-|[« [-|-[;@[-|- | [-|[- [Te FRO, WR Data Hold Time [wa | mie GE ns Data Hold Tine [Read | im _| fe f-l-|e [-{-[el-]-J]e [-[- [= FD, WF Pulse Wiath” [ PWaw_| [aso P— | — | oe [= [= feo [= |= | [= [= |e oss [ta | ee RD, WA Hold Time [tw | (-|-l[#|[-|-|#{[-/-[#]-[- [= {= TR Delay Time ‘oa f= [= [oo |= [= [oo [= [= Peo] = | fo | os TR Heid Time ‘wa fw {-[-[e|-|-[e|-[-]s |-|- [= Perteral Read Aosess Time wo [b= be PL P= fe ee MA Setup Timo® [sof — | — | eo [— [= fae [= [|e | [= [os MR Hold Time wun] ve2 [-]—]o| — [=f [-[- [| - |- [ales E Clock Pulse Width at MA | Pew | (-f-fe]-{-[s[-|-;e{- [- [els Femoreninetew [be] -,,, [-t- =] -|-[=| - [= [@]= |= [|= Processor ConielFaltine | tor | |= |— fro] — [— {wolf ~ [ = [roo] = [| s | os BA Delay Time [tn | Fes | -|—] | — |- [om {- |= [ol | [ra] ss Reset Pulse Wieth [Per | 1s 1-1-2 [-[-fs [-|[-T? |-]- | PERIPHERAL PORT TIMING ‘em eo, an | oe [max] min | we [max | min | wo [max | min | ove [max] YM a ce Delay Time (From Port 1,2.3. | Figs | — | -| 300 | ns Ferpheral Ouran” [485.F || WO | TM isa wos | [mp to pm fae [| ae] = Input Data Set-Up Time| Port 6 us foo) — [— [rool = [- [roo |= | = [ow | = | - [ os =e eee eee | @HITACHI | 132 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 TIMER, SCI TIMING ” Condition [rin [wp [max [min [wp] max | min | we] max | min | we | max] Y™ Tiertiwwrronwan | wr | rx | 20[-|-|29{-|-|2o[-|-[20]-| - [oe Delay Time (Enabie Positive Teeurenevimrouwes | 00 | re | = | = [ow | - | [wo | - | - [wo] - | - [ao [ sci input | Atyne, Mode | [Feo | so] - | - fro [Tro | | - fro TT Tee Clock Cycle eee Sooo feve SCI Transmit Data Delay SCI Receive Data Set-up ‘SCI Receive Data Hold (Clock Sync. Mode) otal Co CT CCT) Width tpwscK ‘Seve Timer a one Gack Gr [ez] |= [eo[- [= |e [-][- [ee] - [ee a oe CY Width ‘PwTCK i Ti 1-2, SCI hi Clock nave | = [= [we] - [fof [fo [- [- [| Timer 1:2, SCI Input Clock Tare [ | =| = [ooo ff = five | - [roo] - [- | [= @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 133

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 ave eee ee ee eee ee a ‘When the falling edge of the input signal is detected at this pin, the current instruction before the acceptance of the request. Unless the CPU eos non-maskable interrupt sequence internally. As the interrupt mask in the condition code register is set, the CPU well as the IRQ mentioned below, the instruction being executed at —_starts an interrupt sequence; if set, the interrupt request will be ig- ‘NMI signal detection will proceed to its compeletion. The interrupt nored. When the sequence starts, the contents of the program mask bit of the condition code register doesn’t affect non-maskable counter, index register, accumulators and condition code register interrupt at all. will be saved onto the stack, then the CPU sets the interrupt mask In response to an NMI interrupt, the contents of the program bit and will not acknowledge the maskable request. During the last counter, index register, accumulators and condition code register cycle, the CPU fetches vectors depicted in Table 1 and transfers will be saved onto the stack. Upon completion of this sequence, a their contents to the program counter and branches to the service vector is fetched from $FFFC and $FFFD to transfer their contents routine. into the program counter and branch to the non-maskable interrupt The CPU uses the external interrupt pins (IRQ, and IRQ,) also service routine. as port pins Pso and P,,, So it provides an enable bit to Bit 0 and 1 of (Note) At reset start, the stack pointer should be initialized on the RAM port 5 control register at $0014. Refer to “RAM/PORT 5 an appropriate memory area and then the falling edge © CONTROL REGISTER” for the details. be input to NMT pin. When one of the internal interrupts, ICI, OCI, TOL, CMI or SIO is generated, the CPU produces internal interrupt signal (IRQs). © Interrupt Request (THO;, IR) IRQ, functions just the same as IRQ, or IRQ, except for its vector These are level-sensitive pins which request an internal interrupt —_address. Fig. 16 shows the block diagram of the interrupt circuit. sequence to the CPU. At interrupt request, the CPU will complete Each Status Register's Interrupt Enable Flag 1"; Enable, "0" ; Disable = fro ; | Condition

1 MASK

IcF =a 1° Debi oo Interrupt iras cw | Souel m Lao | ch Sleep ige Cancel ircuit a swi Figure 16 Interrupt Circuit Block Diagram i @ HITACHI 138 Hitachi America, Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01YO Table 1 Interrupt Vector Memory Map. low-speed memories (See Fig. 2). Up to 9us can be stretched. During internal address space access or nonvalid memory access, MR is prohibited internally to prevent decrease of operation Priority Interrupt speed. Even in the halt state, MR can also stretch “High” period of system clock to allow peripheral devices to access low-speed memo- Highest [ FFFF | RES ties. Refer to “RAM/PORT 5 CONTROL REGISTER” for more FeFD | NMI © Halt (HALT; Pgs) rrFA | FeFB swi This is an input control signal to stop instruction execution and {Software Interrupt) to release buses. When tis Signal switches to “Low”, the CPU stops to enter into the it state after having executed the present [rere | FeFo | TAQ}, ISF (port 6 Input Strobe) instruction. When entering into the halt stale, it makes BA (P,.) rg en “High” and also an address bus, data bus, RD, WR, R/W high (Timer 1 input Capture) impedance. When an interrupt is generated in the halt state, the Oc! ~~ __ CPU uses the interrupt handler after the halt is cancelled. FFFS | Framer 1 Output Compare 1, 2) (Note) Please don’t switch the HALT signal to “Low” when the CPU executes the WAI instruction and is in the in- rer2 | rre3 | TO terrupt wait state to avoid the trouble of the CPU's op- (Timer 1 Overflow) eration after the halt is cancelled. (Timer 2 Counter Match) © Bus Available (BA; P74) This is an output control signal which is normally “Low” but | Feea | FreB | TRO “High’* when the CPU accepts HALT and releases the buses. The Lowest [Fro | SiO HD6800 and HD6802 make BA “High” and release the buses at (RORF +ORFE +TDRE +PER) WAI execution, while the HD6301Y0 doesn’t make BA “High” under the same condition. © Mode Program (MP, MPy) These two pins decide the operation mode. Refer to “MODE PORT SELECTION” for more details. The HD6301Y0 provides seven 1/0 ports. Port 1, 2, 3, 4, 5, and 6 are 8-bit I/O ports. Each port provides Data Direction The following signal descriptions are applicable only for the Register(DDR). Port 1 and port 3 select the I/O state by the byte expanded mode. and port 2, 4, 5 and 6 the I/O state by the bit. Port 7 is a 5-bit out- put-only port. In the expanded mode (mode 1, mode 2), port 3 © Read/Write (R/W; P72} becomes data buses, port I and port 4 address buses and port 7 con- This signal, usually be in read state (“High”), shows whether _trol signal pins. the CPU is in read (“High”) or write (“Low”) state to the peripheral or memory devices. This can drive one TTL load and Table 2 Port end Data Direction Register Address 30pF capacitance. © AD, WA (P20, P21) Port Data Direction Register These signals show active low outputs when the CPU is reading/ Pott | $0002 | $0000 writing to the peripherals or memories. This enables the CPU easy to access the peripheral LSI with RD and WR input pins. These pins Por2 | $0003 | $0001 can drive one TTL toad and 30pF capacitance Port3 $0004 © Load instruction Register (CIR; Py3) Port 4 $0005 This signal shows the instruction opecode being on data bus Pons | soo1s | $0020 (active low). this pin can drive one TTL load and 30pF capacitance. Port 6 $0016 © Memory Ready (MR; P52) Por? This is the input control signal which stretches the system clock’s “High"period to access low-speed memories. HD6301Y0 can select three kinds of low-speed memory access method by RAM/ —@_—Port1 Port 5 Control Register’s MRE bit and AMRE bit. In the case that An 8-bit I/O port. The DDR of port 1 (PIDDR) controls the 1/0 CPU accesses low-speed memories by the external MR signal _ state. It provides a bit which select the I/O state by the byte (‘‘0” for (MRE="1", AMRE="‘0"), the system clock operates in normal _input and “1” for output). sequence when this signal is in “High”. As it is cleared during reset, port t is an input port. But this signal in “Low”, the “High” period of the system clock In the expanded mode (mode 1, mode 2), port 1 functions as a will be stretched depending on its “Low” level duration in integral lower address buses (Ap to A,). Port 1 can drive one TTL load and multiples of the cycle time. This allows the CPU to interface with 90pF capacitance. @HITACHI Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 139

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 ea—— ss ee ee WP1D Mode 1 |, oo Mode 2 RES —R - 3 P1DDR* o g a |3 $ |< Mode 3 2 ls i g |€ ror <] la ° a |z2 Mode 1 Pin DATA 3a |# 2 ols Mode 2 © 8 |: _—— wet = 48 RES: Reset Signal WP1D: DDR Write Signal WP1 : Port Write Signal RP1 _ : Port Read Signal *8 bit Common Register Priority : Set > reset MSB B Port 1 DDR ($0000) PY | (Wate only, bit 0 DOR is cleared during reset) Port 1 ($0002) PEPEPEEE tialized during reset) © Port2 can produce IMA when Voy=1.5V to drive directly the base of An 8-bit I/O port. Port 2 DDR (P2DDR) controls the I/O state. Darlington transistor. This port provides DDR corresponding to each bit and can define input or output by the bit (‘0 for input, “1” for output). P29 (Tin) As Port 2 DDR is cleared during reset, it will be an input port. Pop is also used as an external input pin for the input-capture. Port 2 is also used as an I/O pin for timer 1, Timer 2and the SCI. __This pin is an I/O port which is an input or output as defined by the Pins for Timers and the SCI set or reset each DDR depending on Data Direction Register (P,,DDR) (‘‘0" for an input and ‘*1” for their functions and become I/O pins. When port 2 functions as an I/ an output). Then either a signal to or from Pz» (“‘to” for an output O port afler used as I/O pins of the timers or the SCI, the I/O direc- port, ‘from’ for an input port) is always input to the Timer | input tion of the pins remain as it is used as the 1/O pin of timer and SCI. capture. Port 2 can drive one TTL load and 30pF capacitance. This port RES R ao 3 Pao DDR g c iS P20 DATA = WP2D : DDR Write Signal WP2_ : Port Write Signal RP2__ : Port Read Signal Timer 1 Input Capture Input @HITACHI | 140 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 ¢ (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Pay (Tout 1), Pag (Tx), Pag (Tout 2), P2g (Tout 3) have a register which enables output. By setting these registers, ‘These four pins can be also used as output pins for Timer 1, they automatically will be output pins of timer or the SCI. Timer 2 and a transmit output of the SCI. Timer 1, and the SCI F RES Q sR D P2n DOR 2 c g g D a PorT| <| 3 a i>) 5 " 2a Pan DATA 2 Timer 1, Timer 2 and SCI d c = r EN 1 t ‘Output Enable Signal P22 (SCLK) bie as an I/O port when the SCI has no dock input or output (as an Pay is also used as a clock I/O pin for the SCI. It is selected as a output port if P,, DDR=1, as an input port if Pz; DDR =0). clock input or output pin by the operating mode of the SCI. It is usa- RES k P22 DDR c 3 s P< hitl Th P22 DATA 3 cle ee A z ' 7" Clock Input Enable signat hs en t Clock Output Enable signal . Input Clock @uHITvacuH | Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 141

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Ayo eee eee Pog (Rx), P27 (TCLK) Since the SCI will be a clocked synchronous mode by an external P,; and P,, are also used as received data input pins for the SCI clock-input during reset, the DDR of P,, is cleared automatically and external clock input pins for Timer 2. The SCI and Timer 2 and P,, is an input port. Set the SCI to a mode where P,, is not used have registers which enable input. If the registers are set, the DDR (CCO or CCI of the RMC Register is “0” or ‘*1” respectively) and (P,,DDR, P,,DDR) are cleared and P,; and P,, will be input pin for _—_write “1” to the P,, DDR to make P,, an output port. Rx and TCLK. RES Re £ | g la 0 a Pan DOR 2 c a 2n Pap DATA ~ SCI, Timer 2. __ c '

7 Input Enable signal

. SCI Receive Data, ae 3 — MSB .sB Par | Pas | Pas | P2e| Pza | Paz | P21] P20] PORT2ODRIS00011 por | 0bR | oR | 0dR | DOR | OOR] DDR] DDR} (Write only. $0 during reset.) PORT2 ($0003) Por Pay {R/W, not ini- tialized during reset) © Port 3 During reset, it is cleared and port 3 becomes an input port. An 8-bit 1/0 port. The DDR of port 3 controls the I/O state. It In the expanded modes {Mode 1, Mode 2), port 3 functions as provides only one bit which defines I/O state by the byte ("0" for data buses (D, to D;). Port 3 can drive one TTL load and 90pF input and **1"* for output) capacitance. wP3D RES Cc R Mode 1 Mode 2 >| Data BUS Controle PORT Le | 3 Pan DATA ba zs s |e c = 3 Mode 1 oz Mode 2 we3 BS = gs |e External Address Internal Address| z |? Read, RP3 READ - WP3D_ DDR Waite signal > =F <| WP3 Port Write signal rT NT RP3 Port Read signal 8 bit Common Register i i | @ HITACHI | 142 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300 i

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 MSB 138, poRT3 DDR ($0004) P3 | (Write only, Bit 0 ODR | is cleared during reset) PORTS ($0006) PPPPPEEE tialized during reset) © Ports internal ROM), the DDR is set automatically and outputs An 8-bit I/O port. The DDR of port 4 controls I/O state. Each bit addresses. But in Mode 2 (expanded mode with internal ROM), the of port 4 has a DDR which defines I/O state (‘*0” for input and ‘*1"” DDR is cleared and port 4 becomes an input port during reset. Set for output). the DDR to ‘‘!”’ to output the upper addresses (A, to A,) to the During reset, the DDR of port 4 is cleared and port 4 becomes ‘outside. If not all of the upper addresses have to be output, the pins an input port. which don’t output addresses can be used as input pins. Port 4 can In the expanded modes (Mode 1, Mode 2), port 4 functions as drive one TTL load and 90pF capacitance. address buses (A, to Aj,). In Mode 1 (expanded mode with no Mode 1 RES sR g {a Q oD a |g Pas DDR e |: c s |5 o |g Mode 3 wP4d 3 3 4n Pas DATA s |e c Fy Mode 1 ¢ Mode 2 wea iS al > WP4D : DDR Write signal WP4_ : Port Write signal RP4 —: Port Read signal * Priority : set > reset MSB LsB (Write only, $00 or | oor | DR | DDR | DDR | DOR | DDR] DOR] sine Cry: > PORT4 ($0007) Pll tialized during reset) © Ports Ps. and Py, are also usable as interrupt pins. The RAM/port 5 An 8-bit I/O port. The DDR of port 5 controls I/O state. Each bit control registers of IRQ, and IRQ, have enable bits (IQIE, 1Q2E). of port 5 has a DDR which defines 1/0 state (‘*0" for input and “1” ‘When these bits are set to “1”, Pyo and Ps, will automatically be for output). interrupt input pins. During reset, the DDR of port 5 is cleared and port 5 becomes an input port P52 (MR), Pp (HALT) Port 5 is also usable as IRQ; TRG, ATT, MR and the strobed Pyy and Ps, are also usable as MR and FTALT inputs. MR and signal of port 6 for handshake US, O8). Its set to input or output HALT have enable bits (MRE, HLTE) in the RAM/Port § Control automatically if it is used as these control signal pins (except P5,, Register as TRQ, and TRQ,. In the single chip mode (Mode 3), Ps; IS). Since the DDR of port 5, as is port 2, is set or reset by the con- _—_and Py, are usable as I/O ports regardless of the value of the enable trot signal, I/O directions of the I/O ports are retained after the con-__ bits. In the expanded mode (Mode 1 or Mode 2), since MRE is trol signal is disabled. Port 5 can drive one TTL load and 90pF _ cleared during reset, P,, is usable as an I/O port. Since HLTE is set capacitance. during reset, the DDR of P,» will be automatically reset to be a HALF input pin. HLTE of the RAM/Port 5 Control Register has to Pg0 (IRGy), Pp, ((RG2) be cleared to use Py, as an I/O port. @ HITACHI H Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 ¢ (415) 589-8300 143

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Aare eer ee ee een ee RES R la D Pes DOR iss g a g & —_WPS5D: DDR Write signal PORT lo D % WPS. : Port Write signal Sn Ps, DATA = RP5— : Port Read signal c E RAM PORT

5 Control

Initializing value during reset;

4 Ps2 and Ps3 can be used as | O ports

in spite of the value of this register in Mode 3. Poa (IS) _ an output port (set the DDR of P,, to ‘*1""), an output signal from Ps, is also usable as the input strobe (IS) for port 6 handshake P,, will be the input to TS. interface. This pin, as is Pz», is always an I/O port. If Ps, is used as RES R la D Psa ODR c 3 a S e <q Qa D a Pse DATA FS c 8 E aa Port 6 Control Status Register iS P55 (05) _ by setting the OS enable register (OSE) of the port 6 Control Status Ps. is also usable as the output strobe (OS) for port 6 handshake —_—_—Register (P6CSR) interface. It will be an I/O port during reset, and an OS output pin | @ HITACHI | 144 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 RES [oe Q i>) 8 Pss DDR g c 6 Pp Ss é s [eH < Pont TE PssDATA > c Port 6 Control/Status Register A r ee ee +— OSE ( : OS output ) f 0: OS output disable Pee. Pov Pys and P,, are 1/0 ports. RES R Q@ op Ps, DDR £ g a g cian 2 weil Psq DATA! 3 £ s MSB LsB (Write only, $00 br | 0A | OR | DDR] DDR | DOR] DOR] ODR| Siring casei) PORTS ($0015) [re [ra rs |] ro] re el Pe tialized during reset) © Ports Port 6 controls parallel! handshake interface besides functions as 8-bit I/O port. Port 6 DDR controls I/O state. Each bit of port 6 an I/O port. Therefore, it provides DDRs to control and IS LATCH has a DDR and designates input or output (““0" for input, ‘“1"" for _—t@ latch the input data, output). During reset, Port 6 DDR is cleared and port 6 becomes an Port 6 can drive one TTL load and 30pF capacitance. It can drive input port. directly the base of Darlington transistor as port 2. | @HITACHI i Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 145

— EEE HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 RES Rr la a Pen DDR 2 c i} WP6D r] PORT. s Poo DATA c ‘WP6 RES RPG ‘ WP6D : DDR Write signal p ql WP6_ : Port Write signal 1S LATCH! RP6_ : Port Read signal c Port 6 mse use Control/Status Register Per | Poo | Pos | Pes | Pes | Per Peo | PORTS DDR ($0016) por | poe | Dor | ODR | DDR eal coe por | {ivaite only $20 PORTE ($0017) [ro Jr [rm] ]ro] |r| Si tialized during reset.) © Port? as an output port. CPU 7 can also read the Port 7 data register to ex- ‘A 5-bit output port. In single-chip mode (Mode 3), port 7 goes ecute bit manipulation instruction. In the expanded mode (Mode 1, to a high impedance state during reset. By a write to Port 7, Port 7 Mode 2), Port 7 is an output pin for control signals (RD, WR, R/ goes to the output state from the high impedance state, and it out- W, IR, BA) from the CPU. puts the written data. Once it becomes output state, Port 7 functions Port 7 can drive one TTL load and 30pF capacitance. RES we7 Mode 1,Mode 2 g a Pm DATA 3 c S = WP7: Port Write signal RP7 : Port Read signal Mode 1 > Mode 2

1 Signal

and becomes the MR input pin. In Mode 3, however, the “‘memory ready doesn’t have to operate. Table 3. “Memory Ready” Function 0 | 0 _| “Memory ready” inhibited. longer. This state is retained during reset. 1 | 0 | “Memory ready’ operates by Pg2 (MR) pin. The function is the same as that of the HD6301X0.

1 When the CPU accesses the external address space with the Ps (MR) pin in “low”, the “auto memory

outside. Input CS signal of slow memory” to MR pin. in “low” When Voc is not provided in standby mode, this bit is cleared. the MCU, “1” is set to this bit, and on-chip RAM is enabled. and the on-chip RAM data is valid.

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 (a) MRE=0, AMRE=1 Address Bus —Xsudress X __erterrel aauross OX Sadreas KX __externel_eddress XX intornal_acaross (b) MRE=1, AMRE=1 E { i { H Address Bus —X_sddves_X__sudvess_ XX y_external_odavess KX Sauress iy __extermel_earess a A, (ES pin of “slow memory”) (c) MRE=1,AMRE=0 (HD6301X0 Compatible Mode) Li---4 tenn Address intemal Bus Ksacress X | external earess TX idaress_X_sudioes_ tsmr MR Figure 17 Memory Ready Timing ™ Port 6 Controi/Status Register the input latch remains canceled and this bit functions as a usual This is the Contro/Status Register for parallel handshake inter- 1/0 port. This bit is cleared during reset. face using Port 6. The functions are as follows; 1) Latches input data to Port 6 at the TS (P,,) falling edge. Bit 4: OSS Output Strobe Select 2) Outputs a strobe signal OS (P,,) outward by reading or writ- This register initiates an output strobe (OS) from Ps, by reading ing to port 6. or writing to port 6. When cleared, OS occurs by reading Port 6. 3) When IS FLAG is set at the TS falling edge, an interrupt When set, OS occurs by writing to Port 6. This bit is cleared during occurs. reset. The following shows Port 6 Control/Status Register (P6CSR). Bit 6: OSE Output Strobe Enable This register decides the enabling or disabling of the output 7 6 54 3 2,71 0 strobe. When cleared, P,, functions as an 1/0 port. When set, Py, 1S] ISIRQ, LATCH $0021 functions as an OS output pin. (P,, DDR is set by OSE.) This bit is FLAG] ENABLE ENABLE cleared during reset. _ Bit 6: 1S IRQ, Enable input Strobe Interrupt Enable Bito ‘Bit 7 is Read-Only bit ‘When set, an IRQ, interrupt to the CPU occurs by setting IS Bit1 —_Notused. FLAG of bit 7. When cleared, the interrupt does not occur. This bit Bit2 is cleared during reset. Bit 3: Latch Enable Bit 7: 1S Flag Input Strobe Flag This register controls the input latch for Port 6 (ISLATCH). This flag is set at the IS (P,,) falling edge. This flag is for read- When this bit is set to ‘“1"", the input data to port 6 will be latched only. When set, the flag is cleared by reading or writing to Port 6 inward at the IS (P,,) falling edge. An input latch will be canceled —_after reading the Port 6 Control Status Register. This bit is cleared by reading Port 6, which enables to latch the next data. If cleared, during reset. | @HITACHI i 148 Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

——— eee HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 HD630TYO MSB_ Port 6 Control/Status Register 1S IRQs IS FLAG ENABLE &—[>o D ) > Roh Figure 18 Input Strobe Interrupt block Diagram | MODE SELECTION address externally can be used as the input port Mode program pins, MP, and MP, determine the operation mode of the HD6301Y0 as Table 4 shows. © Mode 3 (Single-chip Mode) In this mode, all ports are available (refer to Fig. 21) © Mode 1 (Expanded Mode) In this mode, port 3 is data bus and port t “ Lower" address bus Table 4 Mode Selection and port 4 ““Upper'’ address bus to interface directly with the HMCS6800 buses. A control signal such as R/W is produced at port 7. In mode 1, on-chip ROM is disabled and 65k bytes of address Mode [ mes jd Interrupt | Operation space are externally expandable (refer to Fig. 19) Vector Mode a Expanded This mode is also expandable as well as mode 1. But in this mode, on-chip ROM is enabled and the expandable address space is 2 bw fey Expanded 48k bytes (refer to Fig. 20). Mode In Mode 2, port 4 is available as an input port during reset, and 3 Singie-chip so the upper address is not output outwards. After reset starts, set Mode the PADDR corresponding to the external address output. By set- ting the DDR, the upper address is output. When a small external “LY = Logic “0”, “H = Logic "1", 1: internal, E; External memory space is provided, the pin not required to output the * The addressing RAM area can be external by clearing RAME bit $0014. ‘© Mode and Port Table 5 shows MCU signals in each mode. Table 5 MCU Signals in Each Mode vee | Port a ee ee Mode 3 Port Address Bus (Ap~Ay) Address Bus (Ag~A7) VO Port Port 3 Data Bus (0p~D7) Data Bus (O9~D,) VO Port Porta Address Bus (Ag~A1s) VO Port or Address Bus (Ag~Ars)__| 1/0 Port Port 5 VO Port VO Port VO Port : Port 7 AD, WA, R/W. LR, BA ‘RD. WR. RW. LR, BA Output Port i @HITACHI ! Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 149

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Table 6 Internal Register ‘i m Initialized vatue

00 Port 1 DDR (Data Direction Register) PIDDR w SFE

o1 Port 2 DDR P2DDR w $00

02 Port 1 PORT1 RW indefinite

03 Port 2 PORT2 RW indefinite

04 Port 3 DDR P30DR w SFE

05 Port 4 DDR P4DDR w $00

06 Port 3 PORT3 RW indefinite

07 Port 4 PORTS RW indefinite

0a Timer Control/Status Register 1 TCSR1 RW $00

09 Free Running Counter (MSB) FRCH RW $00

OA Free Running Counter (LSB) FRCL RW $00 0B Output Compare Register 1 (MSB) OcRiH RW SFF oc Output Compare Register 1 (LSB) OcRiL RW SFE 0D Input Capture Register (MSB) ICRH R $00 OE Input Capture Register (LSB) ICRL R $00 OF Timer Control/Status Register 2 TesR2 RW $10

10 Rate/Mode Control Register AMCR RW sco

n Tx/Rx Control Status Register 1 TRCSR1 RW $20

12 Receive Data Register RDR R $00

13 Transmit Data Register TOR w indefinite

14 RAM/Port 5 Control Register RPSCR RW $F8 or $78

15 Port 5 PORTS RW indefinite

16 Port 6 DDR P6DDR w $00

7 Por 6 PORTS RW indefinite

18 Port 7 PORT? RW indefinite

19 Output Compare Register 2 (MSB) OCR2H RW SFF

1A Output Compare Register 2 (LSB) OcR2L RW SFE 1B Timer Control/Status Register 3 TCSR3 RW $20 1c Time Constant Register TCONR w SFF 1D Timer 2 Up Counter T2CNT RW $00 1E ‘Tx/Rx Control Status Register 2 TRCSR2 RW $28 1€ Test Register” TSTREG - -

20 PORT 5 DDR P5DDR pow $00

21 PORT 6 Control/Status Register P6CSR ; RW $07

22 _ - pom - 23 — - - - 2 = Reserved = z z 26 — - - - 27 = - = - * Register for test. Don't access this register. R: Read-only register, W: Write-only register, R/W: Read/Write register. * When empty bit is in the register, it is set to "1" @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 151

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 read-only which indicate the following timer status. the ICR after the TCSR1 or TCSR2 read at ICF=1. Bit 5 The counter value reached to $0000 as a result of count- ing-up (TOF). © Timer Control/Status Register 2 (TCSR2) {$000F) Bit6 A match has occurred between the FRC and the OCR 1 The timer control/status register 2 is a 7-bit register. All bits are ; (OCFI). readable and the lower 4 bits are also writable. But the upper 3 bits Bit7 Defined transition of the timer input signal causes the are read-only which indicate the following timer status, counter to transfer its data to the ICR (ICF). Bit 5 A match has occurred between the FRC and the OCR2 The followings are the each bit descriptions. (OCF2). Bit 6 The same status flag as the OCFI flag of the TCSR1, bit 6. Timer Control/Status Register 1 Bit 7 The same status flag as the ICF flag of the TCSRI, bit 7. The followings are the each bit descriptions. 7 6 5 4 3 2 1 0 [er] oer] 0" wet ]even ron encfouves] $0008 Timer Control/Status Register 2 7 8 5 4 3 2 +1 ~O PEELE P | Bit 0 OLVL1 Output Level 1 OLVL is transferred to port 2, bit 1 when a match occurs be- tween the counter and the OCR1. If bit 0 of the TCSR2 (OE1) is set to “1”, OLVLI will appear at bit 1 of port 2. BitO _OE1 Output Enable 1 Bit1 _ IEDG input Edge This bit enables the OLVL! to appear at port 2, bit 1 when a This bit determines which edge, rising or falling, of input sig- match has occurred between the counter and the output com- nal of bit 0 of port 2 will trigger data transfer from the counter to pare register 1. When this bit is cleared, bit 1 of port 2 will be an the ICR. For this function, the DDR corresponding to port 2, bit 1/0 port. When set, it will be an output of OLVL1 automatically. 0 should be cleared beforehand. Bit1 —_ OE2 Output Enable 2 IEDG =0, triggered on a falling edge This bit enables the OLVL2 to appear at port 2, bit 5 when a “High” to “Low”) match has occurred between the counter and the output com- IEDG =1, triggered on a rising edge pare register 2. When this bit is cleared, port 2, bit 5 will be an “Low” to “High”) O port. When set, it will be an output of OLVL2 automatically. Bit2 ETO! Enable Timer Overflow interrupt Bit 2 OLVL2 Output Level 2 When this bit is set, an internal interrupt (IRQ,) by TOI inter- OLVL2 is transferred to port 2, bit 5 when a match has occur- rupt is enabled. When cleared, the interrupt is inhibited. red between the counter and the OCR2. If bit 5 of the TCSR2 Bit3 _ EOCI1 Enable Output Compare Interrupt 1 (OE2) is set to “1”, OLVL2 will appear at port 2, bit 5. When this bit is set, an internal interrupt (IRQ,) by OCI Bit3 — EOCI2 Enable Output Compare Interrupt 2 interrupt is enabled. When cleared, the interrupt is inhibited. When this bit is set, an internal interrupt (IRQ,) by OCI2 Bit4 _ EIC! Enable Input Capture Interrupt interrupt is enabled. When cleared, the interrupt is inhibited. When this bit is set, an internal interrupt (IRQ,) by ICI inter- Bit4 —Notused rupt is enabled. When cleared, the interrupt is inhibited. Bit& _ OCF2 Output Compare Flag 2 Bit5 TOF Timer Overflow Flag This read-only bit is set when a match has occurred between This read-only bit is set when the counter increments from the counter and the OCR2. Cleared when writing to the OCR2 SFFFF by 1. Cleared when the counter’s MSB byte ($0009) is ($0019 or SOLA) after the TCSR2 read at OCF2=1. read by the CPU after the TCSR1 read at TOF =1. Bit6 — OCF1 Output Compare Fiag 1 Bit6 OCF1 Output Compare Flag 1 Bit7 _ICF input Capture Flag This read-only bit is set when a match occurs between the OCF and ICF are dual addressed. If which register, TCSR1 OCR) and the FRC. Cleared when writing to the OCR1 ($000B or TCSR2, CPU reads, it can read OCF1 and ICF to bit 6 and bit ‘or $000C) after the TCSR1 or TCSR2 read at OCF =1. 7. Bit? ICF Input Capture Flag Both the TCSR1 and TCSR2 will be cleared during reset. This read-only bit is set when an input signal of port 2, bit 0 (Note) If OE1 or OE? is set to ‘*1”” before the first output com- makes a transition as defined by IEDG and the FRC is transfer- pare match occurs after reset restart, bit 1 or bit 5 of port 2 red to the ICR. Cleared when reading the upper byte (S000D) of will produce “0 respectively. @HITACHI : Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300 153 i

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 s: it s: | Tso. Output Compare Ouiput Compare Free Running Toput Capture Register 2 Rogister 1 16 Bit Counter Register ==) Se) Ga —s pt | | RES ee ee a ti — Farr Pe empeteolerpe | Log | | pa] _— a Tse |_| Peidaicec cocoa IRs { CI LCF = | UU CJ {Pas Pa Pao Figure 24 Timer 1 Block Diagram @ TIMER2 selected by TOSO and TOS! of the TCSR3 will appear at port 2, bit In addition to the timer 1, the HD6301Y0 provides an 8-bit 6. When CMF is set, the counter will be cleared simultaneously and reloadable timer, which is capable of counting the external event. _ then start counting from $00. This enables regular interrupts and The timer 2 contains a timer output, so the MCU can generate waveform outputs without any software support. The TCONR is set three independent waveforms. (Refer to Fig. 25.) to “SFF™ during reset. The timer 2 is configured as follows: + Controt/Status Register 3 (7 bits) © Timer Control/Status Register 3 (TCSR3) ($001B) + 8-bit Up Counter The timer controV/status register 3 is a 7-bit register. All bits are + Time Constant Register (8 bits) readable and 6 bits except for CMF can be written. The followings are each pin descriptions. © Timer 2 Up Counter (T2CNT) ($001D) This is an 8-bit up counter which operates with the clock decided ‘Timer Control/Status Register 3 by CKSO and CKS] of the TCSR3. The CPU can read the value of the counter without affecting the counter. In addition, any value 27 6 5 4 3 2 1 can be written to the counter by software even during counting. CMF] ECM 72 ]7081| rosolexsi] cxsol_soore The counter is cleared when a match occurs between the counter and the TCONR or during reset. If the write operation is made by software to the counter at the cycle of counter clear, it does not reset the counter but put the write BitO CKSO input Clock Select 0 data to the counter. Bit? — CKS1 Input Clock Select 1 Input clock to the counter is selected as shown in Table 7 © Time Constant Register (TCONR) ($001C) depending on these two bits. When an external clock is selected, The time constant register is an 8-bit write only register. It is bit 7 of port 2 will be a clock input automatically. Timer 2 detects always compared with the counter. the rising edge of the external clock and increments the counter. When a match has occurred, the counter match flag (CMF) of The external clock is countable up to half the frequency of the the timer control status register 3 (TCSR3) is set and the value system clock. | @HITACHI | 154 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 HD6301Y0 Internal Data Bus igi ie Timert FRC Clock ons Upéoo Constant Clock Port 2 Register Up Counter >] Select ' Bit 7 Output t Level ; Port2 ial : “ em] To os foefn fait 'RQs qg_—— | Figure 25 Timer 2 Block Diagram Table 7 input Clock Select Bit4 T2E Timer 2 Enable Bit When this bit is cleared, a clock input to the up counter is inhibited and the up counter stops. When set to “1”, a clock CKS1 | cxso_| Input Clock to the Counter selected by CKS1 and CKSO (Table 7) is input to the up counter. o | 0 | Ectock (Note) Py. outputs “0” when T2E bit cleared and timer 2 set in 0 | 1 |e etocnie output enable condition by TOSI or TOSO. It also outputs “0” when T2E bit set “1” and timer 2 set in output ena- t_ [0 | Eetock/i28" ble condition before the first counter match occurs. 1 External clock Bit& Not Used. [| Bit6 _ ECMI Enable Counter Match Interrupt * These clocks come from the FRC of the timer 1. If one of these clocks is When this bit is set, an internal interrupt (IRQ,) by CMI is ‘selected as an input clock to the up counter, the CPU should not write to enabled. When cleared, the interrupt is inhibited. ‘the FRC of the timer 1 Bit? CMF Counter Match Flag This read-only bit is set when a match occurs between the up counter and the TCONR. Cleared by writing ‘*0" at CMF =1 by Bit2 TOSO Timer Output Select 0 software (unable to write “‘1"’ by software). Bit3 _ TOS1 Timer Output Select 1 Each bit of the TCSR3 is cleared during reset. ‘When a match occurs between the counter and the TCONR timer 2 outputs shown in Table 8 will appear at port 2, bit 6 ®@ SERIAL COMMUNICATION INTERFACE (SCI) depending on these two bits. When both TOSO and TOSI are The Serial Communication Interface (SCI) in the HD6301Y0 "0", bit 6 of port 2 will be an I/O port. contains the following two operating modes: asynchronous mode by the NRZ format, and clocked synchronous mode which transfers Table 8 Timer 2 Output Select data synchronously with the clock. In the asynchronous mode, data length, parity bits and number of stop bits can be selected, and eight | toso | transfer formats are provided. Tosi | Toso Timer Output The SCI consists of the following registers as shown in Fig. 26 0 | 0 | _ Timer Outputinnibited Block Diagram. Toggle Output” + Transmit/Receive Controt Status Register 1 (TRCSR1) ed ee outp + Rate/Mode Control Register (RMCR) to | output + Transmit/Receive Control Status Register 2 (TRCSR2) 1 ‘Output “1” + Receive Data Register (RDR) P| + Recevie Shift Register * When a match occurs between the counter and the TCONR, timer 2 + Transmit Data Register (TDR) output level is reversed. This leads to production of » square wave with + Transmit Shift Register 50% duty to the extemal without any software support. To operate the SCI, initialize the RMCR and TRCSR2, after selecting the desirable operating mode and transfer format. Next, @HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 155

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 set the enable bit (TE or RE) of the TRCSR1. Operating mode and ing mode or transfer format, interval of more than a 1-bit cycle of transfer format should be changed when the enable bit (TE, RE) is the baud rate or bit rate is necessary. If a 1-bit cycle or more is not cleared. When setting the TE or RE again after changing the operat- allowed, the SCI block may not be initialized. Parity Check fr — TRCSR2 Pe} mecanenee | || fowbefonlro] Doors MSB toi tt TRCSA1 mC ETT TLL | | betel De] foo a A ee prensa psir pe ti ;—_—— penerster Timer 2 Figure 26 SCI Block Diagram © Asynchronous Mode the contents of the TRCSR2 and RMCR at first, and set RE bit of Asynchronous mode contains 8 transfer formats as shown in TRCSRI. The first ‘*0” (space) synchronizes the receive bit flow. Fig. 27. Each bit of the following data will be strobed in the middle. Ifa stop Data transmission is enabled by setting TE bit of the TRCSR1, _bit is not “*1”, a framing error assumed and ORFE is set. then port 2, bit 4 will unconditionally become a serial output inde- When a framing error occurs, receive data is transferred to the pendently of the corresponding DDR. Receive Data Register and the CPU can read the error-generating To transmit data, set the desirable transmit format with RMCR —_—_ data. This makes it possible to detect a line break. and TRCSR2. When the TE bit is set, the data can be transmitted When PEN bit is set, the parity check is done. If the parity bit after transmitting the one frame of preamble (“1”). does not match the EOP bit, a parity error occurs and the PER bit is The conditions at this stage are as follows. set, not the RDRF bit. Also, when the parity error occurs the 1) If the TDR is empty (TDRE=1), consecutive 1's are pro- _receive data can be read just like in the case of the framing error. duced to indicate the idle state. The RDRF flag is set when the data is received without a fram- 2) If the TDR contains data (TDRE=0), data is sent to the ing error and a parity error. Transmit Shift Register and data transmit starts. If RDRF is still set when receiving the stop bit of the next data, During data transmit, a start bit of “0” is transmitted first. Then ORFE is set to indicate the overrun generation. CPU can get the 7-bit or 8-bit data (starts from bit 0) is transmitted. With PEN=1, receive data by reading RDR. When 7 bit data format is selected, the parity bit, even or odd, selected by EOP bit is added, lastly the the 8th bit of RDR is “0”. stop bit (1 bit or 2 bis) is sent. When the CPU read the receive Data Register as a response to When the TDR is “empty”, hardware sets TDRE flag bit. Ifthe RDRF flag or ORFE flag after having read TRCSR, RDRF or CPU doesn’t respond to the flag in proper timing (the TDRE is in | ORFEis cleared. set condition till the next normal data transfer starts from the (Note) Clock Source in Asynchronous Mode. transmit data register to the transmit sift register), *1"" is transfer- If CC1:CCO= 10, the internal bit rate clock is provided at Py» red instead of the start bit 0" and continues to be transferred till regardless of the values for TE or RE. Maximum clock rate is data is provided to the data register. While the TDRE is “*1"", “0” is E+ 16, not transferred. If both CC] and CCO are set, an external TTL compatible clock Data receive is possible by setting RE bit. This makes port 2, bit must be connected to P,, at sixteen times (16% ) the desired bit 3. serial input. The operation mode of data receive is decided by rate, but not greater than E. i | @ HITACHI | 156 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01YO Bito sso Biro ‘WU Wake-up In a typical multi-processor configuration, the software pro- Bit sei Speed Select tocol provides the destination address at the first byte of the BRE = ss2 message. In order to make uninterested MCU ignore the femaining message, a wake-up function is available, By this, These bits control the baud rate used for the SCI. Table 9 lists uninterested MCU can inhibit all further receive processing till _the available baud rates. The timer 1 FRC (SS2=0) and the timer 2 the next message starts. up counter (SS2=1) provide the internal clock to the SCI. When Then wake-up function is triggered by consecutive I's with 1 _ selecting the timer 2 as a baud rate clock source, it functions as a frame length. The software protocol should provide the idle time baud rate generator. The timer 2 generates the baud rate listed in between messages. Table 10 depending on the value of the TCONR. By setting this bit, the MCU stops data receive till the next (Note) When operating the SCI with intemal clock, do not per- message. The receive of consecutive “1” with one frame length form write operation to the timer/counter which is the wakes up and clears this bit by hardware and then the MCU clock source of the SCI. restarts receive operation. However, the RE flag should be already set before setting this bit. In the clocked synchronous -Bit2- CCO mode WU is not available, so this bit should not be set. Bit3 CC1} Clock Control/Format Select” Bit1 TE Transmit Enable Bits cc2 When this bit is set, transmit data will appear at port 2, bit 4 after one frame preamble in asynchronous miode, while in These bits contro! the data format and the clock source (refer to clocked synchronous mode it appears immediately. This is Table 11). executed regardless of the value of the corresponding DDR. * COO, CCI and CC2 are cleared during reset and the MCU When TE is cleared, the serial I/O doesn’t affect port 2, bit 4 goes to the clocked synchronous mode of the external clock Bit2 TIE Transmit Interrupt Enable operation. Then the MCU automatically set port 2, bit 2 into When this bit is set, an internal interrupt (IRQ,) is enabled the clock input state. When using port 2, bit 2 as an output when TDRE (bit 5) is set. When cleared, the interrupt is port, the DDR of port 2 should be set to “I” and CC] and inhibited. CCO to “0” and “1” respectively. Bit3 RE Receive Enable When set, a signal is input to the receiver from port 2, bit3 - Bit6 Not Used. regardless of the value of the DDR. When RE is cleared, the Bit? Not Used serial I/O doesn’t afffect port 2, bit 3. Bits RIE Receive Interrupt Enable © Transmit/Receive Controt Status Register 2 (TACSR2) When this bit is set, an internal interrupt (IRQ,) is enabled The TRCSR2 is a 7-bit register which can select a data format in when RDRF (bit 7) or ORFE (bit 6) is set. When cleared, the _the asynchronous mode. The upper 3 bits are the same address as. interrupt is inhibited. the TRCSR1. Therefore, the RDRF, ORFE and TDRE can be read Bit 5 TDRE Transmit Data Register Empty by either the TRCSR1 or TRCSR2. Bits 0 to 2 of the TRCSR2 are TDRE is set by hardware when the TDR is transferred to the _—_used for read/write. Bits 4 to 7 are used only for read. Transmit Shift Register in the asynchronous mode, while in clocked synchronous mode when the TDSR is “empty”. This . ; bit is cleared by reading the TRCSR1 or TRCSR2 and writing Transmit/Receive Control Status Register 2 new transmit data to the TDR when TDRE= 1. TDRE is set to 4 2 1 (Note) TDRE should be cleared in the transmittable state after [row [ors|rone] ren | — [ren] cor] oa] soo1e the TE set. Bit6 ORFE Overrun Framing Error ORFE is set by hardware when an overrun or a framing error is generated (during data-receive only). An overrun error occurs when new receive data is ready to be transferred to the RDR ——-BitO_—SBL_ Stop Bit Length during RDRF still being set. A framing error occurs when a stop This bit selects the stop bit length in the asynchronous mode. bit is “0”. But in clocked synchronous mode, this bit is not If this bit is “0”, the stop bit is 1-bit. If “1”, the stop bit is 2-bit. affected. This bit is cleared by reading the TRCSR1 or TRCSR2, This bit is cleared during reset. and the RDR, when RDRF=1. ORFE is cleared during reset. Bitt EOP Ever/Odd Parity Bit7 _ RDRF Receive Data Register Full This bit selects the parity generated and checked when the RDRF is set by hardware when data is received normally and PEN is “1”. If this bit is “0”, the parity is even. If '1", it is odd. transferred from the Receive Shift Register (RSR) to the RDR This bit is cleared during reset. This bit is cleared by reading TRCSR1 or TRCSR2, and the —-Bit2_—PEN Parity Enable RDR, when RDRF =I. This bit is cleared during reset This bit decides whether the parity bit should be generated and checked in the asynchronous mode or not. If this bit is “0”, © Transmit Rate/Mode Control Register (RMCR) the parity bit is neither generated nor checked. If “I”, it is The RMCR controls the following serial 1/0 generated and checked. This bit is cleared during reset + Baud Rate + Data Format The 3 bits above do not affect the SCI opertion in the clocked + Clock source + Port 2, Bit 2 Function synchronous mode. « Operation Mode Bit3 Not Used All bits are readable/writable. Bit 0 to 5 of the RMCR are cleared during reset. Transfer Rate/Mode Control Register 7 6 5 4 3 2 1 Oo Le Pe lee[ |=] 2° @ HITACHI 158 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300

When SS2 is “1”, Timer 2 provides SCI clocks. The baud rate is shown as follows with the TCONR as N. ‘operatable up to DC ~ 1/2 system clock. *° The bit rate is shown as follows with the TCONR as N. *E/8 clock is input to the timer 2 up counter and E clock otherwise. Table 11. SCI Format and Clock Source Control 1 10 | 7bit data | Asynchronous Internal Output" See ne ecshtavigtoommut.

Clock output regardless of the TRCSR1, bit RE and TE.

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Bit4 PER Parity Error * Each flag of the TDRE, ORFE, and RDRF can be read from This bit is set when the PEN is “1” and a parity error occurs. either the TRCSR1 or TRCSR2. It is cleared by reading the RDR after reading the TRCSR2, when PER=1. 1 PRECAUTION 1 Bite TORE In the synchronous clocked receive operation with clock- Transmit Data Register Empty ise timi Bite ORFE output, there are three cases for clock pulse timing after RDRF Overrun/Framing Error clear as shown below. Bit? RDRF Please consider above in designing system, since transmitting/ Receive Data Register Full receiving time is not uniform. RDR read cycle (RDRF clear) FTL LI LF LS US LS bito bit? clock-output case 1 t bito case 2 fa bit 0 case 3 J (note) Whenbitrateis E/2, t:=E, and t, = 2. Precaution 1 Diagram The clock-output of casel or case 2 is determined by “1” or “0” of SCI internal operation clock of RDRF clearing cycle. In addition, in the case of low voltage operation (Vcc < 4.5V), the clock-output of casel may transfer to case 3. PRECAUTION 2 When transmitting through clock-synchronous serial communi- If transmit data is written to TDR, and then TE bit is cleared with cation interface, TE bit should not be cleared with TDRE of TRCSR -—- TDRE = 0 to stop transmitting, TDRE remains “0”. (SI) is “0”. In this case, even if TE bit is set and transmit data is written again, The TDRE set and clear conditions of SCI are shown as follows. the TDR data is not transmitted. Please note that TE bit must be cleared after the last data has been Clear condition transmitted. 7. TDR = transmit When writing to TOR (This caution is not applied to asynchronous serial communica- shift register after TRSCR read, tion interface.) (asynchronous) with TDRE = 1, TDRE Tore | 2. Transmit shitt is cleared. register is empty. (clock-synchronous) 3. RES = 0 @HITACHI 160 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

the timer 1, timer 2 and SCI. Table 12. Timer 1, Timer 2 and SCI Stetus Flag

Read the TCSR2 then write to the OCR2H
Framing Error (Asynchronous Mode) 1. Read the TRCSR1 or TRCSR2 then RDR, when
Overrun Error (Asynchronous Mode) 2. RES =0
Asynchronous Mode Read the TRCSR1 or TRCSR2 then write to the

Transmit Shift Register is “empty” Note) TDRE should be reset after the TE set.

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01YO = LOW POWER DISSIPATION MODE This sleep mode is effective to reduce the power dissipation for a The HD6301Y0 provides two low power dissipation modes; system with no need of the HD6301Y0s consecutive operation. sleep and standby. © Standby Mode © Sleep Mode The MCU goes to the standby mode with the STBY “Low” or The MCU goes to the sleep mode by SLP instruction execution. by clearing the STBY flag. In this mode, the HD6301Y0 stops all In the sleep mode, the CPU stops its operation, while the registers” the clocks and goes to the reset state. In this mode, the power dis- contents are retained. In this mode, the peripherals except the CPU sipation is reduced to several 4A. During standby, all pins, except such as timers, SCI, etc. continue their functions, The power dis- the power supply (Vcc, Vss), the STBY, RES and XTAL (which sipation of sleep-condition is one fifth that of operating condition. outputs 0"), go to the high impedance state. In this mode, power The MCU returns from this mode by an interrupt, RES or (Voc) is supplied to the HD6301Y0, and the contents of RAM is STBY; it goes to the reset state by RES and the standby mode by _retained. The MCU returns from this mode during reset. When the STBY. When the CPU acknowledges an interrupt request, it cancels MCU goes to the standby mode with STBY “Low”, it will restart at the sleep mode, returns to the operation mode and branches to the _the timing shown in Fig. 29(a). When the MCU goes to the standby interrupt routine. When the CPU masks this interrupt, it cancels mode by clearing the STBY flag, it will restart only by keeping the the sleep mode and executes the next instruction. However, for RES ‘‘Low’’ for longer than the oscillating stabilization time. example, if the timer 1 or 2 prohibits a timer interrupt, the CPU (Fig. 29(b)) doesn’t cancel the sleep mode because of no interrupt request. Vee 1 Mi _ 1 =|am 1 t wos201v0 | | as || Srey a , \\ [> 1 2 S| | ! roq 1 ! cola 14 ' f Ves Ves ‘Standby Mode © oxeteto © Save Registers Start op SRE wines Hyg Restart {a) Standby Mode by STBY Vee ———— . Ly 0630170 ‘p> ! Standby Mode ‘ OsTeY FLAG © Oscitetor, Clear pal od ime {Restart RES [> j Ves__Ves LJ (b) Standby Mode by the STBY Flag Figure 29 Standby Mode Timing @HITACHI 162 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300

——— HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 = TRAP FUNCTION Tes secon hand 8 The CPU generates an interopt with the highest priory foot Es] Nomen. (TRAP) when fetching an undefined instruction or an instruction from non-memory space. The TRAP prevents the system-burst nae Reps 8) caused by noise or a program error. © Op Code Error [a When fetching an undefined op code, the CPU saves registers as well as a normal interrupt and branches to the TRAP (SFFEE, | a FFEF). This has the priority next to reset. 2 8 prionity CLEATS) eeu con ne on © Address Error cavern Ham 8 ‘When an instruction fetch is made excluding internal ROM, Steal RAM and extemal memory area, the MCU generates an interrupt some as well as an op code error. But on the system with no memory in its ee trom external memory area, this function is not applicable if an instruc, tion fetch is made from the external non-memory area. Table 1. . provides addresses where an address error occurs to each mode. Figure 30 CPU Programming Model This function is available only for an instruction fetch and is not applicable to the access of normal data read/write. © CPU Addressing Mode The HD6301Y0 provides 7 addressing modes. The addressing . mode is determined by an instruction type and code. Tables 14 Table 13 Addresses Applicable to Address Errors through 18 show addressing modes of each instrution with the execution times counted by the machine cycle. ‘Mode [fo o1 [| 2 | 3 ‘When the clock frequency is 4MHz, the machine cycle time becomes microseconds directly. $0000 $0000 $0000 Accumulator (ACCX) Addressing t t ' Only an accumulator is addressed and the accumulator A or B is, Address $0027 $0027 $003F selected. This is a one-byte instruction. Immediate Addressing $0140 This addressing locates a data in the second byte of an instruc- t tion, However, LDS and LDX< locate a data in the second and third SaFFF byte exceptionally. This addressing is a 2 or 3-byte instruction. Direct Addressing In this addressing mode, the second byte of an instruction shows (Note) The TRAP interrupt provides a retry function differently the address where'a data is stored. 256 bytes ($0 through $255) can from other interrupts. This is a program flow return to the be addressed directly. Execution times can be reduced by storing address where the TRAP occurs when a sequence returns data in this area so it is recommended to make it RAM for users” to a main routine from the TRAP interrupt routine by data area in configurating a system. This is a 2-byte instruction, RTL. The retry can prevent the system burst caused by while 3 byte with regard to AIM, OIM, EIM and TIM. noise, etc. Extended Addressing However, if another TRAP occurs, the program repeats In this mode, the second byte shows the upper 8 bit of the data the TRAP interrupt forever, so the consideration is stored address and the third byte the lower 8 bit. This indicates the necessary in programming. absolute address of 3 byte instruction in the memory. Indexed Addressing ® INSTRUCTION SET The second byte of an instruction and the lower 8 bit of the The HD6301Y0 provides object code upward compatible with index register are added in this mode. As for AIM, OIM, EIM and the HD6801 to utilize all instruction set of the HMCS6800. It also -—-TIM, the third byte of an instruction and the lower 8 bits of the reduces the execution times of key instructions for throughput _index register are added. improvement. This carry is added to the upper 8 bit of the index register and Bit manipulation instruction, change instruction of the index the result is used for addressing the memory. The modified address register and accumulator and sleep instruction are also added. is retained in the temporary address register, so the contents of the The followings are explained here. index register doesn't change. This is a 2-byte instruction except + CPU Programming Model (refer to Fig. 30) AIM, OIM, EIM and TIM (3-byte instruction). + Addressing Mode Implied Addressing + Accumulator and Memory Manipulation Instruction (refer to An instruction itself specifies the address. This is, the instruction Table 14) addresses a stack pointer, index register, etc. This is a one-byte : + New Instruction instruction. + Index Register and Stack Manipulation Instruction (refer to Relative Addressing Table 15) The second byte of an instruction and the lower 8 bits of the + Jump and Branch Instruction (refer to Table 16) program counter are added. The carry or borrow is added to the : + Condition Code Register Manipulation (refer to Table 17) upper 8 bit. So addressing from —126 to +129 byte of the current : + Op Code Map (refer to Table 18) instruction is enabled. This is a 2-byte instruction. (Note) CLI, SEI Instructions and Interrupt Operation © Programming Model When accepting the IRQ at a preset timing with the i Fig. 30 depicts the HD6301 YO programming model. The double CLI and SEI instructions, more than 2 cycles are neces- i accumulator D consists of accumulator A and B, so when using the sary between the CLI and SEI instructions. For exam- | accumulator D, the contents of A and B are destroyed. ple, the following program (a) (b) don’t accept the IRQ | @HITACHI | Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 163

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 but (c) accepts it. ~ . : : : cL CLI cLI ‘NOP SEI NOP NOP . SE! SEI 0) () © The same thing can be said to the TAP instruction instead of the CLI and SEI instructions. , Table 14 Accumulator, Memory Manipulation Instructions Conaiion Codk Addressing Modes on © Operations iMMED [DIRECT [ INDEX [EXTEND [MPLIED | grammer Operation | 5[4 [2]? [1 [O naa [anon yas] RTA 7 [isos —fesfatteets ferteteteetetst |} fesurss ————trfefet rps en ae a a Aad Accurvistorns | ABA | [|] ||. 4 { tieti [faves COE EREED Aadwin cary | ance feo |2|2 le |alz|as«[2lea|eis[ | | [asmec-a (elele[s(sfa [avce [co [2[2loolstaleofelz|rojalat | [Jeemecme [atelatatits ‘AND pawee pee acta tei aces 4) [dems =A fefeliti ale j_ anos [ca |2|2[oe[3 [2 [ea[a}2 [ra [a (a) [| fem=e 0 Peretti [ale Bi Tew [era | manaaaond peat few ett ete jee Jes [2 {2 Jos [s [2 [es | COED i Co CC I Creer poem OT TTT | fer [s [apr [sts] | [oom eo Te las [aia ee R [curs [| Harriet ries ee se lst Compare [ene —fen ape ter te fea tee eet petefititeys | cmea [ox [2 [2 Jor} [2 fer |«]? | CEL es OCOD ER Saree jm | Seen ee ODDO Compiement.v+ | com | a et ee [coma pa fama Oona +-soue ttt dt tthe ten et eee es s Component | nes | | | | TToo] [| foo-m=m ee fr foje (agate) neca {| 1 1 | Ty | [| Yao [ifs Joo-a=a fede [rT Jojo. [neces TTP | [ [so [1 ]roo-s=8 fw fe ft [sJolo owmarnawna lt omm [TT TTT TY | | | fe [aps seeceraoaes toner [+ [f+] f9 Decremene [oes TT fea fe 2 a fe [a [wom ee fe fale ce ee Ttjastsa aged j oecs | [Ty tT yt Try yy ify fe-t=8 BoggOd Enciusiw OR [| €ORA [es |? [2 [90 [3 [2 [as |e |2 joe [a [3] | [AG m=” fe Jefe te aye [eons [oe [21 [2 [eee] [rele [s[ [[ feouse Jefe fa faye Increment [we TTT [| 2 {7c neritic mooggod a VTasi sa BOBBOo [mes Ty oy ser fete ee [F[F fale Toes [toa | fee fefa fa tase aecteat TT [usa Tefen le Accumulator [uae [os |2[2loe{a|zlec[al2 fre [ala] [ [ im-e ole fe[rfale seme [oo [cf ele eee cece O00 Mutoly Uneared |_wun | | | i 7fifare=ae [=| [|= [-|0 OR. inchww | OnAA [ea 7 ]2 wala 2 [Aswad fe fete fay [~onas—[eala[2 foals [afeateta [ale ia[ [| [oem 8 ee ep efaye oak Bare ie a [4 [v[e=Me.se-1=se Tele fofelele Pail we a Ee ee re eee a Rotate Lett foro [TTT TT [eo [e [2 [79 | [Tn efefefe loft fro Ty et) | Segoe fee ef foe [Troe te Que" Rotate Rah Pee tee be teat * Goes PES [moma TP tr ty | Sod felt felt i [vrore PP Tr epi ogeOu i (Note) Condition Code Register will be explained in Note of Table 17 (continued) | @HITACHI | 164 Hitachi America, Ltd. * Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Table 14 Accumulator, Memory Manipulation Instructions __ ne | = Boolean) c Sr ate [ass TP TT TT Tyesfele pe fest TT. —_ ogoOo Aranenetie Pasa TOT TT Tr ety Tt ett | Oc « fo fe fre oye jase [TPT Tr Tyr yt fet pte [> [e[e]F Ole Double Shite caries | ae tT ded Pesamaraerar [+1 Ef) Fs a [ete tT fol: webs asm OO pee | Oro [ele fe fe fol se pee Oog8 On Shift Right [ {yy Ty feefe fa toe Tota TT lu — [efe [ale Fors Lonicat pesra | TET Pye eee oy ety |e) fe [> Tals tole j usas T TTT TTT Ty Ty tse tatete [eTe trys ol? oe ee ee Right Logie! af ‘Store [ {er [ste far]]2 for [a [s] [| [a-w Tele ts ta tale Accumolator STAB LHe afer ete fertets] tes foe : rr feteme | sro [| | foofe|e|eofs 2 |rofs fa] | [ecu Tele] [+ a] Subtrect [suena [eo [2 {2 ]o0 [3 |2]ao]«|2 Joo [ela] [| [a-w-a Teleheia tet fsvse— foo fa foo fa teeta tee eee oo o Double Subirect | suso [aa [3/3 [oa [4 | fesfest TTT fee [ete [eye iminen po tt BOBO 000 : Suet ne {2 faa{a fa fea te[st [ [ fa-m-cwa felets tes [s Wan Cary | sace ea 2}2 Joz[s {2 fez[e 2 fezfela| | | je-w-cse fe fete tate Transfer Ca OO OO 0 Accumuirors [reat TT TT tif fe a Te fe te Ta Jao Tenzwoor = [rst | {TT feolatafofetst TT [woo Tele [s [a [ria Mews eee ee OO [wsre {TTT TTT Tey yy feof fs fe = 00 ete fe le fafa Andimmedate [am [| T [afelsterfa{st TTT TT [www Tele fr tiiate ORimmediae [om TTT frefefatez(7[st TTT TY [momma Tele li fi [ale conimmedate [em [| T [rsfelatest7isf TTT | [womm—m Tele lil: Tale Testimmedare | wm TTT ref efofes] stat TTT TT [ui Telfer y fale (Note) Condition Code Register will be explained in Note of Table 17 @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 ¢ (415) 589-8300 165

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 In addition to the HD6801 instruction set, the HD6301Y0 pre- Executes “AND” operation to immediate data and changes pares the following new instructions. the relative flag of the condition code register. Executes “AND” operation to immediate data and the second immediate data and the third address modifier. Executes “OR” operation to immediate data and the memo- register. ry contents and stores its result in the memory. SLP Executes “EOR” operation to immediate data and the TION MODE” for more details of the sleep mode. memory contents and stores its result in the memory. Table 15 Index Register, Stack Manipulation Instructions Adsrenng Moon ; Congiaion Cos fern Operavon [Tameo [oineer [woex [exteno [wrvieD | annmceOoenen [sels [2] vo E Her henry tram Ett Decrement Index Reg pee) PPP EPP tr tt etre =1=% fofefte {i {ele Ovcrement Stack Pritt tt} tH [1 [y jsp t= se [o]>fofefe[s “increment index Rea [wx TT TT oe afc tax me OOGROo Increment Stack Prtr sf tt taetatrteetotat ME Ce eee OOD Loed index Reg [ vox |ce{a {aoe laa ee [| [3] TT [w= xn meta Tete fof fate ood Stack Pate {ees fae fo fa pee feats tte BL He Fy. % Lele loli [ale Store loden Res srx[ [TY for feta fer {s [2] [kw = xe= owe To fo fOfs tafe Store Stack Pate STs TT] far [5 [2] Tsry-M,SP~ Moi [ole lO [Rlo oder Reg = Stack Pow | THS, TTI | tT 1x1 [=[-Tofete[> _Stack Pre index Reg TSX PPP rer yr Tey 3 fsrvra x Tetetetetete hes [Ax | PPP Py pati foe x= fofots fe tele Push Dawe PSHX XU = Mp. P= a Xyq—> Map. SP - 1 = SP Pull Oats 1 Puux SP 1 = SP My hy . SP +1 SP, Myy = Xi, Exchange xeox [TTP TTT Ter TT pete t accom Telefelofofe (Note) Condition Code Register will be explained in Note of Table 17. i @HITACHI 166 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Table 16 Jump, Branch Instruction Oneravione me fa [s{<[a[2[sTo [or] ~[+ Jor|~]« lor[~T+ lor |~ [a jor]~[+ | [afi fwiz [vie Brench Alwoys [ena faofafat TTT TT ey Ty TT Tron TetefoTeTeye Branch Never [ean fatsi2t TPT PP Ty tT [ene fete Te te Te fe Branch Corry Cir a * Branch CerrySex_| acs [2s{3f2{ [Tt TT | tb tft [elelefelele Branch f= Zero___| @EQ__[27. [I Exal fe[ele[elele Soe) stenetiete ees Branch > Zero 2 eee ooo Branch If Higher {a3 Pt oar tote ey : Branch I< Zero Psfet TTT TT Tt Tt [ewes nogad : severe [ms feist TTT TTT TTT Ty feces Tefe teil reat be abbL LE Lippe cosh Branch Minus | em [aatstal ttt tt ty wat Bodo servnerewn [owe Tella TTT TTT TT fee Pelee be el Eee re ec Branch 1f Overflow = o ee Sc Branch To Subrovtine rae eebt ber] detielee . sume [wwe yee fs [2 fre fa is le fe [e [= le Te dump To Subroutine [us [| | jso[s [2 jaols j2 feole ja) | I | — ooggod ne ovemien [mor TTT TET TTT TT lo fas [esimemrn cor feo [fe Revwrn Frominewrrvor] ATE [TTT TT TT TT TY foe fofs | — + — tn oe ee ele le [el ‘Sottwere Interrupt tae fo Ts fe fe fe fo weirtorinteruors [war TT TT TT TT TT pels moggoo Seep se eae eo Te fo fete (Note) * WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state. Condition Code Register will be explained in Note of Table 17. @ HITACHI Hitachi America, Ltd. Hitachi Plaza # 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 » (415) 589-8300 167

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Table 17 Condition Code Register Manipulation Instructions daressingModed Gonsinien Core Register Operations [ wprieo | Boolean Operation fst«[sT2T To [or [~ Te | jut i [wtetvic ‘Ghoee Carry =< 2s Cheer Interrupt Mask = 2s OO > OO ee Clear Overtiow ey fee pee ete pe * Set Corry [sec fie fete ett s Set interrvet Mask Seen neete [el s{eleo]o To Set Overflow , ye pe a o ‘Accummuletor A= CCA [a= cor > GOR = AcewmuisrorA [tea fon Pv fv ccna eo To Te Te To Te LEGEND CONDITION CODE SYMBOLS OP Operation Code {Hexadecimal} H Half-carry from bit 3 to bit 4 ~ Number of Mcu Cycles 1 Interrupt mask Mgp Contents of memory location pointed by Stack Pointer N Negative (sign bit} # Number of Program Bytes Z Zero (byte) + Arithmetic Pius V_ Overtiow, 2's complement ~ Arithmetic Minus C Cerry/Borrow from/to bit 7 © Boolean AND Ro Reset Always + Boolean Inclusive OR S Set Always © Boolean Exclusive OR $ Setif true after test or clear M Complement of M © Not Affected > Transfer into

0 Bit = Zero

00 Byte = Zero

(Note) Condition Code Register Notes: (Bit set if test is true and cleared otherwise) ® (Birv) Test: Result = 100000007 @ (BitC) Test: Result § 000000007 @ (BitC) —_ Test: BCD Character of high-order byte greater than 107 (Not cleared if previously set) @® (Bit V)_—_ Test: Operand = 10000000 prior to execution? © (Bit) —_ Test: Operand = 01111111 prior to execution? @® (itv) Test: Set equal to N@ C= 1 after the execution of instructions ® (Bit N) Test: Result tess than zero? (Bit 15=1) ® {AllBit) Load Condition Code Register from Stack. @ (Bit) Set when interrupt occurs. if previously set, a Non-Maskable Interrupt is required to exit the wait state. @ {ANBit) Set according to the contents of Accumulator A. @ (Bit C) Result of Multiplication Bit 7=1? (ACCB) Table 18 OP-Code Map aCe Tw [ACCA or SPT ACB or X Ll 0 [wm [om [wo Text | oe eee ovr | 0110 [row | LC TC Poyuya ts Tats Te tres Tate Te TopeTr | [ocor[s [Nop [cea [oan fins [am CMP [+] [ow [2 | [Tom [rua [om sec [2] CO eae com | Sue0 A000 [3] [ooo | « [tsRo [ LSR “AND, le] ee ee oe: _—____AS. [7] STA LT sta 7 | [vooe [a [wx [ xcox] eve | ASL [tone Fn fe [ ge [wrefatcw [sr [en [aex [orc | [a] eee ea gg ee [weefe Tore [ —“Tect [rsux[ nc crx te | [wei o [sec | “Tour | a <a [o| {wn fr] [-—[eue | ee ee STS eet Le Tuy? ] eTsTeTr yes Taye yl Povete | UNDEFINED OP CODE C=) * Onty each instructions of AIM, OIM, EIM, TIM @ HITACHI 168 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 ® CPU OPERATION . and port states. © CPU Instruction Flow When operating, the CPU fetches an instrution from a memory © Operation at Each Instruction Cycle and executes the required function. This sequence starts with RES __ Table 20 shows the operation at each instruction cycle. By the cance] and repeats itself limitlessly if not affected by a special pipeline contro} of the HD6301Y0, MULT, PUL, DAA and XGDX instruction or a control signal. SWI, RTI, WA] and SLP instructions instructions, etc. prefetch the next instruction. So attention is change this operation, while NMT, IRQ,, IRQ,, IRQs, HALT and necessary to the counting of the instruction cycles because it is ‘STBY control it. Fig. 31 gives the CPU mode transition and Fig. 32 different from the usual one—from op code fetch to the next the CPU system flow chart. Table 19 shows CPU operating states instruction op code. by & S YW. “ a > o OA 2 BY AR. ; oz a\\e J 2 \\% RES=0 3 Ay ; a 4 EE EX \\y a y Ae, i] » oOo Xe ae si & Standby |_STBY=0 Mode Figure 31 CPU Operation Mode Transition Table 19 CPU Operation State and Port State a Pon 1 [Mode 2 t HK ora) [Modes | __ Keep Port 3 t r T [Mode 4 (A8 t0.A15) T [Mode pi" |__keep | Keep | ee cr a : ee pone [Mode 2 t a ee port [Mose 2 t [= H: High, L; Low. T. High Impedance Keep; The output port is retained. and the input port goes to the high impedance state. + RD, WA RMW, UR = HBA = RD, WR, RAW = T, UR, BA =H * HALT is unacceptable in mode 3. ** E pin goes to high impedance state. *** Address output pin = H Input por = 7 @ HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 169

gfe § . "68 8 y: ae oH nd &—EH IH gs2 ae = ee) d We | io) >| faa] OH OOO4O-Oip OOO Woh | @HITACHI | 170 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Table 20 Cycle-by-Cycle Operation IMMEDIATE ADC ADD Op Code Address +1 Operand Data AND BIT Op Code Address +2 Next Op Code CMP EOR LDA ORA SBC SUB ‘ADDO CPX Op Code Address +1 Operand Data (MSB) LoD = LDS HH Op Code Address +2 Hi Operand Data (LSB) Lox suBD Op Code Address +3 Next Op Code DIRECT ADC ADD T | Op Code Address +1 ‘Address of Operand (LSB) AND BIT 2 | Address of Operand Operand Data CMP EOR 3. | Op Code Address+2 Next Op Code LDA ORA | SBC SUB STA 1 _| Op Code Address+1 Destination Address 2 | Destination Address Accumulator Data 3__| Op Code Address +2 Next Op Code ADDD CPX ‘Op Code Address+1 7 0 1 | Address of Operand ((SB) LoD LOS. Address of Operand 1 ° 1 | Operand Data (MSB) LOX SUBD Address of Operand+1 1 0 1 | Operand Data (LSB) Op Code Address +2 1 ° © | Next Op Code STO STS Op Code Address +7 Destination Address (LSB) STX Destination Address Register Data (MSB) Destination Address +1 Register Data (LSB) Op Code Address +2 Next Op Code JSR ‘Op Code Address +1 Jump Address (CSB) FREE Restart Address (LSB) Stack Pointer Return Address (LSB) Stack Pointer—1 Return Address (MSB) Jump Address First Subroutine Op Code. Tim (Op Code Address +1 0 Immediate Data

4 Op Code Address +2 ° Address of Operand (LSB)

Address of Operand 0 Operand Data | Op Code Address +3 ° Next Op Code Aim EIM ‘Op Code Address +1 0 7 immediate Data OIM Op Code Address +2 ° 1 Address of Operand (LSB)

6 Address of Operand ° 1 Operand Data

FFFF 1 1 Restart Address (LSB) Address of Operand 1 o New Operand Data Op Code Address +3 ° 1 Next Op Code (Continued) @ HITACHI Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 171

4 FFE Restart Address (LSB)

(X + Offset Accumulator Data Op Code Address +2 Next Op Code ‘ADOD Op Code Address +1 0 Offset cPX DD FFE 1 Restart Address (LSB) LDS LOX IX+Offset ° Operand Data (MSB) sueD IX+Offset+1 0 Operand Data (LSB) Op Code Address +2 C) Next Op Code STO STS Op Code Address +1 0 T Offset STX FFF 1 1 Restart Address (LSB) IX+ Offset 1 ° Register Data (MSB) 1X+Offset+1 1 ° Register Data (LSB) Op Code Address +2 ° 1 Next Op Code ISR Op Code Address+1 0) Offset FFFF 1 Restart Address (LSB) Stack Pointer 1 Return Address (LSB) Stack Pointer—1 1 Return Address (MSB) 1X+Offset ° First Subroutine Op Code ASL ASR T | Op Code Address +1 7 Offset COM DEC 2 | FreF 1 Restart Address (LSB) INC LSR 3 | iX+Offset 1 Operand Data NEG = ROL 4 | FFE 1 Restart Address (LSB) ROR 5 | 1X+Offset ° New Operand Data 6 _| OpCode Address+ 2 1 Next Op Code TIM 1 | Op Code Address +1 0 Immediate Data 2 | Op Code Address +2 ° Offset 3. | FFFF 1 Restart Address (LSB) 4 | 1X+Offset ° Operand Data 5 | Op Code Address+3 ° Next Op Code cir ‘Op Code Address +1 T | Offset FFFF 1 | Restart Address (LSB) 1X +Oftset 1 | Operand Data IX + Offset 1 00 Op Code Address +2 0 _| Next Op Code Aim IM Op Code Address +1 0 T | Immediate Data OM Op Code Address +2 1 | Offset FFFE 1 | Restart Address (LSB) 7 (K+ Offset 1 | Operand Data FFFF 1 | Restart Address (LSB) 1X+ Offset 1 | New Operand Data Op Code Address+3 ° Next Op Code (Continued) i @ HITACHI | 172 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 I

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 instructions 8 EXTEND IMP Op Code Address +1 ) Jump Address (MSB) Op Code Address +2 Jump Address (LSB) Jump Address Next Op Code ‘ADC ADD TST Op Code Address +1 T o ‘Address of Operand (MSB) AND BIT Op Code Address +2 1 C) Address of Operand (LSB) CMP EOR Address of Operand 1 ° Operand Data LDA ORA Op Code Address +3 1 ° Next Op Code SBC__ SUB STA i Op Code Address +1 iy T Destination Address (MSB)

14 Op Code Address +2 1} Destination Address (LSB)

Destination Address 1 | Accumulator Data Op Code Address +3 0 | Next Op Code ADDD Op Code Address +1 iy T ‘Address of Operand (MSB) cPxX LOD Op Code Address +2 ° 1 Address of Operand (LSB) LOS LOX Address of Operand 0 1 Operand Data (MSB) suBD Address of Operand+1 0 1 Operand Data (LSB) Op Code Address +3 ° 1 Next Op Code “STO STS Op Code Address +7 0 1 Destination Address (MSB) STX Op Code Address +2 ° 1 Destination Address (LSB) Destination Address 1 ° Register Data (MSB) Destination Address +1 1 0 Register Data (LSB) Op Code Address +3 0 1 Next Op Code ISR T__| Op Code Address +1 oy Jump Address (MSB) 2 | Op Code Address+2 1 ° 1 Jump Address (LSB) 3 | FFF 1 1 1 Restart Address (LSB) 4 | Stack Pointer 0 1 ° Return Address (LSB) 5 | Stack Pointer~1 0 1 ° Return Address (MSB) 6 __|_Jump Address 1 0) 1 First Subroutine Op Code ASL ASR | T__| Op Code Address +1 T ) ‘Kddress of Operand (MSB) COM DEC 2 | Op Code Address +2 1 ° Address of Operand (LSB) INC _LSR | 6 3 | Address of Operand 1 0 Operand Data NEG ROL 4 | FFFF 1 1 Restart Address (LSB) ROR 5 | Address of Operand 0 1 New Operand Data _ 6 _| Op Code Address +3 1 0) Next Op Code “CLR Op Code Address +1 0 Address of Operand (MSB) Op Code Address +2 ° Address of Operand (LSB) Address of Operand ° Operand Data Address of Operand 1 00 Op Code Address +3 ° Next Op Code (Continued) @HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 173

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 oo ee OS eee Instructions (MPLIED ABA ABX ‘Op Code Address +1 Next Op Code ASL ASLO ASR CBA cic cur cLR CLV COM DEC DES DEX INC INS INX —_LSR LSRD ROL ROR NOP SBA SEC SEI «SEV TAB TAP TBA TPA Tst TSX TXS DAA XGDX Op Code Address +1 Next Op Code PULA PULB Op Code Address +1 1 Next Op Code FFFF 1 Restart Address (LSB) Stack Pointer+1 1 Data from Stack PSHA PSHE Op Code Address +1 Next Op Code FFFF Restart Address (LSB) Stack Pointer Accumulator Data Op Code Address +1 Next Op Code PULX Op Code Address+1 Next Op Code FFFF Restart Address (LSB) Stack Pointer+1 Data from Stack (MSB) Stack Pointer +2 Data from Stack (LSB) PSHX Op Code Address Next Op Code FFFF Restart Address (LSB) Stack Pointer Index Register (LSB) Stack Pointer—1 Index Register (MSB) Op Code Address +1 Next Op Code ATS Op Code Address +1 0 jext Op Code FFFF Restart Address (LSB) Stack Pointer+1 Return Address (MSB) Stack Pointer +2 Return Address (LSB) Return Address First Op Code of Return Routine MUL ~ T Op Code Address +7 T o Next Op Code 2 | FFF 1 1 | Restart Address {LSB} 3 | FFF 1 1 | Restart Address {LSB} 4 (| FFF 1 1 | Restart Address (LSB) 5 | FFF 1 1 | Restart Address (LSB) 6 | FFFF 1 1 | Restart Address (LSB) 7_| FFF 1 1_|. Restart Address (LSB) (Continued) @HITACHI ' 174 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 # (415) 589-8300

HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 Instructions Ea IMPLIED WAT T_] Op Code Address +1 7 0 T_] Next Op Code | 2 | FFFF loa 1 1 1 | Restart Address (LSB) | 3 | Stack Pointer lo 1 0 1} Return Address (LSB) | 4 | Stack Pointer—1 | 0 1 ° 1 | Return Address (MSB) 9 5 Stack Pointer —2 o 1 ° 1 Index Register (LSB) 6 | Stack Pointer—3 lo 1 ° 1 | Index Register (MSB) | 7 | Stack Pointer—4 / 0 1 ° 1 | Accumulator A | 8 | Stack Pointer—5 | 0 1 ° 1} Accumulator B | 9 | Stack Pointer—6 0 1 ° 1__| Conditional Code Register RTI ° 7) Op Code Address +1 6 7 Next Op Code | 2 FFFF 1 1 Restart Address (LSB) | 3 | Stack Pointer+1 ° 1 Conditional Code Register | 4 | Stack Pointer+2 ° 1 Accumulator 8 10 | 8 | Stack Pointer-+3 ° 1 Accumulator A 6 | Stack Pointer+4 ° 1 Index Register (MSB) 7 | Stack Pointer+5, oj; Index Register (LSB) 8 | Stack Pointer +6 ° 1 Return Address (MSB)

9 Stack Pointer +7 ° 1 Return Address (LSB)

10_| Return Address 0 1 First Op Code of Return Routine Swi rs Op Code Address +1 7 0 T T Next Op Code 2 | FFF 1 1 1 1 | Restart Address (LSB) 3 | Stack Pointer 0) 1 ° 1 | Return Address (LSB) | 4 | Stack Pointer—1 o | 1 | 0 | 1 | Return Address (MSB) | 5 | Stack Pointer—2 0 1 ° 1 | Index Register (LSB) 12 | 8 | Stack Pointer—3 0) 1 | 0 1 | Index Register (MSB) | 7 | Stack Pointer—4 ° 1 ° 1 | Accumulator A | 8 | Stack Pointer—5 ° 1 ° 1 | Accumulator B 9 | Stack Pointer—6 ° 1 | 0 1 | Conditional Code Register 10 | Vector Address FFFA 1 ° 1 1] Address of SW! Routine (MSB) 11 | Vector Address FFFB 1 0,4 1 | Address of SW! Routine (LSB) 12__| Address of SWI Routine 1 oj4 © __| First Op Code of SWI Routine ‘sLP ~ 1 Op Code Address +1 7 0 7 T Next Op Code 2. | FFF 1 1 1 1 | Restart Address (LSB) , | | | | 3. | FFF 1 1 1 1 | Restart Address (LSB) 4 _| Op Code Address+1 1 0 1 0 | Next Op Code RELATIVE BCC 6G: ‘Op Code Address +1 T () T T | Branch Offset BEQ = BGE FFF 1 1 1 1 | Restart Address (LSB) BGT BHI {Branch Address: —-Test="1 1 ° 1 First Op Code of Branch Routine BLE BLS | Op Code Address + 1-Test="0 © | Next Op Code BLT = BMT BNE = BPL BRA BRN Bvc _BVS BSR Op Code Address+1~ Tq 0 1 7 Offset ~ ~ FFFE toa 1} 4 1 | Restart Address (LSB) Stack Pointer 0 1 ° 1} Return Address (LSB) Stack Pointer ~1 ° 1 0 1 | Return Address (MSB) Branch Address 1 | 0 1 oO First Op Code of Subroutine @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300 175

——— HD6301Y0, HD63A01Y0, HD63B01Y0, HD63C01Y0 = WARNING CONCERNING WAI INSTRUCTION : If the HALT signal is accepted by the MCU while the WAI in- struction is executing, the CPU will not operate correctly after HAUT input HALT mode is canceled. waiting for 5 WAL is a instruction which waits for an interrupt. The cor- Linterrupt responding interrupt routine is executed after an interrupt {interrupt occurs occurs ; ; wrong vector adaver 4 However, during the execution of the WAI instruction, (MSB) HALT input makes the CPU malfunction and fetch an abnormal vector fetch for interrupt wrong vector address interrupt vectoring address. (LsB) { In HALT mode, the CPU operates correctly without the WAI = +t instruction, and WAI is executed correctly without HALT input. 4 Therefore, if HALT input is necessary, make interrupts wait . interrupt routine during the loop routine, as shown in Figure 35. . | @ WRITE-ONLY REGISTER Figure 35 MAC function during WAI When the CPU reads a write-only register, the read data is always $FF, regardless of the value in the write-only register. Therefore, be careful of the results of instructions which read write-only register . and perform an arithmetic or logical operation on its contents, such . ha as AIM, ADD, or ROL. is executed, because the arithmetic or : logical operation is always done with the data $FF. In particulars, Loop don’t use the AIM, OIM or EIM instruction to manipulate the DDR bit of PORT. ° : @ WARNING CONCERNING POWER START-UP 1) MAL function ii) Recommended method RES must be held low for at least 20 ms when the power starts up. In this case, the internal reset function is not effective until the Figure 36 Program to wait for interrupt oscillation begins at power-on. The RES signal is input to the LSI in synchronism with the internal clock @ (shown in Figure 37.) Therefore, after power starts up, the LSI condition such as its 1/0 ports and operating mode, are unstable. Fix the level of I/O ports by Lsi ° 3 means of an external circuit to determine the level for system opera- tion during the oscillator stabilization time. __ internal reset RES pin. oO signal Figure 37 RES Circuit @ DIFFERENCES BETWEEN HD63701Y0 AND HD6301YO Input Low Voltage Vit = 0.6V max. Vip = 0.8V max. of RES, MPo, MP, lin = 10 xA max. lin = 1.0 pA max. Cin = 65 pF max. Cin = 12.5 pF max. lin and Ci, of RES tin and Cip are larger than HD6301Y0 because RES: is also used as Vpp. Internal resistance of crystal oscillator Rg Internal resistance of crystal oscillator Rg i Met Rg = 600 max. ‘Storage Temperature Tstg = 55 t0 125°C Tetg = —55 to 150°C The HD63701Y0 difters from HD6301 YO in chip design and manufacturing process. When applying the Caution HD63701Y0 system to HD6301Y0, and HD6301Y0 system to HD63701Y0, note that characteristic values are not exactly the same even if guaranteed values are the same. @HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 177

SHIPPING CONTAINERS AND HANDLING

1.1 SHIPPING CONTAINER FORMS

3 Eee — A

Figure 1. Shipping Containers.

1.2 NOTES ON HANDLING

(1) Handles the outer cardboard carton with care. Sudden drops or © Water leakage will cause the anti-static material to peel off shocks can cause damage to the enclosed products. Be sure not and lose it effectiveness to overstack the cartons. © The anti-static material may become sticky in high- (2) Prevent water leakage. Do not leave shipping containers outside temperature, high-humidity environments. or store them in high-temperature, high-humidity areas. © The anti-static material may warp over time; avoid storage (3) Handle the inner cartons with care. Dropping a box may dis- beyond six months. Do not reuse the material, lodge a magazine stopper, allowing devices to slide out in which * Note that the surface resistance of transparent magazines is care their leads may be deformed. Dropping may also cause less than 1x10" Ohms, and the surface resistance of black damage to ceramic packages and cause leaks to air-tight seals. magazines is less than 1 x 10° Ohms. The surface of transparent vinyl-chloride magazines are treated ® Store vinyl-chloride trays between -25°C and +40°C. Both with an antistatic coating to prevent static charge. Be aware of the shape and color may change in an environment above the following notes concerning this coating: 55°C.

1.3 PARTIAL SHIPMENTS PACKING

<—- Pink Foam* a (Antistatic) f

1 Inner Box or

i ! MOS Pack ‘ ' \\ ' f f ' 1 | ' 1 1 ' ' 1 1 ! ane, 1 g 1 ‘ Packing List* | HITACHI On 9 Ve Label (Bar Coded)* ; CIMENSION Wd DDMENSION WINCHES WxHxLl WxeHxLl 250 x 250 x 500 10 x 10 x 20 250 x 225 x 550 10x 9x 22 175 x 150 x 550 7x 6x 22 * Materials or placement may vary. | Figure 2. Partial Shipments @ HITACHI | 14 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300

MOISTURE-PROOF (DRY PACK) PACKING AND HANDLING

prevent moisture absorption during shipping or storage, the pack- how to handle this material. Figure 3. Vacuum Packed Moisture-Proof (Dry Pack) Packing

2.1. STORAGE METHOD: 2.3 BAKING BEFORE SOLDER REFLOW: Storing packed ICs under inappropriate conditions can cause de- Baking is necessary if the indicator of the silica gel does not terioration in solderability and performance. Hitachi recommends appear blue-colored throughout; more than one week has elapsed that products in vacuum packed moisture-proof (dry pack) packing since opening (even stored under the conditions listed above); or the material be stored in tray boxed. If this is not possible, packages affixed label indicates baking is required. should be stored under the following conditions: ‘© Temperature: 5 10 30°C 2.4 RECOMMENDED BAKING CONDITIONS: © Humidity: less than 60% RH Baking should be performed under the following conditions: ‘© Temperature: 125°C Parts stored in unopened vacuum packed moisture-proof (dry * Duration: 16 to 24 hours ; pack) condition may remain solderable for three (3) to five (5) years. The magazines, trays, and tape reels normally used for shipment are not heat-proof, therefore containers cannot be baked as shipped. 2.2 HANDLING AFTER OPENING: Devices must first be transferred into a heat-proof container. Heat- In order to prevent re-absorption after opening the moisture- proof magazines and trays are currently under development. proof material, store under the conditions listed above and reflow Tray labelled as heat-proof can be used, however do not bake with mount the packages within one week. If the packages must be placed the moisture-proof bag. Bake on a level plane to prevent sliding. into storage again after opening, then seal in a new (non-moisture contaminated) silica gel (confirm with blue-colored indicator) and store under the conditions listed above. Try to reseal in vacuum packed moisture-proof (dry pack) packing material 3. PACKING SPECIFICATIONS FOR VARIOUS PACKAGES

3.1 PACKING SPECIFICATIONS for DIP Packages

112.5 x 59.4 x 500 DP-28 (Aor B) 13 (4% x 2% x 20) 112.5 x 59.4 x 500 DP-40 (4% x 2% x 20) 75 x 59.4 x 500 DP-64S (Cc) 12 — (3 x 2% x 20) 80 x 16 x 240 ) DC-40 (D) _ NIA Gh x % x 9%) 80 x 16 x 240 Dc-40P (>) = NIA Gh x % x 9%) 80 x 16 x 240 DC-64S - | 10 NIA aaa j (ih x % x 9%) 80 x 16 x 240 DC-64SP N/A (ih x % x 9%) Figure 4(a). Packing Specifications for DIP Packages *(see Fig. 1, this section) i | @ HITACHI | 16 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300

“Teanparen hard chlroetyene maasine ad ayarne manne - (sid eaisatie fai) hon mica passes Ca Se chorotyneneper ‘Now migration plasticined iow) tol loretiglee stot ‘ean SF Gre Magazine board thickness: 0.8 +0. 3mm Length: 500 ¢ 200 Magazine board thickness: 1.0.40. 2ea iw Length: 495 + Jem [Ai sat (500 #308) Dimensional tolerance: + 0.5aa en tolerance: +0.5ea llustration (A) Illustration (B) Clear Plastic (anti-static) (om (erage) “OE Af ite oe es “SS Clear Plastie (anti-static) Ge t Magazine board thickness: 1.0 £0, 3aa 80.0 mm Length: 495 ¢ 3 a (500 4308) | aoe! Liat [Pirerston Black Foam Cardboard lerance: 0. (carbon treated) (Faraday) 1.0mm “ , t 1 Pink Foam Cardtoard 1.0mm (anti-static) (Faraday) Illustration (C) Illustration (D) Figure 4(b). Packing Materials for DIP Packages @ HITACHI : Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 17

a Device Packing

3.2 QFP AND LCC PACKING SPECIFICATION

Viny!-Chloride Deice( Mustration (A)t iitustration (B)t a =| tl I | i Hi iim 1 eT Ce ee laa A HH - wnt og ese ee fife | ty | Tl elletlleslleall ees - sm es15 a Mlustration (Cyt ” Illustration (D}$ oe aieoosea=aregt _ 2 Be . r, a a SH Og ISS at zp ee | : Se | GRIG eee zee i] vs Fe pop ee OSoeceSgow + | - 1b fey j-— —- 111. SSssogsgogco] +, | * — _ : 213) SSS “ht ee at 7 : “eg ~ we Be ‘el Mlustration (E}t By, Fat t883 Tyee SEEBeCoaa,: |, iGaneeeed Hue, ! Spek SEeGEees) ; [+ en ae ~ | @ HITACHI j 18 Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. ® Brisbane, CA 94005-1819 * (415) 589-8300

**Figure 5. QFP and LCC Packing Specifications and Materials *(see Fig. 1, this section)**

3.3 PACKAGE PACK SPECIFICATIONS sc csrannine

**Figure 6. PLCC Packing Specifications and Materials *(see Fig. 1, this section)**

4.0 PACKING LABELS

Figure 8. Inner Box Label

Product Information

HD63B01Y0F specifications and overview.

Summary

CMOS MCU(MICROCOMPUTER UNIT)

Description

CMOS MCU(MICROCOMPUTER UNIT)

Source title HD63B01Y0F Datasheet(PDF) - Hitachi Semiconductor

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