HD6305X1 HITACHI | Alldatasheet
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HD6305X1,HD63A05X1,HD63B05X1 HD6305X2,HD63A05X2,HD63B05X2 . . CMOS MCU (Microcomputer Unit) The HD630SX1 and the HD630SX2_ are memory expanda- ble versions of the HD630SXO, which is CMOS 8-bit single chip | Hopapeaxip HosaoeRaR’ microcomputer. A CPU, a clock generator, a 128-byte RAM, HD63A05X2P, HD63B08X2P 1/0 terminals, two timers and a serial communication interface “A (SCI) are built in both chip of the HD6305X1 and the HD a 6305X2. Their memory spaces are expandable to 16k bytes ill Y externally. - “NN ve ‘The HD6305X1 and the HD6305X2 have the same functions ANY as the HD6305X0’s except for the number of 1/O terminals. ASN The HD6305X1 has a 4k byte ROM and its memory space is o- mA V expandable to 12k bytes externally. The HD6305X2 is a micro- aN computer unit which includes no ROM and its memory space (oP-64s) is expandable to 16k bytes externally HD6305X1F, HD63A05X1F, "HARDWARE FEATURES HD63B05X1F, HD6305X2F, #B.bit based MCU HD63A05X2F, HD63B05X2F © 4k-bytes of internal ROM (HD6305X1) No internal ROM (HD6305X2) © 128-bytes of RAM UC A total of 31 terminals, including 24 1/0’s, 7 inputs Sal — ¢ Two timers > UX« — B-bit timer with a 7-bit prescaler (programmable prescaler; >>. KES event counter) PID — 15-bit timer (commonly used with the SCI clock divider) On-chip serial interface circuit (synchronized with clock) (FP-64) #Six interrupts (two external, two timer, one serial and one software) * Low power dissipation modes CPU halts but the timer/serial/interrupt func- _° Similar to HD6800 tion is operatable. « Byte efficient instruction set — Stop... In this mode, the clock stops but the RAM Powerful bit manipulation instructions (Bit Set, Bit Clear, and data, 1/0 status and registers are held. Bit Test and Branch usable for all RAM bits and all 1/0 termi- — Standby.. In this mode, the clock stops, the RAM data nats) is held, and the other internal condition is A variety of interrupt operations reset Index addressing mode useful for table processing Minimum instruction cycle time A variety of conditional branch instructions = HD6305X1/X2 .. Tus (f= 1 MHz) Ten powerful addressing modes = HD63A05X1/X2. . 0.67 us (f= 1.5 MHz) © All addressing modes adaptable to RAM, and 1/0 instructions = HD63B05X1/X2.. 0.5ys (f= 2 MHz) Three new instructions, STOP, WAIT and DAA, added to the Wide operating range HD6805 family instruction set Vc = 3 to BV (f= 0.1 to 0.5 MHz) — HD6305X1/X2_.. f= 0.1 to 1 MHz (Vcc = SV + 10%) | PROGRAM DEVELOPMENT SUPPORT TOOLS — HD63A05X1/X2. . f= 0.1 to 1.5MHz (Vcc =5V + 10%) ——_@ Cross assembler software for use with IBM PCs and compat- = HO63B05X1/X2.. f= 0.1 to 2MHz (Vcc = 5V £ 10%) ibles © Incircuit emulator for use with IBM PCs and compatibles i i @HITACHI / Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 + (415) 589-8300 431
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 = PIN ARRANGEMENT © HD6305X1P, HD63A0SX 1P, HD63B05X1P, HD6305X2P, © HD6305X1F, HD63A05X1F, HD63B05X1F, HD6305X2F, HD63A05X2P, HD63B05X2P HD63A05X2F, HD63B05X2F Yss Ci GB DATA Res CJ BY DATA, 2 Sadia? int ia DATA. zi ig gt FER EE steve IED bata; SEEBEBR 855555 % xTat Cl ED DATA. BIGISIBIEIDIEIBIBIEIGIEIE eExTAL (ed OATAs num C7] BH DATAs Timen [ay [Sr] DATA Timer (CH {EJ DATA, A] [50] DATA, ag Be ap] {29} € A Ba aw asta fas] As 5H Ao. Wir. BJ ADR: “Cl 2] son, a BQ ADR: af] fee] A082 ag ET) ADR o i [4s] Aor, a. ED ADA af] [44] AOR.o Aollt HB ADRs cL] [43] AORs coir. HER ADR, 8>[ro} [az] ADRs
6.08 HD ADRs ssf] [ei] Aor,
- 2 WH ADR. : io 5 none Petal] a ADR * * 8,2 IY AOR, e3[r4] [3a] Aon. 8 fry ADR: 8,[05] [a7] aor, Boga GY) ADRo : cyte Bl Qo; °C pl Ars Co/Rx PE 06 /INTs Be [35] aon, Cy /CK BY ee c./Tx [3] [34] Aor, c. a fm o, C/A , Cs ie Ds EI pale em Bao EREEEREEEEEE) Coy] IT Vee Bsssos Racgsssy é S (Top View) (Top View) . | @HITACHI | 432 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 _____BDGB0AI, HEAL A oer Errore’ ® BLOCK DIAGRAM ATALEXTAL RAW RES num int = Ste | tweconvot | r _“ x gi cru > Terminals te Me omen Ey Congition Code kK 33 Bote s ° 5 FeO cg #8 Tomine : | ve — . rots o:|te 6H ecH nu . ton eila3 : ton Yerminats 8 FB SEO 5 aon a e\\|3s§ a “Cow Pci é ADRs e 3 5 AOR, 8 6 AOR; é sont 3 aOR. « < AR, mcf a son uo cr Ls 3 ADA, Terminals ¢3 3FKD e we 68 om tt - . ara, ll No internal ROM in HO630SX2 Data, : bares as DATA, Sera! << Fr bares eat, al cael Es Ky DATA, @HITACHI Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300 433
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 ® ABSOLUTE MAXIMUM RATINGS. Supply Vole 33070 ¥ Storage Terperture -35— 180 °c [NOTE] These products have 8 protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding, be careful not to apply any voltage higher than the absotute maximum rating to these high input impedance circuits. To assure normal operation, we recommended Vin, Vout: Vss $ (Vin OF Vout) S Vc. = ELECTRICAL CHARACTERISTICS © DC CHARACTERISTICS (Vcc = 5.0V 410%, Vss = GND, Ta = 0 ~ +70°C, unless otherwise noted.) trem [ symbot | Test Condition | min | typ | max unit RES, STBY _ . [Vec-0.5 | — | Vect0.3 | [Other inputs | [20 [= | Vcc#0.3 | Output “High” Voltage| All Outputs Von How==200HA | 2a ey — [lon=-10uA {Vec-o7 | = |= | Output "Low Votioge| Al Outputs [Wor [ious tema [|= fos INT, ‘Ao ~ Ay, Bo ~ Ba, Vin = 0.5 ~ Vec-0.5 Three-state Current Co ~ C7, ADRo ~ ADRi3”,| II rsil uA DATAg~ DATAz, E*.R/W* [Operating [ = [ 6 | io | ma Current Dissipation®*® | Walt fe amuse [= 2 mA [sep jp = [2 | HA [= 0a Input Capacitance Alll Terminals f=1MHz,Vin=ov [| - [| - | 12 [| pF * Only at standby Vin min = Vec-1.0V, Vi_ max = 0.8V * The value at f= xMHz is given by using lee (f= xMH2) = leg (f= 1MHz) xx © AC CHARACTERISTICS (Vc = 5.0V 10%, Vs = GND, Ta = 0 ~ +70°C, unless otherwise noted.) Item symbot |. Test HD6305x1/x2_[ _HD63A05X1/x2 | HDE3B05X1/x2 | veve! [condition Tin | eye [max] min [wo [ max | min | wp [max | O™ Cydle Time T= [10 sss} - [10 | 10_| Enable Rise Time - | - | 20 | - | 20 | [ 20 | s Enable Fall Time - | - | 2 | = [2 [= [= [20 | os : Enable Pulse Width(“High” Level)| PWen | 450 | — | = j — [= [220] - | = [os Address Delay Time <a = [= [a0 f= | = [700 [ns ‘Address Hold Time 40 | - [ 30 | - [| - | 20 | =| ns Data Set-up Time (Read) [ tose | so | - | - [oo | - [= | =| 9s Data Hot Tine (Read | wn] o> pep f= fet f= Ts i | @ HITACHI | 434 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 One een eee © PORT TIMING (Vcc = 5.0V 410%, Vss = GND, Ta = 0 ~ +70°C, unless otherwise noted.) ‘tem symbot Test HD6305X1/X2 HD63A05X1/X2 Unit . Condition [main [twp [max |-min | typ [max | min [ tye [mex |" Port Data Set-up Time | te Fig.2) |} —— Port Data Hold Time t 200 {Port A,B, C, D) _ POH ss Port Data Delay Time - | 200 | © CONTROL SIGNAL TIMING (Vcc = 5.0V+10%, Vgs = GND, Te = 0 ~ +70°C, unless otherwise noted.) tem Symbol |. Test HD6305X1/X2 HDBSBOSX1/X2_| INT ~ Teye te) t T " ve | eve | ae fel | (em | (om) T= INT; Pulse Width twee So | - | 13601 - |_| #360 | - | ns RES Pulse Width __ trwe s|-|[-|s |] -|- [ue Control Set-up Time tes [ Fis. 5 | 250 | — | - | 250 [- | - | ns Oscillation Start Time (Crystal) | tose | Fig5.Fig.20°) | — [- || - | - | 2] - ft ms * Cy = 22pF +20%, Rs = 602 max. © SCI TIMING (Voc = 5.0V#10%, Vsg= GND, Te = 0 ~ +70°C, unless otherwise noted.) Data Hold Time ee @ HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 435
Figure 2. Port Data Set-up and Hold Times Figure 3 Port Data Delay Time (MCU Write)
7 TUUU ULL LL UL LLL
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 oooh, oe eee —T1Nn e ed 5.5V-— Vee 4.5V. ~ tose tose: STBY Vec-0.5V tes Vec—0.5V RES Vec—0.5V Bus TFFF o1FFF IFFF FFF FFE 1FFF New Pi FFF AY a FigureS Reset Timing Clock Output Dav i cs/Ck o6v _o6v o.6v txo c/Tx K ogy t ‘SAX. tHax — _— Data Input Z0V TOV Ce/RX o.8V 0.8V Figure6 SCi Timing (Internal Clock) -——— tse — ii re Clock Input i 2.0V cs/CK osv_oev 0.8V toxo Data Output DAV C7/TX N o.6v Data Input ZOv 20v Co/Rx Nov oavs Figure7 SC! Timing(External Clock) @HITACHI Hitachi America, Ltd, * Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 437
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 \\ Data Bus (DATA, ~ DATA,) ce This TTL compatible three-state buffer can drive one TTL TTL Load load and 90pF. (Port) for=1.6mA S 2-4k2 Test point —_— Address Bus (ADR, ~ ADR,;) terminat Each terminal is TTL compatible and can drive one TTL load and 90pF. Q90pF S12ko Input/Output Terminals (Ao ~ A7, Bo ~ Br, Co ~ C5) These 24 terminals consist of three 8-bit 1/0 ports (A. B, C) Each of them can be used as an input or output terminal on a bit through program control of the data direction register. ° For details, refer to “I/O PORTS.” {NOTES} 1. roe load capacitance includes stray capacitance caused Input Terminals (Di ~ D7} y the probe, etc. These seven input-only terminals are TTL or CMOS com- 2. All olodes are 152074 @. patible. Of the port D's, Ds is also used as INT2. If De is Figure @ Test Load used as a port, the INT interrupt mask bit of the miscellane- 9 a ous register must be set to “1” to prevent an INT2 interrupt from being accidentally accepted. ™ DESCRIPTION OF TERMINAL FUNCTIONS °STBY The input and output signals of the MCU are described This terminal is used to place the MCU into the standby here. mode. With STBY at “Low” level, the oscillation stops and the internal condition is reset. For details, refer to “Stand- °Vcc, Vss by Mode.” Voltage is applied to the MCU through these two terminals. Voc is 5.0V + 10%, while Vsg is grounded. The terminals described in the following are 1/O pins for ee serial communication interface (SCI). They are also used as eiNT, INT? ports Cs, C, and Cy. For details, refer to “SERIAL COM- External interrupt request inputs to the MCU. For details, MUNICATION INTERFACE.” refer to “INTERRUPT”. The INT} terminal is also used as _ the port D, terminal. CK (Cs) Used to input or output clocks for serial operation. oXTAL, EXTAL These terminals provide input to the on-chip clock circuit. Rx (Cob A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic Used to receive serial data. filter is connected to the terminal. Refer to “INTERNAL Tx (C) OSCILLATOR” for using these input terminals. Used to transmit serial data. TIMER This is an input terminal for event counter. Refer to “TIMER” for details. |=MEMORY MAP The memory map of the MCU is shown in Fig. 9. $1000 ~ oRES SIFFF of the HD630SX2 are external addresses. However, Used to reset the MCU. Refer to “RESET” for details care should be taken to assign vector addresses to $1FF6 ~ SIFFF. During interrupt processing, the contents of the CPU oNUM registers are saved into the stack in the sequence shown in This terminal is not for user application. In case of the Fig. 10. This saving begins with the lower byte (PCL) of the HD630SX1, this terminal should be connected to Vcc program counter. Then the value of the stack pointer is through 10kQ resistance. In case of the HD6305SX2. this decremented and the higher byte (PCH) of the program terminal should be connected to Vss- counter, index register (X), accumulator (A) and condition code register (CC) are stacked in that order. In a subroutine Enable (E) call, only the contents of the program counter (PCH and PCL) This output terminal supplies E clock. Output is a single- are stacked. phase, TTL compatible and 1/4 crystal oscillation frequency or 1/4 external clock frequency. It can drive one TTL load and a 90pF condenser Read/Write (R/W) This TTL compatible output signal indicates to peripheral and memory devices whether MCU is in Read (“High”), or | in Write (“Low”). The normal standby state is Read (“High”) : Its output can drive one TTL load and a 90pF condenser. | @ HITACHI | 438 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 tions. The CC bits are as follows: Of these six interrupts, the INT2 and TIMER or the SCI Half Carry (H): Used to indicate that a carry occurred be- and TIMERa generate the same vector address, respectively. tween bits 3 and 4 during an arithmetic oper- When an interrupt occurs, the program in progress stops ation (ADD, ADC). and the then CPU status is saved onto the stack. And then, Interrupt (1): Setting this bit causes all interrupts, except the interrupt mask bit (I) of the condition code register is a software interrupt, to be masked. If an set and the start address of the interrupt processing routine interrupt occurs with the bit I set, it is is obtained from a particular interrupt vector address. Then latched. It will be processed the instant the interrupt routine starts from the start address. System the interrupt mask bit is reset. (More specifi- can exit from the interrupt routine by an RTI instruction. cally, it will enter the interrupt processing When this instruction is executed, the CPU status before routine after the instruction following the the interrupt (saved onto the stack) is pulled and the CPU CLI has been executed.) restarts the sequence with the instruction next to the one at Negative (N): Used to indicate that the result of the most which the interrupt occurred. Table 1 lists the priority of recent arithmetic operation, logical operation interrupts and their vector addresses. or data processing is negative (bit 7 is logic “1, , 8 ative (bi et Table 1 Priority of Interrupts Zero (Z): Used to indicate that the result of the most — recent arithmetic operation, logical operation Interrupt Vector Address or data processing is zero. i Carry/ Represents a carry or borrow that occurred RES __! _SIFFE, SIFFF Borrow (C): in the most recent arithmetic operation. This swi 2 SIFFC, $1FFD bit is also affected by the Bit Test and Branch =§ ——_——--—— —— instruction and a Rotate instruction. INT 3 SIFFA, SIFFB
2 INTERRUPT TIMER/INT2 4 | SIFF8, $IFFQ
There_are six different types of interrupt: external. inter- SCI/TIMER2 SIFF6, S1FF7 tupts (INT, INT), internal timer interrupts (TIMER, ieiwy Serial interrupt (SCI) and interrupt by an instruc- A flowchart of the interrupt sequence is shown in Fig. 12. a A block diagram of the interrupt request source is shown in Fig. 13. | is y__INT | Tot / ~~ Set N y SFF +SP | a> 0--00R's 1] Fetch 4 CLR INT Logic Instruction y sc SFF--TOR Ket $7F-Timer Prescaler N $50-—-TCR N $3F—-SSR KAS $00--SCR y ST ter, $7F-+MR " Stack PC, X,A,CC Load PC From Reset $1FFE, $1FFF | i <> Y N ona 6 fram N | Swisurcseo RM swasine Tine s06r8 806F9 | Execute Execute saseresie? Instruction | | insteuction | | fiuen sires? | J ul —— \\ Figure 12. Interrupt Flow Chart @HITACHI 440 Hitachi America, Ltd. * Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300
In the block diagram, both the external interrupts INT and Bit 7 of this register is the INT2 interrupt request flag. the INT processing routine. Meanwhile, the INT: request is _is INT: interrupt. Bit 7 can be reset by software. cleared if “0” is written in bit 7 of the miscellaneous register. Figure 13. Interrupt Request Generation Circuitry
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 register (TDR) becomes “0”, the timer interrupt request © Timer Control Register (TCR; $0009) bit (bit 7) in the timer control register is set. In response to Selection of a clock source, selection of a prescaler fre- the interrupt request, the CPU saves its status into ‘the stack quency division ratio, and a timer interrupt can be controlled and fetches timer interrupt routine address from addresses by the timer control register (TCR; $0009). SIFF8 and $1FF9 and execute the interrupt routine. The For the selection of a clock source, any one of the four timer interrupt can be masked by setting the timer interrupt modes (see Table 2) can be selected by bits 5 and 4 of the mask bit (bit 6) in the timer control register. The mask bit timer control register (TCR). (I) in the condition code register can also mask the timer interrupt. The source clock to the timer can be either an external Timer Control Register (TCR; $0009) signal from the timer input terminal or the internal E signal 765432410 (the oscillator clock divided by 4). If the E signal is used as the source, the clock input can be gated by the input to the [ceferefenelrcadrcngrenfrem frend timer input terminal. Once the timer count has reached “0”, it starts counting L Prescaler division ratio selection down with “SFE”. The count can be monitored whenever Prescaler initialize desired by reading the timer data register. This permits the tock input source program to know the length of time having passed after the Timer interrupt mask occurrence of a timer interrupt, without disturbing the con- imer interrupt request tents of the counter. When the MCU is reset, both the prescaler and counter are After reset, the TCR is initialized to “E under timer termi- initialized to logic “1”. The timer interrupt request bit nal control” (bit 5 = 0, bit 4 = 1). If the timer terminal is (bit 7) then is cleared and the timer interrupt mask bit (bit “1”, the counter starts counting down with “SFF” immediate- 6) is set. ly after reset. To clear the timer interrupt request bit (bit 7), it is neces- When “1” is written in bit 3, the prescaler is initialized. sary to write “0” in that bit: This bit always shows “O” when read. Table 2 Clock Source Selection TCR? Timer interrupt request
0 Absent TCR Clock input
1 Present
0 [ o | Internal clock E TCR6 Timer interrupt mask 0 | 1 | E under timer terminal control
0 Enabled 1 fo | No clock input (counting stopped)
1 Disabled 1 [1 | Event input from timer terminal
fe) Timer Control R | Resister Unternat (TCR;$0009) Clock) E > > ccrelrcns}rcralrcrafrcnafrcn|rcro| D—D ; CTI TIMER ~ Input Timer Data Register (TDR;$0008) Clock input Timer interrupt Write Read Figure 14 Timer Block Diagram i | @uTacu | 442 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 « (415) 589-8300
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 _ Bbotoal, Eee eee ee OO Se A prescaler division ratio is selected by the combination of A timer interrupt is enabled when the timer interrupt mask three bits (bits 0, 1 and 2) of the timer control register (see _bit is “0”, and disabled when the bit is “1”. When a timer Table 3). There are eight different division ratios: +1, +2, +4, interrupt occurs, “1” is set in the timer interrupt request bit. 28, +16, +32, +64 and +128. After reset, the TCR is set to the This bit can be cleared by writing “O” in that bit. +t mode. =SERIAL COMMUNICATION INTERFACE (SCI) Table 3 Prescaler Division Ratio Selection This interface is used for serial transmission or reception of 8-bit data. Sixteen transfer rates are available in the range TCR from 1 us to approx. 32 ms (for oscillation at 4 MHz). [aco | Protester avision ratio The SCI consists of three registers, one octal counter and Bir2 [ais | Bit one prescaler. (See Fig. 15.) SCI communicates with the CPU 0 [oo [ o | #1 via the data bus, and with the outside world through bits 5, 6 and 7 of port C. Described below are the operations of 0 fof? | 22 each register and data transfer. SCI Control Register (SCR; $0010) of ats | 8 1 +16 pfefs | erin nino emt ISCR7|SCR6/SCRS|SCR4 ISCR2|SCR1/SCRO v{ vo | 364 SCI Control Registers (SCR; 0010) scra| scra sera] snr scro : scaler Generator «wrt — H H b 4 1 ' SCI Data Registers LN . ‘Octal i + 6s aoa a ees Initialize cm} tts? TT TET Te] cut | \\ — t Lennneod 6 5 4 1 (9) Status Registers af fonder DD sa ZVNYS ee — I y Not Used SCI/TIMER2 Figure 15 SCI Block Diagram @HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 443
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 eee eeeeeeeeeeeeEeEeaeeeeeeEeEeEeEE————eeee ees , Bit 7 (SSR7) SCR? Cr terminal Bit 7 is the SCI interrupt request bit which is set upon ry Used as 1/0 terminal (by DDR). completion of transmitting or receiving 8-bit data. It is cleared when reset or data is written to or read from the 1 Serial data output (DOR output) SCI data register with the SCRS="1". The bit can also be cleared by writing “0” in it. SCRE Cy terminal Bit 6 (SSR6) ~ Bit 6 is the TIMER, interrupt request bit. TIMER; is used 0 Used as I/O terminal (by DDR). commonly with the serial clock generator, and SSR6 is set each time the internal transfer clock falls. When reset, the u Serial data input (DDR input) bit is cleared. It also be cleared by writing “O” in it. (For details, see TIMER, .) SCRS [sera] Clock source | Cs terminal Bit 5 (SSR5) 0 | - | ; Bit 5 is the SCI interrupt mask bit which can be set or | ° | bon" MO terminal (by cleared by software. When it is “1”, the SCI interrupt (SSR7) 1 [0 | internat | Clock output (DDR output) Bit 4 (SSR4) 1 [1 | externat | Clock input (DDR input) Bit 4 is the TIMER, interrupt mask bit which can be set or cleared by software. When the bit is “1”, the TIMER, interrupt (SSR6) is masked. When reset, it is set to “1”. Bit 7 (SCR7) . When this bit is set, the DDR corresponding to the C, _Bit 3 (SSR3) . becomes “I” and this terminal serves for output of SCI data When “1” is written in this bit, the prescaler of the transfer ‘After reset, the bit is cleared to “0” clock generator is initialized. When read, the bit always is “0” Bit 6 (SCR6) Bits2~0 When this bit is set, the DDR corresponding to the Cy Not used. becomes “0” and this terminal serves for input of SCI data. After reset, the bit is cleared to “0”. SSR7 SCI interrupt request Bits 5 and 4 (SCRS, SCR4) ° Absent These bits are used to select a clock source. After reset, 1 Present the bits are cleared to “0”. Bits 3~ 0 (SCR3 ~ SCRO) SSR6 TIMER; interrupt request These bits are used to select a transfer clock rate. After () Absent reset, the bits are cleared to “0”. SCR3 | SCR2 SCRO | 400MH2 | 4.194 MHz SSR5 SCI interrupt mask 0 0 0 tps 0.95 us J Enabled 0) 0 1 2us 1.91 us 1 Disabled 0 0 ° 4us 3.82 us 0 0 1 Bus 7.64 ps SSR4 TIMER; interrupt mask t 2 2 2 2 o- ____Enabled 1 1 1 32768 us 1/328 1 Disabled . Data Transmission SCI Data Register (SDR; $0012) . By writing the desired control bits into the SCI control A serial-parallel conversion register that is used for transfer registers, a transfer rate and a source of transfer clock are of data. determined and bits 7 and 5 of port C are set at the serial - data output terminal and the serial clock terminal, respec- SCI Status Register (SSR; $0011) tively. The transmit data should be stored from the accumu- 2 6 s 46 3 2 3 6 lator or index register into the SCI data register. The data iw written in the SCI data register is output from the C,/Tx SSR7| SSR6| ssns sore] sna] XX] <IX<] terminal, starting with the LSB, synchronously with the LN“ falling edge of the serial clock. (See Fig. 16.) When 8 bit of @ HITACHI ' 444 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 register, miscellaneous register or serial status register, there Fig. 24 shows a flowchart for the stop function. Fig. 25 is no interrupt request to the CPU, so the wait mode cannot shows a timing chart of return to the operation mode from be released. the stop mode. Fig. 23 shows a flowchart for the wait function. For releasing from the stop mode by an interrupt, oscilla- tion starts upon input of the interrupt and, after the internal Stop Mode delay time for stabilized oscillation, the CPU becomes active. When STOP instruction being executed, MCU enters into For restarting by RES, oscillation starts when the RES goes the stop mode. In this mode, the oscillator stops and the CPU “Q” and the CPU restarts when the RES goes “1”. The dura- and peripheral functions become inactive but the RAM, tion of RES=0" must exceed tose to assure stabilized oscil- registers and I/O terminals hold their condition just before lation. entering into the stop mode. The escape from this mode can be done by an extemal «Standby Mode interrupt (INT or INTz), RES or STBY. The RES resets the The MCU enters into the standby mode when the STBY MCU and the STBY brings into the standby mode. terminal goes “Low”. In this mode, all operations stop and When interrupt is requested to the CPU and accepted, the internal condition is reset but the contents of the RAM are the stop mode escapes, then the CPU is brought to the opera- hold. The I/O terminals turn to high-impedance state. The tion mode and vectors to the interrupt routine. If the inter- standby mode should escape by bringing STBY “High”. The rupt is masked by the I bit of the condition code register, CPU must be restarted by reset. The timing of input signals after releasing from the stop mode, the MCU executes the at the RES and STBY terminals is shown in Fig. 26. instruction text to the STOP. If the INT? interrupt is masked Table 4 lists the status of each parts of the MCU in each by the miscellaneous register, there is no interrupt request to low power dissipation modes. Transitions between each mode the MCU, so the stop mode cannot be released. are shown in Fig. 27. (Note) __When I bit of condition code register is “I” and interrupt (INT, TIMER/INT;, SCI/TIMER;) is held, MCU does not enter WAIT mode by the execution of WAIT instruction. In that case, after the 4 dummy cycles MCU executes the next instruction. In the same way, when external interrupts (INT, INT) are held at the bit I set, MCU does not enter STOP mode by the execution of STOP instruction. In that case, also, MCU executes the next instruction after the 4 dummy cycles. @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 447
Figure 23. Wait Mode Flow Chart
a HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 Dhaene Stop Oscillator and All Clocks Yes > No to Standby a N Mode <> 2. Turn on Oscillator 4 fait for Time Delay| No. to Stabilize | MRE > he ae “> <> < Load PC from Turn on Oscillator SIFFE, $1FFF it for Time Delay to Stabilize ee Load PC from interrupt Vector Addresses Fetch Instruction Figure 24 Stop Mode Flow Chart @ HITACHI Hitachi America, Ltd, « Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 449
Figure 27. Transitions among Active Mode, Wait Mode, The MCU can use a single instruction (BSET or BCLR) to the byte that follows the operation code. may use a bit within the RAM as a flag or handle a single 1/O dress space so that the direct addressing mode may be utilized. The program shown can activate the triac within a time of addressing instruction requires a length of 3 bytes. ! requires a length of 2 bytes.
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 Table 5 Register/Memory instructions Indexed indexed Booleen/ Condition Opraton tie one earonw|oearome] mie | Sade Jor] « [= Jor] « [- Jor] « [- jor = | - lor] «| - jor] s [- [eT i[nyz[c Leed A trom Memory Loe —fpetsta ete teeters press eeerete tees Peete O Loed Xtrom Memory [tox [ae] [3 feels [4 [re[ 1 [3 [ee] 2 [4 foe] 37s] lefela[aTo Sire Ain Honor ISJENESGIRRESCUEREACHED efalate Store X in Memory sex_| J" {~ fer[2[ ferl a | [rr] 3 [4 Jer! 2 [4 [or] 3 | OBO Med Memory to A OE eters eal ste rsa] + |oe! Oni "Add Memory and Carry TT mi toa aoc _|as|2|2 9) 2 | 4 |o9| AEM4C-8 afelafe|- Subrract Memory | Su8 [ao|2 [2 [80] 2| 3 [co 8} 4 [ro] 1 | eo] 2[aloola[sfa-m-a felelayala ‘Subtract Memory from. al foto | aoe_balaizle a e9fala|siaiaelelas|slamen [eles AND Memory 10 | aN” [al 2 [a [ea] 21 3 [cal cal2taloafats[a-moa_|ele|-i-te OR Memory wih A | ORA__faal2{2[eal2|a|cal ea) 2] 4 [oa] 3] [Arma [elatale Exclusive OR Memory ~ with A 2| 4 [p8| 3} 5 |AgM a vfele Arithmetic Compare A _ with Memory cy a-M afe|s “Arithenetic Compare X ~ wath Memory elejalel: Bit Test Memory with 1 A (Logical Compare) sr las alele “Jump Unconditional IMP pert eet ef tetetetel ° Jump to Subrounne | asa] | eo] 2[s [col 3 [6 fro] s [s Jeo) 2] s joo] 3] [o[elefele ‘Symbols: Op = Operation # = Number of bytes ~ = Number of eycles Table 6 Read/ModifyMrite Instructions ‘Addressing Modes . To [ indesed | ideeed | Condition Operations | Meamonis | iguecis | imoteatxs | Dvect !tNo Of 6-b4 ort joolean/Arithmetic Operation jor] = | Jor] = [Tor] « [for] = | Jor[ =| - [ay [w[z[e Increment we fact [2 Fa facla[s [vel] s [6c 2] 6[Avi-aarxs1-XorMsi-mlele| [lo Decrement [ore Jaa 2 [2 i3a]2|s l7alt [5 |eat2 6 [a-1-aorx-1-xorM-1-mfelels|-le Ci [eta far fa fart] TTL [ata | 6 [00-9 00-Xa Mf lel 8) tLe “Complement [com faalt fa [salva] 7a) t] 8 leat 2] 6 [Ra or x or MoM eletataty Negete ‘00-A-A or OO-K--X - (2's Complement) 6 | or OO—-M-M @lelaiats ERE memrwen [mA pe tree fT Sree ce COO SUED otetaesorses Se C0Og wwensrnes | ono ofa foo] sooo] | Cireeaeer 8 || fe wmmesnen | ae fo} af of alo el s]o [sled [6] Ceara || [|| “Keahmetic Shift Loft ASL [re] 1) (68) 2 | 6 | equal to tsi [efelafala “Test for Negstive ~ ~~ o Zero 1st ‘A=00 oF X-00 or M-00 alate Symbols: Op = Operation # = Number of bytes ~ = Number of cycles | @ HITACHI | 456 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 I
a HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 Table 7 Branch Instructions Operations Branch Test [rls [| [RDN TzTe Branch Aways [aaa [202 | 3 [Noe ——S—=i# fw fe Tew Branch Never [ean [arf 2 [3 [None id fe of @ BranchiFRigher | em’ | [2] efeezeo ite fe lelele Branch F Lower or Same va feet Side fee lere BranchiF Carry Clear [cc | 2a] 2 [alco _—itefelelele (Branch IF Higher or Same) (BHs) | 24 | [3a feo [elelelel ry Branch IF Carry Set Bcs_ | 25 | [ 3 |c=1 felelelele (Branch IF Lower) | 3 [c=1 [elel[elele “Branch Wot Eqwst [ONE | 26 | 2 | 8 [2-0 oooom Branch IF Equal ~ seq | 27 | 2 | 3 |Z=1 [elelelele “Branch IF Half Carry Clear BHcc | 28{ 2 | 3 |H=0 [elelelele Branch IF Half Carry Set BHCS | 29 | H=1 ; elelelele Branch IF Plus BPL N=0 _ jelele Branch IF Minus BMI | 28 | —3 [Net - [elele Branch IF Interrupt Mask | Bit is Clear BMC 2c | 2 | 3 |I=0 ° a ° Branch IF Interrupt Mask iz ~ Bit is Set BMS | 2Dj| 2 | 3 |I=1 ejeleleie Branch (F Interrupt Line ” — is Low BIL 2 | 2| 3 |INt=0 lelelele ° Branch IF Interrupt Line ” is High | BIH 2F ; 2 | 3 |INT=1 Aa eleje Branch to Subroutine BSR 5 |— [elejelele Symbols: Op = Operation # = Number of bytes ~ = Number of cycles Table 8 Bit Manipulation Instructions ‘Addressing Modes — [or [= [=| or [21 | Orrtton Perr NTeye Branch Fetnisset | BRSETAN=O-7 | — |-|—| 2 [3] 5] [Mn=1 [Te] [eta “Branch IF Bit nis clear | BRCLAnin=O-7)| — | —|—[o1+2-n[3[ 5] HH a Serie ter ht fe hee tose Clear Bit n BCL nin=0--7) pee Eee oe ‘Symbols: Op = Operation # = Number of bytes ~ = Number of cycles : @HITACHI ! Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 457
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 Table 9 Control Instructions ‘Addressing Modes 7 Operations Implied Boolean Operation Condition Code op] # | ~ ATTN] z[c Transfer A to X [tax [ert [2 fax Te foo fel e “Transfer X to A” a efefetets “Set Carry Bit [| sec | 1 eo ~ felefefelt Clear Carry Bit CLC 1 o=¢ Te Bae 0 ‘Set interrupt Mask Bit ~~ SEI g8 {4 Tot [elilelele Clear interrupt Mask Bit | CLI | 9A| 1 | 2 [O41 [elolelele Sofware inverpt | swi[ 63. | 1 | 10 — reftfetele Return from Subroutine | ATS | 81; 1] 5] __ [elelelele Return from Interrupt an feof eee eee eset Stack Pinter a 2 No-Operation Nop [eo [1 | ¥ [Advance Prog. Caw. Only fe folelole Decimal Agust A [DAA 8] | 2 | gapamaarey aes oTeCD weer Te Te [ATALA® Stop id es C0 Wit Ss)SCOATC or TT 4a TTTTTTC™C™~™_Cdd@ feo ofoo ‘Symbols: Op = Operation * Are BCD characters of upper byte 10 or mora? (They are not cleared if set in advance.) ‘# == Number of bytes ~ = Number of cycles. Table 10 Instruction Set (in Alphabetical Order) Addressing Modes Condition Code Mnemonic | : | indexed | indexed | indexed | Set/ | Test & Implied _| immediate | Direct Extended! Relative |(No Offser)| (8-81) | (16-Bit) | Clear | Branch c me ee Pe [fetatata a OE CS CSN ASL x ie OSES a a OS CCE er oe ee acl eee etete a a a ee ee 0 ance a [epee te CS | Sa es ee I) Ss a | a ee BiH a OO NS EC a em, | oo. * or [ x | fo» px [ox {UT fefefatate oy Te foo fee oe IE Bc rs re es ee ee : es $f {| fejefelete BNE a aS oe Ss art aS NS A SO SY GO OO DECC) BRA SR ND OOS CS Condition Code Symbols {to be continued) H Half Carry (From Bit 3) © Carry/Borrow 1 1 Interrupt Mask ‘A Test and Set if True, Cleared Otherwise N Negative (Sign Bit) @ Not Affected
2 Zero 7 Load CC Register From Stack
i | @ HITACHI | 458 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300
Table 10. Instruction Set (in Alphabetical Order)
Table 11. Operation Code Map (NOTES) 1. “—" is an undefined operation code.
- The lowermost numbers in each column represent a byte count and the number of cycles required (byte counUnumber of cycles).
- The parenthesized numbers must be added to the cycle count of the particular instruction.
DAA Converts the contents of the accumulator into BCD code. ing sequence. WAIT Causes the MCU to enter the wait mode. For this mode, (i) Reads the contents from appointed address. & PRECAUTION 1—BOARD DESIGN OF write only register such as DDR. When connecting crystal and ceramic resonator with the XTAL BCLR instructions. the board. writing into the write only register. (3) Board design of situating signal lines or power supply lines near ing serial data. 10M © or more mode by executing the WAIT instruction.
HD6305X1, HD63A05X1, HD63B05X1, HD6305X2, HD63A05X2, HD63B05X2 eee eee eee eee @@ PRECAUTION TO USE BSR = a If there is 2nd BSR programmed on the address which is directed xtat [> by first BSR, 2nd BSR may not be executed correctly. For this extat }-—4 reason, BSR should not be programmed on the address which is ES cs directed by first BSR. = If necessary, please program as following. (1) On the address which first BSR directed, NOP instruction HD6305X [7 should be inserted before second BSR. HD6305y (2) Onthe address which first BSR directed, JSR instruction should HDG3POSY be programmed instead of 2nd BSR. BSR LBLI Figure 39 Design of Oscillation Circuit Board \\ i LBL BSR LBL2 = <* ' f a H ca | H ae LBL3 Ty ----2 ----] in viet Signal € exemple of malfunction xtaL [ of 2nd BSR execution an “L ExtTaL[ } ‘ rt ctw BSR L6Lt te 1 io | HD6305K i HD6305¥ LBL1 NOP BD63P03¥ ssh LBL2 | ] LBL2 7 -— Figure 40 Example of Circuit Causing Trouble in Oscillation exemple of counter meswure (NOP is inserted)
1 PRECAUTION WHEN USING BIL/BIH INSTRUCTION BSR LBLI
(1) Execute Instruction after the INT Voltage level has stabilized 1 above Vip or below Vip. 1 (2) INT voltage level needs to be stabilized while BIL/BIH Instruc- LBL1 JsALBL2 tion Execution. | There may be a malfunction by glitch on control signal if ! BIL/BIH Instruction Execution has exercized in unstablized INT 1 signal level. LBL2—-7p— == + ooo )7"1 example of counter measure _ vi SR is used instead of BSA) Vik: it Tt {} a Avoid BIUBIH Instruction Execution @ HITACH! Hitachi America, Ltd. ¢ Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 461