HD63485PS48

HD63485 HITACHI | Alldatasheet

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Technical content

drawing. Incorporating bus driver circuits and a handle a maximum output current Io, of 24mA. DRAM (dynamic RAM) interface, the GMIC allows Table 1 describes the pins. Figure 1. Pin Arrangement

Memory Cycle (MCYC): The MCYC input address ‘MA1, MAO), the GMIC can directly indicates the ACRTC’s frame buffer access timing, control up to four memory banks. Up to eight MCYC is low when the ACRTC is in the address memory banks can be controlled by externally cycle. and high when the ACRTC is in the data decoding the address ADRC: and WE3-WE0. cycle WES.WEO are bus driver that can handle a Draw (DRAW): The DRAW input indicates maximum output current Iu. of 24 mA, whether the ACRTC memory cycle is a drawing __ cycle. DRAW is low during drawing cycle, and high Output Enable ‘OE): The GMIC_outputs the otherwise. The GMIC uses DRAW to recognize DRAMSs' output timing signal on the OF output. OF display cycles, and also to generate DRAM control is a bus driver that can handle a maximum output signals (WE3-WE 0). current Ip, of 24 mA. Memory Read (MRD): The MRD input controls Frame Buffer Address (FA 7-FA 0); The GMIC data transfer between frame buffers and the outputs the multiplexed DRAM address on FA 7. ACRTC. The ACRTC pulls MRD high when it FA0. How the address is multiplexed depends on reads data from the frame buffer, and low when it the incerment mode «table 4.. FA7-FA 0 are bus writes data drivers that can handle a maximum output current In, of 24 mA. The only exception is when the ACRTC is in superimpose display mode dual access mode 1). In Address (ADRA-ADRC!: The GMIC latches superimpose display mode, the ACRTC inputs a low three address bits other than those delivered on the level and reads data from a frame buffer in order to FA7-FA 0 bits and outputs them on ADRA-ADRC indicate that the display cycle is for a superimposed in one memory cycle. screen (window screen'. __ __ GVAC Control Signals Address Storbe (AS): The AS input is a latch timing signal for the memory address sent from the Shift Clock Enable ‘SCKE?: The SCKE output ACRTC. Additionally, AS indicates whether controls the GVACs' video signal generation shift memory is begin accessed. For example, for register. It outputs a control signal for zooming horizontal zooming. the SLDB signal is provided at according to the horizontal zoom signal ‘attribute a lower frequency. corresponding to the lower control signal from the ACRTC. The GVAC frequency of AS. performs horizontal zoom by halting the clock when SCKE is low. Memory Address Bus (MAis-MAo): The MAy. MA. inputs are address signals for frame buffer Shift Load Signals ‘SLDB, SLDW): The SLDB access, provided by the ACRTC. and SCDW outputs are load signals for the display _ data of the video signal generation shift register. Horizontal Syne ‘HSYNC): The HSYNC input The SLDB output is used for single access mode. is a DRAM refresh cycle control signal to hori: dual access mode (), and dual access mode 1, The zontally synchronize CRT displays. The GMIC SLDW output controls the window screen in dual ; performs RAS only refresh when HSYNC is low access mode 1 and DRAW is high when AS pulses are input. Display Cycle (DSPCYC): The DSPCYC output Setting HSYNC low informs the GMIC of the end indicates whether a memory cycle is a display of a raster display, Usually, the ACRTC’s HSYNC cycle. output supplies this input. DSPCYC is high during display cycle, and low Frame Buffer Access Signals otherwise. Row Address Strobe (RAS): The GMIC outputs KS RAW MRO cycle mode memory cycle 99010 the DRAMs’ RAS timing signal on the RAS output LL Drawing Write Memory Write Column Address Strobe (CAS): The GMIC LJ L_H_ Drawing Read_Memory Read _t-_ outputs the DRAMs’ CAS timing signal on the CAS iow HL Window Screen Display Memory Read__H output. pulse 4 =H Backscreen Display Memory Read H Write Enable (WE3-WE0): The GMIC outputs Hox x - No Acesss__ it the DRAM’s WE timing signals on the WE outputs Since WE3-WE0 are controlled by the incerment mode (IM 1, IM 0) and by the lower two bits of the @ HITACHI Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 263

on the dot clock (DOTCK) supplied to the GMIC ACRTC. DOTCK depends on the speed and resolution of the DOTCK frequency is limited to 32 MHz. foorch= (Horizontal resolution (pixels/raster) ]/ DRAM access signals RAS, CAS, WE, and OE. RAM, timeshared according to RAS and CAS. Figure 4. DOTCK Division

Table 7 shows the output condition of the write be varied for scrolling. Video Shifter Shift Load Signals (SLDB, amount in one display cycle. to-serial conversion circuit). SLDB is used for base is output earlier by one dot clock. screen in single access made. dual access mode 0. When WSS= in single access or dual access ACRTC and the corresponding scrolling amounts. horizontal scroll dot attribute control signals 3.2 CRT Interface. Table 8. WSS, Access Mode, Shift Load Signals

0 Single access, Scrolling amount is permitted No output

1 Dual access 1, Scrolling impossible Scrolling amount is permitted

Figure 8. Shift Load ‘SLDB, SLDW) Output Timing

Table 9. ACRTC Attribute Codes and Scrolling Amounts adress bits are used (MAI for 64-bit shifts, MAQ for 32-bit shifts), they must not be changed during one horizontal period. Table 10. GMIC Division Ratio and GVAC Shift Lengths Note: This mode cannot be used directly because the maximum shift register length is 32 dots.

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Figure 9. SLDB Timing (Single Access Mode) Figure 10. SLDB Timing (Dual Access Mode 0)

Window Dsplay———} | | toe TAA mo eae, be le ie be bs hy be he fe fe | 2 R a mS ST EES tt eg sone Ht! +44 sone Hh" | | o> , | (WSS =0} }[+0 Scroll) SUDB i | | L+n Scroil] | i SLOB ] | | 1 | | IWSS= 1] | | | [+0 Scroll] | i i SstOW | i stow | | R: Refresh Cycle Bn: Base Display Cycle A: Attribute Cycle Wn: Window Display Cycle D: Drawing Cycle Figure 1i. SLDB and SLDW Timing (Dual Access Mode 1) @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 273

Figure 14. Zoom Display Timing | Dual Access Mode 1,Double Zoom

when display data is provided in the same manner the GVAC video signal generation shift register. completed, low-level output are provided until the the dot clock frequency to set the zoom scale. next display cycle. Figure 15 shows triple zoom (HZ=0011) timing. Table 11. Attribute Codes and Zoom Scales Figure 15. Triple Zoom Timing

Absolute Maximum Ratings (All voltages referenced to Vss = 0 V) Item Symbol Rating Unit Supply voltage Voc = 0.3 to + 7.0 v Input voltage Vin ~ 0.3 to Vec + 0.3 v Output voltage Vout 55 v Operating temperature Tope 0 to + 70 °c Storage temperature Tstr = 55 to + 150 °c Notes: Using an LS! beyond in maximum ratings may result in its permanent destruction. LSIs should usually be operated under the recommended: operating conditions. Exceeding any of these conditions may adversely affect its reliability Recommended Operating Conditions (All voltages referenced to Vss = 0 V) Item Symbol Min Typ Max Unit Input voltage high ssi‘ Operating temperature Tope 0 25 70 °c

Electrical Characteristics

DC Characteristics (Vcc = 5.0 V + 5%, Vss = 0 V, Ta = OC to70 unless otherwise noted! Item ‘Symbol Min Max Unit Test Condition Input voltage high Via 22 Vee Vv Input voltagetowss—i“‘i‘wSSS!!OC OCCU fn = —18mA Output voltage ‘ADRA-ADRC, SLDB, Vou 27. Veo = 4.75V, high SLOW, DSPCYC, SCKE, lox = —400 mA 2CLKOUT RAS, CAS, OE low = -15 mA Output voltage ADRA-ADRC, SLDB, Vou 05 v Veo = 4.75 V, low SLOW, DSPCYC, SCKE fo. = BMA 2CLKOUT WE3-WEO, FA7-FAO, Vou 05 v Voe = 4.75 V, RAS, CAS, OF lo, = 24mA W=27V v=04V Output short circuit current tos =40 -120 mA Veo = 5.25 V Current consumption lee 160 mA Voc = 5.25V Input capacitance Cin 10 pF @HITACHI 278 Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

AC Characteristics (Vcc = 5.0 V + 5%, Vss = OV, Ta = 0 to + 70)

32 MHz 48 MHz 64 MHz

No Item Symbol Min = Max = Min = Max = Min Max Unit Figure DOTCK operation f 32 48 64 MHz frequence 2D DOTCK cycle time tc 31.3 20.8 15.6 ns 18

2 DOTCK high level thw 12 9 6 ns

__ pulse width 3D DOTCK tow level tw 12 9 6 ns pulse width @ DOTCK rise time tr 5 5 5 ns 2, © DOTCK fall time tr 5 5 5 ns © 2CLKOUT delay tecuxo 24 17 14 ns 19 D MCYC setup time tucves te+ tet te+ ns 20-23 20 20 20 ® MCYC hold time tucyou 0 ° 0 ns @ HSYNC setup time Huss to + te + to + ns 20-22 20 20 20 4& SYNC hold time tse 0 0 0 ns 23 4} MRO setup time turos te+ te+ to+ ns 20-22 20 20 20 i MRD hold time tro 5 5 5 ns 20, 21, 23

43 DRAW setup time toraws, to+ te+ te+ ns 20-22

i DRAW hold time torawe 5 5 5 ns 20, 21, 23 @& AS setup time tass tet tet te+ ns 20-23 (CDM = 01) 25 25 25 AS setup time tass ato + 2te + 2te + ns (CMD = 10) 25 25 25 AS setup time tass dtc + ate + ate + ns (CDM = 11) 25 25 25

38 AS pulse width tasw 25 25 25 ns

i? Memory address tas, 10 10 10 ns 20-23 setup time oe d@ Memory address tan 5 5 5 ns hold time ® Attribute code tacs 20 20 20 ns 23 setup time ® Attribute code tach 5 5 5 ns hold time @ RAS setup time trss to — te- te- ns 20-23 (CDM = 01) 20 20 20 RAS setup time trss 2te - 2tc ~ ate — ns (COM = 10) 20 20 20 RAS setup time trss Ate — ate — ate — ns (CDM = 11) 20 20 20 % RAS hold time trsn 3 3 3 ns @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 279

AC Characteristics (cont) 32MHz _ 48 MHz 64 MHz No Item Symbol Min = Max = Min = Max = Min Max_—_Unit ‘Figure ® CAS delay time teaso te- te- te — ns 20, 21 (CDM = 01) 7 7 7 CAS delay time tcasp 2tc - atc - 2te - ns (CDM = 10) 7 7 7 _ CAS delay time tcaso atc — 4tc — 4te — ns (CDM = 11) - 7 7 7 . @A CAS delay time tcasoH 20 20 15 ns from 2CLK a a @® CAS hold time toasH EB s 5 ns @ Memory address twas to + te+ to+ ns 20-23 setup time (CDM = 01) 25 25 25 a Memory address twas 2te + 2te + 2te + ns setup time (CDM = 10) 25 25 25 Memory address twasc ate + 4te+ Ate + ns . setup time (CDM = 11) 25 25 25 % Row address tras 0 0 0 ns setup time . __ @ Row address hold time — tran te/2 te/2 te/2 ns Row address hold time tran te te te ns Row address hold time tray 2te 2te ate ns @® Column address teas 0 te) 0 ns 20, 21 setup time ® Column address toa 0 ° ° ns hold time ® OE delay time tozo 20 20 20 ns 20 @ OE hold time toeH 3 3 3 ns @ WE delay time tweo 5 30 5 30 5 30 ns 21 ® WE hold time twen 3 3 3 ns ® Address delay time tao 30 30 30 ons ® Address hold time ten 0 ) 0 ns B® SCKE delay time tscko 5 4 5 7 5 4 ns 18 @ SLO delay time ts. 5 2605 75 14 ns @ DSPCYC delay tospon 40 40 40 ns 20 time from AS @A DSPCYC delay tosPoo 20 20 20 ns time from DRAW _ ® DSPCYC hold time tosPH 5 5 5 ns ee Se @HITACHI 280 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 # (415) 589-8300