HD6301V1

HD6301V1 HITACHI | Alldatasheet

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HD6301V1,HD63A01V1, The HD6301V1 is an 8-bit CMOS single-chip microcom- puter unit, Object Code compatible with the HD6801. 4kB HD6301V1P, HD63A01V1P, HD63B01V1P. ROM, 128 bytes RAM, Serial Communication Interface (SCI), parallel 1/O ports and multi function timer are incorporated in the HD6301V1. It is bus compatible with HMCS6800. Ex- ¥ ecution time of key instructions are improved and several ve new instructions are added to increase system throughput. " The HD6301V1 can be expanded up to 65k bytes. Like the Ah] HMCS6800 family, I/O level is TTL compatible with +5.0V ryt single power supply. As HD6301V1 is fabricated by the ad- yy" vanced CMOS process technology, power dissipation is extreme- . ye ly reduced. In addition to that, HD6301V1 has Sleep Mode and y i Standby Mode at lower power dissipation mode. Therefore (DP-40) flexible low power consumption application is possible. HD6301V1F, HD63A01V1F, HD63B01VIF = FEATURES oe © Object Code Upward Compatible with HD6801 Family — @ Abundant On-Chip Functions Compatible with HD6801V0; 4kB ROM,128 Bytes RAM, 29 Parallel 1/O Lines, 2 Lines of ZG wa Data Strobe, 16-bit Timer, Serial Communication Interface y we © Low.Power Consumption Mode: Sleep Mode, Standby Mode ee © Minimum Instruction Execution Time (FP-54) _ Mas (© 1MH2}, 0.67us (f= 1.5MHz), 0.5ys (f-2MHz) HD6301V1CG,HD63A01V1CG,HD63B01V1CG ®@ Bit Manipulation, Bit Test Instruction © Protection from System Upset: Address Trap, On-Code Trap © Up to 65k Words Address Space © Wide Operation Range >_> Vee=3 to 6V (f=0.1~0.5MHz). > ial f=0.1 to 2.0MHz (Vcc=5V +10%) = TYPE OF PRODUCTS Type No. Bus Timing {CG-40) HD6301V1 1 MHz HD6301V1CP, HD63A01V1CP HD63A01V1 | 1.5 MHz HD63B01V ICP HD63B01v1 | 2 MHz ll PROGRAM DEVELOPMENT SUPPORT TOOLS © Cross assembler and C compiler software for IBM PCs and compatibles © In circuit emulator for use with IBM PCs and compatibles pa (cP-52) HD6301V1L, HD63A01V1L HD63BO1V1L (CP-44) @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 41

a HD6301V1, HD63A01V1, HD63B01V1 = BLOCK DIAGRAM a > we - Dow»t Sic? Essté see a | cru ll ms Coan EE HER fe) pe Port K)) MUX » >» (th pee pS 3 ma Ss | Dim names, Ess HH SC2 Timer SC i; a Pao Pio Pai ddre Prt Pas Port Port Pre P44 4 1 Pia Ps P45 Pas Pig Paz P17 128 x8 4k x8 RAM ROM | @ HITACHI | 42 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

————s HD6301V1, HD63A01V1, HD63B01V1 = PIN ARRANGEMENT ©@ HD6301V1P, HD63A01V1P, @ HD6301V1F, HD63A01V1F, © HD6301V1CG, HD63A01V1CG, HD63B01V1CG HD63B01V1P HD63B01V1F “sifo kg « ize coe: eee iRE PETE xracGq] B sc. 23553 og2e TAS Sia R RN er extal FF sc, doggemouoed CABBIE) Bis BS SSRs wi pa P= <nc > fe)<we> Pv pes earn ina, G] fae, < ne >C} fa}<nc> P30 [57 al Pas es G] fa Ps RES (+) [e<nc> <3 be rev] fae, == «Ney mer $938 Bara P, (8 fg Pp. Prof] =) Pos sc. [30t 2} Par eG Rae. ae ion in Sav. PO bd P eneley oe vest 7} foe. Pe OF Bg P.. Pees ee exta fa pa P. Ba r., cs] one 35 8} Pas et Fae. { in 33 fg] ps Pld FP. EEE EEE] TSLIRM fet (oT (S1 (E81 Fen Pa fat og pe. faced 883d Epéeiiscce | BI vec (Top View) (Top View) (Top View) © HD630V1CP, HD63A01ViCP © HDG301V1L, HDG3A01V1L, HD63B01V1L HD63B01V1CP z Zaz =2 25 <6 ESES cSa5 ges hed s Si.sse NONANNANANNONAo ee Reesor ges ees q bese no Ce 46 [51 NC aTey Cho 4D Pa ae Bese) Poo G11 3B Pau rd Bree Py Ghz «2 No 2G Bp Pp Es MEF Pas Pa hed Ps Ch 4055] Pog Hone Bre Pg O15 39fD P57 H Be. seche att reg Bre Chr 75 P. - ay Chis 36) Pa re G pre fa the Sane CTT TT TT See PE SS8Esay (Top View) (Top View) @ HITACHI Hitachi America, Ltd. Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 43

HD6301V1, HD63A01V1, HD63B01V1 |= ABSOLUTE MAXIMUM RATINGS ec a Un Supply Voltage Vee 0.3 ~47.0 l Vv Input Voltage Vin .3~ Vect03 a Opetirg Tepe Tor ° (NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field. But be careful not to apply overvoitage more than maximum ratings to these high input impedance protection circuits. To assure the normal operation, we recommend Vin, Vour : Vss & (Vin OF Vout) & Vcc- = ELECTRICAL CHARACTERISTICS © DC CHARACTERISTICS (Voc = 5.0V10%, Vsg = OV, Ta = 0~+70°C, unless otherwise noted.) Tem [Grebo [Test Condition —[ min [wo [max] Unt [Vec-os] - |. Input “High” Voltage | EXTAL Vin [Vecx07| - | ig5| V Input "Low" Voltage [Allinpus | Va | 0 | - Joa Tt Vv Input Leakage Current | NMI, IRO,, AES, STBY| Min! | Vin=0-5~Vec-05V| — | — [1.0 | A Three State (off-state) Pio~Piz, Pro~Pas. . =0.5~' - A Leakage Current Pyp~Pss, Pag~Pey TSA | lIts1!_ | Vin =0.5~Veo -O.5V) ia Output “High” Volt v, [ton =-20A | 24 | -[- | v - OM Tron ==10HA | Vec-0.7[ - [= Tv Output “Low” Voltage | Ail Outputs [ Vor [lo=16ma | - | ~ Joss] v Vin OV, f= 1.0MHz, ’ n= OV, , F ede Vic (STBY) = 0~06 Non Operati 1 Vin (RES) = A Standby Current jon Operation cc Vee -0.5-Ve,¥ H Vit (RES)= 0~0.6V, current Dissipation* [Oneratingtf=imHz"*}| - | 60 [100] * Viyg min = Voc~1.0V, Vi_ max = 0.8V ** Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typ. or max. vaiues about Current Dissipations at f = x MHz operation are decided according to the following formula; typ. value [f =x MHz) = typ. value (f = 1MHz) x x mex. value (f =x MHz) = max. value (f = 1MHz) xx (both the sleeping and operating) | @ HITACHI | 44 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300

HD6301V1, HD63A01V1, HD63B01V1 © AC CHARACTERISTICS (Vcc = 5.0V£10%, Vss = OV, Ta = 0~+70°C, unless otherwise noted.) BUS TIMING dition | rin [yp | max] min [typ | max | min | typ | max| Oyele Time [1] = | t0fossel— | ro [os [- | 10] us figrevee ewe [rw | [azo] = | - | so[- | - [ovo] - | | oh * Address Strobe Rise Time [tase | [= |= | 20] - {= | 20] - |= [20] ns Address Strobe Fall Time [= [= | 20] = {= | 20f- [= [20] ns Address Strobe Deley Time" [taso | | @0| — | ~ | ao|— [~ | 20] - [= | m Enable Rise Time [= [= {| 20] {= | aot [— [20] os Enable Fall Time [ex | [= [=] 2of- [- | 2of— [- [20] rs Enable Pulse Width “High” Level" |PWen | | 450| ~ | - [300 [- | - [220] - | - | ns Enable Pulse Width “Low” Level”|PWer | | 480| ~ | - [300 [- [- [2a0| ~ | = | rm co ee ime werent fp, PERBEE pats ‘Address Delay Time for Latch> [taou _| Sees ese ns oat Sev tne P= fo |= P= Yo = [= Poe [Read [tun _| [- | as i cc Ce Rott tas T= Address Set-up Time for Latch* [eo] = [= | aol- [- | 20] - | - | os Address Hold Time for Latch | sof - [= | ao[- |= | aol- |= | ns Address Hold Time fan | = [of = | = [20 |= [2o[= [= | is Ay~Ay Sevup Tne BetowE* [txsw | [ROP = | = [110|= [=| eo[=[- | mw wi mle fel= l- | le Access Time [= |= [eso|- [= | se5[— | - [270] ns Oscillator stabilization Time [tac [Fig 10/ 20] — | - | 20[- |= [ 20)- | - | ms Prema Gone! St Ti ris 11/200] — | — [200 |= |= [200] == [m ‘These timings chenge in epproximate proportion to teye. The figures in this characteristics represent these when teye is minimum (= in the highest speed operation). PERIPHERAL PORT TIMING em dition | min [typ | max| min [typ [max] min [ typ | max] Sipe” | e224 [vone [rm [amo] ~ | ~ [zoo] ~ | - [20] - | - | ToS” | for2.34 [ton [rea] 00] — | - [zoo - | ~ [amo] = | | Delay Time, Enable Positive see elo [ot | = : Transition Gmaew eet” [ow [ree] - |= [em | - [| -|- [oe Transition to OS3 Positive ns Transition Delay Time, Enable Nese] port 1, tive Transition to Peri | 2°34 | tewo ns ps Sah la Wi — Sees eee Input Strobe Pulse Width [tewis_| Fig. 6 | 200] ns Input DataHoldTime | PortS [tm | Fig.6[ 180] - | — [reo] - | - [aso] - [- | ns Input Data Setup Time | Ports [ts [Fia@[ of - | - | of-[-] o]-[- [rs * Except Pay i @ HITACHI | Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 45 i

a HD6S0IVi, HD6SAOIVi, HDSSBOIVE TIMER, SCI TIMING fn em ition | rein [tye | max min] typ [ max] min] evo | max| Timer input Pulse Width [wr | | 20[ =| = [20] — [ao] - | - [oe Delay Time, Enable Positive t Fig. 7 | +00] ne Transition to Timer Out Too ris: SCI Input Clock Gycle [tre | | 20] = | = [2of -[- [aol - | - [re SCI Input Glock Pulse Width | trwscx| | 04 [ - [06 [oa] - [os [oa] - [06 [tee MODE PROGRAMMING 1" i _ Sree eon |e [ve [max in [ve Tox min] wo | may RES “Low” Pulse Width [s {== [se [= Te fs [= J = [ewe Mode Programming Setup Time | twes Fis. 8] 2 |- | — [2 |- | —- [2 |- | - [tre ‘Mode Programming Hold Time | ten _| [sso] - | — [iso] - | = [150] - T - | ns tee Address Strobe av tr) oav 2av Enable ity co TG alll : nD, /, aly. tam ae meu Wate 7 7a "YW 24aV O~Dy hear » YK we ) MN oev Dave vai |) cu Rass I, Tov acca No Vaid Figure 1 Expanded Multiplexed Bus Timing | @ HITACHI | 46 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 (415) 589-8300

quency. It will drive two LS TTL load and 40pF. Figure 12. Crystal Interface Table 1 Interrupt Vectoring memory map mode, see the Standby section. for at least 3 system clock cycles. From the third cycle. all SFFFO to SFFF7. code register, if being set, will keep the both interrupts off. program control register. during suspension, that IRQ: is ignored. starts (see Table 1), interrupt is invoked. This interrupt has priority next to RES.

This signal controls [$3 interrupt and the latch of Port 3. indicating effective data is on the I/O pins. The timing chart for _than 2,0V for logic ““1” and less than 0.8 V for logic “O”. Figure 2. of these three pins during reset are latched into the upper 3 bits by address strobe as shown in Figure 18. Thereby, I/O Port 3 Timer output. Addresses of each port and associated Data Direction Registers Data Direction Register. are reset. input strobe signal.

HD6301V1, HD63A01V1, HD63B01V1 Port 3 strobe and latch timing is shown in Figs. 5 and 6 —_port becomes inputs, In order to use these pins as addresses, respectively. they should be programmed as outputs. When all of the eight 1/O Port 3 Control/Status Register is explained as follows: _bits are not required, the remaining lines can be used as 1/O lines (input only). W/O Port 3. Control/Status Register Expanded Multiplexed Mode (Mode 0, 2, 4): In this mode, Port poe os « 3 7 so 4 becomes output for upper order address lines (As to Ais) ee PET T regardless of the value of data direction register. S000F [FLAG TENABLE [ENABLE The relation between each mode and I/O Port 1 to 4 is Bit 0 Not used. summarized in Table 3. Bit 1 Not used. Bit 2 Not used. = MODE SELECTION Bit3 LATCH ENABLE. The operation mode after the reset must be determined by Bit 3 is used to control the input latch of Port 3, If the bit is the user wiring the Pao, Pai and P22 pins externally. These three set at “1”, the input data on Port 3 is latched by the fallingedge _pins are lower order bits; 1/0 0, I/O 1, I/O 2 of Port 2. They are of IS3. The latch is released by the MCU read to Port 3; now —_ latched into the control bits PCO, PCI, PC2 of I/O Port 2 regis- new data can be latched again by IS3 falling edge. Bit 3 is _ ter when reset goes “High”. 1/O Port 2 Register is shown below. cleared by a reset. If this bit is “O", IS3 does not affect 1/0 Port 3 latch operation. Port 2 DATA REGISTER Bit 4 OSS (Output Strobe Select) This bit identifies the cause of output strobe generation: a y 6 s 4 3s 7 4: write operation or read operation to I/O Port 3. When the bit is $0003 [ra] |r [vee [vn [103 | v0 [100] cleared, the strobe will be generated by a read operation to Port 3. When the bit is not cleared, the strobe will be generated by a write operation, Bit 4 is cleared by a reset. An example of external hardware used for Mode Selection is Bit 5 Not used. shown in Fig. 13. The HD14053B is used to separate the pe- Bit 6 IS3 TRO: ENABLE. ripheral device from the MCU during reset. It is necessary if If this bit is set, IRQi interrupt by [S3 Flag is enabled. the data may conflict between peripheral device and Mode Otherwise the interrupt is disabled, The bit is cleared by a _generation circuit. reset. No mode can be changed through software because the bits Bit 7 IS3 FLAG. 5, 6, and 7 of Port 2 Data Register are read-only. The mode Bit 7 is a read-only bit which is set by the falling edge of IS3 selection of the HD6301V1 is shown in Table 4. (SC1). It is cleared by a read of the Control/Status Register fol- The HD6301V1 operates in three basic modes: (1) Single lowed by a read/write of I/O Port 3, The bit is cleared by reset. Chip Mode; (2) Expanded Multiplexed Mode (compatible with the HMCS6800 peripheral family), (3) Expanded Non Multi- Expanded Non Multiplexed Mode (mode 1,5) plexed Mode (compatible with HMCS6800 peripheral family). In this mode, Port 3 becomes data bus. (Do ~ D7) Expanded Multiplexed Mode (mode 0, 2, 4, 6) © Single Chip Mode (Mode 7} Port 3 becomes both the data bus (Do ~ D7) and lower bits In the Single Chip Mode, all ports will become 1/O. This is of the address bus (Ao ~ A7). An address strobe output is “High” shown in Figure 15. In this mode, SC1 , SC2 pins are configured while the address is on the port. for control lines of Port 3 and can be used as input strobe (IS3) and output strobe (OS3) for data handshaking. © 1/0 Port 4 This is an 8-bit port that becomes either I/O or address © ‘Expanded Multiplexed Mode (Mode 0, 2, 4, 6) outputs depending on the selected operation mode. In order In this mode, Port 4 is configured for 1/O (inputs only) or to be read accurately, the voltage at the input lines must be address lines. The data bus and the lower order address bus are greater than 2.0V for a logic “1”, and less than 0.8V for a logic multiplexed in Port 3 and can be separated by the Address “0”. For outputs, each line is TTL compatible and can drive one Strobe. TTL load and 90pF. Function of Port 4 for each mode is Port 2 is configured for 5 parallel 1/0 or Serial 1/O, or Timer, explained below. or any combination thereof. Port | is configured for 8 parallel Single Chip Mode (Mode 7): Parallel Inputs/Outputs as pro- I/O. In this mode, HD6301V1 is expandable up to 65k words grammed by its associated data direction register. (See Fig. 16). Expanded Non Multiplexed Mode (Mode 5): In this mode, Port 4 becomes the lower address lines (Ao to Ax) by writing © @ Expanded Non Multiplexed Mode (Mode 1, 5) “I"s on the data direction register. After reset, this port In this mode, the HD6301V1 can directly address HMCS6800 becomes inputs. In order to use these pins as addresses, they peripherals with no address latch. In mode 5, Port 3 becomes a should be programmed as outputs. data bus, Port 4 becomes Ao to Ar address bus or partial When all of the eight bits are not required as addresses, the address bus and I/O (inputs only). Port 2 is configured for a remaining lines can be used as 1/O lines (Inputs only). parallel 1/O, Serial 1/O, Timer or any combination thereof. Expanded Non Multiplexed Mode (Mode 1): In this mode, Port Port 1 is configured as a parallel 1/0 only 4 becomes output for upper order address lines (As to Ais) In this mode, HD6301V1 is expandable to 256 locations. regardless of the value of the direction register. In mode 1, Port 3 becomes a data bus and Port 1 becomes Expanded Multiplexed Mode (Mode 6): In this mode, Port 4 Ao to Ax address bus, and Port 4 becomes As to Ais address becomes the upper address lines (Ae to Ais). After reset, this bus, @HITACHI Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 589-8300 51

HD6301V1, HD63A01V1, HD63B01V1 HADOSOLVI, HDOSAUIVI, BMOSBUIVE In this mode, the HD6301V1 is expandable to 65k bytes address bus in Port 3 in the expanded multiplexed mode, with no address latch. (See Fig. 17). address bits must be latched. It requires the 74LS373 Trans- parent octal D-type to latch the LSB. Latch connection of © Lower Order Address Bus Latch the HD6301 V1 is shown in Figure 18. Because the data bus is multiplexed with the lower order Veo a | (Pct) et [Tt co ae Oo ton __JNO140538 Note 1) Figure of Mode 7 c 6, 6, 6 oae 2) RC~Reset Constant | bana 3) R, 10k Figure 13 Recommended Circuit for Mode Selection Veo Truth Table g Yoo Control ingot lano ; a ee stn 3 inary to 1-01 anibet t BT cattle, [J Decoder with tone Tea] A] wo10638 Be Inhibit POOR o_jelols] alle, Vss OVee @ folio, vil xo a TT rex o {rfofot zlvax. vio st o [rfolrT alex, Y,o—— te Y 0 er ete x i = 2,0 £3 o [iftiet aly). z oz 1 bbb Figure 14 HD140538 Multiplexer s/De-Multiplexers Yee Yee

9 Enable

cae 2 ° AM & = __ TH Onm STy © © IRQ, SB o- 0 180, AES o—>|n06301V1 ai wie nossa wan rea Pott ons Ponsa <— K_> Port 3 ‘Address Strobe ] 4/0 Strobes Port 2 Porta

5170 Lines

Port Port 2 <— K—»> 8 Adavess Bo tines < K > Silo Lines sci tines sct Tuner 81/0 Lines ves Timer Vss {inputs Only? Figure 15 HD6301V1 MCU Single-Chip Mode Figure 16 HD6301V1 MCU Expanded Multiplexed Mode @HITACHI | 52 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 i

8 Parallel 1/0 <—) kK» 8 Data Lines To B Address Lines <I = 8 Data Lines

5 Parallel 1/0 8 Address yen

Table 3. Feature of each mode and lines

HD6301V1, HD63A01V1, HD63B01V1 HVOSUING, inves Table 4 Mode Selection Summary °, Pe, Pe Interrupt Operating wwe [in | fen | Boo | nom [mom | verte | a | ts Ee a a eT wpe Tit Multiplexed/Partiel Decode Ea a [ Waux(4) | Non-Multiplexed/Pertia! Ovcode Ce a [MUX |" Muttiplexed/RAM Fe es es ae a pay [et ux | Muttiptexea Ram yop te Taw [eat ye mux | Non-Muttiplexed CS Ss OS Os LEGEND (NOTES) 1) = Internal 1) Internal RAM is addressed at $0080. E — External 2) Internal ROM is disabled. MUX — Multiplexed 3) Reset vector is external for 3 or 4 cycles after NMUX —— Non-Muttiplexed RES goes “high”. L — Logic “0” 4) Idle lines of Port 4 address outputs can H = Logic "1" be assigned to Input Port. = Memory Map The MCU can provide up to 65k byte address space depending on the operating mode. Fig. 19 shows a memory map for each operating mode. The first 32 locations of each map are for the MCU’s internal register only, as shown in Table 5 Table 5 Internal Register Area Repate Taare Port 1 Date Direction Register** 00° Port 2 Date Direction Register or ort 1 Oate Reguter 2" Port 2 Onte Repater 03 Port 3 Data Direction Register oars Port 4 Date Direction Register ose" Fort 3 Date Regute 06+ Port & Date Regater or Ter Control and Status Rogiter os Counter (High Byte) 08 Counter (Low Byte oA Output Compare Register (High Byte) 08 Output Compare Regater (Low Bytel oc Input Capture Repater {High Byte) 00 Input Capture Reputer {Low Byte oe Port 3 Control and Status Register oF Rate and Mode Control Register 10 Trarumt/Recewe Control ang Status Reguter | 11 Aecene Onte Register 2 Tramumut Oate Repater 2 RAM Control Regater 1 Reread tsa External address in Modes 0, 1, 2, 4, 6; cannot be sccetied in Mode 5 * External address in Modes 0, 1.2, 4 see" t= Output, 0 = Input @HITACHI 54 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300

HD6301V1, HD63A01V1, HD63B01V1 HO6301V1 HD6301V1 Mode Mode Multiplexed Test mode Non-Multiplexed Partial Decode $0000!) OGY. $0000 Wy soot YY -w:e0 reason soote Wf | Inceroal Registers | __fexrnar memory soace } |} exer Memory Soace $0080 \\y $0080 y Yyy SOOFF s SOOFF a | External Memory Space External Memory Space $000 (NOTES) (NOTES 1) Encludes the folowing addresses which may be Excludes the following addresses which may be used externally $04, $05, $06, $07 and SOF used externally, $00, $02, $04, $05, $06, $07 2) Addresses SFFFE and SFFFF are considered nd SOF. 2) Atter 3 of 4 CPU cycles, there must be no overlapping roving the data bus with more than one devee 4) Thus mode s the only mode which used for Figure 19 HD6301V1 Memory Maps @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 55

HD6301V1, HD63A01V1, HD63B01V1 HD6301V1, HDGSAQIVI, HDOSBUIVE HD6301V1 HD6301V1 HD6301V1 Mode Mode Mode Multiplexed/RAM Non-Muitiplexed/Partial Oecode $0000 px Yip) $0000 Wi) | Internal Registers so01F ZA: Internat Registers sooir # 4 ' |_|}. exert Memory Sone scoes Y/ internal RAM SooFF | ne Ram score ddd soreo i External Memory Space SOIFF External Memocy Space Unugabte $000 Internal ROM SFFFF SFFFE Internat Interrupt Vectors $07, SOF ‘externally. (io be continued) Figure 19 HOD6301V1 Memory Maps i @HITACHI | 56 Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

63011, HDSSAOIV1, HDESBOIVI Multiplexed/Partial Decode Single Chip $0000 H Internal Registers S000 Internal Registers so080 $0080 sFo00p $F000 Wj; (NOTE) Excludes the following address which may be Used externally: $04, $06, SOF. Figure 19 HD6301V1 Memory Maps @ HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300 57

HD6301V1, HD63A01V1, HD63B01V1 = PROGRAMMABLE TIMER . The HD6301V1 contains 16-bit programmable timer which Soo woe Hon Wee may be used to make measurement of input waveform. In iin addition to that it can generate an output waveform by itself. e es For both input and output waveform, the pulse width may vary Counter : ARB from a few microseconds to several seconds. ' : The timer hardware consists of (SAE3 written to the counter? + an 8-bit control and status register +a 16-bit free running counter Figure 21 Counter Write Timing +a 16-bit output compare register, and +a 16-bit input capture register © Output Compare Register ($000B:$000C) A block diagram of the timer is shown in Figure 20. This is a 16-bit read/write register which is used to control an output waveform. The contents of this register are constantly being compared with current value of the free running counter, When the contents match with the value of the free running counter, a flag (OCF) in the timer control/status register 100.06 (TCSR) is set and the current value of an output level Bit (Se: | ges) Get (OLVL) in the TCSR is transferred to Port 2 bit 1. When bit 1 se reve of the Port 2 data direction register is “1” (output), the OLVL value will appear on the bit 1 of Port 2. Then, the value of Out- put Compare Register and Output level bit may be changed .. for the next compare, [omer] [erowe] The output compare reyster is set to SEFFF during reset. The compare function is inhibited at the cycle of writing Treo | Cet to the high byte of the output compare register and at the core Too [eros koefood em] cycle just after that to ensure valid compare. It is also inhibited laoavee fic in same manner at writing to the free running counter. ca r—_ an In order to write a data to Output Compare Register, a Som double byte store instruction (ex. STD) must be used. UYUY UO] a LPY Hi © Input Capture Register ($000D:$000E) Suro Compare Pune | === =-2 net Eee The input capture register is a 16-bit read-only register used pond pon? to hold the current value of free running counter when the Figure 20 Programmable Timer Block Diagram proper transition of an external input signal occurs. The input transition change required to trigger the counter © Free Running Counter ($0009: $000A) transfer is controlled by the input edge bit (IEDG). The key element in the programmable timer is a 16-Dit free To allow the external input signal to go in the edge detect running counter, that is driven by an E (Enable) clock to unit, the bit of the Data Direction Register corresponding to bit increment its values. The counter value will be read out by the 0 of Port 2 must have been cleared (to zero). CPU software at any time with no effects on the counter. To insure input capture in all cases, the width of an input Reset will clear the counter. pulse requires at least 2 Enable cycles. When the upper byte of this counter is read, the lower byte is stored in temporary latch. The data is fetched from this latch © Timer Control/Status Register (TCSR) ($0008) by the subsequent read of the lower byte. Thus consistent This is an 8-bit register. All 8 bits are readable and the lower double byte data can be read from the counter. S-bit may be written. The upper 3 bits are read-only, indicating When the CPU writes arbitrary data to the upper byte ($09), the timer status information as is shown below, the value of SFFF8 is being pre-set to the counter ($09, $0A) (1) A proper transition has been detected on the input pin regardless of the write data value. Then the CPU writes arbi- (ICE), tray data to the lower byte (SOA). the data is set to the “Low” (2) A match has been found between the value in the free byte of the counter, at the same time, the data preceedingly running counter and the output compare register (OCF). written in the upper byte (S09) is set to “High” byte of the (3) When counting up to $0000 (TOF). counter. Each flag has an individual enable bit in TCSR which When the data is written to this counter. a double byte store determines whether or not an interrupt request may instruction (ex. STD) must be used. If only the upper byte of occur (IRQ2z). If the I-bit in Condition Code Register has counter is written, the counter is set to SFFF8. been cleared, a priority vectored address occurs correspond- The counter value written to the counter using the double ing to each flag. A description of each bit is as follows, byte store instruction is shown in Figure 21. To write to the counter may disturb serial operations, so it Timer Control / Status Register should be inhibited during using the SCI in internal clock mode > 8 5 «a9 2 [ct [ocr [ror] ees] cons] cron] cos owe] some Bit 0 OLVL (Output Level); When a match is found in the value between the counter and the output com- | @HITACHI | 58 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ° Brisbane, CA 94005-1819 » (415) 589-8300

HD6301V1, HD63A01V1, HD63B01V1 pare register, this bit is transferred to the Port 2 With this hardware feature, the non-selected MCU is re- bit 1. If the DDR corresponding to Port 2 bit | is enabled or (“waked-up”) by the next message. set “1”, the value will appear on the output pin of Port 2 bit 1. © Programmable Options Bit 1 1EDG (Input Edge): This bit control which transition The HD6301V1 has the following programmable features. of an input of Port 2 bit O will trigger the data + data format; standard mark/space (NRZ) transfer from the counter to the input capture + clock source; external or internal register. The DDR corresponding to Port 2 bit 0 + baud rate; one of 4 rates per given E clock frequency or must be cleared in advance of using this function: 1/8 of external clock When IEDG = 0, trigger takes place on a negative + wake-up feature; enabled or disabled edge (“High” to “Low” transition), When IEDG = sinterrupt requests; enabled or masked individually for 1, trigger takes place on a positive edge (“Low” to transmitter and receiver “High” transition). + clock output; internal clock enabled or disabled to Port Bit 2 ETO! (Enable Timer Overflow Interrupt); When set, 2 bit 2 this bit enables TOF interrupt to generate the +Port 2 (bits 3, 4); dedicated or not dedicated to serial interrupt request (TRQz). When cleared, the inter- 1/0 individually tupt is inhibited, Bit 3 EOC! (Enable Output Compare Interrupt); When set, © Serial Communication Hardware this bit enables OCF interrupt to generate the The serial communications hardware is controlled by 4 interrupt request (TRQz). When cleared, the inter- registers as shown in Figure 22. The registers include: rupt is inhibited. + an 8-bit control/status register Bit 4 EICI (Enable Input Capture Interrupt); When set, this + a 4-bit rate/mode control register (write-only) bit enables ICF interrupt to generate the interrupt + an 8-bit read-only receive data register request (TRQz). When cleared, the interrupt is + an 8-bit write-only transmit data register inhibited. Besides these 4 registers, Serial I/O utilizes Port 2 bit 3 Bit 5 TOF (Timer Over Flow Flag); This read-only bit is set (input) and bit 4 (output). Port 2 bit 2 can be used when an at the transition of $FFFF to $0000 of the option is selected for the internal-clock-out or the external- counter. It is cleared by CPU read of TCSR (with lock-in. TOF set) followed by an CPU read of the counter ($0009). © Transmit/Receive Control Status Register (TRCSR) Bit 6 OCF (Output Compare Flag); This read-only bit is set TRCS Register consists of 8 bits which all may be read while when a match is found in the value between the only bits 0 to 4 may be written. The register is initialized to $20 output compare register and the counter. It is on RES. The bits of the TRCS register are explained below. cleared by a read of TCSR (with OCF set) fol- lowed by an CPU write to the output compare Transmit / Receive Control Status Register register ($000B or s000C), + ob 8 at a pt Bit 7. ICF (Input Capture Flag); The read-only bit is set by a proper transition on the input, and is cleared by [ron Jorre] one] mie ] ne J re ] re [ ww Jacon a sead of TCSR (with ICF set) followed by an fons CPU read of Input Capture Register (S000D). Reset will clear each bit of Timer Control and Status Bit © WU {Wake Up); Set by software and cleared by hardware Register, on receipt of ten consecutive ““1"’s. While this bit is “I, RDRF and ORFE flags are not set even | SERIAL COMMUNICATION INTERFACE if data are received or errors are detected. There- The HD6301V1 contains a full-duplex asynchronous Serial fore received data are ignored. It should be noted Communication Interface (SCI). SCI may select the several that RE flag must have already been set in advance kinds of the data rate. It consists of a transmitter and a receiver of WU flag’s set. which operate independently but with the same data format Bit 1 TE (Transmit Enable) ; This bit enables transmitter. When and the same data rate, Both the transmitter and receiver com- this bit is set, bit 4 of Port 2 DDR is also forced municate with the CPU via the data bus and with the outside to be set. It remains set even if TE is cleared. world through Port 2 bit 2,3 and 4. Description of hardware, Preamble of ten consecutive “1”'s is transmitted software and register is as follows. just after this bit is set, and then transmitter becomes ready to send data. © Wake-Up Feature If this bit is cleared, the transmitter is disabled In typical multiprocessor applications the software protocol and serial I/O affects nothing on Port 2 bit 4. will usually have the designated address at the initial byte of the Bit 2 TIE (Transmit Interrupt Enable); When this bit is set, message. The purpose of Wake-Up feature is to have the non- TDRE (bit 5) causes an IRQz interrupt. When selected MCU neglect the remainder of the message. Thus cleared TDRE interrupt is masked. the non-selected MCU can inhibit the all further interrupt Bit3 RE (Receive Enable); When set, Port 2 bit 3 can be used process until the next message begins. as an input of receive regardless of DDR value for Wake-Up feature is re-enabled by a ten consecutive “1"s this bit. When cleared, the receiver is disabled. which indicates an idle transmit line. Therefore software pro- Bit 4 RIE (Receive Interrupt Enable); When this bit is set, tocol must put an idle period between the messages and must RDRF (bit 7) or ORFE (bit 6) cause an IRQ prevent it within the message. interrupt. When cleared, this interrupt is masked. @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 59

the Transmit Data Register. TDRE is initialized is detected. Otherwise Framing Error occurs. framing error occurs (receive only), this bit is set by RES. data register while the RDRF is “1”. Framing receive shift register to the receive data register. by reading the receive data register, or by RES. Figure 22. Serial 1/O Register

HD6301V1, HD63A01V1, HD63B01V1 Table 7 SCI Format and Clock Source Control corcco [Forma [clock sowce [Pon znin2 [Pon zena | port zen o 60 - - - oo1 Internat Not Used *** ”

100 Internal | outpur* ”

11 External | Input ”

• Clock output is available regardiess of values for bits RE and TE. ‘ Bit 3 is used for serial input if RE = "1" in TRCS. Bit 4 1s used for serial output if TE = “1” in TRCS. * This pin can be used as I/O port. © Transfer rate/Mode Control Register (RMCR) register. When set, the output of the transmit shift register The register controls the following serial 1/O functions: is connected with Port 2 bit 4 which is unconditionally con- + Bauds rate sdata format — + clock source figured as an output. *Port 2 bit 2 feature After RES, the user should initialize both the RMC register It is 4-bit write-only register, cleared by RES. The 4 bits are and the TRCS register for desired operation. Setting the TE bit considered as a pair of 2-bit fields. The lower 2 bits control the causes a transmission of ten-bit preamble of “1”s. Following the bit rate of internal clock while the upper 2 bits control the preamble, internal synchronization is established and the trans- format and the clock select logic. mitter is ready to operate, Then either of the following states Bit 0 SSO exists, Bit 1 sil Speed Select (1) If the transmit data register is empty (TDRE = 1), the These bits select the Baud rate for the internal clock. The consecutive “1"s are transmitted indicating an idle rates selectable are function of E clock frequency of the CPU. states, Table 6 lists the available Baud Rates. (2) If the data has been loaded into the Transmit Data Bit2 CCO Register (TDRE = 0), it is transferred to the output Bit 3 cc} Clock Control/Format Select shift register and data transmission begins. They control the data format and the clock select logic. During the data transfer, the start bit (“O”) is first trans- Table 7 defines the bit field. ferred. Next the 8-bit data (beginning at bit 0) and finally the stop bit (“1”), When the contents of the Transmit Data Register © Internally Generated Clock is transferred to the output shift register, the hardware sets the If the user wish to use externally an internal clock of the TDRE flag bit: If the CPU fails to respond to the flag within serial 1/O, the following requirements should be noted. the proper time, TDRE is kept set and then a continuous string *CC1, CCO must be set to “10” of I'sis sent until the data is supplied to the data register. +The maximum clock rate must be E/16 «The clock rate is equal to the bit rate. © Receive Operation +The values of RE and TE have no effect. The receive operation is enabled by the RE bit. The serial input is connected with Port 2 bit 3. The receiver operation © Externally Generated Clock is determined by the contents of the TRCS and RMC register. If the user wish to supply an external clock to the Serial The received bit stream is synchronized by the first “O” (start 1/O, the following requirements should be noted. bit). During 10-bit time, the data is strobed approximately at ‘The CC1, CCO must be set to “11” (See Table 7). the center of each bit. If the tenth bit is not “1” (stop bit), +The external clock must be set to 8 times of the desired the system assumes a framing error and the ORFE is set. baud rate, If the tenth bit is “1”, the data is transferred to the receive +The maximum external clock frequency is E/2 clock. data register, and the RDRF flag is set. If the tenth bit of the next data is received and still RDRF is preserved set, then © Serial Operations ORFE is set indicating that an overrun error has occusred The serial [/O hardware must be initialized by the software After the CPU read of the status register as a response to before operation. The sequence will be normally as follows. RDRF flag or ORFE flag, followed by the CPU read of the *Writing the desired operation control bits of the Rate and receive data register, RDRF or ORFE will be cleared. Mode Control Register. ‘Writing the desired operation control bits of the TRCS | RAM CONTROL REGISTER register. The register assigned to the address SOO1I4 gives a status If Port 2 bit 3, 4 are used for serial I/O, TE, RE bits may be information about standby RAM. kept set. When TE, RE bit are cleared during SCI operation, and subsequently set again, it should be noted that TE, RE RAM Control Register must be kept “0” for at least one bit time of the current baud 1 6 5 4 3 2 1 rate. If TE, RE are set again within one bit time, there may be score EZZEanaee the case where the initializing of internal function for trans- Lasiel mitter and receiver does not take place correctly. Bit 0 Not used, ‘© Transmit Operation Bit 1 Not used, Data transmission is enabled by the TE bit in the TRCS —_Bit 2 Not used. @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 61

i HD6301V1, HD63A01V1, HD63B01V1 Bit 3 Not used. © CPU Addressing Modes Bit 4 Not used. The HD6301V 1 has seven address modes which depend on Bit 5 Not used. both of the instruction type and the code. The address mode for Bit 6 RAM Enable. every instruction is shown along with execution time given in Using this control bit, the user can disable the RAM, RAM terms of machine cycles (Table 8 to 12). When the clock Enable bit is set on the positive edge of RES and RAM is frequency is 4 MHz, the machine cycles will be microseconds. enabled, The program can write “1” or “0”. If RAME is Accumulator (ACCX) Addressing cleared, the RAM address becomes external address and the Only the accumulator (A or B) is addressed. Either accumula CPU may read the data from the outside memory. tor A or B is specified by one-byte instructions. Bit 7 Standby Bit Immediate Addressing This bit can be read or written by the user program. It is In this mode, the operand is stored in the second byte of the cleared when the Voc voltage is removed. Normally this bit instruction except that the operand in LDS and LDX, etc are is set by the program before going into stand-by mode. When stored in the second and the third byte. These are two or the CPU recovers from stand-by mode, this bit should be three-byte instructions. checked, If it is “1”, the data of the RAM is retained during Direct Addressing stand-by and it is valid. In this mode, the second byte of instruction indicates the address where the opstand is stored. Direct addressing allows | GENERAL DESCRIPTION OF INSTRUCTION SET the user to directly address the lowest 256 Bytes in the machine The HD6301V1 has an upward object code compatible with ‘locations zero through 255. Improved execution times are the HD6801 to utilize all instruction sets of the HMCS6800. achieved by storing data in these locations. For system ‘The execution time of the key instruction is reduced to increase configuration, it is recommended that these locations should be the system through-put. In addition, the bit operation instruc- RAM and be utilized preferably for user's data realm. These are tion, the exchange instruction between the index and the two-byte instructions except the AIM, OIM, EIM and TIM accumulator, the sleep instruction are added. This section which have three- byte. describes: Extended Addressing *CPU programming model (See Fig. 23) In this mode, the second byte indicates the upper 8 bits + Addressing modes addresses where the operand is stored, while the third byte + Accumulator and memory manipulation instructions (See indicates the lower 8 bits. This is an absolute address in Table 8) memory. These are three-byte instructions. + New instructions Indexed Addressing Index register and stack manipulation instructions (See In this mode, the contents of the second byte is added to the Table 9) lower 8 bits in the Index Register. For each of AIM, OIM, EIM + Jump and branch instructions (See Table 10) and TIM instructions, the contents of the third byte are added Condition code register manipulation instructions (See to the lower 8 bits in the Index Register. in addition, the Table 11) resulting “carry” is added to the upper 8 bits in the Index + Op-code map (See Table 12) Register. The result is used for addressing memory. Because the « Cycle-by-Cycle Operation (See Table 13) modified address is held in the Temporary Address Register, there is no change to the Index Register. These are two-byte © CPU Programming Model instructions but AIM, OIM, EIM, TIM have three-byte. The programming model for the HD6301V1 is shown in Fig- Implied Addressing ure 23. The double accumulator is physically the same as the In this mode, the instruction itself gives the address; stack accumulator A concatenated with the accumulator B, so that pointer, index register, etc. These are |-byte instructions. the contents of A and B is changed with executing operation of Relative Addressing an accumulator D. In this mode, the contents of the second byte is added to the lower 8 bits in the program counter. The resulting carry or borrow is added to the upper 8 bits. This helps the user to 7 a 7 FF 7 O] enix accumuistors A and 8 address the data within a range of —126 to +129 bytes of the 2 ° [THT Tr Jz [v Je] conaition coe Repister (cr) cary /B.rroW fom MS Ovation Necative alt Cary (From Bit 3) Figure 23 CPU Programming Model | @ HITACHI | 62 Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

HD6301V1, HD63A01V1, HD63B01V1 Table 8 Accumulator, Memory Manipulation Instructions Conaivon Coae Operations wwremores Tiaweo [oiRECT | INDEX [EXTENOTIMPLIED | pranmencOperanon [5 [#2 [2[1 1 [or [=| lo |= [e[or]-[+for]-[elor[-]-| ba foie fv fe ‘Aad [aooa [as [2 [2 [90 [2 [2 [aa] [2 wee ee ¢ | aops [cs [2/21 eotel2[reye[s) [| feem=e frtefefe tet Aad Dove | A000} ca [3/3 / eas [2 ale y ee eee o Cor A EBC = leet ‘Aad with Cary [| _aoca [eo [2l7l99|3|2{aol«f2 [eo lejs] [ [ Jarmecwa [a le[efe [sis | —aoea joo [2{2 foe] [2 fee [a fra fala) {| fewwrene feet agi EE ge 100 8009000 eno OCG j anos [ce [2/2 [oa] [2 [ea |< [2 [ra [a | oonnio Ba Test ee GAGA estes] [ [fam Te Tela |e Tale [ are [es | [afes[a]2 tes fe [s] | [fem Te [eta ela] Chae Ce C2 Ck ee [ele fals [ala ee totes ta beter’ [1 [oo ~8 [ole Jals [aja corswe Fiz (ERECT CHEN felefelelele et hee tet G Season | ce PET PT Ey depp face ele fetes Compamenn, te {| com [TTT | | feslela ta felst [ [ [msm [ere Tie [als pea EC ee eee [coms] TTT TTT Ty ee $ conn. Ponce PY Chalet ee eee roe (Negara [nega TOT PT PT TT eo [rf oo pele [Ts [ol a [rece TO feo [ai ooo [ole Decrement [ oec TTT] fT Teatela [rate la] tT [w-1-™ [efit o> [Toece fT eat fan eT ol foes TTT} Py Ty Tt fsa fyfe-sse de Pee [Jol Excinneon | €onA faa [2 [2 [oe [3 |2 [as [a]? les [43] | | [A@w=~a Te [efi [a ale [eons jefe [| frei owe Therement | aan [eT [i Tol fies t+ H feet fers —_ INCE Py Ty TT [sete jageGgod (ows LAA fe eee [a elas esses 1 ogeGo Accumuistor cons [os [2 {2 Joss [2 | [re | 2 Ce ee COCO EG scam | 100 ee eles ofa rl Lf fwcrwemna [ef [ef la] Multiply Unugned [MUL Pry Ty Ty [| tsofrfvfaxe-a eT Te le ToT [elo OR, inciuswve ORAA [2] cy AMA Boguuo (onae~ gi FA oem fT a oe eee ee [esnw TT TT rr TT far [afi Teme set se Te [eof oto re Pall Deve pre ETE EE Pt at eee o Rowen [noe | at tte . oli PE ecg eee Te ¢ rae ep ETT a] rowenan Fone TO alee pe tes Perr or Pree ar +) Qo ere rol prone TT TT Py Dossy srt Tort Note} Condition Code Register will be explained in Note of Table 11 (to be continued) @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300 63

HD6301V1, HD63A01V1, HD63B01V1 Table 8 Accumulator, Memory Manipulation Instructions Aadressing Modes Consition Case Operations weomone Vrmaeo Toimeet [ woex TexTeN [MMi | aye Sowaren (Sf [2f2 fifo jor == for [> [or |= [> for [= [+ [or]=[o] pm[' [nz [ve gan [ase TTT TT feefs tebe left TT —_ pdggoo [asta [TTT TTT Tr Tei by 4| eeseenses OGG O0 jase TTT TTP Tr yr tse tii> le fo [e[ Ole Doveie shit = Grthiinne | mse LTT TTT TT | | lo legac ge |+ Jol: spit ame ee epee tell ‘oo —— [fe fe[s fle " [asa fT 4] Gorey fle ht op ase tt tte eee Jefe fale Ole Sa Ren [TTT TT feTele pe telat TT Tw ——- [+f tale tole owes cme TP i pee eae |-CoooT Dp fefefal iat: [csme TTT Tr a ee fo foTals ]+ pamien | mo TTT TTT TTT TT fos egaeien ze |] elo: Bae UST HEE aire Hhes hb Accemelnter sraa [TT Tor] [fer [« fe [rr [a [a [fe [ele [efe [Rye Tiare Double = iene | se | Lele teelsDlrolspt | t feeme __felefalelet : Supwrect i_suaa too fafa foo ta foote te toot tt AnM =A [efefafe lee [2[2 fools {afeo[a{2|rol«[a] tT [ [e-m-8 [elelate[es Dev br | sven [ea |3[3 joa [« [2 [aa[s 2 [ea [s [a] | | ae-m wer-ae [olets [efile Seen ee 000 : Superet » eee fee a pet eet OocneG =e [ sece [cz |2[2 Joa {a |2 [ez [4 [2 ra {* [a] i Cr ee CC Transtar [rap TP TTT Trt Try eee tet o accumamors [reat Tt) f Pt tty Ty iw these igoqngod Ferzwoor | sr) TTT TT teofe le pola tat TP [mzoo te fe fifi fafa ‘ous [orsra TTT PT Tao ti I [a 00 Te fe Teta Ta a he ee R Ard immediate |AIM [fofefafefotst TT TT [mmm Telefe [aye oRimmedae [om [TT Prefefateat ata TTT TT [osm Tele ti Te Tale conimmedae [em [TT Vosfelsfesfatat [ [TTT [wemmom Tele le [i tale Test immediate Tow TTT ref Tatoo] stat TPT TT [om Tele fifa Note) Condition Code Register will be explained in Note of Table 11. © New Instructions TIM- ---(M) + (IMM) | In addition to the HD6801 Instruction Set, the HD6301V1 Evaluates the AND of the immediate data and the | has the following new instructions: memory, changes the flag of associated condition code AIM ----(M) + (IMM) > (M) register i Evaluates the AND of the immediate data and the Each instruction has three bytes; the first is op-code, the : memory, places the result in the memory. second is immediate data, the third is address modifier. OIM---- (M) + (IMM) ~ (M) XGDX--(ACCD) + (IX) Evaluates the OR of the immediate data and the Exchanges the contents of accumulator and the index memory, places the result in the memory. register. j EIM-- --(M) @ (IMM) > (M) SLP----The CPU is brought to the sleep mode. For sleep | Evaluates the EOR of the immediate data and the mode, see the “sleep mode” section. | contents of memory, places the result in memory. @ HITACHI 64 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

HD6301V1, HD63A01V1, HD63B01V1 Table 9 Index Register, Stack Manipulation Instructions Adgrening Moder Conginan Code —— Boolean’ egister Powter Operavont [rmaeo[oinecr | WWOEX [EXTEND [PLIED | Arunmeve Opeaton [8[e]3[2]¥]o for [-[»[or |~[+ [or [-[= or |-Ts]or]- Te] [atin z|vfe _Comone index Ag ee peel ye[afeppetss tects oT tage : Decrement index Reg Py TTT Tet Tf foe fh fy xasax Tete fete fee i aoe oe Sreemecroneren foes TT gogugd Increment Stack Pate teetstotoeta fs teets} te aan Fe se Terria a (eed inges Reg [40x] 3 = Koa eH ale Rl> SS eicoe ae elas oe nesses] Troe wa fof fas Store Index Reg ef fore eeceeet i yam x= [ole lole fale storesuecn Pow [sts [or [ala [ar] [s]3]_ [7 |sru= msec men [le (Ola [ale index Regs Suck Pmt TS TT TT TTT TT ein. lefs Binet Prova ingee Real Tox | TT TTT sevx og ‘aed [aex TT aati fh ox x Tete fefeye ye Push Date X_= My. 15 . eee eee Pai Bove Fux BP 1= $F, Mg = Xn . —— SP += SPM = Xe Exchange jxcox [TTT TTT ery Ti tele faceom felelololol Note} Condition Code Register will be explained in Note of Table 11 Table 10 Jump, Branch Instruction Tadaresnng Moaes Conan Code Ormaonm | Mewwone [revatne omnbey [ocx [extend fume | temnten fefaTa[afiTo [or] ~[ Jor] ~[+ [or [~[« lor |~]sjor]~] | {u] [wz [vfc Branch Always gee feet ote ft fee : Branch Never jean fa taieT PPP Pr ey ee OOOOOD Beane tcory cua | ace fzeTat2 tT TTT TTT TTT ey tere fete fe ye teye Branch Carry Set 9g. Bf LPT tt fee = Branch if = Zero pret te o Brencn > Zero | ace | jet TP ee ty woveo Tee Te Te ToT Brncnw>2eo [act [zefaiat TT PTT TT TT feewow-o [ele[e le feye Beonch it Higher re pee EE eee ee a @arcnwe zo [ee aefatal TTT PPT tty ly jewouet [elele [ele] Serer os PITT EET TTT Ty fees TEE ye Branch It < Zero eur et TTT ey [woven Telefe ]* [els Branch if Minus Mt zt ttre Eel * raneh 1 Not Eau face "tere [one [ae |! PT i tp ee EEE corre [we la HE ee EEE Branch tf Overflow Set fats t Ty rr [Py ver [ele ls [efoto Branenitrive | em_{zala]? sane rT I Neo le [e le |e [oe Branch To Subroutine {esx fool sa aa ooggggd Ed Le a taotetraofe tet tt jefe te Te feTe sme Te Subroutine [asa [TT [os [2 [aol s [2 | 2 | goggod reorenion [sor TT TT TTT TTT Ty be fefs fasmeron com [Jee [es Rewn From mend amt ttt Pt {tty ype pele | —— Return From soon fs | ET ee oagg6 ‘Software Interrupt Pe — tH RH [= [s[» [oe Te , won torinvervors [war TT TT TT rr fot | g@aqgad ' Seep se ae fo foo fo te | Note) ‘WAI puts R/W high; Address Bus goes to FFFF: Data Bus goes to the three state | Condition Code Register will be explained im Nate of Table 11 @HITACHI | Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy, © Brisbane, CA 94005-1819 © (415) 589-8300 65

HD6301V1, HD63A01V1, HD63B01V1 Table 11 Condition Code Register Manipulation instructions TadavessinaModed Condition Code Register Overaians [impcieo | Bolen Operation (s[«[a[2]1 Jo por [- Te | Pot itwizivic Cleo Corey {ae tet te a Te fe [eTe [eta hoor nteropt Mask | ar fee a Ce CeCe Cheer Overtiow cu [oa [sy [ry [=v pote [eTeotate Set Corry [sec Too Tt fs 1=6 [> fe {s Set Interrupt Mani [se Por Ps =1 co LTH * Set Overtiow [sev foe Py fy a jel+Te{eTs To a a a or oes CCR = Accumulator A 1A [or | con =A Omcmirmend [NOTE 1] Condition Code Register Notes: (Bit set if test 1s true and cleared otherwise) @ (Bit) — Test: Result = 10000000? @ = (BitC) Test: Result 4 000000007 @ (Bit) Test: BCD Character of high-order byte greater than 9? [Not cleared if previously set) @® (Bit) Test: Operand = 10000000 prior to execution? ® (Bit V) — Test: Operand = 01111111 prior to execution? ® (Bir V) Test: Set equal to NeC=1 after the execution of instructions @ (Bit) — Test: Result less than zero? (Bit 15=1) @® {AIBit) Load Condition Code Register from Stack. ® (Bit!) Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait nate, @ (AilBit) Set according to the contents of Accumulator A. @ (Bic) Result of Multiplication Bit 7=1 of ACCB? [NOTE 2] CLI instructions and interrupt. —— — If interrupt mask-bit is set (1="1") and interrupt is requested (IRQ, = “O" or IRQ: = “O"), and then CLI instruction is executed, the CPU responds as follows. 1 the next instruction of CLI is one-machine cycle instruction. ‘Subsequent two instructions are executed before the interrupt is responded. That is, the next and the next of the next instruction are executed. 2. the next instruction of CLI is two-machine cycle (or more) instruction. Only the next instruction is executed and then the CPU jump to the interrupt routine. Even if TAP instruction is used, instead of CLI, the same thing occurs. Table 12 OP-Code Map oF Pace TACT) 0 TEI ROCK oe HCH COvE [a8 ir MM | DIR | IND. EXT | IMM] DIR IND * EXT Na Wooi_ | 0010 [ 001s | 100 oor | vive | ort + 1000 v00r | 110 orn | 100] vor ino | nn | woNSepi tsps te ts petrtets tate feto_ ele mo Sex [ora [75x neG = ees) ees bent ttn fern [ws [I —_ ewe fonts 77] puis com sued OT Tsao [<7 ece [oes Tse Ln Os a = [ou] e | Tar | Tas PHA ROR —— cox $ Ton [7 | tea_| Tea psuaf CSR 57 el [000 ['s [wx] xox] Ast [ton [ior] + [oe [oaa | wDC . [notte [sor_on_f oat ore oma ~ * fon tet em ™ eC) Te nei | 0 [ se Zs MUL 1st asA isk Tso, ape feu [>] Za is aT Loteye Tepes Tevet s Tae Te Tote Tey UNDEFINED OP CODE C=) * Only for instructions of AIM, OIM, EIM, TIM | @HITACHI | 66 Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300

© Instruction Execution Cycles cuted. current instruction fetch and just before the start of the sub- cles such as MULT, PULL, DAA and XGDX in the HD6301V1. trol for the instruction fetch and the subsequent instruction _ in cycle-by-cycle basis during the execution of each instruction. Table 13. Cycle-by-Cycle Operation

4 Op Code Address+2 1__| Next Op Code

4 Stack Pointer—1 a) Return Address (MSB)

5 Jump Address hoa First Subroutine Op Code

4 Op Code Address +2 1 | Address of Operand (LSB)

Table 13. Cycle-by-Cycle Operation (Continued)

5 Op Code Address+2 1 | Next Op Code

3 FFFF [oa | Restart Address (LSB)

6 IX+ Offset New Operand Data

3 Stack Pointer ° | Accumulator Data

HD6301V1, HD63A01V1, HD63B01V1 Table 13 Cycle-by-Cycle Operation (Continued) Instructions t IMPLIED WAT TT Op Code Address +1 T | Next Op Code 2 | FFF 1 | Restart Address (LSB) 1 3 Stack Pointer ° Return Address (LSB) | 4 | Stack Pointer—1 © | Return Address (MSB) 9 5 Stack Pointer—2 i) Index Register (LSB) 6 | Stack Pointer—3 © | Index Register (MSB) | 7 | Stack Pointer—4 © | Accumulator A 8 | Stack Pointer—5. © | Accumulator B 9 | Stack Pointer—6 0 _| Conditional Code Register RTI - ~~ 1 | Op Code Address +1 T_ | Next Op Code

12 FFFF 1 Restart Address (LSB)

1 3 Stack Pointer +1 1 | Conditional Code Register 4 | Stack Pointer +2 loa | Accumulator B ho 8 Stack Pointer + 3 | 1 | Accumulator A { , 6 Stack Pointer + 4 ; 1 Index Register (MSB) | | 7 | Stack Pointer +5 | 1 | Index Register {LSB) i | 8 | Stack Pointer +6 Joa Return Address (MSB) | | 9 | Stack Pointer +7 1 | Return Address (LSB) i | 10. | Return Address 1_| First Op Code of Return Routine Sw ia ‘1 | Op Code Address+? = [1 Next Op Code : 2 | RFF 1 | Restart Address (LSB) | 3. | Stack Pointer © | Return Address (LSB) 4 | Stack Pointer — 1 © | Return Address (MSB)

5 Stack Pointer — 2 ie) Index Register (LSB)

| & | Stack Pointer — 3 | © | Index Register (MSB) 7 | Stack Pointer - 4 j 9 | Accumulator A | 8 | Stack Pointer -5 | 0 | Accumulator B : ; 9 ' Stack Pointer — 6 | © | Conditional Code Register i 10 Vector Address FFFA id | Address of SWI Routine (MSB)

11 Vector Address FFFB | 1 | Address of SWI Routine (LSB)

i | 12 | Address of SWI Routine 1 First Op Code of SWI Routine SLP - —T ~-— bb Gp Code Address+1 | 1 Next Op Code ' | 2 | FFE 1 | Restart Address (LSB) \\ to. | FRFE High Impedance-Non MPX Mode i + sieep | Address Bus -MPX Mode 4: Sleep { | it : | 4 3. | FFE | Restart Address (LSB)

4 Op Code Address+1 |_Next Op Code

— Continued — | @HITACHI Hitachi America, Ltd. » Hitachi Ptaza » 2000 Sierra Point Pkwy. ® Brisbane, CA 94005-1819 « (415) 589-8300 71

= LOW POWER CONSUMPTION MODE CPU. The escape from this mode can be done by interrupt, RES, _is the typical application of this mode. be released due to the absence of the interrupt request to the each Line in this application is shown in Figure 24.

HD6301V1, HD63A01V1, HD63B01V1 ® ERROR PROCESSING When the HD6301V1 fetches an undefined instruction or Table 14 Address Error fetches an instruction from unusable memory area, it generates the highest priority internal interrupt, that may protect from {eee wl ca eat stot acon] system upset due to noise or a program error. 1 sear © Op-Code Error adaress sow Fetching an undefined op-code, the HD6301 V1 will stack the ‘ CPU register as in the case of a normal interrupt and vector to Elissd the TRAP (SFFEE, $FFEF), that has a second highest priority (RES is the highest). © Address Error ‘System Flow chart of HD6301V1 is shown in Fig. 25. When an instruction is fetched from other than a resident ROM, RAM, or an extemal memory area, the CPU starts the Transitions among the active mode, sleep mode, standby same interrupt as op-code error. In the case which the instruc- mode and reset are shown in Fig. 26. tion is fetched from external memory area and that area is not Figures 27, 28, 29 and 30 shows a system configuration. usable, the address error cannot be detected. The addresses which cause address error in particular mode are shown in Table 14. This feature is applicable only to the instruction fetch, not to normal read/write of data accessing. @HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 73

a HD6301V1, HD63A01V1, HD63B01V1 HD6301V1, HD63A01V1, HD63BOIVt, Crs) ® © [ec ret] ve ves is a te ret mse us poe ss NO IK -MSP-2 0) ACCB -MSP-5 <> © wat No <> a = ‘YES ; Sees & ® NO YES <hr> ~ <n ) Ot a es E> “es <=> = COE = [Free rer | [Frec. rero] [Ferra rere | [ Free. rrrs | [rere errs |] [rrez. fers] [Fro Fri | ' EXCEPT NMI CLEAR Figure 25 HD6301V1 System Flow Chart t | @HITACHI | 74 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

a HD6301V1, HD63A01V1, HD63B01V1 cu Raaren

5 Srose |g

nosso Jenene 6 . | = mcU ae | _] to) temo r fon | ’ TT Aaapter pf on | sige yo | Figure 28 HD6301V1 MCU Expanded Non-Multiplexed Mode Figure 29 HO6301V1 MCU Expanded Multiplexed Mode (Mode 5) 16 8 ea ame on es Figure 30 HD6301V1 MCU Expanded Non-Multiplexed Mode (Mode 1) | @HITACHI 76 Hitachi America, Ltd. ¢ Hitachi Plaza # 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

(1) Construct the system that disables the externai memory during reset. This operation makes port 3 high impedance state. and E clock pin are the same as those of operation. Refer to caused by noise generation in the system using the HD6301V1. Only power supply pins and STBY pin are active. As for the with simply designed power source and the GND line. noise by the transient current generated during switching. The difference between HD6301VO and HD6301V1 is shown may cause data write error. Table 17. Difference between HD6301V0 and HD6301V1 Chip Mode (Mode 7) of the HD6301V1 has no such a problem fem | HD6301VO HD6301V1 Assuming the HD6301V1 is used as CPU in a system. Timer (Can be avoided by soft The problem is solved.

HD6301V1, HD63A01V1, HD63B01V1 Oe OO Ee ee AS / \\ [—_ RW \\ [- (SC) Arm Aas (Port 4) Ae Non De~D, ~~ (Port 3) Fig. 33 Noise Occurrence in address bus during write cycle If the data bus Dy ~ Dy changes from “FE” to “00”, ex- y y tremely large transient current flows through the GND line. " . Then the noise is generated on the LSI’s Vss pins proportioning to the transient current and to the impedance [Zg] of the GND line. Vee Ca red i root ‘ De | id E N or re 9 ' ' Va: Noise Voltage Zg: GND Impedance “aA Cd: Date bus load capacitance

29 N: Number of data bus lines switching from H to L

Fig. 34 Noise Source Fig. 35 Dependency of the noise voltage on each parameter This noise level, Vp, appears on all output pins on the LSI {1 Noise Protection including the address bus. To avoid the noise on the address bus during the system Fig. 35 shows the dependency of the noise voltage on the ‘operation mentioned before, there are two solutions as follows: each parameter. The one method is to isolate the HD6301V1 from peripheral devices so that peripherals are not affected by the noise. The other is to reduce noise level to the extent of not affecting peri- pherals using analog method. 1. Noise Isolation Addresses should be latched at the negative edge of the AS signal or at the positive edge of the E signal. The 74LS373 is often used in this case. @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 79

HD6301V1, HD63A01V1, HD63B01V1 FiboveN Tee ee be ~o trolling those analog parameters. (a) Transient Current Reduction (1) Reduce the data bus load capacitance. If large load Ts373 capacitance is expected, a bus buffer should be in- Pae~P. Ag = Ay serted. Pan . (2) Lower the power supply voltage Vcc within specifi- SG cation. HO6301V1 (3) Increase a time constant at transient state by insert- ing a resistor (100 ~ 20082) to Data Buses in series Pap. aan to keep noise level down. Po wZ + As Table 18 shows the relationship between a series as resistors and noise level or a resistor and DC/AC < characteristics N Additional Latch R (7418373 for 0; noise isolation) 2. Noise Reduction v0 As the noise level depends on each parameter such Cd, Vc, }HDe301V Zg, the noise level can be reduced to the allowable level by con- Table 18. —_ Resistor Hern oo [we | too 2008 Noise Voltage Level See Fig. 36 DC Characteristics 1.6 mA 1.6 mA 1,0mA f= 1 MHz No change ‘arac: = 1.5 MHz t 395 375 ns teristics ‘ACCM ns ns 160 ns 180 ns 200 ns fo Mie ‘ast 208 Ons Fig. 36 shows an example of the dependency of the noise “Note: The value af series resistor should be carefully selected because it voltage on the load capacitance of the data bus.* heavily depends on each parameter of actual application system ‘conditions aa erence ot Fig 37 shows the typical wave form of the noise. 15 the HO6301V1 , Vee=5.0V | cd=90pF\\. specification Ta = 25°C { Za-0 N=8 ' > ‘ R=0 gio 0.8v : 3 4 D R= 1000 Epin 8 LA. eT s p R = 2002 2 ’ 0s o— 25.05 95 ng 3 ! Vo Ma As pin ' R: Series Resistor 50 100 Cd (pF) 7 Data bus load capacitance Fig. 37 Fig. 36 | @HITACHI | 80 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD6301V1, HD63A01V1, HD63B01V1 (b) Reduction of GND line impedance (3) Insert a bypass capacitor between the Vcc line and the (1) Widen the GND line width on the PC board. GND of the HD6301V1. A tantalum capacitor (about (2) Place the HD6301 V1 close by power source 0.1uF) is effective on the reduction. Vee Power (Recommended! Vee GND Fig. 38 Layout of the HD6301V1 on the PC board = RECEIVE MARGIN OF THE SCI Table 19 Receive margin of the SCI contained in the HD6301V1is shown in Table 19. Bit distortion tolerance ‘Character distortion tolerance Note: SCI = Serial Communication Interface {t—to) /to (T-To) /To 437.5% +328" stant. 1-23 48 6 7 8 STOP Ideal Waveform | I Bit tenath e-to—>| Character length To, bee T | @ HITACHI | Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 81

HD6301V1, HD63A01V1, HD63B01V1 Abo, Eaves ee = WARNING CONCERNING WAI INSTRUCTION . If the HALT signal is accepted by the MCU while the WAI in- : : struction is executing, the CPU will not operate correctly after : HALT mode is canceled. LOOP WAI is a instruction which waits for an interrupt. The cor- responding interrupt routine is executed after an interrupt ° . occurs. . . However, during the execution of the WAI instruction, . ° HALT input makes the CPU malfunction and fetch an abnormal interrupt vectoring address. i) MAL function ii) Recommended method In HALT mode, the CPU operates correctly without the WAT a instruction, and WAI is executed correctly without HALT input. Figure 40 Program to wait for interrupt Therefore, if HALT input is necessary, make interrupts wait during the loop routine, as shown in Figure 39. = WRITE-ONLY REGISTER When the CPU reads a write-only register, the read data is . always $FF, regardless of the value in the write-only register. : Therefore, be careful of the results of instructions which read a [ward write-only register and perform an arithmetic or logical opera- WAI i i wands for AT tion on its contents, such as AIM, ADD, or ROL, is executed, wrerrapt ) because the arithmetic or logical operation is always done with the data SFF. In particular, don’t use the AIM, OIM or EIM {interrupt occurs instruction to manipulate the DDR bit of PORT. (| (MSB} vector fetch for interrupt 1@ WARNING CONCERNING POWER START-UP | RES must be held low for at least 20 ms when the power starts up. (usB) a In this case, the internal reset function is not effective until the 4 oscillation begins at power-on. The RES signal is input to the LSI in . interrupt routine synchronism with the internal clock (shown in Figure 41). . | Therefore, after power starts up, the LSI conditions such as its 1/O ports and operating mode, are unstable. Fix the level of I/O ports , ; ; by means of an external circuit to determine the level for system Figure 39 MAC function during WAI operation during the osciilator stabilization time.

1 NOTICE ON HD6301V1 ist > z

The HD6301 V0 (including A and B version) was upgraded to the HD6301V1 series in early 1983. The specification deviation between the HD6301V0 series and RES pin: to incon reve the HD6301V1 series is as follows. Please refer to the data sheet for detailed specifications of the HD6301V1 series. Figure 41 RES circuit Table 20 Specification Deviation Between the HD6301V0 and the HD6301V1 tems HD6301V0 HD6301V4 Mode 2: Not defined Mode 2: Expanded multiplexed mode (equivalent rating Mode to Mode 4) Operating Mode 3: Not defined Mode 3: Not defined | The electrical characteristics of 2 MHz version (B | The 2 MHz version is guaranteed. Electrical Characteristics version) are not specified. Ti Has problem in output compare function. (Can be | Fixed imer avoided by software). @ NOTICE ON HD6303R NOTICE ON HD6303R1 The HD6303R is the same die as the HD6301V1. The on-chip The HD6303R has been upgraded to HD6303RI. Refer to the Mask ROM is disabled by mask option; therefore not all modes of following figures for differences between the devices. All other operation are available on the HD6303R. Please note that wherever characteristics remain the same. HD6301V1 jis referenced, the information also applies to the HD6303R. | @ HITACHI | 82 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

— ee HD6301V1, HD63A01V1, HD63B01V1 @ DIFFERENCES BETWEEN HD6301V1, HD6303R, HD6303R1, HD63P01M1, AND HD63701V0 a HD63701V0 RAM Size: 128-byte RAM Size: 192-byte Address: $0080-$00FF Address: $0040-$00FF $0000 F777 Jregister $0000 P7777 Register $0080 EZ RAM Ze Zz SOOFF L _| SOOFF | HD63701V0 does not have Mode 4 After providing supply voltage, output level is undefined | The Output Level Register is initialized to 0 by reset. (0 or 1) unless the contents of the Output Compare Register matches with those of the Free Running Counter. The Output Level Register is not initialized by reset. Timer Ee=] Ge] =] a | : ire == Le ci tcl [ebeToTecRodrokebs]| rx a So a) | pes a | a ma =, H Figure 20 Programmable Timer Block Diagram Figure 20 Programmable Timer Block Diagram HD6301V1, HD6303R, HD6303R1 Receive data is transferred from Receive Shift Register to HD63P01M1 RDR even if framing error occurs. ‘When framing error occurs, | Receive data is transferred receive data is not transfer- | from Receive Shift Register red from the Receive Shift to ROR even if framing Register to Receive Data _| error occurs. Register (RDR). [—e) @HITACHI Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 83

HD6301V1, HD63A01V1, HD63B01V1 i DIFFERENCES BETWEEN HD6301V1, HD6303R, HD6303R1, HD63P01M1, AND HD63701V0 (Continued) The DDA of por is reset synchronously with E clock. 0 | The DDR of port is reset asynchronously with E clock. state is undefined from providing power supply til CPU enters into high impedance state (input state) by oscillation start (max. 20ms). bringing RES Low. on Reset release and MCU internal reset is performed 10 MCU internal reset synchronously with E clock. Port Reset ne 4 weg od < = = Liagl nv a TT tntecna o<] A {=| a 1/0 reset ror STBY signal is latched synchronously with E clock. STBY signal is latched asynchronously with E clock. CPU 5 enters into standby state by bringing STBY low. Standby Mode Say —+p—_r-— sTBY aw sTBy HD6301V1, HD6303R, HDB3POIM1 HDeS03R ime eee es ee i es ee es a Loutput yz as j (Address Strobe) In Expanded Multiplexed | During reset, AS functions | During reset, AS functions normally. Mode (mode 0, 2, 40° 6), | normally. ‘AS becomes high impe- dance state for a half clock cycle during reset. Therefore, VO Port 3 functions as data bus during reset. HD6301V1, HD6303R, The SCI receive margin is shown below. NDESOSt HO63POIM1 The SCI receive margin is | The SCI receive margin is sTart. 1 23 4 5 6 7 8 STOP shown below. shown below. Bit distortion Bit distortion eee orm tolerance +37.5%| | |tolerance te. (tH) (toto scene Character Character se eee oe distortion +3.5%| | |distortion Real t tolerance -2.5%| | |tolerance +£3.75%| | waveform Led |(T-ToVTo (T-T VT T Bit distortion tolerance (t-toV/tg Character distortion tolerance (T-To)/Tp @ HITACHI i 84 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300

HD6301V1, HD63A01V1, HD63B01V1 l§ DIFFERENCES BETWEEN H06301V1, HD6303R, HD6303R1, HD63P01M1, AND HD63701V0 (Continued) H06301V1, HDE303R, DesP HD6303R1 HD6SPO1Mt Supply Voltage | Voc = 5V + 10% Voc = 5V + 10% (f = 0.1 ~ 2 MHz) (f= 0.1 ~ 2MHz) Voc = 5V + 10% Voc = 3 ~ 6V (f= 0.1 ~ 1 MHz) (f= 0.1 ~ 0.5 MHz) 3 tay = 20 ns min, tans tHw = 60 ns (f = 1 MHz) § tw = 20 ns min = 40 ns (f = 1.5 MHz) ba tan and thaw ate constant independently of operating = 30 ns (f = 2 MHz) fi /. ti L(t = it Address/Data | Mequency. ‘mand traw are proportion to 1/t. (f = operating fre- Hold Time a (tare tow) ‘ml \\ a tem (1) tap) and tap2 are constant independently of operating | tap1, tang and tapy_ are related to operating frequency frequency. In HD63B01V (B version of HD6301V), tap; | (They are in proportion to 1/1. f = operating frequency). and tape are 160 ns max. at 0.1 MHz through 2MHz | Therefore, if HD637B01V operates at lower operating Address operation. frequency, taps, tang and tap, will become 160 ns or Delay (2) tapi is related to operating frequency. (tap. is in more. tap, tang and tapi are calculated as follows. Time proportion to 1. f = operating frequency) tap (f MHz) + 250 ns (1 MHz) x 1/f (MHz) le and, lin = 10 pA max. Cig = 50 pF max. Since RES is RES” | lin = 104A max., Ciq = 12.5 pF max. multiplexed with Vp, Cin and li, are larger than those of < HD6301V. Ss

3 Load

2 2-LSTTL + 40pF 1-TTL + 90pF | Capacitance 3 ore lo, = 0.8 MA, Ioy = -200 pA lol = 1.8 MA, lop = -200 yA a Load Capacitance | 1-TTL + 30pF 1-TTL + 90pF of Port 1 Spec. Spec. of rst | SPH oek reqveney mre) [25 [40 | 60 | 20 | R, = 600 max. Storage f ° Mad = o88o tteere @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 85

HD6301V1, HD63A01V1, HD63B01V1 FAVOSVIV I, Tomi GE, see i DIFFERENCES BETWEEN HD6301V1, HD6303R, HD6303R1, HD63P01M1, AND HD63701V0 (Continued) [fom Mosso | ossroNve HD6303R1, HD6301V1, HD6303R, HDeSPOIM en os an sf \\ aft \\ { ss GND Noise i Ds =~ Noise is —_ YX reduced Noise is reduced by 50%. by 33%. - Vf foad capacitance in each data line and GND impedance are large, noise may appear on address bus during MCU write cycle and data won't be written into RAM correctly. The noise is caused by GND impedance which becomes large when large transient current flows into GND at High to Low transition of data line. Chip design and manufacturing process of the HD6301V differ from those of the HD63701V0. Therefore, actual spec. Miscellaneous | and margin are different between the HD6301V and the HD63701V0. Please carefully examine your system before applying HD6301V or HD63701V0 to your system. | @ HITACHI | 86 Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300