HD404356

HD404358 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

Rev. 6.0 Sept. 1998

Description

The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input capture timer, and two low-power dissipation modes. The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the HD407A4359 with 16-kword PROM. The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum instruction cycle time: 0.47 ms) The HD407A4359 is a PROM version (ZTATä microcomputer). A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTATä version is 27256-compatible.) ZTAT ä : Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

• 34 I/O pins ¾ One input-only pin ¾ 33 input/output pins: 4 pins are intermediate-voltage NMOS open drain with high-current pins (15 mA, max.)
• On-chip A/D converter (8-bit · 8-channel) ¾ Low power voltage 2.7 V to 6.0 V
• Three timers ¾ One event counter input ¾ One timer output ¾ One input capture timer
• Eight-bit clock-synchronous serial interface (1 channel)
• Alarm output

• Built-in oscillators ¾ Ceramic oscillator or crystal ¾ External clock drive is also possible
• Seven interrupt sources ¾ Two by external sources ¾ Three by timers ¾ One by A/D converter ¾ One by serial interface
• Two low-power dissipation modes ¾ Standby mode ¾ Stop mode
• Instruction cycle time ¾ 0.47 ms (f OSC = 8.5 MHz, 1/4 division ratio): HD40A4354, HD40A4356, HD40A4358, HD407A4359 ¾ 0.8 ms (f OSC = 5 MHz, 1/4 division ratio): HD404354, HD404356, HD404358

Ordering Information

Time Product Name Model Name ROM (Words) RAM (Digit) Package Mask ROM Standard versions HD404354 HD404354S 4,096 384 DP-42S (fOSC = 5 MHz) HD404354H FP-44A HD404356 HD404356S 6,144 DP-42S HD404356H FP-44A HD404358 HD404358S 8,192 DP-42S HD404358H FP-44A High speed versions HD40A4354 HD40A4354S 4,096 384 DP-42S (fOSC = 8.5 MHz) HD40A4354H FP-44A HD40A4356 HD40A4356S 6,144 DP-42S HD40A4356H FP-44A HD40A4358 HD40A4358S 8,192 DP-42S HD40A4358H FP-44A ZTATä (fOSC = 8.5 MHz) HD407A4359 HD407A4359S 16,384 512 DP-42S HD407A4359H FP-44A

/SCK /SI /SO /TOC R4 1/AN5 AV CC VCC D 0/INT0 D 1/INT1 D 2/EVNB D 3/BUZZ D 4/STOPC NC R4 2/AN6 R4 3/AN7 R0 0/SCK R0 1/SI R0 2/SO R0 3/TOC TEST RESET OSC 1 OSC 2 AV SS R8 3 R8 2 R8 1 R8 0 D 8 D 7 D 6 D 5 D 4/STOPC D 3/BUZZ D 2/EVNB D 1/INT1 D 0/INT0 RA 1 R2 3 R2 2 R2 1 R2 0 R1 3 R1 2 R1 1 R1 0 DP-42S V CC AV CC R3 0/AN0 R3 1/AN1 R3 2/AN2 R3 3/AN3 R4 0/AN4 R4 1/AN5 R4 2/AN6 R4 3/AN7 GND

Item Symbol DP-42S FP-44A I/O Function Power supply VCC 21 16 Applies power voltage GND 10 5 Connected to ground Test TEST 6 1 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 7 2 I Resets the MCU Oscillator OSC1 8 3 I Input/output pin for the internal oscillator. Connect these pins to the ceramic oscillator or crystal oscillator, or OSC 1 to an external oscillator circuit. OSC 2 94O Port D 0–D 8 22–30 17–21, 23–26 I/O Input/output pins addressed individually by bits; D0–D 8 are all standard-voltage I/O pins. RA 1 1 39 I One-bit standard-voltage input port pin R0 0–R1 3, R3 0–R4 3, R8 0–R8 3 2–5, 12–19, 31–38 40–43, 7–14 27–34 I/O Four-bit input/output pins consisting of standard-voltage pins R2 0–R2 3 39–42 35–38 I/O Four-bit input/output pins consisting of intermediate voltage pins Interrupt INT0, INT1 22, 23 17, 18 I Input pins for external interrupts Stop clearSTOPC 26 21 I Input pin for transition from stop mode to active mode Serial Interface SCK 2 40 I/O Serial interface clock input/output pin SI 3 41 I Serial interface receive data input pin SO 4 42 O Serial interface transmit data output pin Timer TOC 5 43 O Timer output pin EVNB 24 19 I Event count input pin Alarm BUZZ 25 20 O Square waveform output pin A/D converter AV CC 20 15 Power supply for the A/D converter. Connect this pin as close as possible to the V CC pin and at the same voltage as VCC . If the power supply voltage to be used for the A/D converter is not equal to VCC , connect a 0.1- mF bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) AV SS 11 6 Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. AN 0–AN 7 12–19 7–14 I Analog input pins for the A/D converter

(14 bits) Instruction decoder SP (10 bits) B (4 bits) A (4 bits) ST (1 bit) CA (1 bit) ALU SPY (4 bits) Y (4 bits) SPX (4 bits) X (4 bits) W (2 bits) RAM (384 4 bits) (512 4 bits) System control Interrupt control Timer A Timer B Timer C Serial interface A/D converter Buzzer Internal data bus Internal data bus Internal address bus BUZZ AV CC AN 7 AV SS AN 0 SI SO SCK TOC EVNB INT0 INT1 Data bus Intermediate voltage pin Directional signal line GND VCC OSC 2 OSC 1 STOPC TEST RESET RA port ROM (4,096 10 bits) (6,144 10 bits) (16,384 10 bits)(8,192 10 bits)

The ROM memory map is shown in figure 1 and described below. Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$0FFF (HD404354, HD40A4354), $0000–$17FF (HD404356, HD40A4356), $0000–$1FFF (HD404358, HD40A4358), $0000–$3FFF (HD407A4359)): The entire ROM area can be used for program coding. $000F $0FFF $1800 $0010 $003F $0040 Vector address (16 words) Zero-page subroutine (64 words) Pattern (4,096 words) Program (4,096 words) Program (8,192 words) $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F JMPL instruction (jump to RESET, STOPC routine) JMPL instruction (jump to INT routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B routine) JMPL instruction (jump to timer C routine) JMPL instruction (jump to A/D converter routine) JMPL instruction (jump to INT routine) JMPL instruction (jump to serial routine) For HD404358, HD40A4358 Program (16,384 words) HD407A4359 $1FFF $2000 $3FFF For HD404354, HD40A4354 $1000 Program (6,144 words) For HD404356, HD40A4356$17FF Note: Since the ROM address areas between $0000–$0FFF overlap, the user can determine how these areas are to be used. Figure 1 ROM Memory Map

The HD404354, HD40A4354, HD404356, HD40A4356, HD404358 and HD40A4358 MCUs contain 384- digit · 4-bit RAM areas. The HD407A4359 MCU contain 512-digit · 4-bit RAM areas. Both of these RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000–$03F):

• Interrupt Control Bits Area ($000–$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01F, $024–$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($050–$17F for HD404354/HD40A4354/HD404356/HD40A4356/HD404358/HD40A4358, $050–$1FF for HD407A4359) Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

A/D channel register (ACR) $000 $000 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $020 $023 $033 $00A $00B $00E $00F W W R/W W W W W W W W W W R R R R W R/W R/W R/W R/W R/W $3C0 RAM-mapped registers Memory registers (MR) Stack (64 digits) Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) Register flag area Port R0 DCR (DCR0) Port R3 DCR (DCR3) Not used 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). 2. Undefined. Timer read register B lower (TRBL) Timer read register B upper (TRBU) Timer read register C lower (TRCL) Timer read register C upper (TRCU) Timer write register B lower (TWBL) Timer write register B upper (TWBU) Timer write register C lower (TWCL) Timer write register C upper (TWCU) R: Read only W: Write only R/W: Read/write $200 Notes: $016 RA/D data register lower (ADRL)$017 $024 $025 $026 $018 $019 $01A $3FF A/D data register upper (ADRU) A/D mode register 1 (AMR1) A/D mode register 2 (AMR2) R W W W Port mode register B (PMRB) Port mode register C (PMRC) Timer mode register B2 (TMB2) Not used W W W $030 Not used Not used Not used -000 0000 0000 Undefined Undefined -000 0000 *2/0000 00-- 0000 0000 0000 0000 1000 0000 --00 0000 00-0 -000 Undefined *2/0000 Undefined Initial values after reset $03F HD404354, HD40A4354, HD404356, HD40A4356, HD404358, HD40A4358 Data (304 digits) HD407A4359 Data (432 digits) 0000 0000 ---0 Port D0–D 3 Port D4–D 7 Port D DCR8 Port R1 DCR (DCR1) Port R2 DCR (DCR2) W W 0000 0000 W W W 0000WPort R8 DCR (DCR8) DCR DCR (DCD0) (DCD1) (DCD2) $02C $02D $02E $02F $031 $032 $038 Not used Not used $180 $034 WPort R4 DCR (DCR4)0000 Figure 2 RAM Memory Map

$000 $003 PMRA $004 SMR $005 SRL $006 SRU $007 TMA $008 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC $00D TRCL/TWCL $00E TRCU/TWCU $00F ACR $016 ADRL $017 ADRU $018 AMR1$019 AMR2 $01A $020 $023 PMRB $024 PMRC $025 TMB2 $026 DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034 DCR8 $038 $03F Bit 3 Bit 2 Bit 1 Interrupt control bits area D 3/BUZZ R0 3/TOC R0 2/SO Serial transmit clock speed selection Serial data register (lower digit) Serial data register (upper digit) Clock source selection (timer A) Clock source selection (timer B) Timer B register (lower digit) Timer B register (upper digit) SO PMOS control Clock source selection (timer C) Timer C register (lower digit) Timer C register (upper digit) Analog channel selection A/D data register (lower digit) A/D data register (upper digit) Register flag area Port D3 DCD Port D7 DCD Port D2 DCD Port D6 DCD Port D1 DCD Port D5 DCD Port D0 DCD Port D4 DCD Port D8 DCD Port R03 DCR Port R23 DCR Port R43 DCR Port R02 DCR Port R22 DCR Port R42 DCR Port R01 DCR Port R11 DCR Port R21 DCR Port R41 DCR Port R00 DCR Port R10 DCR Port R20 DCR Port R40 DCR 0/SCK Bit 0 Auto-reload on/off Pull-up MOS control A/D conversion time SO output level control in idle states Serial clock source selection Input capture selection Notes: R0 1/SI R3 3/AN R3 2/AN2 R3 1/AN1 R3 0/AN0 3*R4/AN 4–AN 7 Port R83 DCR Port R82 DCR Port R81 DCR Port R80 DCR D 4/STOPC Buzzer output D 2/EVNB D 1/INT1 EVNB detection edge selection D 0/INT0 Port R13 DCR Port R33 DCR Port R12 DCR Port R32 DCR Port R31 DCR Port R30 DCR Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Figure 5 Special Function Register Area

$040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F 960 $3C0 1023 $3FF MR(0) MR(1) MR(2) MR(3) MR(4) MR(5) MR(6) MR(7) MR(8) MR(9) Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 MR(10) MR(11) MR(12) MR(13) MR(14) MR(15) PC PC PC PC PC PC PC PC PC PC PC PC ST PC CA PC Bit 3 Bit 2 Bit 1 Bit 0 $3FC $3FD $3FE $3FF 1020 1021 1022 1023 PC –PC : ST: Status flag CA: Carry flag Program counter Stack area Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described below. (B) (A) (W) (X) (Y) (SPX) (SPY) (CA) (ST) (PC) (SP)11 11 Accumulator B register W register X register Y register SPX register SPY register Carry Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: 1, no R/W Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing.

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one t RC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1. Interrupts The MCU has 7 interrupt sources: two external signals (INT0 and INT1), three timer/counters (timers A, B, and C), serial interface, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in table 3.

figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The interrupt program, and reset the IF by a software instruction within the interrupt program.

Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt flags/mask Interrupt enable flag (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests I/O Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0 – DCD1) All bits 0 Turns output buffer off (to high impedance) (DCD2) - - - 0 (DCR0 – DCR4, DCR8) All bits 0 Port mode register A (PMRA) 0000 Refer to description of port mode register A Port mode register B bits 2–0 (PMRB2 – PMRB0)

000 Refer to description of port mode

Port mode register C (PMRC) 00 - 0 Refer to description of port mode register C Timer/ counters, serial interface Timer mode register A (TMA) - 000 Refer to description of timer mode register A Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1 Timer mode register B2 (TMB2) - 000 Refer to description of timer mode register B2 Timer mode register C (TMC) 0000 Refer to description of timer mode register C Serial mode register (SMR) 0000 Refer to description of serial mode register Prescaler S (PSS) $000 — Timer counter A (TCA) $00 — Timer counter B (TCB) $00 — Timer counter C (TCC) $00 — Timer write register B (TWBU, TWBL) $X0 — Timer write register C (TWCU, TWCL) $X0 — Octal counter 000 —

Item Abbr. Initial Value Contents A/D A/D mode register 1 (AMR1) 0000 Refer to description of A/D mode register A/D mode register 2 (AMR2) - - 00 A/D channel register (ACR) - 000 Refer to description of A/D channel register A/D data register (ADRL) 0000 Refer to description of A/D data register (ADRU) 1000 Bit registers Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter IAD off flag (IAOF) 0 Refer to the description of A/D converter Input capture status flag (ICSF) 0 Refer to description of timer B Input capture error flag (ICEF) 0 Refer to description of timer B Others Miscellaneous register (MIS) 00 - - Refer to description of operati ng modes, I/O, and serial interface Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. – indicates that the bit does not exist. Item Abbr. Status After Cancellation of Stop Mode by STOPC Input Status After all Other Types of Reset Carry flag (CA) Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-MCU-reset values are not guaranteed; values must be initialized by program Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 Port mode register B bit 3 (PMRB3) Pre-stop-mode values are retained

Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* — $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B 4 $0008 Timer C 5 $000A A/D 6 $000C Serial 7 $000E Note: * The STOPC interrupt request is valid only in stop mode.

$ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,0 $ 002,1 $ 002,2 $ 002,3 $ 003,0 $ 003,1 Sequence control

• Push PC/CA/ST
• Reset IE
• Jump to vector address Priority control logic Vector address Note: $m,n is RAM address $m, bit number n. IFS IMS $ 003,2 $ 003,3 INT0 interrupt INT1 interrupt Timer A interrupt Timer B interrupt Timer C interrupt A/D interrupt Serial interrupt Figure 8 Interrupt Control Circuit

Table 3 Interrupt Processing and Activation Conditions Interrupt Source INT0 INT1 Timer A Timer B Timer C A/D Serial IE 1111111 IF0 · IM0 1000000 IF1 · IM1 * 100000 IFTA · IMTA 10000 IFTB · IMTB * 1000 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1234 56 Instruction execution* IE reset Interrupt acceptance Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Vector address generation Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Stacking Figure 9 Interrupt Processing Sequence

RESET = 0? Reset MCU Interrupt request? Execute instruction PC (PC) + 1← PC $0002← PC $0004← PC $0006← PC $0008← PC $000A← PC $000E← IE = 1? Accept interrupt IE 0 Stack (PC) Stack (CA) Stack (ST) INT0 interrupt? INT1 interrupt? Timer-A interrupt? Timer-B interrupt? No Yes No Yes No Yes Yes Yes Yes Yes Yes No No No No (serial interrupt) PC $000C← A/D interrupt? Yes No No Timer-C interrupt? Figure 10 Interrupt Processing Flowchart

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled

0 Disabled

1 Enabled

External Interrupts (INT0, INT1): Two external interrupt signals. External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising edge of signals input to INT0 and INT1, as listed in table 5. Table 5 External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0) IF0, IF1 Interrupt Request 0N o

1 Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1) IM0, IM1 Interrupt Request

0 Enabled

1 Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0N o Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8.

Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0) IFTB Interrupt Request 0N o Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1) IMTB Interrupt Request Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0N o Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request

Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 13. Table 13 Serial Interrupt Request Flag (IFS: $003, Bit 2) IFS Interrupt Request 0N o Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. Table 14 Serial Interrupt Mask (IMS: $003, Bit 3) Mask IMS Interrupt Request A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in table 15. Table 15 A/D Interrupt Request Flag (IFAD: $003, Bit 0) IFAD Interrupt Request 0N o A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 16. Table 16 A/D Interrupt Mask (IMAD: $003, Bit 1) IMAD Interrupt Request

The MCU has three operating modes as shown in table 17. The operations in each mode are listed in tables 18 and 19. Transitions between operating modes are shown in figure 11. Table 17 Operating Modes and Clock Status Mode Name Active Standby Stop Activation method RESET cancellation, interrupt request, STOPC cancellation in stop mode SBY instruction STOP instruction Status System oscillator OP OP Stopped Cancellation method RESET input, STOP/ SBY instruction RESET input, interrupt request RESET input, STOPC input in stop mode Note: OP implies in operation Table 18 Operations in Low-Power Dissipation Modes Function Stop Mode Standby Mode CPU Reset Retained RAM Retained Retained Timer A Reset OP Timer B Reset OP Timer C Reset OP Serial Reset OP A/D Reset OP I/O Reset Retained Note: OP implies in operation Table 19 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode Stop Mode Active Mode RA 1 — — Input enabled R 0–D 8, R0–R4, R8, Retained or output of peripheral functions High impedance Input enabled

RAME = 0 RAME = 1 STOP instruction STOPC Oscillate Stop f cyc fOSC : øCPU : øPER : Oscillate f cyc fcyc fOSC : øCPU : øPER : Stop Stop Stop f OSC : øCPU : øPER : Main oscillation frequency f OSC /4 System clock Clock for other peripheral functions f OSC : fcyc: øCPU : øPER : Figure 11 MCU Status Transitions Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC 2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 12.

Oscillator: Active Peripheral clocks: Active All other clocks: Stop No Yes No Yes No Yes No Yes No Yes No Yes Yes Restart processor clocks Reset MCU Execute next instruction Accept interrupt Restart processor clocks No YesIF = 1, IM = 0, and IE = 1? RESET = 0? IF0 • IMO = 1? IF1 • IM1 = 1? IFTA • IMTA = 1? IFTB • IMTB = 1? IFTC • IMTC = 1? IFAD • IMAD = 1? No Yes IFS • IMS = 1? No Stop Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop RESET = 0? STOPC = 0? RAME = 1 RAME = 0 Yes Yes No No Execute next instruction Figure 12 MCU Operation Flowchart Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.

IF = 1? Instruction execution SBY/STOP instruction? PC Next location PC Vector address Low-power mode operation cycle IE 0 Stack (PC), (CA), (ST) IM = 0 and IE = 1? Yes No No Yes Yes No IF: IM: IE: PC: CA: ST: Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 15 MCU Operating Sequence (MCU Operation Cycle)

IF = 1 and IM = 0? Hardware NOP execution ←PC Next Iocation MCU operation cycle Standby mode IF = 1 and IM = 0? Hardware NOP execution PC Next Iocation Instruction execution Stop mode No Yes No Yes For IF and IM operation, refer to figure 12. STOPC = 0? RAME = 1 Reset MCU No Yes Figure 16 MCU Operating Sequence (Low-Power Mode Operation)

Table 20 Oscillator Circuit Examples Circuit Configuration Circuit Constants External clock operation External oscillator OSC Open OSC 2 Ceramic oscillator (OSC 1, OSC2) OSC C 1 OSC R fCeramic GND Ceramic oscillator: CSA4.00MG (Murata) R f = 1 MW –20% C 1 = C2 = 30 pF –20% Crystal oscillator (OSC 1, OSC2) OSC C 1 OSC R fCrystal GND L SC R S C O OSC 1 OSC 2 R f = 1 MW –20% C 1 = C2 = 10 to 22 pF –20% Crystal: Equivalent to circuit shown below C 0 = 7 pF max. R S = 100 W max. Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross other wiring (see figure 18).

The MCU has 33 input/output pins (D0–D 8, R0–R4, R8) and an input pin (RA1). The features are described below.

• Four pins (R20–R2 3) are high-current (15 mA max) input/output with intermediate voltage NMOS open drain pins.
• The D0–D 4, R0, R3–R4 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R0 2/SO pin can be set to NMOS open- drain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state.
• Each input/output pin except for R2 has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 19, programmable I/O circuits are listed in table 21, and I/O pin circuit types are shown in table 22. Table 21 Programmable I/O Circuits MIS3 (bit 3 of MIS) 0 1 DCD, DCR 0 1 0 1 P D R 01010101 CMOS buffer PMOS ———O n ———O n Note: — indicates off status.

DCD, DCR PDR Input data VCC HLT Pull-up control signal Buffer control signal Output data Figure 19 I/O Buffer Configuration

Table 22 Circuit Configurations of I/O Pins I/O Pin Type Circuit Pins Input/output pins VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 PDR Input control signal DCR, DCD D 0–D 8, R0 0, R01, R03 R1 0–R1 3, R3 0–R3 3, R4 0–R4 3, R8 0–R8 3 VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 DCR PDR Input control signal MIS2 R0 2 HLT DCR PDR Input data Output data Input control signal R2 0–R2 3 Input pins Input data Input control signal RA 1 Peripheral function pins Input/output pins VCC VCC Pull-up control signal Output data Input data HLT MIS3 SCK SCK SCK Notes on next page.

TOC, BUZZ TOC, BUZZ Input pins Input data VCC HLT MIS3 PDR SI, INT0, INT1, EVNB, STOPC A/D input Input control signal VCC HLT MIS3 PDR AN 0–AN 7 Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins enter the high-impedance state. 2. The HLT signal is 1 in active and standby modes.

Evaluation Chip Set and ZTAT ä /Mask ROM Product Differences As shown in figure 20, the NMOS intermediate breakdown voltage open drain pin circuit in the evaluation chip set differs from that used in the ZTATä microcomputer and built-in mask ROM microcomputer products. Please note that although these outputs in the ZTATä microcomputer and built-in mask ROM microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs cannot be set to high impedance in the evaluation chip set. Table 23 Program Control of High Impedance States Register Set Value DCR 0 1 PDR * 1 Notes:* An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation. This applies to the ZTATä and built-in mask ROM microcomputer NMOS open drain pins. VCC VCC HLT MIS3 DCR PDR CPU input Input control signal Evaluation Chip Set Circuit Structure Input control signal ZTAT and Built-in Mask ROM Microcomputer Circuit Structure HLT DCR PDR CPU input Figure 20 NMOS Intermediate Breakdown Voltage Open Drain Pin Circuits

D Port (D0–D 8): Consist of 9 input/output pins addressed by one bit. Pins D0–D 8 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0–D 8 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are cont rol l ed by D -port d at a control regis t er s ( D C D0–DC D2: $02C– $02E) that are mapped to memory addresses (figure 21). Pins D0–D2, D4 are multiplexed with peripheral function pins INT0, INT1 , EVNB, and STOPC , respectively. The peripheral function modes of these pins are selected by bits 0–3 (PMRB0–PMRB3) of port mode register B (PMRB: $024) (figure 22). Pin D3 is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 23). R Ports (R00–R4 3, R8): 24 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0–DCR4: $030–$034, DCR8: $038) that are mapped to memory addresses (figure 21). Pin R0 0 is multiplexed with peripheral function pin SCK. The peripheral function mode of this pin is selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 24). Pins R0 1–R0 3 are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function modes of these pins are selected by bits 0–2 (PMRA0–PMRA2) of port mode register A (PMRA: $004), as shown in figures 23. Port R3 is multiplexed with peripheral function pins AN0–AN 3, respectively. The peripheral function modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019) (figure 25). Ports R4 is multiplexed with peripheral function pins AN4–AN 7, respectively. The peripheral function modes of these pins can be selected in 4-pin units by setting bit 1 (AMR21) of A/D mode register 2 (AMR2: $01A) (figure 26). Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off control of that pin alone (table 21 and figure 27). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kW .

W W W W DCD0, DCD2, DCR0 to DCR4, DCR8 Data control register(DCD0 to 2: $02C to $02E) (DCR0 to 4: $030 to $034, DCR8: $038) Correspondence between ports and DCD/DCR bits DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR8 Off (high-impedance) On Bits 0 to 3 CMOS Buffer On/Off Selection Register Name D 3 D 7 Not used R1 3 R2 3 R3 3 R4 3 R8 3 Bit 3 D 2 D 6 Not used R1 2 R2 2 R3 2 R4 2 R8 2 Bit 2 D 1 D 5 Not used R1 1 R2 1 R3 1 R4 1 R8 1 Bit 1 D 0 D 4 D 8 R0 0 R1 0 R2 0 R3 0 R4 0 R8 0 Bit 0 DCD03, DCD13, DCR03– DCR43, DCR83 DCD02, DCD12, DCR02– DCR42, DCR82 DCD01, DCD11, DCR01– DCR41, DCR81 DCD00– DCD20, DCR00– DCR40, DCR80 Figure 21 Data Control Registers (DCD, DCR)

W SMR3 W SMR2 W SMR0 W SMR1 Serial mode register (SMR: $005) SMR2 SMR0SMR1SMR3 R0 0/SCK Mode Selection R0 0 SCK Transmit clock selection. Refer to figure 55 in the serial interface section. Figure 24 Serial Mode Register (SMR) Bit Initial value Read/Write Bit name W AMR13 W AMR12 W AMR10 W AMR11 AMR10

1 AN 0

A/D mode register 1 (AMR1: $019) AMR11 AN 1 AMR12 2/AN2 Mode Selection R3 2 AN 2 AMR13 R3 3/AN3 Mode Selection R3 3 AN 3 R3 0/AN0 Mode Selection R3 0 R3 1/AN1 Mode Selection R3 1 Figure 25 A/D Mode Register 1 (AMR1)

The MCU has four timer/counters (A to C).

• Timer A: Free-running timer
• Timer B: Multifunction timer
• Timer C: Multifunction timer Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are listed in table 25. The operating modes are selected by software. Table 25 Timer Functions Functions Timer A Timer B Timer C Clock source Prescaler S Available Available Available External event — Available — Timer functions Free-running Available Available Available Event counter — Available — Reload — Available Available Watchdog — — Available Input capture — Available — Timer output PWM — — Available Note: — implies not available.

Timer A Functions: Timer A has the following functions.

• Free-running timer The block diagram of timer A is shown in figure 29. System clock Selector Prescaler S (PSS) Internal data bus Timer A interrupt request flag (IFTA) Overflow Timer counter A (TCA) Timer mode register A (TMA) øPER 128 512 1024 2048 Clock Figure 29 Timer A Block Diagram Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode and input clock source as shown in figure 30.

W TMA2 W TMA0 W TMA1 Timer mode register A (TMA: $008) 0 0 PSS PSS PSS PSS PSS PSS PSS PSS TMA1TMA2 TMA0 Source Prescaler Input Clock Frequency 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc Figure 30 Timer Mode Register A (TMA)

Timer B Functions: Timer B has the following functions.

• Free-running/reload timer
• External event counter
• Input capture timer The block diagram for each operation mode of timer B is shown in figures 31 and 32. Timer counter B (TCB) 128 512 2048 Timer mode register B2 (TMB2) EVNB Selector System clock øPER Prescaler S (PSS) Edge detector Edge detection control signal Timer write register B lower (TWBL) Timer mode register B1 (TMB1) Timer write register B upper (TWBU) Clock Free-running timer control signal Timer read register B lower (TRBL) Interrupt request flag of timer B (IFTB) Timer read register B upper (TRBU) Overflow Internal data bus Figure 31 Timer B Free-Running and Reload Operation Block Diagram

(TCB) Internal data bus Timer mode register B2 (TMB2) EVNB Selector System clock Prescaler S (PSS) Edge detector Edge detection control signal Timer mode register B1 (TMB1) Clock Input capture timer control signal Timer read register B lower (TRBL) Interrupt request flag of timer B (IFTB) Timer read register B upper (TRBU) Overflow Read signal Input capture status flag (ICSF) Input capture error flag (ICEF) Error controller 128 512 2048 øPER Figure 32 Timer B Input Capture Operation Block Diagram

Timer B Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer B is used as an external event counter by selecting the external event input as an input clock source. In this case, pin D 2/EVNB must be set to EVNB by port mode register B (PMRB: $024). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be cyc or longer. Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026). The other operation is basically the same as the free-running/reload timer operation.
• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVNB. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by timer mode register 2 (TMB2: $026). When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL: $00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $026) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register B (PMRB: $024)
• Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 33. It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. Bit Initial value Read/Write Bit name W TMB13 W TMB12 W TMB10 W TMB11 Timer mode register B1 (TMB1: $009) 2048t cyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc TMB12 TMB10TMB11 Input Clock Period and Input Clock Source D 2/EVNB (external event input) TMB13 Free-Running/Reload Timer Selection Free-running timer Reload timer Figure 33 Timer Mode Register B1 (TMB1)

Timer C Functions: Timer C has the following functions.

• Free-running/reload timer
• Watchdog timer
• Timer output operation (PWM output) The block diagram of timer C is shown in figure 40. Timer counter C (TCC) Port mode register A (PMRA) Selector System clock Prescaler S (PSS) Timer write register C lower (TWCL) Timer mode register C (TMC) Timer write register C upper (TWCU) Clock Free-running timer control signal Timer read register C lower (TRCL) Interrupt request flag of timer C (IFTC) Timer read register C upper (TRCU) Overflow TOC Timer output control signal Watchdog timer controller Watchdog on flag (WDON) System reset signal Internal data bus Timer output control logic 128 512 1024 2048 øPER Figure 40 Timer C Block Diagram

T (N + 1) T 256T T (256 – N) TMC3 = 0 (free-running timer) TMC3 = 1 (reload timer) Notes: T: Input clock period supplied to counter. (The clock source and system clock division N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) ratio are determined by timer mode register C.) Figure 42 PWM Output Waveform Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 26. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not change the timer C value. Timer C is changed to the value in timer write register B at the same time the upper digit (TWCU) is written to. Table 26 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer Write Register is Updated during Low PWM Output Reload Timer write register updated to value N Interrupt request TT × (255 – N)T Timer write register updated to value N Interrupt request T T × (255 – N) T

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C (TMC: $00D) Port mode register A (PMRA: $004) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F)

• Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 43. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C write instruction. Setting timer C’s initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Bit Initial value Read/Write Bit name W TMC3 W TMC2 W TMC0 W TMC1 Timer mode register C (TMC: $00D) 2048t cyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc TMC2 TMC0TMC1 Input Clock Period TMC3 Free-Running/Reload Timer Selection Free-running timer Reload timer 1024tcyc Figure 43 Timer Mode Register C (TMC)

Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D3/BUZZ pin function as shown in figure 44. It is reset to $0 by MCU reset. Serial Interface The serial interface serially transfers and receives 8-bit data, and includes the following features.

• Multiple transmit clock sources ¾ External clock ¾ Internal prescaler output clock ¾ System clock
• Output level control in idle states Five registers, an octal counter, and a selector are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register (SMR: $005) Port mode register A (PMRA: $004) Port mode register C (PMRC: $025) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector The block diagram of the serial interface is shown in figure 51.

(PMRC) SCK Selector System clock ø PER Prescaler S (PSS) Idle controller Serial mode register (SMR) Clock Serial data register (SR) Serial interrupt request flag (IFS) Selector 1/2 1/2 SI SO Octal counter (OC) I/O controller Transfer control signal Figure 51 Serial Interface Block Diagram Serial Interface Operation Selecting and Changing the Operating Mode: Table 27 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to the serial mode register. Note that the serial interface is initialized by writing data to the serial mode register. Refer to the following Serial Mode Register section for details. Table 27 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode

1 Transmit mode

1 Transmit/receive mode

Pin Setting: The R00/SCK pin is controlled by writing data to the serial mode register (SMR: $005). The R0 1/SI and R02/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007). Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SMR0– SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0) of port mode register C (PMRC: $025) as listed in table 28. Table 28 Serial Transmit Clock (Prescaler Output) PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0000 ‚ 2048 4096tcyc 1 ‚ 512 1024tcyc 10 ‚ 128 256t cyc 1 ‚ 32 64tcyc 10 0 ‚ 8 16t cyc 1 ‚ 24 tcyc 1000 ‚ 4096 8192tcyc 1 ‚ 1024 2048tcyc 10 ‚ 256 512t cyc 1 ‚ 64 128tcyc 10 0 ‚ 16 32t cyc 1 ‚ 48 tcyc

Operating States: The serial interface has the following operating states; transitions between them are shown in figure 52. STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode)

• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04, 14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait state is entered.

(Octal counter = 000, transmit clock disabled) Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) MCU reset00 SMR write 04 STS instruction01 Transmit clock02 8 transmit clocks STS instruction (IFS 1) SMR write (IFS 1)06 ← External clock mode STS wait state (Octal counter = 000, transmit clock disabled) Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) SMR write 14 STS instruction11 Transmit clock12 STS instruction (IFS 1)← 8 transmit clocks13 Internal clock mode Continuous clock output state (PMRA 0, 1 = 0, 0) SMR write Transmit clock17 Note: Refer to the Operating States section for the corresponding encircled numbers. MCU reset10 ←SMR write (IFS 1) Figure 52 Serial Interface State Transitions Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC: $025) to 0 or 1. The output level control example is shown in figure 53. Note that the output level cannot be controlled in transfer state.

/,/#01/#05 /#09/#0A/#0E /#14/#15 State MCU reset PMRA write SMR write PMRC write SRL, SRU write STS instruction SCK pin (input) SO pin IFS STS wait state Transmit clock wait state Transfer state Transmit clock wait state STS wait state Port selection External clock selection Output level control in idle states Dummy write for state transition Output level control in idle states Data write for transmission Undefined LSB MSB Flag reset at transfer completionExternal clock mode State MCU reset PMRA write SMR write PMRC write SRL, SRU write STS instruction SCK pin (output) SO pin IFS STS wait state Transfer state Transmit clock wait state STS wait state Port selection Internal clock selection Output level control in idle states Data write for transmission Output level control in idle states Undefined LSB MSB Flag reset at transfer completionInternal clock mode Figure 53 Example of Serial Interface Operation Sequence

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 54. Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1 Transmit clock error processing Normal termination Yes No Transmit clock error detection flowchart /#12/#17 Transmit clock error detection procedure State SCK pin (input) Transmit clock wait state Transfer state Transfer state Transmit clock wait state Noise Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. Flag set because octal counter reaches 000 Flag reset at transfer completion SMR write IFS 12 345678 Figure 54 Transmit Clock Error Detection

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and therefore the error can be detected. Notes on Use:

• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode register (SMR: $005) again.
• Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request flag, serial mode register write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register (SMR: $005) Serial Data Register (SRL: $006, SRU: $007) Port Mode Register A (PMRA: $004) Port Mode Register C (PMRC: $025) Miscellaneous Register (MIS: $00C) Serial Mode Register (SMR: $005): This register has the following functions (figure 55).
• R0 0/SCK pin function selection
• Transmit clock selection
• Prescaler division ratio selection
• Serial interface initialization Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.

W SMR3 W SMR2 W SMR0 W SMR1 Serial mode register (SMR: $005) SMR2 SMR0SMR1SMR3 R0 0/SCK Mode Selection R0 0 SCK SCK Output Output Input Clock Source External clock Prescaler Division Ratio Refer to table 28 Prescaler System clock Figure 55 Serial Mode Register (SMR) Port Mode Register C (PMRC: $025): This register has the following functions (figure 56).

• Prescaler division ratio selection
• Output level control in idle states Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer. By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle states. The output level changes at the same time that PMRC1 is written to.

Registers for A/D Converter Operation A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as shown in figure 63. Bit Initial value Read/Write Bit name W AMR13 W AMR12 W AMR10 W AMR11 AMR10 A/D mode register 1 (AMR1: $019) AMR11 AN 1 AMR12 2/AN2 Mode Selection R3 2 AN 2 AMR13 R3 3/AN3 Mode Selection R3 3 AN 3 R3 0/AN0 Mode Selection R3 0 R3 1/AN1 Mode Selection R3 1 Figure 63 A/D Mode Register 1 (AMR1) A/D Mode register 2 (AMR2: $01A): Two-bit write-only register which is used to set the A/D conversion period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D conversion period, and bit 1 selects port R4 as pins AN4–AN 7 in 4-pin units (figure 64). Bit Initial value Read/Write Bit name Not used Not used W AMR20 W AMR21 AMR20 1 67tcyc A/D mode register 2 (AMR2: $01A) AMR21 AN 4–AN 7 Conversion Time 34tcyc R4/AN 4–AN 7 Pin Selection Figure 64 A/D Mode Register 2 (AMR2)

A/D channel register value AMR A/D mode register value Figure 71 R Port/Analog Multiplexed Pin Circuit

Pin Description in PROM Mode The HD4074359 is a PROM version of a ZTAT ä microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 13 9 R A 1 IO 0 I/O 24 0 R 00/SCK I/O VCC 34 1 R 01/SI I/O VCC 44 2 R 02/SO I/O O 1 I/O 54 3 R 03/TOC I/O O 2 I/O 6 1 TEST I VPP

72 RESET I RESET I

15 10 R3 3/AN3 I/O O 3 I/O 16 11 R4 0/AN4 I/O O 4 I/O 17 12 R4 1/AN5 I/O M0 I 18 13 R4 2/AN6 I/O M1 I 19 14 R4 3/AN7 I/O 20 15 AV CC VCC 21 16 VCC VCC 22 17 D 0/INT0 I/O O 3 I/O 23 18 D 1/INT1 I/O O 4 I/O 24 19 D 2/EVNB I/O A1 I 25 20 D 3/BUZZ I/O A2 I 26 21 D 4/STOPC I/O 27 23 D 5 I/O A3 I 28 24 D 6 I/O A4 I 29 25 D 7 I/O A9 I 30 26 D 8 I/O VCC

Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 31 27 R8 0 I/O CE I 32 28 R8 1 I/O OE I 33 29 R8 2 I/O A13 I 34 30 R8 3 I/O A14 I 35 31 R1 0 I/O A5 I 36 32 R1 1 I/O A6 I 37 33 R1 2 I/O A7 I 38 34 R1 3 I/O A8 I 39 35 R2 0 I/O A0 I 40 36 R2 1 I/O A10 I 41 37 R2 2 I/O A11 I 42 38 R2 3 I/O A12 I Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin 2. O0 to O4 consist of two pins each. The each pair together before using them.

Programming the Built-In PROM The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling RESET , M0, and M1 low, as shown in figure 72. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a 100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 29. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000–$7FFF) must be specified. Table 29 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacture Model Name Package Manufacture Model Name DATA I/O corp 121 B DP-42S Hitachi HS4359ESS01H FP-44A HS4359ESH01H AVAL corp PKW-1000 DP-42S Hitachi HS4359ESS01H FP-44A HS4359ESH01H Control signals Address bus Data bus VCC GND VPP O 7–O 0 O 7 O 6 O 5 O 4–O 0 CE, OE A14–A0 O 4–O 0 RESET VCC GND VPP HD407A4359 PROM mode pins Socket adapter PROM programmer Figure 72 PROM Mode Connections

1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased and reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (V PP ): 12.5 V and 21 V. Remember that ZTATä devices require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 30. For details of PROM programming, refer to the following Notes on PROM Programming section. Table 30 PROM Mode Selection Pin Mode CE OE VPP O 0–O 4 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance

The MCU has three RAM addressing modes, as shown in figure 73 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. AP 9 AP 0 W 1 Y0 W register X register Y register RAM address Register Direct Addressing AP 9 AP 0RAM address Direct Addressing d 9 d0 2nd word of Instruction Opcode 1st word of Instruction AP 9 AP 0RAM address Memory Register Addressing m 3Opcode Instruction 000100 AP 8 AP 7 AP AP 5 AP 46 AP 3 AP 2 AP 1 AP AP AP AP AP AP AP AP87654321 d 8 d7 d6 d 5 d4 d3 d2 d1 AP 8 AP 7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 W 0 X3 X2 X1 X0 Y3 Y2 Y1 m 2 m 1 m 0 Figure 73 RAM Addressing Modes

ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 74 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–PC 0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC 7–PC 0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 76. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC 5–PC 0), and 0s are placed in the eight high- order bits (PC13–PC 6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 75. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter

d9 d 8 d7 d6 d 5 d4 d3 d2 d1 d0 2nd word of instruction Opcode 1st word of instruction [JMPL] [BRL] [CALL] PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0PC PC PC PC10 11 12 13Program counter Direct Addressing Zero Page Addressing a5 a 4 a3 a2 a 1 a 0 Instruction [CAL] Opcode PC 98 PC 76 PC 54 PC 3 PC 1 PC 0PCPC 10 11 12 13Program counter 0000 0 0 0 0 PC PC PC PC PC PC 2 B 1 B 0 A 3 A 2 A 1 A 0 Accumulator Program counter Table Data Addressing PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0PC PC PC10 11 12 13 B 2B 3 B register p3 p0[TBR] Instruction Opcode 0 0 p2 p1 PC Opcode b7 b6 b 5 b4 b3 b2 b1 b0 Instruction PC 90PC PC PC11 12 13Program counter Current Page Addressing [BR] PC 10 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PCPC 8 PC p0p1p2p3 Figure 74 ROM Addressing Modes

RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0RA RA RA10 11 1213 B 2B 3 B register 0 0 p3 p0[P] Instruction Opcode p2 p1 RA RO 9 RO 0RO 8 RO 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 BBB B AA AA321 0 32 10 If RO = 18Accumulator, B register ROM data Pattern Output RO 9ROM data R2 3 R2 2 R2 1 R2 0 R1 3 R1 2 R1 1 R1 0 If RO = 19Output registers R1, R2 RO 0RO 8 RO 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 Figure 75 P Instruction

256 (n – 1) + 255 256n BR AAA BR BBB 256n + 254 256n + 255 256 (n + 1) BBB NOP Figure 76 Branching when the Branch Destination is on a Page Boundary

Item Symbol Value Unit Notes Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V 1 Pin voltage VT –0.3 to VCC + 0.3 V 2 –0.3 to +15.0 V 3 Total permissible input currentå IO 105 mA 4 Total permissible output current –å IO 50 mA 5 Maximum input current IO 4 mA 6, 7 30 mA 6, 8 Maximum output current –I O 4 mA 7, 9 Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD407A4359. 2. Applies to all standard voltage pins. 3. Applies to intermediate-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from V CC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports D 0 to D8, R0, R1, R3, R4, and R8. 8. Applies to port R2. 9. The maximum output current is the maximum current flowing from V CC to each I/O pin.

Electrical Characteristics

DC Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C; HD404354/ HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Notes Input high voltage VIH RESET, SCK, INT0, INT1, STOPC, EVNB 0.8VCC —V CC + 0.3 V SI 0.7 VCC —V CC + 0.3 V OSC 1 VCC – 0.5 — V CC + 0.3 V Input low voltage V IL RESET, SCK, INT0, INT1, STOPC, EVNB –0.3 — 0.2V CC V SI –0.3 — 0.3V CC V OSC 1 –0.3 — 0.5 V Output high voltage V OH SCK, SO, TOC V CC – 0.5 — — V –I OH = 0.5 mA Output low voltage V OL SCK, SO, TOC — — 0.4 V I OL = 0.4 mA I/O leakage current IL| RESET, SCK, SI, SO,TOC,OSC 1, INT0, INT1, STOPC, EVNB —— 1 mAV in = 0 V to VCC 1 Current dissipation in active mode I CC VCC — — 5.0 mA V CC = 5 V, fOSC = 4 MHz Current dissipation in standby mode I SBY VCC — — 2.0 mA V CC = 5 V, fOSC = 4 MHz Current dissipation in stop mode I STOP VCC —— 1 0 mAV CC = 5 V 4 Stop mode retaining voltage V STOP VCC 2— — V Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at GND

1. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at VCC TEST at GND D 0–D 8, R0–R4, R8, RA1 at VCC 4. This is the source current when no I/O current is flowing. Test conditions: Pins:RESET at VCC TEST at GND D 0–D 8, R0–R4, R8, RA1 at VCC I/O Characteristics for Standard Pins (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C; HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Note Input high voltage VIH D 0–D 8, R0, R1, R3, R4, R8, RA1 0.7VCC —V CC + 0.3 V Input low voltage VIL D 0–D 8, R0, R1, R3, R4, R8, RA1 –0.3 — 0.3V CC V Output high voltage VOH D 0–D 8, R0, R1, R3, R4, R8 VCC – 0.5 — — V –I OH = 0.5 mA Output low voltage VOL D 0–D 8, R0, R1, R3, R4, R8 — — 0.4 V I OL = 1.6 mA Input leakage current |IIL|D 0–D 8, R0, R1, R3, R4, R8, RA1 —— 1 mAV in = 0 V to VCC 1 Pull-up MOS current –IPU D 0–D 8, R0, R1, R3, R4, R8 30 150 300 mAV CC = 5 V, Vin = 0 V Note: 1. Output buffer current is excluded.

I/O Characteristics for Intermediate-Voltage Pins (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C;HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD 40A4358: V CC = 2.7 to

6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)

Item Symbol Pins Min Typ Max Unit Test Condition Note Input high voltage VIH R2 0.7V CC —1 2V Input low voltage V IL R2 –0.3 — 0.3V CC V Output high voltage V OH R2 11.5 — — V 500 kW at 12 V Output low voltage V OL R2 — — 0.4 V I OL = 0.4 mA — — 2.0 V I OL = 15 mA, VCC = 4.5 to 5.5 V I/O leakage current IL| R 2 ——2 0 mAV in = 0 V to 12 V 1 Note: 1. Excludes output buffer current.

A/D Converter Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C; HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Note Analog supply voltage AV CC AV CC VCC – 0.3 VCC VCC + 0.3 V 1 Analog input voltage AV in AN 0–AN 7 AV SS —A V CC V Current flowing between AV CC and AVSS IAD — — 200 mAV CC = AVCC = 5.0 V Analog input capacitance CA in AN 0–AN 7 ——3 0 p F Resolution 8 8 8 Bit Number of input channels 0 — 8 Channel Absolute accuracy —— –2.0 LSB Conversion time 34 — 67 t cyc Input impedance AN 0–AN 7 1— — M W Note: 1. Connect this to VCC if the A/D converter is not used.

Standard fOSC = 5.0 MHz Version AC Characteristics (HD404354/HD404356/HD404358: VCC = 2.7 to

6.0 V, GND = 0 V, Ta = –20 to +75°C)

Item Symbol Pins Min Typ Max Unit Test Condition Note Clock oscillation frequency fOSC OSC 1, OSC2 0.4 4 5.0 MHz 1/4 system clock division ratio Instruction cycle time tcyc 0.8 1 10 ms Oscillation stabilization time (ceramic oscillator) t RC OSC 1, OSC2 — — 7.5 ms 1 Oscillation stabilization time (crystal oscillator) t RC OSC 1, OSC2 — — 40 ms 1 External clock high width t CPH OSC 1 8 0 ——n s 2 External clock low width tCPL OSC 1 8 0 ——n s 2 External clock rise time tCPr OSC 1 — — 20 ns 2 External clock fall time tCPf OSC 1 — — 20 ns 2 INT0, INT1, EVNB high widths tIH INT0, INT1, EVNB 2 ——t cyc 3 INT0, INT1, EVNB low widths tIL INT0, INT1, EVNB 2 ——t cyc 3 RESET low width t RSTL RESET 2 ——t cyc 4 STOPC low width t STPL STOPC 1 ——t RC 5 RESET rise time t RSTr RESET — — 20 ms 4 STOPC rise time t STPr STOPC — — 20 ms 5 Input capacitance C in All input pins except and R2 — — 15 pF f = 1 MHz, V in = 0 V R2 — — 30 pF f = 1 MHz, V in = 0 V Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After V CC reaches 2.7 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC . When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 77. 3. Refer to figure 78. 4. Refer to figure 79. 5. Refer to figure 80.

High-Speed fOSC = 8.5 MHz Version AC Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C; HD40A4354/HD40A4356/HD40A4358: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C) Item Symbol Pins Min Typ Max Unit Test Condition Note Clock oscillation frequency fOSC OSC 1, OSC2 0.4 4 5.0 MHz 1/4 system clock division ratio 0.4 4 8.5 MHz 1/4 system clock division ratio, V CC = 4.5 to 5.5 V Instruction cycle time tcyc 0.8 1 10 ms 0.47 1 10 msV CC = 4.5 to 5.5 V Oscillation stabilization time (ceramic oscillator) t RC OSC 1, OSC2 — — 7.5 ms 1 Oscillation stabilization time (crystal oscillator) t RC OSC 1, OSC2 — — 40 ms 1 External clock high width t CPH OSC 1 80 — — ns 2 47 — — ns V CC = 4.5 to 5.5 V 2 External clock low width t CPL OSC 1 80 — — ns 2 47 — — ns V CC = 4.5 to 5.5 V 2 External clock rise time t CPr OSC 1 — — 20 ns 2 — — 15 ns V CC = 4.5 to 5.5 V 2 External clock fall time tCPf OSC 1 — — 20 ns 2 — — 15 ns V CC = 4.5 to 5.5 V 2 INT0, INT1, EVNB high widths tIH INT0, INT1, EVNB 2 — — t cyc 3 INT0, INT1, EVNB low widths tIL INT0, INT1, EVNB 2 — — t cyc 3 RESET low width t RSTL RESET 2— — t cyc 4 STOPC low width t STPL STOPC 1— — t RC 5 RESET rise time t RSTr RESET — — 20 ms 4 STOPC rise time t STPr STOPC — — 20 ms 5 Input capacitance C in All input pins except TEST and — — 15 pF f = 1 MHz, V in = 0 V TEST — — 15 pF f = 1 MHz, V in = 0 V 6 — — 180 pF f = 1 MHz, V in = 0 V 7 R2 — — 30 pF f = 1 MHz, V in = 0 V

Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 2.7 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC . When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 77. 3. Refer to figure 78. 4. Refer to figure 79. 5. Refer to figure 80. 6. Applies to the HD40A4354, HD40A4356, HD40A4358. 7. Applies to the HD407A4359.

Serial Interface Timing Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C; HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1— — t cyc Load shown in figure 82 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc Load shown in figure 82 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc Load shown in figure 82 1 Transmit clock rise time tSCKr SCK — — 80 ns Load shown in figure 82 1 Transmit clock fall time tSCKf SCK — — 80 ns Load shown in figure 82 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 82 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1— — t cyc 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc 1 Transmit clock rise time tSCKr SCK ——8 0 n s 1 Transmit clock fall time tSCKf SCK ——8 0 n s 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 82 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 Note: 1. Refer to figure 81.

Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404354, HD40A4354, HD404356 and HD40A4356 as an 8-kword version (HD404358, HD40A4358). The 8-kword and 16-kword data sizes are required to change ROM data to mask manu facturing data since the program used is for an 8-k or 16-kword version. This limitation applies when using an EPROM or a data base. Vector address Zero-page subroutine (64 words) Pattern & program (4,096 words) Not used ROM 4-kword version: HD404354, HD40A4354 $0000 $000F $0010 $003F $0040 $0FFF $1000 $1FFF Fill this area with 1s Vector address Zero-page subroutine (64 words) Pattern & program (6,144 words) Not used ROM 6-kword version: HD404356, HD40A4356 $0000 $000F $0010 $003F $0040 $17FF $1800 $1FFF

HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358 Please check off the appropriate applications and enter the necessary information. 2. ROM code media Date of order Customer Department Name ROM code name LSI number EPROM: Ceramic oscillator Crystal oscillator External clock f = MHz f = MHz f = MHz 3. System Oscillator (OSC1, OSC2) The upper bits and lower bits are mixed together. The upper five bits and lower five bits EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS.

5 MHz operation

8.5 MHz operation

1. ROM size DP-42S FP-44A 5. Package Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). Used Not used 4. Stop mode

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