HD3SS3212 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 27
Technical content
10 RSVD1
11 GND
Copyright © 2016, Texas Instruments Incorporated B0± A0+ A0± B0+ A1+ A1± C0+ C0 ± SEL B1+ B1± C1+ C1 ± Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. HD3SS3212,HD3SS3212I SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 HD3SS3212xTwo-ChannelDifferential2:1/1:2USB3.1Mux/Demux
1 Features
1• Provides MUX/DEMUX Solution for USB Type- C™ Ecosystem for USB 3.1 Gen 1 and Gen 2 Data Rates
- Compatible With MIPI DSI/CSI, FPDLinkIII, LVDS, and PCIE Gen II, III
- Operates up to 10 Gbps
- Wide –3-dB Differential BW of over 8 GHz
- Excellent Dynamic Characteristics (at 5 GHz) – Crosstalk = –32 dB – Off Isolation = –19 dB – Insertion Loss = –1.6 dB – Return Loss = –12 dB
- Bidirectional "Mux/De-Mux" Differential Switch
- Supports Common Mode Voltage 0 to 2 V
- Single Supply Voltage VCC of 3.3 V
- Commercial Temperature Range of 0°C to 70°C (HD3SS3212RKS)
- Industrial Temperature Range of –40°C to 85°C (HD3SS3212IRKS)
2 Applications
- USB Type-C™ Ecosystem
- Desktop and Notebook PCs
- Server/Storage Area Networks
- PCI Express Backplanes
- Shared I/O Ports
- FPDLinkII and FPDLinkIII Switching
3 Description
The HD3SS3212 is a high-speed bidirectional passive switch in mux or demux configurations suited for USB Type-C™ application supporting USB 3.1 Gen 1 and Gen 2 data rates. Based on control pin SEL, the device provides switching on differential channels between Port B or Port C to Port A. The HD3SS3212 is a generic analog differential passive switch that can work for any high-speed interface applications requiring a common mode voltage range of 0 to 2 V and differential signaling with differential amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the entire common mode voltage range. Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the signal eye diagram with very little added jitter. It consumes <2 mW of power when operational and has a shutdown mode exercisable by OEn pin resulting <20 µW. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) HD3SS3212 VQFN (20) 2.50 mm × 4.50 mm × 0.5-mm pitchHD3SS3212I (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Simplified Schematic Pinout
HD3SS3212,HD3SS3212I SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Table of Contents
13.2 Receiving Notification of Documentation Updates 19
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (May 2016) to Revision F Page Changes from Revision D (March 2016) to Revision E Page
- Changed text "HD3SS3212 requires 3.3-V ±10%" To: "HD3SS3212 requires 3.3-V" in the Design Requirements Changes from Revision C (January 2016) to Revision D Page Changes from Revision B (January 2016) to Revision C Page
- Changed pin 1 From: NC To: RSVD1 , changed pin 10 From: NC To: RSVD2, and updated the Description in the Changes from Revision A (August 2015) to Revision B Page
HD3SS3212,HD3SS3212I www.ti.com SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated Changes from Original (May 2015) to Revision A Page
HD3SS3212,HD3SS3212I SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
5 Device Comparison Table
OPERATING TEMPERATURE (°C) PACKAGE(1)(2) ORDERABLE PART NUMBER 0 to 70 RKS 20 pins HD3SS3212RKSR –40 to 85 RKS 20 pins HD3SS3212IRKSR (1) The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when the port is selected.
6 Pin Configuration and Functions
TYPE(1) DESCRIPTION NAME NO. VCC 6 P 3.3-V power OEn 2 I Active-low chip enable L: Normal operation H: Shutdown A0p 3 I/O Port A, channel 0, high-speed positive signal A0n 4 I/O Port A, channel 0, high-speed negative signal GND 5, 11, 20 G Ground A1p 7 I/O Port A, channel 1, high-speed positive signal A1n 8 I/O Port A, channel 1, high-speed negative signal SEL 9 I Port select pin. L: Port A to Port B H: Port A to Port C C1n 12 I/O Port C, channel 1, high-speed negative signal (connector side) C1p 13 I/O Port C, channel 1, high-speed positive signal (connector side) C0n 14 I/O Port C, channel 0, high-speed negative signal (connector side) C0p 15 I/O Port C, channel 0, high-speed positive signal (connector side) B1n 16 I/O Port B, channel 1, high-speed negative signal (connector side) B1p 17 I/O Port B, channel 1, high-speed positive signal (connector side) B0n 18 I/O Port B, channel 0, high-speed negative signal (connector side)
HD3SS3212,HD3SS3212I www.ti.com SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. B0p 19 I/O Port B, channel 0, high-speed positive signal (connector side) RSVD1 1 O Can be left not connected or can be fed to VCC RSVD2 10 O (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
see (1) MIN MAX UNIT VCC Supply voltage –0.5 4 V Voltage Differential I/O –0.5 2.5 V Control pins –0.5 VCC+ 0.5 Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 2.7 3.6 V Vih Input high voltage (SEL, OEn pins) 1.7 VCC V Vil Input low voltage (SEL, OEn pins) –0.1 0.8 V Vdiff High-speed signal pins differential voltage 0 1.8 Vpp Vcm High speed signal pins common mode voltage 0 2 V TA Operating free-air/ambient temperature HD3SS3212RKS 0 70 HD3SS3212IRKS –40 85 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) HD3SS3212 UNITRKS (VQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 46.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 41.8 °C/W RθJB Junction-to-board thermal resistance 4.4 °C/W ψJT Junction-to-top characterization parameter 17.6 °C/W ψJB Junction-to-board characterization parameter 1.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 17.6 °C/W
HD3SS3212,HD3SS3212I SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) There is a 20-kΩ pull-down in non-selected port.
7.5 Electrical Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Device active current VCC = 3.3 V, OEn = 0 0.6 0.8 mA ISTDN Device shutdown current VCC = 3.3 V, OEn = VCC 5 20 µA CON Output ON capacitance 0.6 pF COFF Output OFF capacitance 0.8 pF RON Output ON resistance VCC = 3.3 V; VCM = 0 to 2 V; IO = –8 mA 5 8 Ω ΔRON On-resistance match between pairs of the same channel VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V; IO = –8 mA 0.5 Ω RFLAT_ON On-resistance flatness RON(MAX) – RON(MAIN) VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V 1 Ω IIH,CTRL Input high current, control pins (SEL, OEn) 1 µA IIL,CTRL Input low current, control pins (SEL, OEn) 1 µA IIH,HS Input high current, high-speed pins [Ax/Bx/Cx][p/n] VIN = 2 V for selected port, A and B with SEL = 0, and A and C with SEL = VCC 1 µA IIH,HS Input high current, high-speed pins [Ax/Bx/Cx][p/n] VIN = 2 V for non-selected port, C with SEL = 0, and B with SEL = VCC (1) 100 140 µA IIL,HS Input low current, high-speed pins [Ax/Bx/Cx][p/n] 1 µA
7.6 High-Speed Performance Parameters
PARAMETER TEST CONDITION MIN TYP MAX UNIT IL Differential insertion loss ƒ = 0.3 MHz –0.5 dB ƒ = 0.625 MHz -0.55 ƒ = 2.5 GHz –0.8 ƒ = 4 GHz –1.4 ƒ = 5 GHz –1.6 BW –3-dB bandwidth 8 GHz RL Differential return loss ƒ = 0.3 MHz –25 dB ƒ = 2.5 GHz –13 ƒ = 4 GHz –13 ƒ = 5 GHz – 12 OIRR Differential OFF isolation ƒ = 0.3 MHz –75 dB ƒ = 2.5 GHz –23 ƒ = 4 GHz –19 ƒ = 5 GHz –19 XTALK Differential crosstalk ƒ = 0.3 MHz –90 dB ƒ = 2.5 GHz –35 ƒ = 4 GHz –32.5 ƒ = 5 GHz –32
7.7 Switching Characteristics
8 Parameter Measurement Information
Figure 1. Test Setup Figure 2. Switch On and Off Timing Diagram
Figure 3. Timing Diagrams and Test Setup
Copyright © 2016, Texas Instruments Incorporated B0± A0+ A0± B0+ A1+ A1± C0+ C0 ± SEL B1+ B1± C1+ C1 ± HD3SS3212,HD3SS3212I www.ti.com SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
The HD3SS3212 is a generic analog differential passive switch that can work for any high-speed interface applications requiring a common mode voltage range of 0 to 2 V and differential signaling with differential amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the entire common mode voltage range. Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the signal eye diagram with very little added jitter. It consumes <2 mW of power when operational and has a shutdown mode exercisable by OEn pin resulting <20 µW.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Output Enable and Power Savings
The HD3SS3212 has two power modes, active/normal operating mode and standby/shutdown mode. During standby mode, the device consumes very-little current to save the maximum power. To enter standby mode, the OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn control pin should be pulled low to GND or dynamically controlled to switch between H or L. HD3SS3212 consumes <2 mW of power when operational and has a shutdown mode exercisable by the EN pin resulting <20 µW.
9.4 Device Functional Modes
care to ensure the same polarity is maintained on Port A versus Ports B/C. Table 1. Port Select Control Logic(1)
0.1 F µ
validate and test their design implementation to confirm system functionality.
10.1 Application Information
pin within a system or from a microcontroller. signals to the correct pin. The other applications are more generic because different connectors can be used. option to provide AC coupling; 0603 size capacitors also work. Avoid the 0805 size capacitors and C-packs. which are usually routed on the top layer of the board. between the switch and endpoint. In this situation, the switch is biased by the system/host controller. Figure 4. AC Coupling Capacitors between Switch TX and Endpoint TX situation, the switch on top is biased by the endpoint and the lower switch is biased by the host controller.
Figure 5. AC Coupling Capacitors on Host TX and Endpoint TX on both sides of the switch (shown in Figure 6). A biasing voltage of <2 V is required in this case. Figure 6. AC Coupling Capacitors on Both Sides of Switch provides the generic location for the AC coupling capacitors for this application.
Figure 7. AC Coupling Capacitors for USB Type C
10 N 1
10.2 Typical Applications
Figure 8. Down Facing Port for USB3.1 Type C Connector
10.2.1.1 Design Requirements
Table 2. Design Parameters
10.2.1.2 Detailed Design Procedure
device can support 2 to 3 inches of board trace and a connector on either end. To design in the HD3SS3212, the designer needs to understand the following.
- Determine the loss profile between circuits that are to be muxed or demuxed.
- Provide clean impedance and electrical length matched board traces.
- Depending upon the application, determine the best place to put the 100-nF coupling capacitor.
- Provide a control signal for the SEL and OEn pins.
- The thermal pad must be connected to ground.
6 VCC
- See the application schematics on recommended decouple capacitors from VCC pins to ground
10.2.1.3 Application Curves
Figure 9. 10 Gbps Source Eye Diagram Figure 10. 10 Gbps Output Eye Diagram
10.3 Systems Examples
Figure 11. Up Facing Port for USB3.1 USB Type-C Connector
10.3.2 PCIE/SATA/USB
Figure 12. PCIE Motherboard
10.3.3 PCIE/eSATA
Figure 13. PCIE and eSATA Combo
10.3.4 USB/eSATA
Figure 14. eSATA and USB 3.0 Combo Connector
10.3.5 MIPI Camera Serial Interface
Figure 15. CSI Camera Array
11 Power Supply Recommendations
at the device VCC near the pin.
12 Layout
12.1 Layout Guidelines
operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias. provided in PowerPAD Thermally-Enhanced Package, SLMA002.
12.2 Layout Example
Figure 16. HD3SS3212 Basic Layout Example for Application Shown
13 Device and Documentation Support
13.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 3. Related Links
13.2 Receiving Notification of Documentation Updates
that has changed (if any). For change details, check the revision history of any revised document.
13.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
13.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C 20X 0.3 0.2 1±0.1 20X 0.5 0.3
1 MAX
(0.2) TYP 0.05 0.00 14X 0.5 3.5 2X 0.5 3±0.1 A 2.6 2.4 B 4.6 4.4 VQFN - 1 mm max heightRKS0020A PLASTIC QUAD FLATPACK - NO LEAD 4222490/A 10/2015 PIN 1 INDEX AREA 0.08 SEATING PLANE (OPTIONAL) PIN 1 ID
0.1 C A B
0.05 EXPOSED THERMAL PAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.300 HD3SS3212,HD3SS3212I SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
20X (0.6) 20X (0.25) 16X (0.5) (4.3) (2.3) (R ) TYP0.05 (1.25) ( ) VIA TYP 0.2 (1) (3) VQFN - 1 mm max heightRKS0020A PLASTIC QUAD FLATPACK - NO LEAD 4222490/A 10/2015 SYMM 129 10 11 SYMM LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) HD3SS3212,HD3SS3212I www.ti.com SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN 20X (0.6) 20X (0.25) 16X (0.5) (2.3) (4.3) 2X (0.95) (0.76) (R ) TYP0.05 2X (1.31) VQFN - 1 mm max heightRKS0020A PLASTIC QUAD FLATPACK - NO LEAD 4222490/A 10/2015 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP BASED ON 0.125 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PAD 83% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 10 11 HD3SS3212,HD3SS3212I SLASE74F –MAY 2015–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: HD3SS3212 HD3SS3212I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) HD3SS3212IRKSR Active Production VQFN (RKS) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HD3212I HD3SS3212IRKSR.B Active Production VQFN (RKS) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HD3212I HD3SS3212IRKSRG4.B Active Production VQFN (RKS) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HD3212I HD3SS3212IRKST Active Production VQFN (RKS) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HD3212I HD3SS3212IRKST.B Active Production VQFN (RKS) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HD3212I HD3SS3212RKSR Active Production VQFN (RKS) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 HDS3212 HD3SS3212RKSR.B Active Production VQFN (RKS) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HDS3212 HD3SS3212RKST Active Production VQFN (RKS) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 HDS3212 HD3SS3212RKST.B Active Production VQFN (RKS) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HDS3212 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1
www.ti.com 23-May-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF HD3SS3212 :
- Automotive : HD3SS3212-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2020 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) HD3SS3212IRKSR VQFN RKS 20 3000 210.0 185.0 35.0 HD3SS3212IRKST VQFN RKS 20 250 210.0 185.0 35.0 HD3SS3212RKSR VQFN RKS 20 3000 210.0 185.0 35.0 HD3SS3212RKST VQFN RKS 20 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2020 Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated