DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 15

Technical content

Features

  • Converter or Repeater Mode
  • Independent Manchester Encoder and Decoder Operation
  • Static to One Megabit/sec Data Rate Guaranteed
  • Low Bit Error Rate
  • Digital PLL Clock Recovery
  • On Chip Oscillator
  • Low Operating Power: 50mW Typical at +5V
  • Pb-Free Available (RoHS Compliant) Pinout HD-6409 (20 LD PDIP, SOIC) TOP VIEW 1BZI BOI UDI SD/CDS SDO SRST DCLK NVM RST GND VCC BZO SS ECLK BOO CTS MS OX IX CO

Ordering Information

(1 MEGABIT/SEC) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HD3-6409-9 HD3-6409-9 -40 to +85 20 Ld PDIP E20.3 HD3-6409-9Z (Notes 2, 3) HD3-6409-9Z -40 to +85 20 Ld PDIP (Pb-fre e) E20.3 HD9P6409-9Z (Notes 2, 3) HD9P6409-9Z -40 to +85 20 Ld SOIC (Pb-fre e) M20.3 HD9P6409-9Z96 (Notes 1, 2, 3) HD9P6409-9Z -40 to +85 20 Ld SOIC Ta pe & Reel (Pb-free) M20.3 NOTES: 1. “96” suffix is for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN2951.4Data Sheet October 1, 2015 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC Copyright Intersil Americas LLC 1997, 2005, 2008, 2015. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2951.4 October 1, 2015 Block Diagram Logic Symbol EDGE DETECTOR COMMAND SYNC GENERATOR OUTPUT SELECT LOGIC BOI BZI UDI RST SD/CDS IX OX CO SS RESET 5-BIT SHIFT REGISTER AND DECODER DATA INPUT LOGIC INPUT/ OUTPUT SELECT OSCILLATOR COUNTER CIRCUITS MANCHESTER ENCODER SDO NVM BOO BZO CTS SRST MS ECLK DCLK SD CLOCK GENERATOR ENCODER CONTROL DECODER SS CO SD/CDS ECLK MS RST SDO DCLK NVM SRST OX IX BOO BZO CTS BOI BZI UDI HD-6409HD-6409

3 FN2951.4 October 1, 2015 Pin Descriptions PIN NUMBER TYPE SYMBOL NAME DESCRIPTION 1 I BZl Bipolar Zero Input Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. 2 I BOl Bipolar One Input Used in conj unction with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. 3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl ), Unipolar Data Input (UDl) is used to input Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for data input, UDI must be held low.

4 I/O SD/CDS Serial Data/Command

In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern. 5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. 6 O SRST Serial Reset In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. 7O N V M Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received. 8 O DCLK Decoder Clock The decoder clo ck is a 1X clock recovered from BZl and BOl, or UDI to synchronously output received NRZ data (SDO). 9I R S T Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode, RST has the same effect on SDO, DCLK and NVM as in the converter mode. When RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received.

10 I GND Ground Ground

11 O C O Clock Output Buffered output of clock input I X. May be used as clock signal for other peripherals. 12 I I X Clock Input I X is the input for an external clock or, if the internal oscillator is used, IX and OX are used for the connection of the crystal. 13 O O X Clock Drive If the internal oscillator is used, OX and IX are used for the connection of the crystal. 14 I MS Mode Select MS must be held low for operation in the conver ter mode, and high for operation in the repeater mode. 15 I CTS Clear to Send In the converter mode, a high disables the encoder , forcing outputs BOO, BZO high and ECLK low. A high to low transition of CTS initiates transmission of a Command sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function of CTS is identical to that of the converter mode with the exception that a transition of CTS does not initiate a synchronization sequence. 16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock o utput used to receive serial NRZ data to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop. 17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency. 18 O BZO Bipolar Zero Output BZO and its logical complement BOO are the Manchester data outputs of the encoder. The inactive state for these outputs is in the high state. 19 O BOO Bipolar One Out See pin 18. 20 I V CC VCC VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 20) to GND (pin 10) is recommended. NOTE: (I) Input (O) Output HD-6409HD-6409

data to the MED at pin SD/CDS. Manchester “0” bits followed by a command sync pulse. synchronized with incoming data for its clocking. pattern. A data sync is a logically inverted command sync. the decoded NRZ data transmitted out of SDO. When RST is low, SDO, DCLK and NVM are forced low. external register on every high to low transition of this clock. FIGURE 1. ENCODER OPERATION

FIGURE 7. MANCHESTER ENCODER UART

8 FN2951.4 October 1, 2015 Common Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 4) JA (°C/W) JC (°C/W) Maximum Junction Temperature http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by 2 IX clock cycles (16X mode) or 6 IX clock cycles (32X mode). 3. The maximum zero crossing tolerance is 2 IX clock cycles (16X mode) or 6 IX clock cycles (32 mode) from the nominal. 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. SYMBOL PARAMETER TEST CONDITIONS (Note 5) MIN MAX UNITS VIH Logical “1” Input Voltage V CC = 4.5V 70% V CC -V VIL Logical “0” Input Voltage V CC = 4.5V - 20% V CC V VIHR Logic “1” Input Voltage (Reset)V CC = 5.5V V CC -0.5 - V VILR Logic “0” Input Voltage (Reset)V CC = 4.5V - GND +0.5 V VIHC Logical “1” Input Voltage (Clock) V CC = 5.5V V CC -0.5 - V VILC Logical “0” Input Voltage (Clock) V CC = 4.5V - GND +0.5 V II Input Leakage Current (Except IX)V IN = VCC or GND, VCC = 5.5V -1.0 +1.0 A II Input Leakage Current (IX)V IN = VCC or GND, VCC = 5.5V -20 +20 A IO I/O Leakage Current V OUT = VCC or GND, VCC = 5.5V -10 +10 A VOH Output HIGH Voltage (All Except OX)I OH = -2.0mA, VCC = 4.5V (Note 6) V CC -0.4 - V VOL Output LOW Voltage (All Except OX)I OL = +2.0mA, VCC = 4.5V (Note 6) - 0.4 V ICCSB Standby Power Supply Current V IN = VCC or GND, VCC = 5.5V, Outputs Open - 100 A ICCOP Operating Power Supply Current f = 16.0MHz, V IN = VCC or GND VCC = 5.5V, CL = 50pF - 18.0 mA FT Functional Test (Note 5) - - - NOTES: 5. Tested as follows: f = 16MHz, VIH = 70% VCC, VIL = 20% VCC, VOH  VCC/2, and VOL VCC/2, VCC = 4.5V and 5.5V. 6. Interchanging of force and sense conditions is permitted HD-6409HD-6409

9 FN2951.4 October 1, 2015 Capacitance TA = +25°C, Frequency = 1MHz. SYMBOL PARAMETER TEST CONDITIONS TYP UNITS CIN Input Capacitance All measurements are referenced to device GND 1 0p F COUT Output Capacitance 12 pF SYMBOL PARAMETER TEST CONDITIONS (Note 7) MIN MAX UNITS fC Clock Frequency - - 16 MHz tC Clock Period - 1/f C -s e c t1 Bipolar Pulse Width - t C+10 - ns t3 One-Zero Overlap - - t C-10 ns tCH Clock High Time f = 16.0MHz 20 - ns tCL Clock Low Time f = 16.0MHz 20 - ns tCE1 Serial Data Setup Time - 120 - ns tCE2 Serial Data Hold Time - 0 - ns tCD2 DCLK to SDO, NVM - - 40 ns tR2 ECLK to BZO - - 40 ns tr Output Rise Time (All except Clock) From 1.0V to 3.5V, C L = 50pF, Note 8 - 50 ns tf Output Fall Time (All except Clock) From 3.5V to 1.0V, C L = 50pF, Note 8 - 50 ns tr Clock Output Rise Time From 1.0V to 3.5V, C L = 20pF, Note 8 - 11 ns tf Clock Output Fall Time From 3.5V to 1.0V, C L = 20pF, Note 8 - 11 ns tCE3 ECLK to BZO, BOO Notes 8, 9 0.5 1.0 DBP tCE4 CTS Low to BZO, BOO Enabled Notes 8, 9 0.5 1.5 DBP tCE5 CTS Low to ECLK Enabled Notes 8, 9 10.5 11.5 DBP tCE6 CTS High to ECLK Disabled Notes 8, 9 - 1.0 DBP tCE7 CTS High to BZO, BOO Disabled Notes 8, 9 1.5 2.5 DBP tCD1 UDI to SDO, NVM Notes 8, 9 2.5 3.0 DBP tCD3 RST Low to CDLK, SDO, NVM Low Notes 8, 9 0.5 1.5 DBP tCD4 RST High to DCLK, Enabled Notes 8, 9 0.5 1.5 DBP tR1 UDI to BZO, BOO Notes 8, 9 0.5 1.0 DBP tR3 UDI to SDO, NVM Notes 8, 9 2.5 3.0 DBP NOTES: Input rise and fall times driven at 1ns/V, Output load = 50pF. 8. Limits established by characterization and are not production tested. 9. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. HD-6409HD-6409

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2951.4 October 1, 2015 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 1, 2015 FN2951.4 Added Rev History beginning with Rev 4. Added About Intersil Verbiage. Updated Ordering Information on page 1 Updated POD M20.3 to most current version. Revision changes are as follows: Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern HD-6409

14 FN2951.4 October 1, 2015 HD-6409 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpen- dicular to datum . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E20.3 (JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.55 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N2 0 2 0 9 Rev. 0 12/93

15 FN2951.4 October 1, 2015 HD-6409 Package Outline Drawing M20.3

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)

Rev 3, 2/11 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW 13.00 0.75 0.25 x 45° 0.32 0.23 MAX 1.27 0.40 10.65 10.007.60 7.40 12 3 INDEX AREA 2.65 2.35 0.30 MAXBSC 1.27 0.35 0.49 0.25 (0.10) MC S BMA 0.10 (0.004) 0.25 (0.10) MB M 1 2

1.27 BSC

(9.40mm) SEATING PLANE (0.60) (2.00) NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension does not include mold flash, protrusions or gate 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 8. Controlling dimension: MILLIMETER. 9. Dimensions in ( ) for reference only. burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. (0.024 inch) 10. JEDEC reference drawing number: MS-013-AC. 12.60