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Document overview

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Technical content

Features

  • Low Bit Error Rate
  • Sync Identification and Lock-In
  • Clock Recovery
  • Manchester II Encoder, Decoder
  • Separate Encode and Decode
  • Single Power Supply
  • 24 Ld Package
  • Pb-Free Plus Anneal Available (RoHS Compliant) d VW ESC TD SDO DC BZI BOI UDI DSC CDS DR GND VCC SCI SD SS EE BOO BZO DBS MR EC SDI OI

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. NO. HD3-6408-9 No longer available or supported, recommended replacement HD3-6408-9Z HD3-6408-9 -40 to +85 24 Ld PDIP E24.6 HD3-6408-9Z (Note) HD3-6408-9Z -40 to +85 24 Ld PDIP* (Pb-Free) E24.6 HD1-6408-9 HD1-6408-9 -40 to +85 24 Ld CERDIP F24.6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Data Sheet October 1, 2015

2 FN2952.3 October 1, 2015 Block Diagrams ENCODER DECODER CHARACTER FORMER COUNT DECODER BIT COUNTER 2 PARITY SYNC DATA  6 EC SCI ESC SD SS SDI 18 EE

17 BOO

3 FN2952.3 October 1, 2015 Pin Description PIN TYPE SYMBOL SECTION DESCRIPTION 1 O VW Decoder Output high indicates receipt of a VALID WORD. 2 O ESC Encoder ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The Encoder samples SDI on the low-to-high transition of ESC.

3 O TD Decoder TAKE DATA output is high during receipt of data afte r identification of a sync pulse

and two valid Manchester data bits. 4 O SDO Decoder SERIAL DATA OUT delivers received data in correct N RZ format.

5 I DC Decoder DECODER CLOCK input drives the transition finder, and the synchronizer which in

turn supplies the clock to the balance of the Decoder. Input a frequency equal to 12X the data rate.

6 I BZI Decoder A high input should be applied to BIPOLAR ZERO IN w hen the bus is in its negative

state. This pin must be held high when the Unipolar input is used.

7 I BOI Decoder A high input should be applied to BIPOLAR ONE IN wh en the bus is in its positive

state, this pin must be held low when the Unipolar input is used.

8 I UDI Decoder With pin 6 high and pin 7 low, this pin enters UNIP OLAR DATA IN to the transition

finder circuit. If not used this input must be held low.

9 O DSC Decoder DECODER SHIFT CLOCK output delivers a frequency (DE CODER CLOCK ³ 12),

synchronized by the recovered serial data stream.

10 O CDS Decoder COMMAND/DATA SYNC output high occurs during output of decoded data which

was preceded by a Command synchronizing character. A low output indicates a Data synchronizing character.

11 I DR Decoder A high input to DECODER RESET during a rising edge of DECODER SHIFT

CLOCK resets the decoder bit counting logic to a condition ready for a new word. 12 I GND Both GROUND supply pin.

13 I MR Both A high on MASTER RESET clears the 2:1 counters in both the encoder and

decoder and the ³  6 counter.

14 O DBS Encoder DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER

CLOCK.

15 O BZO

Encoder BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative sense of a bipolar line driver. 16 I OI Encoder A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.

17 O BOO Encoder BIPOLAR ONE OUT is an active low output designed to drive the one or positive

sense of a bipolar line driver.

18 I SDI Encoder SERIAL DATA IN accepts a serial data stream at a d ata rate equal to ENCODER

SHIFT CLOCK. 19 I EE Encoder A high on ENCODER ENABLE initiates the encode cycle . (Subject to the preceding cycle being completed).

20 I SS Encoder SYNC SELECT actuates a Command sync for an input hi gh and data sync for an

input low.

21 O SD Encoder SEND DATA is an active high output which enables th e external source of serial

data. 22 I SCI Encoder SEND CLOCK IN is 2X the Encoder data rate. 23 I EC Encoder ENCODER CLOCK is the input to the 6:1 divider.

24 I V

CC Both V CC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24) to GND (pin 12) is recommended. HD-6408

4 FN2952.3 October 1, 2015 Encoder Operation The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SClock input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SClock by dividing the DClock. The Encoder’s cycle begins when EE is high during a falling edge of ESC (1). This cycle lasts for one word length or twenty ESC periods. At the next low-to-high transition of the ESC, a high at SS input actuates a Command sync or a low will produce a Data sync for that word (2). When the Encoder is ready to accept data, the SD output will go high and remain high for sixteen ESC periods (3) - (4). During these sixteen periods the data should be clocked into the SD Input with every high-to-low transition of the ESC (3) - (4). After the sync and Manchester II encoded data are transmitted through the BOO and BZO outputs, the Encoder adds on an additional bit which is the (odd) parity for that word (5). If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (5) as shown to prevent a consecutive word from being encoded. At any time a low on OI will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To Abort the Encoder transmission a positive pulse must be applied at MR. Any time after or during this pulse, a low-to- high transition on SCI clears the internal counters and initializes the Encoder for a new word. 1ST HALF 0 1 2 3 4 5 6 7 15 16 17TIMING 1918 3 210101112131415

32101112131415 P2ND HALF

32101112131415 PSYNCSYNC

DON’T CARE DON’T CAREVALID HD-6408

5 FN2952.3 October 1, 2015 Decoder Operation The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DClock input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BOI and BZI inputs will accept data from a differential output comparator. The UDI input can only accept noninverted Manchester II coded data (e.g. from BOO of an Encoder through an inverter to UDI). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized (1), the type of sync is indicated by the CDS output. If the sync character was a command, this output will go high (2) and remain high for sixteen DSC periods (3), otherwise it will remain low. The TD output will go high and remain high (2) - (3) while the Decoder is transmitting the decoded data through SDO. The decoded data available at SDO is in a NRZ format. The DSC is provided so that the decoded bits can be shifted into an external register on every low-to-high transition of this clock (2) - (3). Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. After all sixteen decoded bits have been transmitted (3) the data is checked for odd parity. A high on VW output (4) indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately 20 DECODER SHIFT CLOCK periods after it goes high if not reset low sooner by a valid sync and two valid Manchester bits as shown (1). At any time in the above sequence a high input on DR during a low-to-high transition of DSC will abort transmission and initialize the Decoder to start looking for a new sync character.2ND HALF1ST HALF 0 1 2 3 4 5 6 7 8 1 61 71 81 9 SYNC SYNC 15 14 13 12 11 10 14 13 12 11 10 0P21 15 14 13 12 4 3 2 1 0 VW SDO CDS TD BZI BOI DSC TIMING FROM PREVIOUS RECEPTION UNDEFINED 21 3 4 HD-6408

6 FN2952.3 October 1, 2015 Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical) JA (°C/W) JC (°C/W) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIH Logical “1” Input Voltage 70% V CC -- V VIL Logical “0” Input Voltage - 20% V CC -V VIHC Logical “1” Input Voltage (Clock) V CC -0.5 - - V VILC Logical “0” Input Voltage (Clock) - GND +0.5 - V II Input Leakage V IN = VCC or GND, DIP Pins -1.0 - +1.0 µA VOH Logical “1” Output Voltage I OH = -3mA 2.4 - - V VOL Logical “0” Output Voltage I OL = 1.8mA - - 0.4 V ICCSB Supply Current Standby V IN = VCC = 5.5V Outputs Open - 0.5 2 mA ICCOP Supply Current Operating (Note 1) V CC = 5.5V, f = 15MHz - 8.0 10.0 mA NOTE: 1. Guaranteed but not 100% tested. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ENCODER TIMING (1) F EC Encoder Clock Frequency C L = 50pF 0 - 12 MHz (2) F ESC Send Clock Frequency C L = 50pF 0 - 2.0 MHz (3) T ECR Encoder Clock Rise Time C L = 50pF - - 8 ns (4) T ECF Encoder Clock Fall Time C L = 50pF - - 8 ns (5) F ED Data Rate C L = 50pF 0 - 1.0 MHz (6) T MR Master Reset Pulse Width C L = 50pF 150 - - ns (7) T E1 Shift Clock Delay C L = 50pF - - 125 ns (8) T E2 Serial Data Setup C L = 50pF 75 - - ns (9) T E3 Serial Data Hold C L = 50pF 75 - - ns (10) T E4 Enable Setup C L = 50pF 90 - - ns (11) T E5 Enable Pulse Width C L = 50pF 100 - - ns (12) T E6 Sync Setup C L = 50pF 55 - - ns (13) T E7 Sync Pulse Width C L = 50pF 150 - - ns (14) T E8 Send Data Delay C L = 50pF 0 - 50 ns (15) T E9 Bipolar Output Delay C L = 50pF - - 130 ns HD-6408

7 FN2952.3 October 1, 2015 (16) T E10 Enable Hold C L = 50pF 10 - - ns (17) T E11 Sync Hold C L = 50pF 95 - - ns DECODER TIMING (18) F DC Decoder Clock Frequency C L = 50pF 0 - 12 MHz (19) T DCR Decoder Clock Rise Time C L = 50pF - - 8 ns (20) T DCF Decoder Clock Fall Time C L = 50pF - - 8 ns (21) F DD Data Rate C L = 50pF 0 - 1.0 MHz (22) T DR Decoder Reset Pulse Width C L = 50pF 150 - - ns (23) T DRS Decoder Reset Setup Time C L = 50pF 75 - - ns (24) T DRH Decoder Reset Hold Time C L = 50pF 10 - - ns (25) T MR Master Reset Pulse Width C L = 50pF 150 - - ns (26) T D1 Bipolar Data Pulse Width Note 2, C L = 50pF T DC +10 - - ns (27) T D2 Sync Transition Span Note 2, C L = 50pF - 18T DC -n s (28) T D3 One Zero Overlap Note 2, C L = 50pF - - T DC -10 ns (29) T D4 Short Data Transition Span Note 2, C L = 50pF - 6T DC -n s (30) T D5 Long Data Transition Span Note 2, C L = 50pF - 12T DC -n s (31) T D6 Sync Delay (ON) C L = 50pF -20 - 110 ns (32) T D7 Take Data Delay (ON) C L = 50pF 0 - 110 ns (33) T D8 Serial Data Out Delay C L = 50pF - - 80 ns (34) T D9 Sync Delay (OFF) C L = 50pF 0 - 110 ns (35) T D10 Take Data Delay (OFF) C L = 50pF 0 - 110 ns (36) T D11 Valid Word Delay C L = 50pF 0 - 110 ns NOTE: 2. TDC = Decoder Clock Period = 1/FDC. (These parameters are guaranteed but not 100% tested). Capacitance TA = +25°C SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CIN Input Capacitance FREQ = 1MHz, all measurements are referenced to device GND -1 5-p F CO Output Capacitance - 15 - pF SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HD-6408

8 FN2952.3 October 1, 2015 AC Testing Input, Output Waveform NOTE: AC Testing: All input s ignals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt. Encoder Timing INPUT VIH 50% VIL 50% VOH VOL SCI VALID (7) TE1 TE3 (9) VALID ESC SDI SC ESC EE SS ESC SD SC BOO OR BZO TE2 (8) (7) TE1 TE10 (16) (10) TE4 (17) TE11 VALID (14) TE8 (15) TE9 (11) TE5 TE7 (13) (12) TE6 HD-6408

9 FN2952.3 October 1, 2015 Decoder Timing DATA SYNC BIT PERIOD BIT PERIOD BIT PERIOD TD2 (27) (26) (26) COMMAND SYNC TD2 (27) (28)TD3 TD3 TD2 (28) TD2 (27) (26) (26) (28) (28) (28) (26) (28) (29) (26) (29) TD4 ONEONE ZERO TD1 TD1 TD1 TD3 TD3 (28)TD1 TD1TD1 TD3 TD3 TD3 TD3 TD1 TD4 TD5TD5 TD2TD2 (27) COMMAND SYNC (27) TD2 TD2 (27) (27) TD4 TD5 TD5 TD4 TD4 (29) (29) (29) (30)ZERO ONE ONEONE DATA SYNC (30) BOI BZI BOI BZI BOI BZI UI UI UI (28) (26) (27) TD3 (28) (30) (30) NOTE: UI = 0, FOR NEXT DIAGRAMS NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS HD-6408

10 FN2952.3 October 1, 2015 Decoder Timing (Continued) (31) TD6 TD7 (32) DSC CDS TD DSC SDO (33) TD8 DATA BIT TD9 (34) (35) TD10 DSC CDS TD VW DSC DR (36) TD11 (22) TDR (23) TDRS (24) TDRH HD-6408

11 FN2952.3 October 1, 2015 Decoder Timing (Continued) (31) TD6 TD7 (32) DSC CDS TD DSC SDO (33) TD8 DATA BIT TD8 (34) (35) TD10 DSC CDS TD VW DSC DR (36) TD11 (23) TCRS (22) TDR (24) TDRH HD-6408

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2952.3 October 1, 2015 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 1, 2015 FN2952.3 Added Rev History beginning with Rev 3. Added About Intersil Verbiage. Updated Ordering Information on page 1 HD-6408