HD3-4702-9

HD-4702_06 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 8

Technical content

Features

• HD-4702 Provides 13 Commonly Used Bit Rates
• Uses a 2.4576MHz Crystal/Input for Standard Frequency Output (16 Times Bit Rate)
• Low Power Dissipation
• Conforms to EIA RS-404
• One HD-4702 Controls up to Eight Transmission Channels
• Initialization Circuit Facilitates Diagnostic Fault Isolation
• On-Chip Input Pull-Up Circuit Truth Table Pinout HD-4702 (16 Ld PDIP) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PART NUMBER PART MARKING PKG. NO. PDIP -40 to +85 HD3-4702-9 HD3-4702-9 E16.3 PDIP (Pb-free) -40 to +85 HD3-4702-9Z* HD3-4702-9Z E16.3 CerDIP SMD# -55 to +125 5962-9051801MEA F16.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.TRUTH TABLE FOR RATE SELECT INPUTS (Using 2.4576MHz Crystal) S3 S2 S1 S0 OUTPUT RATE (Z) L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H MUX Input (IM) MUX Input (IM)

50 Baud

75 Baud

134.5 Baud

200 Baud

600 Baud

2400 Baud

9600 Baud

4800 Baud

1800 Baud

1200 Baud

300 Baud

150 Baud

110 Baud

NOTE: 19200 Baud by connecting Q2 to IM. E CP CP OX GND IX VCC Z CO IM Data Sheet August 24, 2006

2 FN2954.2 August 24, 2006 Pin Description PIN NUMBER TYPE SYMBOL DESCRIPTION 16 V CC VCC: Is the +5V power supply pin. A 0.1 μF capacitor between pins 16 and 8 is recommended for decoupling. 8G N D G R O U N D

5 I CP EXTERNAL CLOCK INPUT

CP EXTERNAL CLOCK ENABLE: A low signal on this input allows the baud rate to be generated from the CP input. 7I I X CRYSTAL INPUT 6O O X CRYSTAL DRIVE OUTPUT

15 I I M MULTIPLEXED INPUT

11, 12, 13, 14 I S0 - S3 BAUD RATE SELECT INPUTS

9 O CO CLOCK OUTPUT

1, 2, 3 O Q 0 - Q2 SCAN COUNTER OUTPUTS

10 O Z BIT RATE OUTPUT

CLOCK MODES AND INITIALIZATION IX E CP CP OPERATION H L Clocked from I X X L Clocked from CP X H H Continuous Reset X L Reset During 1st CP = High Time H = HIGH Level L = LOW Level X = Don’t Care = Clock Pulse = 1st HIGH Level Clock Pulse after E CP goes LOW NOTE: Actual output frequency is 16 times the indicated Output Rate, assuming a clock frequency of 2.4576MHz. HD-4702

3 FN2954.2 August 24, 2006 Block Diagram OSCILLATOR CIRCUIT IX OX CO INITIALIZATION CP ECP DQ FF CP Q MR CIRCUIT MR Q0 Q1 Q2 1 2 3 PIN 16VDD VSS PIN 8 PIN NUMBER SCAN COUNTER CP MR 9600 4800 2400 1200 600 300 150 IM Z COUNTER NETWORK MULTIPLEXER 15 14 13 12 11 S0 S1 S2 S3 CP 8 MR DQ FF CP MR 134.5 200 600 2400 9600 4800 1800 1200 2400 300 150 110 CP 4÷ Q MR CP 18÷ Q MR CP 6÷ Q MR CP 16/3÷ Q MR CP 22÷ Q MR (NOTE) NOTE: See Figure 4 in Design Informat ion for Crystal Specifications. HD-4702

4 FN2954.2 August 24, 2006

Application Information

Single Channel Bit Rate Generator Figure 1 shows the simplest application of the HD-4702. This circuit generates one of five possible bit rates as determined by the setting of a single pole, 5-position switch. The Bit Rate Out- put (Z) drives one standard TTL load or four low power Schot- tky loads over the full temperature range. The possible output frequencies correspond to 110, 150, 300, 1200, and 2400 Baud. For many low cost terminals, these five bit rates are ade- quate. FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR

19200 Baud Operation

2 output to IM input and applying select code. Baud” feature on select code 1 for the HD-4702 (See Figure 3).

2.4576 MHz

TABLE 1. CRYSTAL SPECIFICATIONS FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH FIGURE 3. 19200 BAUD OPERATION

5 FN2954.2 August 24, 2006 Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical) θJA θJC Maximum Junction Temperature Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8) SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONSMIN MAX VIH Input High Voltage V CC 70% - V V CC = 4.5V VIL Input Low Voltage - V CC 30% V V CC = 4.5V VOH1 Output High Voltage V CC -0.1 - V I OH ≤ -1μA, VCC = 4.5V, (Note 1) VOL1 Output Low Voltage - 0.1 V I OL ≤ +1μA, VCC = 4.5V, (Note 1) IIH Input High Current -1 +1 μAV IN = VCC, All 0ther Pins = 0V, VCC = 5.5V IILX Input Low Current (lX Input) -1 +1 μAV IN = 0V, All Other Pins = VCC, VCC = 5.5V IIL Input Low Current (All Other Inputs) -- 1 0 0 μAV IN = 0V, All Other Pins = VCC, VCC = 5.5V (Note 2) IOHX Output High Current (OX) -0.1 - mA V OUT = VCC - 0.5, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOH1 Output High Current (All Other Outputs) -1.0 - mA V OUT = 2.5V, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOH2 Output High Current (All Other Outputs) -0.3 - mA V OUT = VCC -0.5, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOLX Output Low Current (OX) 0.1 - mA V OUT = 0.4V, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table IOL Output Low Current (All Other Outputs) 1.6 - mA V OUT = 0.4V, VCC = 4.5V Input, at 0V or VCC per Logic Function or Truth Table ICC Supply Current (Static) - 1500 μAE CP = VCC, CP = 0V, VCC = 5.5V, All Other Inputs = GND, (Note 2) - 1000 μAE CP = VCC, CP = 0V, VCC = 5.5V, All Other Inputs = VCC, (Note 2) NOTES: 1. Interchanging of force and se nse conditions is permitted. 2. Input Current and Quiescent Power Supply Current are relative ly higher for this device because of active pull-up circuits on all inputs except IX. HD-4702

6 FN2954.2 August 24, 2006 Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8) SYMBOL AC PARAMETER LIMITS UNITS TEST CONDITIONSMIN MAX tPLH Propagation Delay, IX to CO - 350 ns VCC = 4.5V CL ≤ 7pF on OX CL = 50pF (Note 1) tPHL - 275 ns tPLH Propagation Delay, CP to CO - 260 ns tPHL - 220 ns tPLH Propagation Delay, CO to Qn - (Note 2) ns tPHL - (Note 2) ns tPLH Propagation Delay, CO to Z - 85 ns tPHL -7 5 n s tTLH Output Transition Time (Except OX) - 160 ns tTHL -7 5 n s ts Set-Up Time, Select to CO 350 - ns th Hold Time, Select to CO 0 - ns ts Set-Up Time, IM to CO 350 - ns th Hold Time, IM to CO 0 - ns twCP(L) Minimum Clock Pulse Width, Low (Notes 3, 4) 120 - ns twCP(H) Minimum Clock Pulse Width, High (Notes 3, 4) 120 - ns twCP(L) Minimum I X Pulse Width, Low (Note 4) 160 - ns twCP(H) Minimum I X Pulse Width, High (Note 4) 160 - ns tPLH Propagation Delay IX to CO - 300 ns VCC = 4.5V CL ≤ 7pF on OX CL = 15pF (Note 1) tPHL - 250 ns tPLH Propagation Delay CP to CO - 215 ns tPHL - 195 ns tPLH Propagation Delay CO to Qn - (Note 2) ns tPHL - (Note 2) ns tPLH Propagation Delay CO to Z - 75 ns tPHL -6 5 n s tTLH Output Transition Time (Except OX) - 80 ns tTHL -4 0 n s NOTES: 1. Propagation Delays (t PLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Setup Times (ts), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance. 2. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be ≤ 367ns. 3. The first High Level Clock Pulse after E CP goes Low must be at least 350ns long to guarantee reset of all Counters. 4. It is recommended that input rise and fall times to the clock inputs (CP, I X) be less than 15ns. HD-4702

7 FN2954.2 August 24, 2006 Switching Waveforms AC Testing Input, Output Waveform Capacitance TA = +25oC; Frequency = 1MHz SYMBOL PARAMETER TYPICAL UNITS CONDITIONS CIN Input Capacitance 7 pF All measurements are referenced the device GND COUT Output Capacitance 15 pF 50% 50% 50% tW(H) tW(L) 50% 50% ts th CP/IX CO IM/SN NOTE: 1. Setup and Hold times are shown as positive va lues but may be specified as negative values. 50% VIL VIH INPUT 50% VOH VOL OUTPUT NOTE: 1. AC Testing: All input signals must switch between V IL and VIH. Input rise and fall times are driven at 1ns per volt. HD-4702

8 FN2954.2 August 24, 2006 Dual-In-Line Plastic Packages (PDIP) NOTES: 2. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 3. Dimensioning and tolerancing per ANSI Y14.5M -1982. 4. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 5. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 6. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 7. E and are measured with the leads constrained to be perpendic- ular to datum . 8. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 9. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 10. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93 HD-4702