HD153129

HD153129 HITACHI | Alldatasheet

Document overview

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Technical content

The HD153129P is a high-speed, high-density, Pin Arrangement low-power color palette with triple 6-bit DA converter. Manufactured using a Hi-BiCMOS process, it realizes advanced DA conversion, high-speed REO {1 281) Vee SRAM and high-speed logic all on a single LSI GREEN [2 277) RS1 chip with its color palette, advanced functions, BLUE (] 3 26 {7 RSO small size and low cost, the HD153129P is an IREF C] 4 25 WA essential component for advanced graphics po ds 24H o7 systems. pi O6 23) Dé p27 221 DS Features p38 210 pa * Displays 256 colors simultaneously from a total pao 201) 03 of 262,144 possible colors. Ps C10 19 fF) b2 * Three 6-bit DA converters for RGB video output Pe C11 18 [ Dt on a single chip P7 C12 17] Do + Pixel mask function for display control POLK (13 BLANK + Compatible with personal system/2 ou 16 Fy BLANK * Dot rate maximum of 50/65 MHz GNO C{ 14 15) RO + TTL compatible /O levels + 28-pin plastic DIP (Top view) Ordering Information Figure 1 Pin Arrangement Max. Type No. Operating Freq. Package HD153129P 50 MHz £600 mil 28 pin HO1S3120P-65 65MHz ——_—_—~Plastic DIP (OP-28) Note: Personal system/2 is a registered trademark of IBM. @ HITACHI 514 Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 (415) 589-8300

» cut XD 1 a "7 256 wor6 X18 asd 6 ~ | 2 [wince | feel en Cel Vos! PouK BLANK ‘Do-07 Figure 2 Block Diagram Table 1 Pin Description Pin name Pin number Description PO-P7 5,6,7,8, CLT address inputs. P7 is MSB, PO is LSB. 9,10, 11,12 DO-D7 17, 18, 19,20, Data port for reading/writing CLT or address, pixel mask, R, G 21, 22, 23,24 and B registers. D7 is MSB, DO is LSB. RD 15 Read clock input. Strobes data from CLT or address, pixel mask, R, G or B registers during read operation. WR 25 Write clock input. Strobes data to CLT or address, pixel mask, R, Gor B registers during write operation. a RSO.AS1 26,27 __Select inputs for CLT, address register or pixel mask register. IREF 4 Terminal for connecting reference resistor to set DAC analog output level RED, GREEN 1,2,3 DAC analog output signals BLUE ee BLANK 16 Video blank input for activating blank signal levels at DAC analog outputs. PCLK 13 Reference clock input for digital and analog sections. On the rise of this signal, CLT and BLANK operations are processed and analog signal outputs become active. Veo 28 Power supply GND 14 Ground @ HITACHI Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 «515

Functions Table 2. Register Selection Accessing the CLT and Registers RS1 RSO_ Selection The CLT and registers are selected with inputs RSO 0 0 Address register (write mode) RS1 . and RSI (see table 2) 1 1 Address register (read mode) 0 1 CLT 1 0 Pixel mask register Address register: To perform read/write Pixel mask register: The pixel mask register ‘operations on the CLT, the CLT address must be _ allows displayed colors to be modified by altering set in the address register through D7 to DO (D7 is __—the value input from video memory and the the MSB and D0 is the LSB). contents of the CLT. The pixel mask register is set For a CLT write operation, write the CLT address by writing a pixel mask value to D7 (MSB) to DO via D7 to DO with RSO = “0” and RS1 = “0” (in (LSB) with RSO “0” and RS1 = “1” (in order to order to select the address register, write mode). select the pixel mask register for a data write) as To set up the address register fora CLT read shown in figure 13. During color palette operation, write the CLT address via D7 to DO with _ operations, the value input from video memory at RSO = “1” and RS1 = “1” (in order to select the P7 (MSB) to PO (LSB) is ANDed with the pixel address register, read mode). mask register value, and the resulting value is Also, the address register contents can be read as applied as an address to the CLT. Consequently, shown in figure 10 and figure 11. pixel mask “0” bits will cancel corresponding video memory value “1” bits. The following table shows the CLT address that results for a particular pixel mask register value and video memory value. Table 3 Pixel Mask Example Pixel mask register 1 i) 1 o 1 1 oO 1 Address input (P7 — PO) Pdy Pde Pds Pd, Pdg Pd2 Pdy Pdo CTL address value Pdz 0 Pds 0 Pd3 Pda 0 Pdo RGB registers: There are two RGB register select the appropriate RGB register wrile types: one for writing color information to the CLT _ performing the read or write via data port DS and one for reading color information from the (MSB) to D0 (LSB). Bits D6 and D7 may be either CLT. Each register type is organized as an 18-bit ‘0’ or ‘1’ at this time. Write or read the data in the word, order of R, G, B as shown in figure 7 and figure 8. To read or write data to the CLT, set RSO = ‘0’ to @HITACHI 516 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

" — ara i SSLLEY, | OE Do-D7 GY 7, =A 22 ‘wore twoHRe Figure 13 Pixel Mask Register Read

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Figure 14 Video Output Waveform @ HITACHI 522 __ Hitachi America. Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane. CA 94005-1819 © (415) 589-8300

Registers Correspondence with the CLT 7 3 (Msp) g Po 3 Address R G 8 (LSB) & decoder 6 bit 6 bit 6 bit 2, 3 —— 8 [a [vince f oor | wi | 8 bit . 8 bit g gz 07 a (MSB) = CLT & 256w x18 bit g Po 8bit 18 bit 18 bit D5(MSB)-DO(LSB) Figure 15 Registers Correspondence with the CLT @HITACHI Hitachi America, Ltd. Hitachi Piaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 623

System Configuration Example [| we -——> | Graphics controller pum ? Video memory B Q g a 3 FE = BLANK Po~P7 a) RED To RSO RSt HD153129P oruN CAT wR i Display ref Display reference Figure 16 System Configuration Example Table 4 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage Voc 7.0 v Input voltage VIN Oto Vog v Operating temperature Topr 0 to +70 °C Storage temperature Tsig 55 to +150 °c @HITACHI 524 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300

Electrical Characteristics

Table 5 DAC Section Electrical Characteristics (Vcc = 5 V, Ta = 25 °C) item Symbol Min Typ Max Unit Test conditions Resolution 6 6 6 bits Maximum operating frequency folk — — 50/65 MHz Analog output voltage Va (Full) -5 5 % of FSR Inge = 4.44 mA Va (Zero)-2 — 2 % of FSR Differential linearity DLE +1 _ +1 LSB 2 Integral linearity ILE + — 41 LSB Output rise time (20 - 80 %) tr - - 10 ns CL = 15 pF Output fall time (80 - 20 %) tf . - 10 ns Cy = 15 pF Settling time ts - - 30 ns Oy = 15 pF Glitch energy Eg — 90 - PVs Table 6 Digital Section DC Characteristics (unless otherwise specified Vcc = 5 V + 5 %, Ta = 0 to +70 °C) tem Symbol Min Typ Max Unit Test conditions Input “High” level voltage Vin 220 — Veo V Input “Low” level voltage Vit 03 - og OV Input clamp voltage vy - - 15 VN Voc = 4.75 V, ly =-18 mA Output “High” level voltage Vou 270 = - Vv Voc = 4.75 V, lon = 400 pA Output “Low’ level voltage Vo - —- 08 V Voc = 4.75 V, lo, = 8 mA Input current \\ - - 1 mA Voc = 5.25 V, Vj=55V “High” level input current Wa - - 200 yA Voc = 5.25 V, Vj=27V “Low” level input current te - = 400 pA Voc = 5.25 V, Vj=0.4V ‘Supply current lec - 110 170 mA Voc = 5.25 V, Incr = 4.44 mA @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-6300 525

Table 7 Digital Section AC Characteristics (Vcc = 5 V, Ta = 25°C) 50 MHz 65 MHz Test Refer. Item Symbol Min Max Min Max Unit conditions —_ figure PCLK cycle time tpck 20 — 53 — ns 9 PCLK low level time twipck 8 —- 6 — ons 9 PCLK high level time twHpck 8 — 6 — ons 9 Data setup time tsp «6 - 5 — 1s 9 Data hold time tye 6 - 5 — ns 9 Data output delay time tppa — 300 30 ons C.=15pF 9 WA low level time twiw 50 — 50 — ns 3,7,8 WR high level time twHw 3Xtpck — 3Xtpck — ns. 7 RD low level time twun 50 — 50 — ons 4,8 RD high level time twHr1 3Xtpck — 3xtpck — ns 8 twHRe 6xtpck — 6 Xtock — __—ns 8 ‘WRAD interval time twat 3Xtpck — = 3Xtpck — ns 5,6 tiwre §Xtock — 6 Xtock — ns. 5,6,8,9 ‘WRRSO, RS1 setuptime — tgw 10 — 1 — os 3 ‘WRIRSO, RStholtime = tyw = «10 — 10 — 1s 3 RD/RSO,RS1 setuptime tsrq «10 — 10 — 1s 4 'RD/RSO, RS1 hold time tunn 10 — 10 — ons 4 WR data setup time tspw 10 — 10 — ons 3 WR data hold time typw 10 — 10 — ons 3 RD data output delay time tppar 5 —- 5 — ns C.=15pF 4 RD data output hold time tyon1 5S - 5 — ons Cy=15pFo 4 tHor2 — 2 — 20 ons C=15pF 4 WR iow level time tuwiw 50 — 50 — ons 12 RD low level time tuwir 50 — 50 — 7s 13 WRIRSO, RS! setup time tygw 10 — 10 — ns 12 tusw2 10 — 10 — ns 12 Unit mm (inch) @HITACHI 526 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 (415) 589-8300

Digital Section AC Characteristics (Vcc = § V, Ta = 25 °C) (cont)

50 MHz 65 MHz Reter-

Item Symbol Min Max Min = Max Unit conditions —_ figure WRRSO, RS1 hol time = tuywi 10 — 10 — os 12 twuwe 10 — 10 — 1s 12 'RD/RSO, RS1 setuptime tysai 10 - 10 — os 13 tusr2 10 — 10 — 1s 13 RD/ASO, RSI hold time tur 10 — 10 — os 13 ) twHR2 10 — 10 — 7s 13 ‘WR data setup time tusow 10 — 1 — ns 12 WR data hol time twHpw 10 — 10 — os 12 ‘RD data output delay time twpr1 5 —- 5 — ns C=15pF 13 twore — 40 — 40 ns C=15pF 13 RD data output holdtime — twoHri 5 — 5 — ns Gm Spr 13 twoHR2 — 200 — 20 ons C= 15pF 13 Connection Example SV Vee 0.1 pF) 10.1 pF] Oo” | Staieiaiaietenenenr? = = 1 47 i? 47 UF i { IREF i | ! ! 1 GND 75Q COAX RED eer GREEN F y : Pano | BivE nic Figure 17 Connection Example @HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 527