HD153009

HD153009 HITACHI | Alldatasheet

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HD153009, 2-7 Code Encoder/Decoder Description HD153009, HD153013 The HD153009/HD153013 2-7 encoder/decoder IC for magnetic disks converts an NRZ signal to be written to a magnetic disk into a 2-7 code, and converts a 2-7 code read from the disk into an NRZ signal. This IC incorporates phase comparator logic for the data separator. In combination with a data separator chip, this IC performs two functions: 2-7 (MP-44) modulation/demodulation and data separation. F . eatures Pin Arrangement + Encode/decode IBM 2-7 codes + Can generate and detect address marks using 2 ae% soft sector approach. 2S 3 8 é * Can synchronize phases in 4T (1000) SYNC Bi gé é3 eg pattern, Baegs stall + Built-in phase comparison logic for data oonon nonononn

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separation E Ro qs fe) xp ant Found + Built-in sync field detection logic q? ep e Read Wite Clack + Maximum data transfer rate: 15 Mbps ne de 35 reat eos + LSTTL-compatible inputs/outputs UinSet G10 35) NAZ Read Data + Small 44-pin MSP package suitable for surface GNO Chit mounting 34) GND * Si GND Giz 33) GND Single 5 V power supply Sede G3 225 Wie Gate Syne. In hia 31) NRZ Wie Data i 13 Set Write Clock Functions tase ie 26 AM Enabe . ; Mode Sel C17 25 Early Clock Ow * NRZ signal to 2-7 code conversion * 2-7 code to NRZ signal conversion esses 25E5% * Write precompensation 68 \\8 > Petre * Phase synchronization in 4T(1000) SYNC gi ¢ Fr 3 z Se pattern ga 48 35286 + Address mark(DC erase) generation 2 + Address mark(DC erase) detection = « Phase comparison for data separator (Top vew) * Sync field detection

Ordering Information

Type No. Package . HD 153009, .. HD153013 MP-44 @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 327

HD153009, HD153013 Block Diagram z® i 8 2 i i i | ee fF FER F f reroion | EE tT | Prase Syme ( w=} oy [SE] $$ ra Do yee | Be oT 27 Erte Je {oes or We | use } | | ee ee | is | alee ras fe EF FREE FEST EE | i pope EERE fy fe | ge oe Bes | Table 1 Pin Description Input/ Inpul! Pin No. Pin name output Pin No. Pin name output 22,24 Vec Power 7 D.RD (Delayed read data) In 11,12,33,34 GND Power 14 Syne. in In 42 2-7 Read data In 7 Mode sel In

1 VCO clock In 9 Ein sel In

38 Read gate In 6 E.RD (E read data) In

4 Reference clock In 10 Lin sel In

31 NRZ write data In 8 L. RD (L head data) In

32 Write gate In 15 L3 set In

21 Write precomp. enable In 16 L4 set In

7 Early clock 2 In 30 Write clock In

26 Early clock 1 In 35 NRZ read data Out

25 Normal clock In 19 2-7 write data Out

24 Late clock 1 In 39 AM found (Address mark found) Out

23 Late clock 2 In 37 Read write clock Out

5 Phase sync. In 28 Early clock out Out

29 AM enable (Address mark enable) In 18 Late write gate Out

40 Reset In 3 Inc out Out

20 Table sel In 2 Dec out Out

36 Invert select In 43 Sync. read data Out 4 Raw read data In 13 Sync. detect Out @ HITACHI 328 Hitachi America, Ltd. » Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

HD153009, HD153013 Pin Function Write Precomp. Enable Setting Write Precomp. Enable low enables write 2-7 Read Data precompensation during writes. In this case, The 2-7 Read Data pin inputs the 2-7 code from provide a write precompensation clock signal. the disk. The signal synchronized in the data seperator is applied to this pin. It must also be — Early Clock 2 synchronized to the VCO Clock from the data’ The phase of the Early Clock 2 write separator. When using the internal phase _precompensation clock input must lead the Normal comparator, input the Sync Read Data signal to this ~~ Clock. pin. Early Clock 1 VCO Clock The phase of the Early Clock 1 write The VCO Clock is input from a data separator, —_ precompensation clock input must lead the Normal which has synchronized it with the 2-7 Read Data. —_ Clock and follow Early Clock 2. The internal phase comparator compares this signal with the Delayed Read Data. Normal Clock The Normal Clock input is used for write Read Gate precompensation. Setting Read Gate input high permits the HD153009 to read data from the disk. It converts —_ Late Clock 1 the 2-7 code read from the disk into NRZ data for | ate Clock 1 input is used for write output. Read Gate activates the gain control circuit, precompensation according to write performs phase comparison, switches internal —_precompensation table 2. Its phase must follow the circuit clocks, and enables NRZ signal output. Normal Clock signal. Reference Clock Late Clock 2 Reference Clock is the reference clock for this IC. The Late Clock 1 write precompensation input It is also the write data clock. Its frequency must myst follow the Normal Clock and lead Late Clock be twice the data transfer rate. 1. NRZ Write Data Phase Syne NRZ Write Data inputs NRZ data to be written t0 senting Phase Sync low at the biginning of a read the disk. It must be input synchronously with the allows 2-7 read data phase to be synchronized in Write Clock signal when E In SelandL In Selpins 47 (1000) SYNC pattem (the phase comparator is are set low. Otherwise it must be set synchronously faced in frequency/phase comparison mode). with the Read Write Clock. The polarity of this a frer synchronization, Phase Sync must be set signal can be switched by the Invert Select pin. high for normal decoding. Normally, input Syne Invert Select high selects inverted input and Invert Det. to this pin. Select low selects noninverted input for 2-7 conversion. AM Enable (Address Mark Enable)

5 Setting AM Enable input high allows soft-sector

Write Gate . . address mark write and detection. During address Write Gate high allows data write; NRZ data to be mark write, DC erase continues while AM Enable written to the disk is converted to 2-7 code for and Write Gate are held high. If an address mark is output. Set Write Gate high for soft-sector address getected, the AM Found signals is output at the mark write and low for address detection. completion of DC erase, which continues for at least 30 Reference Clock periods. When the AM Found signal is output, the disk controller must clear Address Mark Enable. @HITACHI Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300 329

HD153009, HD153013 Reset E. RD (E Read Data) A low-level Reset input initializes the internal When E In Sel input is low, input the E. RD signal circuits at power on. Hold Reset high for normal _ instead of the D. RD signal into the internal phase operation. comparator for the PLL. Table Sel L In Set Table Sel input high selects write precompensation _ Setting the L In Sel input low inputs the L. RD table 1, and Table Sel input low selects write _signal instead of the D. RD signal into the internal precompensation table 2. phase comparator for the PLL. When E In Sel and L In Sel are low, the NRZ Write Data signal is Invert Select synchronized with the Write Clock. Invert Select input switches the NRZ polarity for the interface with the controller. When Invert __L. RD (L Read Data) Select is high, the NRZ signal is inverted. When When L In Sel input is low, input the L. RD signal Invert Select is low, the NRZ signal input/output is _ instead of the D. RD signal into the internal phase noninverted. comparator for the PLL. Raw Read Data L3 Set, L4 Set Raw Read Data inputs the 2-7 code read from the —_L3 Set and LA Set input specify the Sync. Detect disk before it is synchronized in the separator. It is output period for the sync field detection gain input to the internal comparator for the PLL. control circuit (table 1. ). D. RD (Delayed Read Data) Write Clock D. RD input is delayed by a period of half the NRZ Write Clock input enables the NRZ Write Data data transfer rate from the Raw Read Data. It is _ signal. It is valid while both E In Sel and L In Sel delivered to the internal comparator for the PLL. are kept low. Sync. In NRZ Read Data Sync. In input goes to the sync field detect gain NRZ Read Data outputs the NRZ signal converted control circuit. When the gain control circuit isin from a 2-7 code read from the disk. This signal is normal mode, input the Read Gate signal to Sync. synchronous with the Read Write Clock. The In. When it is in frequency verify mode, input the _ polarity can be switched by the Invert Select pin. one-shot output activated by the Raw Read Data _Invert Select high selects inverted output, and signal. Invert Select low specifies noninverted output. Mode Sel 2-7 Write Data Mode Sel input selects the mode of the sync field 2-7 Write Data outputs 2-7 codes converted from detect gain control circuit. Mode Sel low specifies | NRZ signals to write to disk. normal mode, and Mode Sel high specifies frequency verify mode. AM Found (Address Mark Found) AM Found goes high when the HD153009 detects EInSel an address mark in a soft sector. It is valid only E In Sel input low inputs the E. RD signal instead = when AM Enable is high. of the D. RD signal into the internal phase comparator for the PLL. When E In Sel and L In Sel are low, the NRZ Write Data signal is synchronized with the Write Clock. @HITACHI 330 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

a HD153009, HD153013 Table 2 Output Period Table 3 NRZ Signal to from L3 Set Laset Period 2:7 Code Conversion High High 6 Bytes — 01 10 0100 Low 2 Bytes ee > 101 010 100100 Low High 4 Bytes —— a 1101 0010 00100100 Low 4 Bytes de —— _ 00 11 1000 100 011 001000 1100 0011 00001000 111 000 000100 Read Write Clock Dec Out For data read, Read Write Clock outputs a clock The Dec Out internal comparator signal is output signal synchronous to the converted NRZ signal. | when Read Data phase follows the VCO Clock For data write, it outputs a clock signal divided by _ phase. This signal is passed to the PLL charge the Reference Clock signal. The disk controller pump. must enable NRZ Read Data (for reads) and NRZ Write Data (for writes) synchronously with Read Sync. Read Data Write Clock. Sync. Read Data outputs the 2-7 Read Data signal phase-synchronized with the PLL, which was Early Clock Out synchronized to the VCO Clock signal. It is Connect the Early Clock Out write provided to the 2-7 Read Data pin for 2-7 reverse precompensation reference clock output directly to conversion. the Early Clock 2 pin. Sync. Detect Late Write Gate The Sync. Detect sync field detect gain control The rising edge of the Late Write Gate signal is circuit output is normally sent to the Phase Sync. delayed about 32 Reference Clock periods from __ pin. While Sync. Detect is output, the voltage can the start of writing. During Late Write Gate output, be quickly stabilized to the PLL voltage by the 2-7 Write Data signal is output normally. increasing the PLL gain. Inc Out Vcc, GND The Inc Out intemal comparator signal is output Vcc supplies the +5 V power. Both Vcc pins must when Read Data phase leads the VCO Clock _be connected to the power line. All four GND phase. This signal is passed to the PLL charge —_ground pins must be directly grounded separately pump. from each other. @ HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane. CA 94005-1819 « (415) 589-8300 331

HD153009, HD153013 Functional Description Phase Synchronization in 4T (1000) SYNC Pattern NRZ Signal to 2-7 Code Conversion When data is being read from a magnetic disk, the The NRZ write signal is converted into a 2-7 code clock phase can be synchronized in 4T (1000) to be written to the disk. Either the NRZ or NRZ_ SYNC pattern. In this case, for NRZ signal signal is selected depending on the Invert Select _ selection, "11 ... 111" data must be in the SYNC pin input level; a high level Invert Select the NRZ _ field and "00 ... 000" for NRZ signal. During read, signal and a low level selects NRZ. The NRZ write _ the synchronous signal is applied, during which the signal is synchronized with the Read Reference __ phase is synchronized. Clock signal and then converted into a 2-7 code according to the conversion Table 2. The resulting Address Mark (DC Erase) Generation 2-7 code is subject to write precompensation. The 2-7 write signal change is halted by the address mark generation signal. The address mark 2-7 Code to NRZ Signal Conversion continues to be written while the address mark The 2-7 code read from the disk is converted into _ generation signal is applied. an NRZ signal; NRZ or NRZ signal is also selected by the Invert Select signal. The 2-7 code is | Address Mark (DC Erase) Detection synchronized with the VCO Clock signal and then The AM detection signal is output following the converted into an NRZ signal based on the —_ address mark when the 2-7 read signal remains conversion table. The NRZ read signal is unchanged for a period exceeding 16 bits of data. synchronized with the read clock signal. . Phase Comparison for the Data Separator Write Precompensation This device incorporates a phase comparator for The converted 2-7 write code (Figure 1) is subject the data separator (HA16658). This comparator to write precompensation according to Table 3 or compares Raw Read Data and Delayed Read Data 4, with VCO Clock phase to provide phase Table Sel pin chooses either write precompensation Comparison signal Inc Out or Dec Out as follows: table 1 (high level) or write precompensation table When Read Data phase leads the VCO Clock 2 (low level). phase, Inc Out is output. The amount of write precompensation is * When Read Data phase follows the VCO Clock determined by the phase of the externally supplied phase, Dec Out is output. clock signal. When the Phase Sync. pin is set low, frequency as When the Write Precomp. Enable is high level and _ well as phase are compared between the Read Data the Table Sel is high level, the HD153013 activates © and VCO Clock signals. Accordingly, this write-precompensation in table 1 by the built-in Comparator can be effectively used to stabilize the delay, and in the other hand, the HD153009 does voltage to the PLL in sync field. The Read Data in not activate write-precompensation. (Refer to _ Sync field is assumed to be 4T (1000). Table 5) The Phase Sync. pin input can be appropriately When the Write Precomp. Enable is high level and the bulein ean the Syne. Detect signal output by the Table Sel is low level, the HD153009 activates ” write-precompensation in table 2 by the built-in . ra delay, and in the other hand, the HD153013 does Gain Control Circuit — not activate write-precompensation. (Refer to The gain Control circuit outputs the Sync. Detect Table 5) signal during SYNC field. Using L3 Set and L4 set input pins, the Sync Detect signal output period can be selected from among 2-, 4-, and 6-byte lengths of the NRZ signal (see Table 6). @HITACHI 332 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300

a HD153009, HD153013 Table 4 Write Precompensation Table 1 Table 5 Write Precompensation Table 2 nm 2 3 4 5 6 7 nm 2 3 4 5 6 7

2 N E2 E2 €2 E2 €&2 2 N E1 E2 E2 E2 €E2

3 l2 E61 E1 Ef E11 €1 3 L1 oN —E1 €1 E11 €1

4 L2 E14 —Ei1 &1 4 Et 4 1 N N =) E41

5 2&1 —E1 E—1 €1 —1 5 a2 ou N N N N 6 l2 61 Ei 1 1 E1 6 l2 o.1 1) N N N 7 l2 Ef —E1 &1 €1 E1 7 2 1 ui N N N Note: N: Normal Clock, L2: Late Clock 2, L1: Late Clock 1, Ez: Early Clock 2, E1: Early Clock 1, Table 6 Selection of Precompensation Mode Write Precompensation Table Select Precompensation Method Write Precomp. Enable Table Sel HD153009 HD153013 HD153009 HD153013 nnn L H 1 1 €xternal delay element External delay element NN L L 2 2 External delay element External delay element ee H H - 1 No precompensation Bulit-in delay Oe H L 2 - Bulit-in delay No precompensation oe Table 7 Selection of Sync Detect Period L3 set High High Low = Low L4 set High Low High Low An example $$$ 012-7 code n m =| A A Syne detect period 6 Bytes 2 Bytes 4 Bytes 4 Bytes before current after Figure 1 2-7 Code Example @ HITACHI . Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 333

HD153009, HD153013 ——SSarveeeeer This circuit has two modes switched via the Mode _ not held low during a 2-bytes NRZ signal after the Sel pin: normal mode (Mode Sel at high) and _ falling Read Gate signal, the Sync. Detect signal frequency verification mode (Mode Sel at low). must be set to low. The Sync. Detect signal output period is specified by L3 Set and L4 Set pins. Normal mode: The Read Gate signal from the controller must be input to the Sync In pin. The Sync. Detect signal must be applied to the Immediately after the rising edge of the Read Gate Phase Sync. pin of this IC to enable the phase signal, the Sync. Detect signal is set to low during —_ comparator to compare phases and frequencies and the period specified by the L3 Set and L4 Set pins. to synchronize the phase for read. By providing the Sync. Detect signal to the HA16658's GS pin, PLL Frequency verification mode: 1 shot output gain can be increased. activated by the Raw Read Data signal must be provided to the Sync In pin. If the 1 shot output is Table 8 Absolute Maximum Ratings (Ta=25°C) Item Symbol Rating Unit Supply voltage Vec 7 Vv Input voltage Mi 5.5 Vv Output voltage Vo 55 Vv Power consumption Pc 460 mw Operating temperature Topr -20 to +75 °c Storage temperature Tstg -65 to +150 °C ny ofthese Sonctons (set guranteed Enposing a cleat tots absoue maximum rang lr extended porous ome may sect he doves onaby Table 9 Electrical Characteristics Table 9-1 DC Characteristics (Ta=20 to + 75°C) Item Symbol Min Typ Max Unit _Test Conditions Supply voltage Vec 475 50 525 V Input high level voltage Vi 2.0 Vv Input low level voltage Vit 0.8 Vv High level input current he 20 BA Vec = 5.25 V, Vi=2.7V Low level input current te -400 pA Veco =5.25 V, Vi=0.4V Output high level voltage VoH 27 v Vec = 4.75 V, lon = 400 pA Output low level voltage Vor 0.5 Vv Vec = 4.75 V, lo. =8 mA High level output current lon -400 yA Low level output current lou 8 mA Off-state output current loze 20 uA Vec = 5.25 V, Vo=2.7V loz -20 Vcc = 5.25 V, Vo=0.4 V : @ HITACHI 334 Hitachi America, Ltd. # Hitachi Plaza 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

HD153009, HD153013 Table 9-2. AC Characteristics (Ta=25°C) Item Symbol Min Typ Max Unit Test Conditions Note Input clock frequency 30. MHz Reference NCO clock Data transfer rate 15 Mbps Reset time RS 50 ns Fig. 2 2-7 read data set-up time tsk 15 ns Fig. 3 2-7 read data hold time tHR 10 ns Fig. 3 NRZ read data set-up time {SNR 45 ns Fig. 4 at 10 Mbps NRZ read data hold time _—itana—_35 ns Fig. 4 at 10 Mbps Decode time too 7 VCO clock Fig. 5 Phase sync. time tps 3 2-7 Read Fig. 6 data pulse Early clock out to precomp. clock tLwP. 30 ons Fig. 7 Read data delay “toc 25 ns Fig. 8 at 10 Mbps Sync. read data set-up time tssR 15 ns __ Fig. 9 Sync. read data hold time tHSR 10 ns ~ Fig. 9 Write clock to read clock twIR 5 VCO clock Fig. 10 VCO clock period = Reference clock period Read clock to write clock tRTW 5 Ref. clock Fig. 10 VCO clock period = Reference clock period NRZ write data set-up time tsNW 10 ns Fig. 11 NRZ write data hold time tw 10 ns Fig. 11 Encode time teD 7 Ref, clock Fig. 12 No write precomp. 16 Ref. clock Fig. 12 With write precomp. Write gate to late write TLwG 30 32 Ref. clock — Fig. 13 Gate (nigh) Write gate to late write TRWG 20 ons Fig. 13 Gate (low) Address mark write enable time taML 2 Ref. clock — Fig. 14 Address mark write disable time tamH 2 Ref. clock — Fig. 14 Address mark detect time tAMR: 30 Ref. clock — Fig. 15 Address mark detect rise time — taFH 30 ons Fig. 15 Address mark detect fall time tart 30 ons Fig. 15 Syne detect fall time tsoo 40 ns Fig. 16 Sync. detect time (normal mode) tsoT 7 Raw read Fig. 16 at 4 bytes ata data Sync. detect time tsOT 7 Raw read Fig. 17 at 4 bytes (frequency verification mode) data @HITACHI Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 335

HD153009, HD153013 i SY 4000 390 3 sv * 22)5 | geve sv smn a Lia} Read #2 5s¥ogg 88 Se one wen FA ergs BE E°8 ——— DECIN cs ‘owl ‘NC ROIN PCS EnSe Bead | NC WOOUT Aout Ne" re tre worse ba es eMac I) {IP : iisy GND, OSCCLK Raw Read Data atte | rmnel er vat? VJ Voor {Oday} 0. RO tase Fy ete ite OO eB egg = LA “er al Sesss che ‘Mode Sei SES55 Eee eee Deco Gren [4 | I [C]Sine Read Data SyreDetact 2222s el page Reed Dot U cd cI Phase 5 ootn Fale Wite Gang Rand Gale oes ‘4 le Piimoe zeros [aa [| Ext cock Oe ‘ead Write Clock Read Reterence Clock Early Clock 2 AM Found © Address Mark Found Power NC — Eatly Clock 1 AM © Address Mark Enable Em te —fremacme Gabe | Groat NC —| Late Goch 1 ‘Write Gate 0 Write Gate NC — Late Clock 2 RZ Wie Daw | —_0, NRZ Wie Data S Wie Clock | Pap’ +5V Notes: 1. P.up indicates pull up to 5 V. 2. Depending on L.sw setting, the Sync Detect period is specified as follows. Sees L3 set open open close close L4 set open close open close Sync detect period 6 Byte 2 Byte 4 Byte 4 Byte ee 3. Write precompensation is also possible by using external delay units. Figure 18 Circuit Example @ HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 341