HD151TS302RP_06 RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Supports 10 MHz to 60 MHz operations. (Designed for XIN = 24 MHz and 48 MHz)
  • 1 copy of clock out with spread spectrum modulation @3.3 V
  • 1 copy of reference clock @3.3 V
  • Programmable spread spectrum modulation (–0.5%, –1.0%, –3.0% down spread modulation and spread spectrum disable mode.)
  • SOP–8pin
  • Pin to pin compatible with HD151TS301RP
  • Ordering Information Part Name Package Type Package Code (Previous code) Package Abbreviation Taping Abbreviation (Quantity) HD151TS302RPEL SOP-8 pin (JEDEC) PRSP0008DD-C (FP-8DCV) RP EL (2,500 pcs / Reel) Key Specifications
  • Supply voltages: VDD = 3.3 V±0.165 V
  • Ta = 0 to 70°C operating range
  • Clock output duty cycle = 50±5%
  • Cycle to cycle jitter = ±250 ps typ.

Rev.6.00 Apr 07, 2006 page 2 of 9 Block Diagram Synthesizer Mode Control 1/n OSC SSC Modulator VDD CLKOUT SSCCLKOUT GND SEL0 XIN XOUT SEL1 1/m R = 100 kΩ R = 1 MΩ R = 100 kΩ Pin Arrangement (Top view)

8 SEL11

7 CLKOUT

6 SEL0

5 XOUT

SEL1 :0 Spread Percentage 0 0 –1.0% 0 1 –3.0% 1 0 SSC OFF 1 1 –0.5% Note: –3.0% SSC is selected for default by internal pull-up & down resistors.

Rev.6.00 Apr 07, 2006 page 3 of 9 Clock Frequency Table XIN (MHz) SSCCLKOUT (MHz) CLKOUT (MHz) 48 48 *1 48 *2 24 24 *1 24 *2 Notes: 1. With spread spectrum modulation. 2. Without spread spectrum modulation. Pin Descriptions Pin name No. Type Description GND 3 Ground GND pin VDD 2 Power Power supplies pin. Normally 3.3 V. CLKOUT 7 Output Normally 3.3 V reference clock output. SSCCLKOUT 1 Output Spread spectrum modulated clock output. XIN 4 Input Oscillator input. XOUT 5 Output Oscillator output. SEL0 6 Input SSC mode select pin. LVCMOS level input. Pull-up by internal resistor. (100 kΩ ). SEL1 8 Input SSC mode select pin. LVCMOS level input. Pull–down by internal resistor (100 kΩ ). Absolute Maximum Ratings Item Symbol Ratings Unit Conditions Supply voltage VDD –0.5 to 4.6 V Input voltage VI –0.5 to 4.6 V Output voltage *1 V O –0.5 to VDD+0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD Maximum power dissipation at Ta = 55°C (in still air) 0.7 W Storage temperature Tstg –65 to +150 °C Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the in put and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage VDD 3.135 3.3 3.465 V DC input signal voltage –0.3 — VDD+0.3 V High level input voltage VIH 2.0 — VDD+0.3 V Low level input voltage VIL –0.3 — 0.8 V Operating temperature Ta 0 — 70 °C Input clock duty cycle 45 50 55 %

Rev.6.00 Apr 07, 2006 page 4 of 9 Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Min Typ Max Unit Test Conditions Input low voltage VIL — — 0.8 V Input high voltage VIH 2.0 — — V — — ±10 VI = 0 V or 3.465 V, VDD = 3.465 V, XIN pin Input current II — — ±100 µA VI = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins Input slew rate 1 — 4 V / ns 20% – 80% Input capacitance CI — — 4 pF SEL0, SEL1 Operating current — 7 — mA XIN = 24 MHz, CL = 0 pF, VDD = 3.3 V Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Min Typ Max Unit Test Conditions VOH 3.1 — — V I OH = –1 mA, VDD = 3.3 V Output voltage VOL — — 50 mV I OL = 1 mA, VDD = 3.3 V IOH — –40 — V OH = 1.5 V Output current *1 IOL — 40 — mA VOL = 1.5 V Note: 1. Parameters are target of des ign. Not 100% tested in production.

Rev.6.00 Apr 07, 2006 page 5 of 9 Ta = 25°C, VDD = 3.3 V, CL = 30 pF Item Symbol Min Typ Max Unit Test Conditions Notes — | 250 | | 300 | SSCCLKOUT,

24 MHz

— | 250 | | 300 | SSCCLKOUT,

48 MHz

SEL1:0 = 10 Fig1 — | 250 | | 300 | SSCCLKOUT, — | 250 | | 300 | SSCCLKOUT, SSC = –0.5% SEL1:0 = 11 Figure 1 — | 250 | | 300 | SSCCLKOUT, — | 250 | | 300 | SSCCLKOUT, SSC = –3.0% SEL1:0 = 01 Figure 1 Cycle to cycle jitter *1, 2 t CCS CLKOUT,

24 MHz &

23.8 — 24.2 SSCCLKOUT, XIN = 24 MHz 47.3 — 48.7 SSCCLKOUT, XIN = 48 MHz SSCOFF SEL1:0 = 10 23.7 — 24.2 SSCCLKOUT, XIN = 24 MHz 47.0 — 48.7 SSCCLKOUT, XIN = 48 MHz SSC = –0.5% SEL1:0 = 11 23.1 — 24.2 SSCCLKOUT, XIN = 24 MHz 45.9 — 48.7 SSCCLKOUT, XIN = 48 MHz SSC = –3.0% SEL1:0 = 01 23.8 — 24.2 CLKOUT, *1, 2 47.3 — 48.7 MHz CLKOUT, t SL 1.0 — — V/ns @48 MHz CLKOUT 0.4 V to 2.4 V Clock duty cycle 45 50 55 % Output impedance — 30 — Ω Spread spectrum modulation frequency — 33 — KHz @48 MHz SSCCLKOUT Input clock frequency 10 — 60 MHz Stabilization time *1,3 — — 2 ms Notes: 1. Parameters are target of design. Not 100% tested in production. 2. Cycle to cycle jitter and output frequenc y are included spread spectrum modulation. 3. Stabilization time is the time required for the integrat ed circuit to obtain phase lock of its input signal after power up. SSCCLKOUT (or CLKOUT) tcycle n t = (tcycle n) - (tcycle n+1)CCS tcycle n+1 Figure 1 Cycle to cycle jitter

Rev.6.00 Apr 07, 2006 page 6 of 9

Application Information

  1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The C2 decoupling capacitor shown should be a tantalum type.

(Crystal or Reference input) (Crystal or Not connection) Notes: C1 = High frequency supply decoupling capacitor. (0.1 µF recommended) C2 = Low frequency supply decoupling capacitor. (22 µF tantalum type recommended) R1, R2 = Match value to line impedance. (22 Ω Reference value) Figure 2 Recommended circuit configuration

Rev.6.00 Apr 07, 2006 page 7 of 9 2. Example Board Layout Configuration G P G G 0.1 µF 22 µF FB VDD (+3.3 V Supply) GNote: Via to GND plane R1, R2 = Match value to line impedance. FB = Ferrite bead. (22 Ω Reference value) Figure 3 Example Board Layout

Rev.6.00 Apr 07, 2006 page 9 of 9 Package Dimensions F*1 p M x y E Index mark A D Z H E b p Terminal cross section ( Ni/Pd/Au plating ) c b Detail F A L L θ 0.75 0.10 1.27 5.80 6.20 0.40 0.34 5.30 Max Nom Min Dimension in Millimeters Symbol Reference 1.75 1.27 0.60 0.40 3.95 0.25 0.14 0.10 0.46 0.25 0.20 0.15 6.10 8°0° 0.25 1.08 4.90 Z HE y x θ c bp E D e e L A NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. MASS[Typ.] FP-8DCVPRSP0008DD-C RENESAS CodeJEITA Package Code Previous Code

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