HD151TS302RP HITACHI | Alldatasheet

Document overview

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Technical content

Features

  • Supports 10 MHz to 60 MHz operation. (Designed for XIN = 24 MHz and 48 MHz)
  • 1 copy of clock out with spread spectrum modulation @3.3 V
  • 1 copy of reference clock @3.3 V
  • Programmable spread spectrum modulation (–0.5%, –1.0%, –3.0% down spread modulation and spread spectrum disable mode.)
  • SOP–8pin
  • Pin to pin compatible with HD151TS301RP Key Specifications
  • Supply voltages : VDD = 3.3 V±0.165 V
  • Ta = 0 to 70°C operating range
  • Clock output duty cycle = 50±5%
  • Cycle to cycle jitter = ±250 ps typ.

Rev.1, Sep. 2001, page 2 of 9 Block Diagram Synthesizer Mode C ontrol 1/n OSC SSC Modulator VDD C LKOUT SSCC LKOUT G N D SEL0 XIN XOUT SEL1 1/m Pin Arrangement (Top view)

8 SEL11

7 CLKOUT

6 SEL0

5 XOUT

Rev.1, Sep. 2001, page 3 of 9 SSC Function Table SEL1 :0 Spread Percentage 0 0 –1.0% 0 1 –3.0% 1 0 SSC OFF 1 1 –0.5% Note: –3.0% SSC is selected for default by internal pull-up & down resistors. Clock Frequency Table XIN(MHz) SSCCLKOUT(MHz) CLKOUT(MHz) 48 48 24 24 Notes: 1. With spread spectrum modulation. 2. Without spread spectrum modulation. Pin Descriptions Pin name No. Type Description GND 3 Ground GND pin VDD 2 Power Power supplies pin. Normally 3.3 V. CLKOUT 7 Output Normally 3.3 V reference clock output. SSCCLKOUT 1 Output Spread spectrum modulated clock output. XIN 4 Input Oscillator input. XOUT 5 Output Oscillator output. SEL0 6 Input SSC mode select pin. LVCMOS level input. Pull-up by internal resistor. (100 kΩ). SEL1 8 Input SSC mode select pin. LVCMOS level input. Pull–down by internal resistor (100 kΩ).

Rev.1, Sep. 2001, page 4 of 9 Absolute Maximum Ratings Item Symbol Ratings Unit Conditions Supply voltage VDD –0.5 to 4.6 V Input voltage V I –0.5 to 4.6 V Output voltage VO –0.5 to VDD+0.5 V Input clamp current I IK –50 mA V I < 0 Output clamp current I OK –50 mA V O < 0 Continuous output current I O ±50 mA V O = 0 to VDD Maximum power dissipation at Ta = 55°C (in still air) 0.7 W Storage temperature T stg –65 to +150 °C Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage VDD 3.135 3.3 3.465 V DC input signal voltage –0.3 — VDD+0.3 V High level input voltage V IH 2.0 — VDD+0.3 V Low level input voltage V IL –0.3 — 0.8 V Operating temperature T a 0— 7 0 ° C Input clock duty cycle 45 50 55 %

Rev.1, Sep. 2001, page 5 of 9 Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Min Typ Max Unit Test Conditions Input low voltage VIL —— 0 . 8 V Input high voltage VIH 2.0 — — V Input current I I —— ± 1 0 µ A V I = 0 V or 3.465 V, VDD = 3.465 V, XIN pin — — ±100 V I = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins Input slew rate 1 — 4 V / ns 20% – 80% Input capacitance CI — — 4 pF SEL0, SEL1 Operating current — 7 — mA XIN = 24 MHz, C L = 0 pF, VDD = 3.3 V Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Min Typ Max Unit Test Conditions Output voltage V OH 3.1 — — V I OH = –1 mA, VDD = 3.3 V VOL —— 5 0 m V I OL = 1 mA, VDD = 3.3 V

Rev.1, Sep. 2001, page 6 of 9 Ta = 25°C, VDD = 3.3 V, CL = 30 pF Item Symbol Min Typ Max Unit Test Conditions Notes Cycle to cycle jitter *1, 2 tCCS — | 250 | | 300 | ps SSCCLKOUT, Fig1, 24 MHz — | 250 | | 300 | SSCCLKOUT, Fig1, 48 MHz SSC = –0.5% SEL1:0 = 11 — | 250 | | 300 | SSCCLKOUT, Fig1, 24 MHz — | 250 | | 300 | SSCCLKOUT, Fig1, 48 MHz SSC = –3.0% SEL1:0 = 01 — | 250 | | 300 | CLKOUT, Fig1, 24 MHz &

48 MHz

*1, 2 23.7 — 24.2 MHz SSCCLKOUT, XIN = 24 MHz 47.0 — 48.7 SSCCLKOUT, XIN = 48 MHz SSC = –0.5% SEL1:0 = 11 23.1 — 24.2 SSCCLKOUT, XIN = 24 MHz 45.9 — 48.7 SSCCLKOUT, XIN = 48 MHz SSC = –3.0% SEL1:0 = 01 23.8 — 24.2 CLKOUT,

24 MHz

47.3 — 48.7 CLKOUT, tSL 1.0 — — V/ns @48 MHz CLKOUT 0.4 V to 2.4 V Clock duty cycle 45 50 55 % Output impedance —3 0— Ω Spread spectrum modulation frequency — 33 — KHz @48 MHz SSCCLKOUT Input clock frequency 10 — 60 MHz Stabilization time *1,3 ——2 m s Notes: 1. Parameters are guaranteed by design and characterization. Not 100% tested in production. 2. Cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up.

Rev.1, Sep. 2001, page 7 of 9 SSCCLKOUT (or CLKOUT) tcycle n t = (tcycle n) - (tcycle n+1)CCS tcycle n+1 Figure 1 Cycle to cycle jitter

Rev.1, Sep. 2001, page 8 of 9 Package Dimensions Hitachi Code JEDEC EIAJ Mass (reference value) FP-8DC 0.08 g Unit: mm *Dimension including the plating thickness Base material dimension 0¡ – 8¡ 1.27 8 5 1 4 0.10 0.25M

1.73 Max

3.90 *0.22 4.89 0.14+ 0.114 – 0.038

0.69 Max

6.02 – 0.18 + 0.034 – 0.017 0.60+ 0.289 – 0.194 1.06 0.40 ± 0.06 0.20 – 0.03

5.15 Max

*0.42+0.063 –0.064

Rev.1, Sep. 2001, page 9 of 9 Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales offices Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan. Hitachi Asia Ltd. Hitachi Tower

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