HD151012 HITACHI | Alldatasheet

Document overview

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Technical content

Features

  • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ)
  • High output current Fanout of 10 LS TTL Loads
  • Wide operating voltage V CC = 2 to 6 V
  • Low supply current (Ta = 25°C) ICC (Static) = 4 µA (max)

CLR PR SPE Mode Operation Description H H H Generally count Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) X X L Synchronous preset Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) L H — Initialize of Q output Initialize of Q = “L” H L — Initialize of Q output Initialize of Q = “H” Notes: 1. Synchronous preset (SPE) input can set max 256 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. H : High level L : Low level X : Immaterial — : Irrespective of condition Pin Arrangement VCC1 7 10 GND (Top view) 8 9 16J 0 J 1 J 2 J 3 J 4 J 5 J 6 CLK CLK Q PR SPE CLR J 7

Input pins J0 to J7 Count data input for option CLK, CLK Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger SPE Preset input for Jn data PR Preset input for D-type Flip Flop (Initialize “L” at Q output) CLR Clear input for D-type Flip Flop (Initialize “H” at Q output) Output pins Q Output for D-type Flip Flop Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage V CC –0.5 to 7.0 V Input / output voltage V IN/VOUT –0.5 to VCC +0.5 V VCC, GND current I CC , IGND –50 mA Output current / pin I OUT –25 mA Power dissipation P T 500 mW Storage temperature Tstg –65 to 150 °C Input diode current I IK –20 mA Output diode current I OK –20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal.

Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 2— 6V Input/output voltage V IN/OUT 0— V CC V Operating temperature Topr –40 — +85 °C Input rise/fall time*1 VCC = 2.5 V t r, tf 0 — 1000 ns VCC = 4.5 V 0 — 500 VCC = 5.5 V 0 — 400 Note: 1. This item guarantees maximum limit when one input switches. Logic Diagram CLK CLK CLK 8-bit binary counter SPE PR CLR PR D CK Q Q CLR QCO SPE J0 J0 J1 J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7

Electrical Characteristics

Ta = 25°C Ta = –40 to 85°C Item Symbol V CC Min Typ Max Min Max Unit Test Conditions High level input VIH 2.0 1.5 — — 1.5 — V J0 to J7 voltage 4.5 3.15 — — 3.15 — SPE 6.0 4.2 — — 4.2 — Low level input VIL 2.0 — — 0.5 — 0.5 V J0 to J7 voltage 4.5 — — 1.35 — 1.35 SPE 6.0 — — 1.8 — 1.8 High level output VOH 2.0 1.9 2.0 — 1.9 — V V IN =I OH = –20 mA voltage 4.5 4.4 4.5 — 4.4 — V IH or VIL 4.5 4.18 4.31 — 4.13 — I OH = –4 mA Low level output VOL 2.0 — 0.0 0.1 — 0.1 V V IN =I OL = 20 mA voltage 4.5 — 0.0 0.1 — 0.1 V IH or VIL 4.5 — 0.17 0.26 — 0.33 I OL = 4 mA Input capacitance IIN 6.0 — — –0.1 — –1.0 mA V IN = VCC or GND Supply current I CC 6.0 — — 4.0 — 40.0 mA V IN = VCC or GND

Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) Sym- Ta = 25 °C Ta = –40 to 85°C Item bol V CC Min Typ Max Min Max Unit Test Conditions Maximum clock f max 2.0 — — 4 — 3 MHz frequency 4.5 — 36 20 — 16 6.0 — — 24 — 19 Output rise/fall time tTLH 2.0 — 30 75 — 95 ns tTHL 4.5 — 8 15 — 19 6.0 — 7 13 — 16 Propagation delay t PLH 2.0 — — 300 — 380 CLK or CLK to Q time t PHL 4.5 — 35 60 — 75 6.0 — — 53 — 65 tPLH 2.0 — — 150 — 185 PR or CLR to Q tPHL 4.5 — 18 30 — 38 6.0 — — 25 — 32 Pulse width tw 2.0 80 — — 100 — ns (CLK, CLK, PR, CLR) 4.5 16 — — 20 — 6.0 14 — — 17 — Setup time ts 2.0 100 — — 125 — ns (Jn - CLK, CLK) 4.5 20 — — 25 — (SPE, CLK, CLK) 6.0 17 — — 21 — Hold time th 2.0 15 — — 15 — ns (Jn - CLK, CLK) 4.5 10 — — 10 — (SPE, CLK, CLK) 6.0 5 — — 5 — Input capacitance C IN — — 5 10 — 10 pF Power dissipation capacitance*1 Note: 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. I CC (opr) = CPD • VCC • fIN + ICC

Z = 50out Pulse generator Z = 50out Ω Ω CLK CLK SPE PR CLR C L Q Output Input Input Note: 1. C L includes probe and jig capacitance. Waveforms – 1 CLK 10 % 90 % 50 % 50 % 90 % 6 ns 6 ns 10 % tw tw VCC GNDCLK Q tPLH 90 % 10 % 50 % tTLH VOH VOL 90 % 10 % 50 % tTHL tPHL

Waveforms – 2 Jn VCC GND VCC VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 50 % 10 % CLK GND ts 50 % CLK F/F Output Internal delay 50 % 6 ns Waveforms – 3 Jn VCC GND VCC VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 50 % 10 % CLK GND th 50 % Internal delay CLK F/F Output 6 ns 50 % Note: 1. F/F output is internal signal of IC.

Waveforms – 4 SPE VCC GND VCC VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % 50 % CLK GND ts 50 % Internal delay CLK F/F Output 50 % 6 ns Waveforms – 5 Internal delay SPE VCC GND VCC VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % 50 % CLK GND th 50 % CLK F/F Output 6 ns 50 % Note: 1. F/F output is internal signal of IC.

Waveforms – 6 CLR PR Q VOH VOL 90 % VCC GND 50 % 10 % tf tr 90 % 50 % 10 % VCC GND 90 % 50 % 10 % tf tr 90 % 50 % 10 % 50 % tPHL 50 % tw tw tPLH

(CO=SPE) CLR Q PR Q Count 5432103210 3 5 3 4 (Initialize of CLR) (Initialize of PR)

Example of Application Circuit AC Signal Generator for STN Type Liquid Crystal Panel Initialize counter: 50 V CC GND J 0 J 1 J 2 J 3 J 4 J 5 J 6 CLK CLK Q PR SPE CLR J 7 Note: When initializing output D-F/F apply “L”

Example of AC Signal Generator CLK SPE (CO=SPE) CLR Q PR Q Count 50 49 48 2 1 0 50 1 0 50 49 1 2 3 49 50 51 52 53 101 102 103 104

Unit : mm TTP-16DA 0.50 – 0.10 0 – 10°

0.03 Min

0.1Max 0.17 – 0.05 6.40 – 0.20 0.10

1.10 Max

0.20 – 0.10 0.10 M 0.65 16 9 4.40

4.50 Max

5.20

5.4 Max

(reference value) TTP-16DA 0.05 g Unit: mm *Dimension including the plating thickness Base material dimension 0.50 – 0.100° – 8° *0.17 – 0.05 6.40 – 0.20 0.10 0.13 M 0.65 16 9 4.40 5.00

5.30 Max

0.07+0.03 –0.04

0.65 Max

1.0 0.20 – 0.06 + 0.08 – 0.07*0.22 0.15 – 0.04

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