HD151011 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 14

Technical content

Features

  • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ)
  • High output current Fanout of 10 LS TTL Loads
  • Wide operating voltage VCC = 2 to 6 V
  • Low supply current (Ta = 25°C) ICC (Static) = 4 µA (max)
  • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD151011FPEL SOP-20 pin (JEITA) FP-20DAV FP EL (2,000 pcs/reel) HD151011TELL TSSOP-20 pin TTP-20DAV T ELL (2,000 pcs/reel) Note: Please consults the sales office for the above package availability.

Rev.2.00, Jul.16.2004, page 2 of 13 Function Table Control Inputs CLR PR SPESPESPESPE C/TTTT Mode Operation Description H H H X Generally count Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) X X L X Synchronous preset Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) — — — H — Clock inputs (CLK, CLK) is CMOS level — — — L — Clock inputs (CLK, CLK) is TTL level L H — — Initialize of Q output Initialize of Q = “L” H L — — Initialize of Q output Initialize of Q = “H” Note: 1. Synchronous preset ( SPE) input can set max 99 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. 4. Clock inputs (CLK, CLK) is selectable CMOS level (V CC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level) Don't set data exceeding 99 to Jn. (J0 : LSB, J7 : MSB) H : High level L : Low level X : Immaterial — : Irrespective of condition Pin Arrangement VCC1 7 14 CO GND (Top view) 8 13 J 0 (Test 1) J 1 J 2 J 3 J 4 J 5 J 6 J 7 12 (Test 2) C / T CLK CLK Q PR SPE CLR

Rev.2.00, Jul.16.2004, page 3 of 13 Pin Description Pin Name Pin Description Input pins J0 to J7 Count data input for option C/T Level change input for CLK, CLK (CMOS level or TTL level) CLK, CLK Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger SPE Preset input for Jn data PR Preset input for D-type Flip Flop (Initialize “L” at Q output) CLR Clear input for D-type Flip Flop (Initialize “H” at Q output) Output pins CO Output for BCD decimal counter Q Output for D-type Flip Flop Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage V CC –0.5 to 7.0 V Input/output voltage V IN/VOUT –0.5 to VCC +0.5 V VCC, GND current I CC, IGND ±50 mA Output current/pin I OUT ±25 mA Power dissipation P T 757 mW Storage temperature Tstg –65 to 150 °C Input diode current I IK ±20 mA Output diode current I OK ±20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 2— 6V Input/output voltage V IN/OUT 0— V CC V Operating temperature Topr –40 — +85 °C Input rise/fall time*1 VCC = 2.5 V t r, tf 0 — 1000 ns VCC = 4.5 V 0 — 500 VCC = 5.5 V 0 — 400 Note: 1. This item guarantees maximum limit when one input switches. Logic Diagram C/T CLK CLK CLK BCD decimal counter SPE PR CLR PR D CK Q Q CLR Q CO CO SPE J0 J0 J1 J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7

Rev.2.00, Jul.16.2004, page 4 of 13

Electrical Characteristics

Sym- Ta = 25°C Ta = –40 to 85°C Item bol V CC Min Typ Max Min Max Unit Test Conditions High level input V IH 2.0 1.5 — — 1.5 — V J0 to J7 voltage 4.5 3.15 — — 3.15 — C/T, SPE 2.0 1.5 — — 1.5 — CLK, CLK C/ T = VIH 6.0 4.2 — — 4.2 — 4.5 to 5.5 Low level input V IL 2.0 — — 0.5 — 0.5 V J0 to J7 voltage 4.5 — — 1.35 — 1.35 C/T, SPE 2 . 0 ——0 . 5 —0 . 5 CLK, CLK C/ T = VIH 4.5 to 5.5 High level output V OH 2.0 1.9 2.0 — 1.9 — V V IN =I OH = –20 mA voltage 4.5 4.4 4.5 — 4.4 — V IH or VIL 4.5 4.18 4.31 — 4.13 — I OH = –4 mA Low level output V OL 2.0 — 0.0 0.1 — 0.1 V V IN =I OL = 20 mA voltage 4.5 — 0.0 0.1 — 0.1 V IH or VIL 4.5 — 0.17 0.26 — 0.33 I OL = 4 mA Input capacitance I IN 6.0 — — ±0.1 — ±1.0 µA V IN = VCC or GND Supply current I CC 6.0 — — 4.0 — 40.0 µA V IN = VCC or GND

Rev.2.00, Jul.16.2004, page 5 of 13 Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) Sym- Ta = 25°C Ta = –40 to 85°C Item bol V CC Min Typ Max Min Max Unit Test Conditions Maximum clock f max 2 . 0 ——4 —3 M H z frequency 4.5 — 36 20 — 16 6.0 — — 24 — 19 Output rise/fall time t TLH 2.0 — 30 75 — 95 ns tTHL 4.5 — 8 15 — 19 6.0 — 7 13 — 16 Propagation delay time t PLH 2.0 — — 250 — 318 ns CLK or CLK to CO tPHL 4.5 — 30 50 — 63 6.0 — — 45 — 53 tPLH 2.0 — — 300 — 380 CLK or CLK to Q tPHL 4.5 — 35 60 — 75 6.0 — — 53 — 65 tPLH 2.0 — — 150 — 185 PR or CLK to Q tPHL 4.5 — 18 30 — 38 6.0 — — 25 — 32 Pulse width t w 2.0 80 — — 100 — ns (CLK, CLK, PR, CLR) 4.5 16 — — 20 — 6 . 0 1 4——1 7— Setup time t s 2.0 100 — — 125 — ns (Jn - CLK, CLK) 4.5 20 — — 25 — (SPE, CLK, CLK) 6.0 17 — — 21 — Hold time t h 2 . 0 1 5——1 5—n s (Jn - CLK, CLK) 4.5 10 — — 10 — (SPE, CLK, CLK) 6.0 5 — — 5 — Input capacitance C IN ——5 1 0—1 0p F Power dissipation capacitance*1 Note: 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. ICC (opr) = CPD • VCC • fIN + ICC

Rev.2.00, Jul.16.2004, page 6 of 13 Test Circuit VCCVCC See Function Table Pulse generator Z = 50out Pulse generator Z = 50out Ω Ω C/T CLK CLK SPE PR CLR C L Q Output Output Input Input C L CO Note: 1. C L includes probe and jig capacitance. Waveforms – 1 CLK 10 % V 90 % 90 % 6 ns ref 6 ns Vref 10 % *1 *1 t w t w VIH GNDCLK Q tPLH 90 % 10 % 50 % tTLH VOH VOL 90 % 10 % 50 % tTHL tPLH 90 % 10 % 50 % tTLH 90 % 10 % 50 % tTHL CO tPHL tPHL VOH VOL Note: 1. In case of C/ T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC × 50%

Rev.2.00, Jul.16.2004, page 7 of 13 Waveforms – 2 Jn VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND Vref t s 50 % CLK F/F Output Internal delay 50 % 6 ns Waveforms – 3 Jn VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND Vref t h 50 % Internal delay CLK F/F Output 6 ns 50 % Notes: 1. In case of C/ T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC × 50% 2. F/F output is internal signal of IC.

Rev.2.00, Jul.16.2004, page 8 of 13 Waveforms – 4 SPE VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND Vref t s 50 % Internal delay CLK F/F Output 50 % 6 ns Waveforms – 5 Internal delay SPE VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND Vref t h 50 % CLK F/F Output 6 ns 50 % Notes: 1. In case of C/ T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC × 50% 2. F/F output is internal signal of IC.

Rev.2.00, Jul.16.2004, page 9 of 13 Waveforms – 6 CLR PR Q VOH VOL 90 % VCC GND 50 % 10 % t f t r 90 % 50 % 10 % VCC GND 90 % 50 % 10 % t f t r 90 % 50 % 10 % 50 % t PHL 50 % t w t w t PLH

Rev.2.00, Jul.16.2004, page 10 of 13 Timing Chart CLK SPE (CO=SPE) CLR Q PR Q Count 5432103210 2 3 (Initialize of CLR) (Initialize of PR)

Rev.2.00, Jul.16.2004, page 11 of 13 Example of Application Circuit AC Signal Generator for STN Type Liquid Crystal Panel CLK (CLK) : CMOS level input Initialize counter : 32 VCCCO GND J 0 NC NC (Test 1) J 1 J 2 J 3 J 4 J 5 J 6 J 7 (Test 2) C/T CLK CLK Q PR SPE CLR Note: When initializing output D-F/F apply "L"

Rev.2.00, Jul.16.2004, page 12 of 13 Timing Chart Example of AC Signal Generator CLK SPE (CO=SPE) CLR Q PR Q Count 1digit=2 2digits=3 32 31 30 2 1 0 32 31 1 0 32 1 2 3 31 32 33 34 35 65 66 67 68

Rev.2.00, Jul.16.2004, page 13 of 13 Package Dimensions Package Code JEDEC JEITA Mass (reference value) FP-20DAV Conforms 0.31 g *Ni/Pd/Au plating *0.40 ± 0.06 0.12 0.15 M 101 *0.20 ± 0.05

0.80 Max

12.6 5.5

2.20 Max

13 Max

0˚ – 8˚ 0.70 ± 0.20 + 0.20 – 0.307.80 1.27 0.10 ± 0.10 1.15 As of January, 2003 Unit: mm Package Code JEDEC JEITA Mass (reference value) TTP-20DAV 0.07 g *Ni/Pd/Au plating 0.50 ± 0.100˚ – 8˚ *0.15 ± 0.05 6.40 ± 0.20 0.10

1.10 Max

0.13 M 0.65 11 0 20 11 4.40 6.50

6.80 Max

*0.20 ± 0.05 0.07+0.03 –0.04 1.0

0.65 Max

As of January, 2003 Unit: mm

Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 RENESAS SALES OFFICES © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .1.0