HD151011 HITACHI | Alldatasheet

Document overview

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Technical content

Features

  • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ)
  • High output current Fanout of 10 LS TTL Loads
  • Wide operating voltage Vcc = 2 to 6 V
  • Low supply current (Ta = 25°C) Icc (Static) = 4 mA (max)

CLR PR SPE C/T Mode Operation Description HHHX Generally count Down count at the rise edge of clock (CLK), Down count at the fall edge of clock (CLK) X X L X Synchronous preset Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) ———H — Clock inputs (CLK, CLK) is CMOS level ———L — Clock inputs (CLK, CLK) is TTL level L H — — Initialize of Q output Initialize of Q = "L" H L — — Initialize of Q output Initialize of Q = "H" H: High level L: Low level Z: Immaterial —: Irrespective of condition 1. Synchronous preset (SPE) input can set max 99 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. 4. Clock inputs (CLK, CLK) is selectable CMOS level (V CC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level) Note: Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB)

(Top view) 8 13 J 0 (Test 1)* J 1 J 2 J 3 J 4 J 5 J 6 J 7 12 (Test 2)* C / T CLK CLK Q PR SPE CLR * Pins 18 and 19 are for function test only and should be open. Pin Description Pin Name Pin Description Input pins J0 to J7 Count data input for option C/T Level change input for CLK, CLK (CMOS level or TTL level) CLK, CLK Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger SPE Preset input for Jn data PR Preset input for D-type Flip Flop (Initialize "L" at Q output) CLR Clear input for D-type Flip Flop (Initialize "H" at Q output) Output pins CO Output for BCD decimal counter Q Output for D-type Flip Flop

Supply voltage V CC –0.5 to 7.0 V Input / output voltage V IN / VOUT –0.5 to VCC +0.5 V VCC, GND current I CC , IGND –50 mA Output current / pin I OUT –25 mA Power dissipation P T 757 mW Storage temperature Tstg –65 to 150 °C Input diode current I IK –20 mA Output diode current I OK –20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 2— 6V Input / output voltage V IN / OUT 0— V CC V Operating temperature Topr –40 — +85 °C Input rise / fall time *1 VCC = 2.5 V tr, tf 0 — 1000 ns VCC = 4.5 V 0 — 500 VCC = 5.5 V 0 — 400 Note: 1. This item guarantees maximum limit when one input switches.

D CK Q Q CLR Q CO CO SPE J0 J0 J1 J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7

Electrical Characteristics

Ta = 25°C Ta = –40 to 85 °C Item Symbol V CC Min Typ Max Min Max Unit Test Conditions High level input VIH 2.0 1.5 — — 1.5 — V J0 to J7 voltage 4.5 3.15 — — 3.15 — C/ T, SPE 2.0 1.5 — — 1.5 — CLK, CLK C/T = VIH 6.0 4.2 — — 4.2 — 4.5 to 5.5 Low level input VIL 2.0 — — 0.5 — 0.5 V J0 to J7 voltage 4.5 — — 1.35 — 1.35 C/ T, SPE 2.0 — — 0.5 — 0.5 CLK, CLK C/T = VIH 6.0 — — 1.8 — 1.8 4.5 to 5.5 High level output voltage VOH 2.0 1.9 2.0 — 1.9 — V V IN = VIH or VIL IOH = –20 mA 4.5 4.18 4.31 — 4.13 — I OH = –4 mA Low level output voltage VOL 2.0 — 0.0 0.1 — 0.1 V V IN = VIH or VIL IOL = 20 mA 4.5 — 0.17 0.26 — 0.33 I OL = 4 mA Input capacitance IIN 6.0 — — –0.1 — –1.0 mA V IN = VCC or GND Supply current I CC 6.0 — — 4.0 — 40.0 mA V IN = VCC or GND

Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) Ta = 25°C Ta = –40 to 85 °C Item Symbol V CC Min Typ Max Min Max Unit Test Conditions Maximum clock frequency fmax 2.0 — — 4 — 3 MHz 4.5 — 36 20 — 16 6.0 — — 24 — 19 Output rise / fall time tTLH 2.0 — 30 75 — 95 ns tTHL 4.5 — 8 15 — 19 6.0 — 7 13 — 16 Propagation delay time tPLH 2.0 — — 250 — 318 ns CLK or CLK to CO tPHL 4.5 — 30 50 — 63 6.0 — — 45 — 53 tPLH 2.0 — — 300 — 380 CLK or CLK to Q tPHL 4.5 — 35 60 — 75 6.0 — — 53 — 65 tPLH 2.0 — — 150 — 185 PR or CLR to Q tPHL 4.5 — 18 30 — 38 6.0 — — 25 — 32 Pulse width tw 2.0 80 — — 100 — ns (CLK, CLK, PR, CLR) 4.5 16 — — 20 — 6.0 14 — — 17 — Setup time ts 2.0 100 — — 125 — ns (Jn - CLK, CLK) 4.5 20 — — 25 — (SPE, CLK, CLK) 6.0 17 — — 21 — Hold time th 2.0 15 — — 15 — ns (Jn - CLK, CLK) 4.5 10 — — 10 — (SPE, CLK, CLK) 6.0 5 — — 5 — Input capacitance C IN — — 5 10 — 10 pF Power dissipation capacitance Note: 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. I CC (opr) = CPD VCC • fIN + ICC

  • Test Circuit VCCVCC See Function Table Pulse generator Z = 50out Pulse generator Z = 50out Ω Ω C/T CLK CLK SPE PR CLR C L Q Output Output Input Input C L CO Note: 1. CL includes probe and jig capacitance.
  • Waveforms – 1 CLK 10 % V 90 % 90 % 6 ns ref 6 ns V ref 10 % *1 *1 tw tw VIH GNDCLK Q tPLH 90 % 10 % 50 % tTLH VOH VOL 90 % 10 % 50 % tTHL tPLH 90 % 10 % 50 % tTLH 90 % 10 % 50 % tTHL CO tPHL tPHL VOH VOL Note: 1. In case of C/ T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC , Vref is VCC · 50%
  • Waveforms – 2 Jn VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND V ref ts 50 % CLK F/F Output Internal delay 50 % 6 ns Notes: 1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC , Vref is VCC · 50% 2. F/F output is internal signal of IC.
  • Waveforms – 3 Jn VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND V ref th 50 % Internal delay CLK F/F Output 6 ns 50 % Notes: 1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC , Vref is VCC · 50% 2. F/F output is internal signal of IC.
  • Waveforms – 4 SPE VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND V ref ts 50 % Internal delay CLK F/F Output 50 % 6 ns Notes: 1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC , Vref is VCC · 50% 2. F/F output is internal signal of IC.
  • Waveforms – 5 Internal delay SPE VCC GND VIH VOH VOL 90 % 6 ns 10 % 90 % 10 % 10 % 90 % 10 % CLK GND V ref th 50 % CLK F/F Output 6 ns 50 % Notes: 1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC , Vref is VCC · 50% 2. F/F output is internal signal of IC.
  • Waveforms – 6 CLR PR Q VOH VOL 90 % VCC GND 50 % 10 % tf tr 90 % 50 % 10 % VCC GND 90 % 50 % 10 % tf tr 90 % 50 % 10 % 50 % tPHL 50 % tw tw tPLH

(CO=SPE) CLR Q PR Q Count 5432103210 2 3 2 2 (Initialize of CLR) (Initialize of PR)

Example of Application Circuit

  • AC Signal Generator for STN Type Liquid Crystal Panel CLK (CLK) : CMOS level input Initialize counter : 32 V CCCO GND J 0 NC NC (Test 1) J 1 J 2 J 3 J 4 J 5 J 6 J 7 (Test 2) C/T CLK CLK Q PR SPE CLR *When initializing output D-F/F apply "L"
  • Example of AC Signal Generator CLK SPE (CO=SPE) CLR Q PR Q Count 1digit=2 2digits=3 32 31 30 2 1 0 32 31 1 0 32 31 1 2 3 31 32 33 34 35 65 66 67 68

Unit : mm 0.50 – 0.100° – 8° 0.17 – 0.05 6.40 – 0.20 0.10

1.10 Max

0.13 M 0.65 11 0 20 11 4.40 6.50

6.80 Max

0.22+0.08 –0.07 0.07+0.03 –0.04 1.0 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-20DA 0.07 g

0.65 Max

0.20 – 0.06 0.15 – 0.04 Unit: mm Dimension including the plating thickness Base material dimension

  1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 Copyright © Hitachi, Ltd., 1999. All rights reserved. Printed in Japan. Hitachi Asia Pte. Ltd.

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