HD146818

HD146818 HITACHI | Alldatasheet

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RTC (Real Time Clock Plus RAM) ‘The HD146818 is a HMCS6800 peripheral CMOS device which combines three unique features: a complete time-of-day H0146818P clock with alarm and one hundred calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of Low-power static RAM. This device includes HD6801, HD6301 multiplexed bus interface circuit and 8085's multiplexed bus interface as well. 80 it can be directly connected to HD6801,, HD6301 and 8085. The Real-Time Clock plus RAM has two distinct uses. First it is designed as battery powered CMOS part including all the ‘common battery backed-up functions such as RAM, time, and P-24) calender. Secondly, the HD146818 may be used with a CMOS (oP. microprocessor to ‘relieve the software of timekeeping work- foad and to extend the available RAM of an MPU such as the | NO146818FP HD6301 © FEATURES @ Time-of-Day Clock and Calendar = Counts Seconds, Minutes, and Hours of the Day + Counts Days of Week, Date, Month, and Year © Binary or BCD Representation of Time, Calendar, and Alarm © 12- or 24 Hour Clock with AM and PM in 12-Hour Mode © Automatic End of Month Recognition © Automatic Leap Year Compensation (rP-24) © Interfaced with Software as 64 RAM Locations + 14 Bytes of Clock and Contro! Register + 50 Bytes of General Purpose RAM © PIN ARRANGEMENT © Three Interrupt are Separately Software Maskable and Test: able + Time-of-Day Alarm, Once:per Second to Once-per-Day ncQ] [24} vee + Periodic Rates from 30.5us to 500ms osc: [2] [23)SQw + End-of Clock Update Cycle osc.[3 | [22}PS © Programmable Square Wave Output Signal AD © Three Time Bate Input Options aD, Ce Lckour + 4.194304 MHz ges [2)CKFS + 1.048576 MHz ao: [e] mie » 788 Kis ADsEH] 10146818 Fars © Clock Output May be used as Microprocessor Clock Input AD. + At Time Base Frequency =4 or =1 «Ce pz]os © Multiplexed Bus Intertace Circuit of HD6801, HD6301 and ADs [7] fe] Nc

8085 ADs[io] fs] RAW

© Low-Power, High-Speed, High-Density CMOS apt] Faas © Battery Backed-up Operation © Motorola MC148818 Compatible Vss [12] {3} CE © 01468184 in Development ron View ‘op View) © ABSOLUTE MAXIMUM RATINGS 5 teem [symeot vate Unit Supply Vol [veces -0.3~+7.0 v Input Voltage 0.3~+70 Vv Operating Temperature T c store Tempeaure 7 ‘c 7" With respect 10 Vgg SYSTEM GND] (NOTE) Permanent LSI damage may occur if maximum rating ore exceeded. Normal operation should be under recomended operating condition. if thete conditions are exceeded. it could affect reliabitity of LSI. @ HITACHI Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1055

™ RECOMENDED OPERATING CONDITIONS tem [Symbor[ min tye max nit Supply Voltage Sa inne Votoee A 7 SE Operating Temperature | Tor | To + With respect to Vgg (SYSTEM GND) (NOTE) Refer to Battery Backed Electrical characteris ® ELECTRICAL CHARACTERISTICS © DC CHARACTERISTICS (Vc = 4.5 ~ 6.25V, Vgs = OV, Ta = 0 ~ +70°C, unless otherwise noted.) Item | Symbot_| TestCondition [min [typ [max | unit ADy ~AD>, CE, AS, R09, CRS, P8 [vee20 [= | vee | Input “High” Voltage [OT vee-t0 [= | vec] v ADo~AD;, CE, AS, RAW, DS, CKFS, PS’ | | - o7 ‘pur "Low" Voltage [RES ] vu | 03 | = [os | ¥ Three-state (off state) ~ Ouiput Leakage Current | TAG | ow | Tt a AD ~AD> | a Output “High” Voltage | SaMt.CROY Vou lon <-10 nA 1 v AD) ~AD> V lop =1.6mA | Output “Low” Voltage CKOUT | Vou lo. = 1.6 mA - v TRO, Saw ‘Do ~AD> ee ee Input Capacitance All inputs except Ce | Mero, | Ta = 25°C pF ADo~ADs f =1MHz Output Capacitance SOW, CKOUT,IRO | Cour [= 25 | oF Supply Current | fose=4MHe | Vec=sov | | - | 0 | eUResarte] [tose = 1 Mie | SoM: aiate [oma operating) | fose=32kHz || (No toad) | _- [= [8] : | feves Uae - [= [os] Supply Current 2 Circuit: Fig. 11 mA (MPU not oper- [fosc=1MHz | | Parameters | = | = [2 ating) [tosc=32kHe | Tobie 1 = HA Supply Current [fosc=4MHz | | Vee=50V0 Lm =| 10 (MPU Read/Write [fose=1MHz | SQW: disable ee ee seer [Tose=a2KHe | CkOUT = toxe [ = oe loo | (No Load) Supply Current | fosc=4MHz | | OSC: open = j= [4 yo, (MPU not ope- [tose = 1 MAE | fovea ee ee stra) [ tose =32kHz | Crean: Fa? [T= | 100 Tua * Supply current of HD 146818 is defined as the value when the time-bese frequency to be used is programmed into Register A. When powers trned on; tase bts are untnad o thar cm tet currant more than the above tpwiication may iw Piao neve fal to tte ine-bae frequency afta turning on power Supe. ** Vin min ® Voo-0.2V Vit mex" Vss*0.2V @HITACHI 1056 — Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300

® AC CHARACTERISTICS (Voc * 4.5 ~ 5.25V, Vsg = OV, Ta = 0 ~ +70°C, unless otherwise noted.) BUS TIMING tem [Svmbot_ [min tye [max [unit Cree Time a Pulse Width, AS/ALE “High” [Pwase | too | = Ts AS Rise Time [ts | - | - | 30 | om AS Fall Time ee Oe ee Delay Time DS/E to AS/ALE Rise [aso | 40 = Ts DS Rise Time [tos [= T= Ts DS Fall Time a Pulse Width, DS/E Low or RO/WA “High” [7 PWosn [35 T= Tne Pulse Width, DS/E High or RO/WR “Low” [PW | 300 T= Delay Time, AS/ALE to DS/E Rise [tasos | 90 | - | - | ns ‘Address Setup Time (RAW) [ass | ts ‘Address Setup Time (CE) [mse | 8s P= ‘Address Hold Time (R/W, CE} [tan [to Muxed Address Valid Time to AS/ALE Fall [ts | 80 | - | - | ms Muxed Address Hold Time [tame 20s Peripheral Data Setup Time tosw [15 | - | - | Write Data Hold Time [tow | of = [= om Peripheral Output Data Delay Time From DS/E or RD toon ; - | - | 20 | ns Read Data Hold Time [town ft T= = Input Rise and Fall Time se CONTROL SIGNAL TIMING teem [symbor [min [ye [max] unit udu we | P= =f ms Coen Sree [sae | ee ee Reset Pulse Width [tam | sof Ts Reset Delay Time [tan | 60 [ - fT = Ts Power Sense Pulse Width [tem | 60 Ts Power Sense Delay Time [tun | so = Ts TRG Release from OS [tinos | = dT = 20s TRG Release from RES [time | = T= 20s VAT Bit Delay [vero | = [= 20 @HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 1057

“ 1, ae u | | * ve tas, tone — ae aD: P| “ AD»~ AD? Vow Vow 2 (ul pe (NOTE) Vin = Vou * Vec-2.0V Vie -090 Vou 08v Figure 1 Bus Read, Write Timing (6801 Family) @ HITACHI 1058 — Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

s.ov Sov AL akan Test Terminat Test Terminal Diode c | A 182074 @ or equiv. is & 2 oer to) TRG Lond circuit RY>285KA (a) AD,~AD,, SQW, CKOUT Figo Test Load = BATTERY BACKED-UP OPERATION (2) Retention of RAM data © DEFINITION OF BATTERY BACKED-UP OPERATION (3) RES, IRQ, CKFS, CKOUT, PS, SQW functions Active functions Inactive functions (1) Clock function (1) Data bus read/write operation © BATTERY BACKED-UP ELECTRICAL CHARACTERISTICS (Vss = OV, Ta = 0 ~ +70°C, unless otherwise noted.) Supply Voltage 2 a = cry Vegegoy we Oscillation GROUT: fore (No Pe a uA Supply tecu” [sanz = T8010 Current Veo. = 3.0V a SS oct mee Te KOUT: fose (No load “ake [T3070 aA Battery Backed-up Transit 0 Setup Time ipply Voltage Fait Time | ter | a a Supply Voltage Rise Time a a ee Input “High*” Vottage Vow voce SEV ~48V [2s = | Vee. | OV i [08G;[08xVe, [= | Ven | V [exrsies [os [= | os |v Input "Low" Volts | Vn ee (osc, | og T= fT os TV Ourput Hah” Valle Saw, CKOUT] O&ven_| =| = 1 V “Lea saw.cxour| =| - [| 8 |v Crone Len” Vonage | Vou | tour toa me =) 88 * The time-bate frequency to be uted needs to be chotan in Register A. @HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 1061

— eee HD146818 ® CRYSTAL OSCILLATION CIRCUIT Table 1 Oscillator Circuit Parameters The on-chip oscillator is designed for a parallel resonant crystal at 4.194304 MHz or 1.048576 MHz or 32.768 kHz frequencies. The crystal connections are shown in Figure 11. Parameta 1.048576 MHz| 32.768 kHz a ee 2) Hora6818 Rr | sox | 150Ka | 5.6 Ma 8c Ost Cn | 22pF | 33pF | 18 Con | 220F | 33pF | 33 pF Ce es ee Dd as ct] 0 ra | 700 a | 40m i (NOTE) 1. RS, CL ore uted for 32.768 kHz only 2) Capacitance (Cin! should be adjurted to accurate frequency Parameters listed sbove are applied to the supply current measuremant (See table of DC CHARACTERISTICS) i 3. Gh: Crystal impedence Cin in i; Figure 11 Crystal Oscillator Connection = NOTE FOR BOARD DESIGN OF THE OSCILLATION (2) Pin 3 signal line should be wired apart from pin 4 signal circuit line as much as possible. Don't wire them in parallel, or In designing the board, the following notes should be taken normal oscillation may be disturbed when this signal is when the crystal oscillator is used. feedbacked to OSC,. (1) Crystal oscillator, load capacity Cin, Couts Cx. and Ry, ; must be placed near the [tas muchas posible. RS (3) A signal line ‘or a power source line must not cross or go lormal oscillation may be disturbed when external near the oscillation circuit line as shown in the right figure noise is induced to pin ? and 3. to prevent the induction from these lines and perform the correct oscillation. The resistance among OSC,, OSC; and other pins should be over 10M. ‘The following design must be avoided. |» Semis

6 Signal ¢ i _o

ose], mo: NEE oe ate To {_]s , []3 cout BS u ~ 1 1 HD146818 HO 146818 Figure 12 Note for Board Design of the Oscillation Circuit @ HITACHI Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1063

® INTERFACE CIRCUIT FOR HD6801, HD6301 AND Figure 13 shows the bus control circuit. This circuit auto-

8085 PROCESSOR matically selects the processor type by using AS/ASE to latch

HD146818 has a new interface circuit which permits the the state of DS/RD pin. Since DS is always “Low” and RD is HD146818 to be directly interfaced with many type of multi- always “High during AS/ALE, the latch automatically indicates plexed bus microprocessor such as HD6801, HD630! and 8085 which processor type is connected, etc. 6801, 1H06301' Type 8085 Type HD146818 2085_Bus ‘gern MPU Signals MPU Signals Pin Signals CI el AS ALE AS O | 0S, E, or 92 RO os s pe tp Read Enable — a Rw wr aw OO TL Write Enable Lb D D> Figure 13 Functional Diagram of the Bus Control Circuit = ADDRESS MAP may initialize the time, calendar, and alarm by writing to Figure 14 shows the address map of the HD146818. The ‘these RAM locations. The contents of the 10 time, calendar, memory consists of 50 general purpose RAM bytes, 10 RAM and alarm byte may be either binary or binary-coded decimal bytes which normally contain the time, calendar, and alarm (BCD). data, and four control and status bytes. All 64 bytes are Before initializing the internal registers, the SET bit in directly readable and writable by the processor program ex- Register B should be set to a “I” to prevent time/calendar cept Registers C and D which are read only. Bit 7 of Register updates from occurring. The program initializes the 10 loca- A and the seconds byte are also read only. Bit 7, of the second tions in the selected format (binary or BCD), then indicates byte, always reads “0”. The contents of the four control and the format in the data mode (DM) bit of Register B. All 10 status registers are described in the Register section. time, calendar, and alarm bytes must use the same data mode, either binary or BCD. The SET bit may now be cleared to © Time, Calendar, and Alarm Locations allow updates. Once initialized the real-time clock makes ‘The processor program obtains time and calendar infor- all updates in the selected data mode. The data mode cannot mation by reading the appropriate locations. The program be changed without reinitializing the 10 data bytes. ° %0 [seconds Joo a [ES Sec Atarm Jor 13 00 2[ inves oa by oe 3 [Min aterm Jos [Hous doe Lace SL He Alor _]08 | Contents Cn Byte 7[ bate of Mofo? RAM 8 [Monin foe ° joo sof Resistar A Joa cS) a ae 12 [Painter doe « ar 1 de Figure 14 Address Map @ HITACHI 1064 — Hitachi America, Ltd, © Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300

Table 2 shows the binary and BCD formats of the 10 time, the update cycle in the processor program. calendar, and alarm locations. The 24/12 bit in Register B ‘The three alarm bytes may be used in two ways. When establishes whether the hour locations represent 1-to-12 or the program inserts an alarm time in the appropriate hours, 0-t0-23. The 24/12 bit cannot be changed without reinitializing minutes, and seconds alarm locations, the alarm interrupt is the hour locations. When the 12shour format is selected the initiated at the specified time each day if the alarm enable bit high-order bit of the hours byte represents PM when it isa “1”, _is “1”, The alternate usage is to insert a “don’t care” state in The time, calendar, and alarm bytes are not always ac- one or more of three alarm bytes. The “don’t care” code is cessable by ‘the processor program. Once-per-second the 10 any hexadecimal byte from CO to FF. That is, the two most- bytes ate switched to the update logic to be advanced by one significant bits of each byte, when set to ‘“I", create a “don't second and to check for an alarm condition. If any of the 10 care” situation. An alarm interrupt each hour is created with bytes are read at this time, the data outputs are undefined. a “don't care” code in the hours alarm location. Similarly, an The update lockout time is 248 us at the 4.194304 MHz and alarm is generated every minute with “don't care” codes in 1.048567 MHz time bases and 1948 ys for the 32.768 kHz time the hours and minutes alarm bytes. The “don't care” codes base. The Update Cycle section shows how to accommodate —_inall three alarra bytes create an interrupt every second, Table 2 Time, Calendar, and Alarm Data Modes T Fan 7 Address | Function | Decimal - mm BCD Locati Ri 9 ‘Seconds soo~sse | soo~sso [is Ta 1 o~s9 $00~ $38 soo~sso | ts fat 2 i Minutes To~s9 '$00~$38 $00~$59 [3a 58

3 Minutes Alarm | 0~59 $00~$38 soo~sso | 3A | 58

Hours 1=12_| S01~S0C (AM) and | $01~$12 (AM) and 05 0s 4 (12 Hour Mode) $81 ~$8C (PM) $81 ~$92 (PM) Hours: ~ ~ ~ } | (24 Hour Mode) o~23 soo~st7 $00~$23 05 0s Hours Alarm 1~12 $01 ~$0C (AM) and | $01 ~$12 (AM) and 05 5 (12 Hour Mode) $81 ~$8C (PM) ‘$81 ~$92 (PM) Hours Alarm 7 a . Day of the Week ~ ~ ~

7 Day of theMonth | 1~31 | $01~SIF $01~$31 5

a Yer so~see | «Fi 78 + Example: 5:58:21 Thursday 15th February 1979 ++ Set the lower two digits of year in AO. If this number is multiple of 4, update applied to leap year is excuted © Static CMOS RAM ® INTERRUPTS The 50 general purpose RAM bytes are not dedicated within The RTC plus RAM includes three separate fully automatic the HD146818. They can be used by the processor program, sources of interrupts to the processor. The alarm interrupt and are fully available during the update cycle. may be programmed to occur at rates from once-per-second ond When time and calendar information must use battery to one-a-day. The periodic interrupt may be selected for rates back-up, very frequently there is other non-volatile data that from half-a-second to 30.517 ys. The update-ended interrupt must be retained when main power is removed. The 50 user may be used to indicate to the program that an up-date cycle RAM bytes serve the need for low-power CMOS battery- is completed. Each of these independent interrupt conditions backed storage, and extend the RAM available to the program. are described in greater detail in other sections. When further CMOS RAM is needed, additional HD146818s The processor program selects which interrupts, if any, it may be included in the system. The time/calendar functions wishes to receive. Three bits in Register B enable the three may be disabled by holding the dividers, in Register A, in the interrupts. Writing a “1” to a interrupt-enable bit permits reset state by setting the SET bit in Register B ot by removing that interrupt to be initiated when the event occurs. A “O” in the oscillator. Holding the dividers in reset prevents interrupts the interrupt-enable bit prohibits the IRQ pin from being ‘or SQW output from operating while setting the SET bit allows _asserted due to the interrupt cause these functions to occur. With the dividers clear, the available 1 an interrupt fag aleady st when the interrupt becomes user RAM is extended to 59 bytes. Bit 7 of Register A, Registers enabled, the IRQ pin is immediately activated, though the and D, and the high-order Bit of the seconds byte cannot interrupt initiating the event may have occurred much earlier. effectively be used as general purpose RAM. Thus, there are cases where the program should clear such @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 1065

earlier initiated interrupts before first enabling new interrupts. IRQF bit in Register C is a “1” whenever the IRQ pin is being ‘When an interrupt event occurs a flag bit is set to a “1” in driven “Low”. Register C. Each of the three interrupt sources have separate The processor program can determine that the RTC initiated flag bits in Register C, which are set independent of the state the interrupt by reading Register C. A “1” in bit 7 (IRQF bit) of the corresponding enable bits in Register B. The flag bit indicates that one of more interrupts have been initiated by may be used with or without enabling the corresponding enable the part. The act of reading Register C clears all the then-active bits. flag bits, plus the IRQF bit. When the program finds IRQF set, In the software scanned case, the program does not enable it should look at each of the individual flag bits in the same the interrupt. The “interrupt” flag bit becomes a status bit, byte which have the corresponding interrupt-mask bits set which the software interrogates, when it wishes. When the and service each interrupt which is set. Again, more than one software detects that the flag is set, it is an indication to soft- interrupt-flag bit may be set. ware that the “interrupt” event occurred since the bit was last read. © DIVIDER STAGES However, there is one precaution, The flag bits in Register The HD146818 has 22 binary-divider stages following the C are cleared (record of the interrupt event is erased) when __ time base as shown in Figure 10. The output of the dividers is Register C is read. Double latching is included with Register a 1 Hz signal to the update-cycle logic. The dividers are con- C so the bits which are set are stable throughout the read troller by three divider bus (DV2, DVI, and DVO) in Register cycle. All bits which are high when read by the program are A. cleared, and new interrupts (on any bits) are held until after the read cycle. One, two, or three flag bits may be found to © ‘Divider Control be set when Register C is read. The program should inspect The divider-control bits have three uses, as shown in Table all utilized flag bits every time Register C is read to insure that 3. Three usable operating time bases may be selected (4.194304 ‘no interrupts are lost. MHz, 1.048576 MHz, or 32.768 kHz). The divider chain may The second flag bit usage method is with fully enabled be held reset, which allows precision setting of the time. When interrupts. When an interrupt-flag bit is set and the correspond- the divider is changed from reset to an operating time base, ing interrupt-enable bit is also set, the IRQ pin is asserted the first update cycle is one second later. The divider<control “Low”. IRQ is asserted as long as at least one of the three bits are also used to facilitate testing the HD146818. interrupt sources has its flag and enable bits both set. The Table 3 Divider Contiguration Time-Base Select Pin | Outputrin | Operation | Divider | Bypass First Frequency = CKFS CKOUT Mode Reset N-Divider Bits [High [4194506 wiz | Neo “acne Mi [oe |e | ¢ [| a ieee “s a a “ [High | 52.768 kee | op708 ke Pej: fe Pe Ne? rs [re es any A SO © Square-Wave Output Selection © Periodic Interrupt Selection Fifteen of the 22 divider taps are made available to a 1-of-15, The periodic interrupt allows the IRQ pin to be triggered selector as shown in Figure 10. The first purpose of selecting from once every 500 ms to once every 30.517 us. The periodic a divider tap is to generate a square-wave output signal in the interrupt is separate from the alarm interrupt which may be SQW pin. Four bits in Register A establish the square-wave output from once-per-second to once-per-day. frequency as listed in Table 4. The SQW frequency selection Table 4 shows that the periodic interrupt rate is selected shares the 1-of-15 selector with periodic interrupts. with the same Register A bits which select the square-wave Once the frequency is selected, the output of the SQW pin frequency. Changing one also changes the other. But each may be tumed on and off under program control with the function may be separately enabled so that a program could square-wave enable (SQWE) bit in Register B. Altering the switch between the two features or use both. The SQW pin divider, square-wave output selection bits, or the SQW output. is enabled by the SQWE bit. Similarly the periodic interrupt is enable bit may generate an asymetrical waveform at the time enabled by the PIE bit in Register B. of execution. The square-wave output pin has a number of Periodic interrupt is usable by practically all real-time sys- potential uses. For example, it can serve as a frequency standard —_tems. It can be used to scan for all forms of input from contact for external use, a frequency synthesizer, or could be used to closures to serial receive bits or tyes. It can be used in multi- generate one or more audio tones under program control. plexing displays or with software counters to measure inputs, create output intervals, or await the next needed software func- @HITACHI 1066 Hitachi America, Ltd. » Hitachi Piaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

Table 4 Periodic Interrupt Rate and Square Wave Output Frequency 4.194304 or 1.048576 MHz 32.768 kHz conte ete 1 Time Base Time Base trol Register Toa Toa Interrupt Rate SQW Output innertupt ate SQW Output asa] nse [ast | nso | Frequency tr Frequency o {of o fo [None High Level | _None | High Level o fo | o Ta | 308t7us 32.768 kHz 256 Hz o fo | 1 [6 | 6r0%6us | 16.384 kHz 7.8125 ms 128 He o | o { a [ 1 | 122070us 8.192 kHz 122.070 us 8,192 kHz of fof of eatat us | 4.006 ee 204.10 4.096 ee ota | [y[age28tus | 2.04e He | 488.281 us 2.048 kHz ot i [0 | 976s62us | 1.024 kHe 976.562 us 1.024 kHz oof a [Tt] .963125 ms | S12 He [1.969125 ms_ [| S12 Hz 1 [oT 0 | oT 3.90625ms [256 He [3.90625 ms | 256 He 1 fo fo [1 | 78125ms | [78125 ms_ [128 He 1 [1 | 0 18.625 ms 15.625 ms 64Hz 1 1 31.25 ms 31.25 ms 32 Hz 1 To | 625ms 62.5 ms 16 Hz topo 6 ms 125 ms SHe vf ao 60m ae 250 ms ae vo s00 ms ae [some 2 He © Initialization of the Time and the Start Sequence day shown below. The first update of the time occurs about $0Oms later after the SET bit of control register B is reset. So keep followings in - mind when initializing and adjusting the time. Calendar, Time of day Procedure of time initialization & Status atter Update (1) Set the SET bit of contro! register B. (SET = “1") If 29th 23:59:59 in all the months is initia apna A ized, update to Ist in the next month is Mar. 29th. (DVO = DV} = Dv2 = “1") Feb. 29th in leap year) (3) Set the time and calendar to each RAM. (5) Reset the SET bit. (SET = “0") moruh isexecuted. Apr. 3st 1f Feb, 28th 23:59:59 (not in leap year) is | Feb, 28th, 1983 Mika qe o—__I L__, _I initialized, update to Feb. 29th is executed. |-+ Feb. 29th.1983 ieee, = | If Feb, 28th 23:69:58 (in leap year) is ini- | Feb. 28th, 1984 sero i tialized, update to Mar. Ist is executed. |->Mar. 1st, 1984 ‘i = UPDATE CYCLE Figure 15 Time Initialization and the First Update ‘The HD146818 executes an update cycle once-per-second, om assuming one of the proper time bases is in place, the divider Restriction on Time-of-day and Calendar Initialization is not clear, and the SET bit in Register B is clear. The SET bit ‘There is a case in HD146818 (RTC) that update is not exe- _in the “1” state permits the program to initialize the time and cuted correctly if time of day and calendar shown below are calendar bytes by stopping an existing update and preventing initialized. Therefore, initialize the RTC without using time of __a new one from occurring. The primary function of the update cycle is to increment the seconds byte, check for overflow, increment the minutes byte when appropriate and so forth through to the year of the century byte. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a “don’t care” code (11XXXXXX) is present in all three positions. With a 4.194304 MHz or 1.048576 MHz time base the up- @HITACHI Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 1067

date cycle takes 248 us while a 32.768 kHz time base update _time needed to read valid time/calendar data to exceed 244 ys. cycle takes 1984 ys. During the update cycle, the time, calen- The third method uses a periodic interrupt to determine if dar, and alarm bytes are not accessable by the processor an update cycle is in progress. The UIP bit in Register A is set program. The HD146818 protects the program from reading —“I"" between the setting of the PF bit in Register C (see Figure transitional data. This protection is provided by switching 16) Periodic interrupts that occur at a rate of greater than the time, calendar, and alarm portion of the RAM off the — tayc + tyc allow valid time and date information to be read microprocessor bus during the entire update cycle. If the at each occurrence of the periodic interrupt. The reads should processor reads these RAM locations before the update is be completed within (tp, + 2) + tauc to insure that data is complete the output will be undefined. The update in progress _not read during the update cycle. (UIP) status bit is set during the interval. ‘A program which randomly accesses the time and date infor- © POWER-DOWN CONSIDERATIONS mation finds data unavailable statistically once every 4032 In most systems, the HD146818 must continue to keep attempts. Three methods of accommodating nonavailability time when system power is removed. In such systems, a con- during update are usable by the program. In discussing the version from system power to an alternate power supply, three methods it is assumed that at random points user pro- usually a battery, must be made. During the transition from grams are able to call a subroutine to obtain the time of day. system to battery power, the designer of a battery backed-up The first method of avoiding the update cycle uses the RTC system must protect data integrity, minimize power update-ended interrupt. If enabled, an interrupt occurs after consumption, and ensure hardware reliability according to every update cycle which indicates that over 999 ms are avail- the specification described in the section regarding Battery able to read valid time and date information. During this time Backed-up operation. a display could be updated or the information could be trans- The chip enable (CE) pin controls all bus inputs (R/W, DS, fered to continuously available RAM. Before leaving the inter- aS, AD, ~ ADz). CE. when negated, disallows any unintended Tupt service routine, the IRQF bit in Register C should be modification of the RTC data by the bus. CE also reduces cleared. power consumption by reducing the number of transitions The second method uses the update-in-progress bit (UIP) seen internally. in Register A to determine if the update cycle is in progress Power consumption may be further reduced by removing or not. The UIP bit will pulse once-per-second. Statistically, resistive and capacitive loads from the clock out (CKOUT) the UIP bit will indicate that time and date information is pin and the squarewave (SQW) pin. unavailable once every 2032 attempts. After the UIP bit goes During and after the power source conversion, the Vin “I”, the update cycle begins 244 ys later. Therefore, if a “0” maximum specification must never be exceeded. Failure to is read on the UIP bit, the user has at least 244 ys before the meet the Viy maximum specification can cause a virtual time/calendar data will be changed. If a ““1" is read in the SCR to appear which may result in excessive current drain UIP bit, the time/calendar data may not be valid. The user and destruction of the part should avoid interrupt service routines that would cause the UIP bit in Regstera Li tuc teuc. UF bit in 1 Register C tprt2 bh" tpyz2 PF bit in Register C tei = Periodic Interrupt Time interval (500 ms, 260 ms, 126 ms, 62.5me, etc.) TUe_ = Updete Cycle Time (248 us or 1984 us) tauc = Daley Tirme Before Update Cycle (244 us) Figure 16 Update-Ended and Periodic Interrupt Relationship @ HITACHI 1068 — Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

|= SIGNAL DESCRIPTIONS by four, Table 5 summarizes the effect of CKFS. Optional a bit in Register B.

4.194304 Miz © ADo ~ AD, — Multiplexed Bidirectional Address/Dsta Bus

curring during the internal RAM access time. Figure 17. External Time-Base Connection at which time the HD146818 latches the address from ADp to © CKOUT — Clock Out HD6301 case or RD rises in the other case.

DS is 2 positive pulse during the latter portion of the bus interrupt is present and the corresponding interrupt-enable bit cycle, and is variously called DS (data strobe), E (enable), and _is set. To clear the IRQ pin, the processor program normally $2 (¢2 clock). During read cycles, DS signifies the time that the _ reads Register C. The RES pin also clears pending interrupts. RTC is to drive the bidirectional bus. In write cycles, the trail- When no interrupt conditions are present, the IRQ level is ing edge of DS causes the Real-Time Clock plus RAM to latch inthe high-impedance state, Multiple interrupting devices the written data. __ may thus be connected to an IRQ bus with one pullup at the The second interpretation of DS is that of RD, MEMR, or processor. TOR emanating from the 8085 ty/pe processor. In this case, DS identifies the time period when the real-time clock plus © RES — Rest RAM drives the bus with read data. This interpretation of The bus control circuit, within the HD146818, latches the — state of the DS pin on the falling edge of AS/ALE. When 6801 The RES pin does not affect the clock, calendar, or RAM mode, DS must be “Low” during AS/ALE, which is the case functions. On powerup, the RES pin must be held “Low” for with 6801 family multiplexed bus processors. To insure the the specified time, tary, in order to allow the power supply 808$ mode of this circuit the DS pin must remain “High” _to stabilize, Figure 18 shows a typical representation of the during the time AS/ALE is “High”. RES pin circuit. When RES is “Low” the following occurs: © RAW — Read/Write a) Periodic Interrupt Enable (PIE) bit is cleared to “0” b) Alarm Interrupt Enable (AIE) bit is cleared to “O”. c) Update ended interrupt Enable (UIE) bit is cleared to “0”. 4) Update ended Interrupt Flag (UF) bit is cleared to “0”. The bus control circuit treats the R/W pin in one of two ¢) Interrupt Request status Flag (IRQF) bit is cleared to ways. When 6801 family type processor is connected, R/W is “0”. a level which indicates whether the current cycle is a read or f) Periodic Interrupt Flag (PF) bit is cleared to “0”. write. A read cycle is indicated with a “High” level on R/W. g) Alarm Interrupt Flag (AF) bit is cleared to “0” while DS is “High”, whereas a write cycle is a “Low” on R/W hh) IRQ pin is in high-impedance state, and during DS — i) Square Wave output Enable (SQWE) bit is cleared to “0”. The_second interpretation of R/W is as a negative write pulse, WR, MEMW, and I/OW from 8085 type processors. This © PS — Power Sense Circuit_in this mode gives R/W pin the same meaning as the © TE -Chip Enable The powersense pin is used in the control of the valid RAM and time (VRT) bit in Register C. When the PS pin is “Low” the VRT bit is cleared to “0”, During powerup, the PS pin must be externally held “Low” The chip-enable (CE) signal must be asserted Clow) for the specified time, tpry. As power is applied the VRT bit for a bus cycle in which the HD146818 is to be accessed. Cl remain “Low” indicating that the contents of the RAM, time is not latched and must_be stable during DS and AS (in the registers, and calendar are not guaranteed. When normal opera- 6801 case) and during RD and WR (in the 8085 case). Bus 2, o cycles which take place without asserting CE cause no actions System Battery to take place within the HD146818. When CE is “High”, the Vee Beckedup multiplexed bus output is in a high-impedance state. When CE is “High”, all address, data, DS, and R/W inputs v, from the processor are disconnected within the HD146818 ce This permits the HD146818 to be isolated from a powered- down processor. When CE is held “High”, an unpowered device oF }HO1 40818) cannot receive power through the input pins from the real- time clock power source. Battery power consumption can thus WES : be reduced by using a pullup resistor or active clamp on CE when the main power is off. 00s ut @ TRO — Interrupt Request I Vss ‘The TRO pin is an active “Low” output of the HD146818 (NOTE) If thé RTC is isolated from the MPU or MCU power by & that may be used as an interrupt input to a processor. The IRQ lode drop, care must be taken to meet Vin requirements output remains “Low” as long as the status bit causing the Figure 18 Typical Powerup Delay Circuit tor RES @HITACHI 1070 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 (415) 589-8300

tion commences PS should be permitted to go “High”. Output © Register B ($08) signal from external power sence circuit will be connected to agg st this input. LSE read/write [or [v6 [os | [os [oz | or [bo | Regier © REGISTERS [ser [me [ave [ure [same | om [24n2 | ose | The HD146818 has four registers which are accessible to the processor program. The four registers are also fully acces- © SET — When the SET bit is a “O”, the update cycle functions sible during the update cycle. normally by advancing the counts once-persecond. When the SET bit is written to a “1”, any update cycle in progress is © Rogister A (SOA) aborted and the program may initialize the time and calendar use Say bytes without a update occuring i the midst of iialing Read/Write is a read/write bit which is not modified by RES or internal [er [v6 [es [oe [eo [be [or [0 | "resister functions of the HD146818 ” [ie [ove ov ovo [asa [sz [Asi [Aso }excert vie PIE — The periodic interrupt enable (PIE) bit is a read/write UIP — The update in progress (UIP) bit is a status flag that may bit which allows the periodic-interrupt flag (PF) bit to cause be monitored by the program. When UIP is a “1” the update _the IRQ pin to be driven “Low”. A program writes a “1” to cycle is in progress or will soon begin. When UIP is 2 “0” the PIE bit in order to receive periodic interrupts at the rate the update cycle is not in progress and will not be for at least specified by the RS3, RS2, RSI, and RSO bits in Control 244 ys (for all time bases). This is detailed in Table 6. The Register A. A “O” in PIE blocks IRQ from being initiated time, calendar, and alarm information in RAM is fully available by @ periodic interrupt, but the periodic flag (PF) bit is still to the program when the UIP bit is zero — it is not in transition. at the periodic rate. PIE is not modified ee” internal The UIP bit is a read-only bit, and is not affected by Reset. HD146818 functions, but is cleared to “0” by a RES. Writing the SET bit in Register B to a“1” inhibit any update cycle and then clear the UIP status bit. AIE — The alarm interrupt enable (AIE) bit is a read/write bit which when set to a “1” permits the alarm flag (AF) to assert, Table 6 Update Cycle Times IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes (including a “don't — Minimum Time care” alarm code of binary 11XXXXXX), When the AIE bit UIP Bit Tose Before Update is a “0”, the AF bit does not initiate an tka signal. The RES 1 'uc) | Cycle (tauch pin clears AIE to “0”. The internal functions do not affect 1 4.194304 MHz 248 us - the AIE bit. 1 | 1.048576 MHz | 248 us - 1 32.768 kHz 1984 us - UIE — The UIE (update-ended interrupt enable) bit is a read/ 0 | 4.106906 sare a 244 ys write bit which enables the update-end flage (UF) bit to assert Py 1048576 MHz - 244.us TRO. The RES pin going “Low” or the SET bit going “1” clears { the UIE bit. 0 32.768 kHz = 244 us SQWE — When the square-wave enable (SQWE) bit is set to a “1” by the program, a square-wave signal at the frequency V2, DV1, DVO — Three bits-are used to permit the program _ specified in the rate selection bits (RS3 to RSO) appears on the to select various conditions of the 22-stage divider chain. The SQW pin. When the SQWE bit is set to a “O” the SQW pin is divider selection bits identify which of the three time-ase held “Low”. The state of SQWE is cleared by the RES pin, frequencies is in use. Table 3 shows that time bases of 4.194304 SQWE is a read/write bit. MHz, 1.048576 MHz, and 32.768 kHz may be used. The divider selection bits are also used to reset the divider chain. When the OM — The data mode (DM) bit indicates whether time and time/calendar is first initialized, the program may start the calendar updates are to use binary or BCD formats. The DM bit divider at the precise time stored in the RAM. When the divider is written by the processor program and may be read by the rest is removed the frst update cycle begins half a second later. program, but is not modified by any intemal functions or These three read/write bits are never modified by the RTC and A “1” in DM signifies binary data, while a “O" in DM are not affected by RES. specified binary-coded-decimal (BCD) data. RS3, RS2, RSI, RSO — The four rate selection bits select one 24/12 — The 24/12 control bit establishes the format of the of 15 taps on the 22-stage divider, or disable the divider output. hours bytes as either the 24-hour mode (a ‘“1") or the 12-hour The tap selected may be used to generate an output square mode (a “O"). This is a read/write bit, which is affected only wave (SQW pin) and/or a periodic interrupt. The program by the software. may do one of the following: 1) enable the interrupt with the . . PIE bit, 2) enable the SQW output pin with the SQWE bit, 3) OSE — The daylight savings enable (DSE) bit is a read/write enable both at the same time at the same rate, or 4) enable Dit which allows the program to enable two special updates neither. Table 4 lists the periodic interrupt rates and the square- (When DSE is a ““1""). On the last Sunday in April the time wave frequencies that may be chosen with the RS bits. These increments from 1:59:59 AM to 3:00:00 AM. On the last four bits are read/write bits which are not affected by RES and Sunday in October when the time first reaches 1:59:59 AM are never changed by the RTC it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a “0”. DSE is not changed by any internal ‘operations or reset. @HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 1071

© Register c ($C) UF ~ The update-ended interrupt flag (UF) bit is set after each se tse update cycle. When the UIE bit is a “I”, the “I” in UF causes [or [ee [eT TT Tor Yoo] Men Be IROF bit to be a1, asserting IRQ. UF is cleared by a Register Register C read or a a Lunar [er [ar [ur To To fo To | b3 to bO — The unused bits of Status Register C are read as IRQF — The interrupt request flag (IRQF) is set to a1” when “0's”. They can not be written. one or more of the following are true: PF =PIE =“1" © Register D ($00) AP = AIES “1” se ise UF =UIE=“1" Reed Only ie, IRQF = PF - PIE+ AF AIE+ UF - UIE [er [v6 [os To [ea [ez Tor [00 | Reoiner Any time the IRQF bit is a “I”, the TRO pin is driven “Low”. All flag bits are cleared after Register C is read by the program or when the RES pin is low. A program write to VAT — The valid RAM and time (VRT) bit indicates the condi- Register C does not modify any of the flag bits. tion of the contents of the RAM, provided the power sense (PS) pin is satisfactorily connected. AO” appears in the PF — The periodic interrupt flag (PF) is a read-only bit which VRT bit when the powersense pin is “Low”. The processor is set toa “1” when a particular edge is detected on the selected program can set the VRT bit when the time and calendar are tap of the divider chain. The RS3 to RSO bits establish the initialized to indicate that the RAM and time are valid. The periodic rate. PF is set to a “1” independent of the state of the RT is a read/only bit which is not modified by the RES pin. PIE bit. PF being a “1” initiates an IRQ signal and the IRQF The VRT bit can only be set by reading the Register D. For bit when PIE is also a “1”. The PF bit is cleared by a RES or _ setting this bit, PS signal needs to be “High” level. a software read of Register C. b6 to bO ~ The remaining bits of Register D are unused. They AF — AI” in the AF (alarm interrupt flag) bit indicates that Cannot be written, but are always read as “0's” the current time has matched the alarm time. A “I” in the AF causes the IRQ pin to go “Low”, and a“1” to appear in © NOTE FOR USE the IRQF bit, when the AIE bit also is a “1”. A RES or a read Input Signal, which is not necessary for user's application, of Register C clears AF. should be used fixed to “High” or “Low” level. This is appli- cable to the following signal pins. CKFS, PS @ HITACHI 1072 Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

RESTRICTION ON HD146818 USAGE (1) The daylight saving function can not be performed on the HD146818P (X type). So do not use this function for the system design. H0146818P JAPAN < Restriction on usage > Please set “0” to DSE bit (Daylight Saving Enable bit) on initializing the control register B. DSE = “1"'is prohibited. RESTRICTION ON HD146818 USAGE (2) Access to HD146818 needs to be performed under following conditions. (i) Chip-enable (CE) must be asserted to active “Low” level only when MPU performs read/write operation from/into internal RAM (Time and Calendar RAM, Control register, User RAM). {ii) User RAM and control register must be accessed in less than 1/4 frequency shown below. (Example: After one access, non-access cycles more than three cycles are necessary to be inserted.) {example 1) 4 Cycles rind Non-Access Acoms to HO146818 {Example 2] fe eles race Cy COROOOO® Cc . v ‘Accass to HD146818 (Two Continuous Accesses) ‘As shown in the shove [example 2], when HD146816 is accessed continuously, continuous access must ‘ot be executed over fifty tires. {iii) The application that User RAM is used for program area should be avoided. (Inhibit continuous access.) {iv) Minimize the noise by inserting noise bypass condenser between power supply and ground pin (Vcc-Vss)- (insert noise bypass condenser as near HD 146818 as possible.) RESTRICTION ON HD146818 USAGE (3) Chip-enable (CE) must be stable between falling edge of OS and rising edge of AS shown below. (Address decoder hazard needs to be externally suppressed in this period.) AS os c \\O eiminse nated nti period @HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-8300 1073