HD1-6408-9

HD-6408 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Low Bit Error Rate
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encoder, Decoder
• Separate Encode and Decode
• Single Power Supply
• 24 Lead Package

Description

The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder for creating a very high speed asynchronous serial data bus. The Encoder converts serial NRZ data (typically from a shift register) to Manchester II encoded data, adding a sync pulse and parity bit. The Decoder recognizes this sync pulse and identifies it as a Command Sync or a Data Sync. The data is then decoded and shifted out in NRZ code (typically into a shift register). Finally, the parity bit is checked. If there were no Manchester or parity errors the Decoder responds with a valid word signal. The Decoder puts the Manchester code to full use to provide clock recovery and excellent noise immu- nity at these very high speeds. The HD-6408 can be used in many commercial applications such as security systems, environmental control systems, serial data links and many others. It utilizes a single 12 x clock and achieves data rates of up to one million bits per second with a very minimum overhead of only 4 bits out of 20, leaving 16 bits for data. Pinout HD-6408 (DIP) TOP VIEW d

Ordering Information

PACKAGE TEMP. RANGE PART NUMBER PKG. NO. PDIP -40 oC to +85oC HD3-6408-9 E24.6 CERDIP -40 oC to +85oC HD1-6408-9 E24.6 VW ESC TD SDO DC BZI BOI UDI DSC CDS DR GND VCC SCI SD SS EE BOO BZO DBS MR EC SDI OI File Number 2952.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

BIT COUNTER÷ 2 PARITY SYNC DATA ÷ 6 EC SCI ESC SD SS SDI 18 EE

17 BOO

PIN TYPE SYMBOL SECTION DESCRIPTION 1 O VW Decoder Output high indicates receipt of a VALID WORD. 2 O ESC Encoder ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The En- coder samples SDI on the low-to-high transition of ESC.

3 O TD Decoder TAKE DATA output is high during receipt of data after identification of a sync pulse

and two valid Manchester data bits. 4 O SDO Decoder SERIAL DATA OUT delivers received data in correct NRZ format.

5 I DC Decoder DECODER CLOCK input drives the transition finder, and the synchronizer which

in turn supplies the clock to the balance of the Decoder. Input a frequency equal to 12X the data rate.

6 I BZI Decoder A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative

state. This pin must be held high when the Unipolar input is used.

7 I BOI Decoder A high input should be applied to BIPOLAR ONE IN when the bus is in its positive

state, this pin must be held low when the Unipolar input is used.

8 I UDI Decoder With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition

finder circuit. If not used this input must be held low.

9 O DSC Decoder DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ÷ 12),

synchronized by the recovered serial data stream.

10 O CDS Decoder COMMAND/DATA SYNC output high occurs during output of decoded data which

was preceded by a Command synchronizing character. A low output indicates a Data synchronizing character.

11 I DR Decoder A high input to DECODER RESET during a rising edge of DECODER SHIFT

CLOCK resets the decoder bit counting logic to a condition ready for a new word. 12 I GND Both GROUND supply pin.

13 I MR Both A high on MASTER RESET clears the 2:1 counters in both the encoder and decod-

er and the ÷ 6 counter.

14 O DBS Encoder DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER

CLOCK. 15 O BZO Encoder BIPOLAR ZER O OUT is a active low output designed to drive the zero or negative sense of a bipolar line driver. 16 I OI Encoder A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.

17 O BOO Encoder BIPOLAR ONE OUT is an active low output designed to drive the one or positive

sense of a bipolar line driver.

18 I SDI Encoder SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER

SHIFT CLOCK. 19 I EE Encoder A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preced- ing cycle being completed).

20 I SS Encoder SYNC SELECT actuates a Command sync for an input high and data sync for an

input low.

21 O SD Encoder SEND DATA is an active high output which enables the external source of serial

data. 22 I SCI Encoder SEND CLOCK IN is 2X the Encoder data rate. 23 I EC Encoder ENCODER CLOCK is the input to the 6:1 divider.

24 I V

CC Both V CC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24) to GND (pin 12) is recommended. HD-6408

The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SClock input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SClock by dividing the DClock. The Encoder’s cycle begins when EE is high during a falling edge of ESC (1). This cycle lasts for one word length or twenty ESC periods. At the next low-to-high transition of the ESC, a high at SS input actuates a Command sync or a low will produce a Data sync for that word (2). When the Encoder is ready to accept data, the SD output will go high and remain high for sixteen ESC periods (3) - (4). During these sixteen periods the data should be clocked into the SD Input with every high-to-low transition of the ESC (3) - (4). After the sync and Manchester II encoded data are transmitted through the BOO and BZO outputs, the Encoder adds on an additional bit which is the (odd) parity for that word (5). If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (5) as shown to prevent a consecutive word from being encoded. At any time a low on OI will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To Abort the Encoder transmission a positive pulse must be applied at MR. Any time after or during this pulse, a low-to- high transition on SCI clears the internal counters and initial- izes the Encoder for a new word. 1ST HALF 0 1 2 3 4 5 6 7 15 16 17TIMING 1918 3 210101112131415

32101112131415 P2ND HALF

32101112131415 PSYNCSYNC

DON’T CARE DON’T CAREVALID HD-6408

The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DClock input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BOI and BZI inputs will accept data from a differential output comparator. The UDI input can only accept noninverted Manchester II coded data (e.g. from BOO of an Encoder through an inverter to UDI). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized (1), the type of sync is indicated by the CDS output. If the sync character was a command, this out- put will go high (2) and remain high for sixteen DSC periods (3), otherwise it will remain low. The TD output will go high and remain high (2) - (3) while the Decoder is transmitting the decoded data through SDO. The decoded data available at SDO is in a NRZ format. The DSC is provided so that the decoded bits can be shifted into an external register on every low-to-high transition of this clock (2) - (3). Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. After all sixteen decoded bits have been transmitted (3) the data is checked for odd parity. A high on VW output (4) indi- cates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is look- ing for a new sync character to start another output sequence. VALID WORD will go low approximately 20 DECODER SHIFT CLOCK periods after it goes high if not reset low sooner by a valid sync and two valid Manchester bits as shown (1). At any time in the above sequence a high input on DR during a low-to-high transition of DSC will abort transmission and ini- tialize the Decoder to start looking for a new sync character. 2ND HALF1ST HALF 0 1 2 3 4 5 6 7 8 16 17 18 19 SYNC SYNC 15 14 13 12 11 10 14 13 12 11 10 0P21 15 14 13 12 4 3 2 1 0 VW SDO CDS TD BZI BOI DSC TIMING FROM PREVIOUS RECEPTION UNDEFINED 21 3 4 HD-6408

Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical) θJA θJC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS VIH Logical “1” Input Voltage 70% V CC -- V VIL Logical “0” Input Voltage - 20% V CC -V VIHC Logical “1” Input Voltage (Clock) VCC -0.5 - - V VILC Logical “0” Input Voltage (Clock) - GND +0.5 - V II Input Leakage -1.0 - +1.0 µAV IN = VCC or GND, DIP Pins VOH Logical “1” Output Voltage 2.4 - - V I OH = -3mA VOL Logical “0” Output Voltage - - 0.4 V I OL = 1.8mA ICCSB Supply Current Standby - 0.5 2 mA V IN = VCC = 5.5V Outputs Open ICCOP Supply Current Operating (Note 1) - 8.0 10.0 mA V CC = 5.5V, f = 15MHz NOTE: 1. Guaranteed but not 100% tested. SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS ENCODER TIMING (1) F EC Encoder Clock Frequency 0 - 12 MHz C L = 50pF (2) F ESC Send Clock Frequency 0 - 2.0 MHz C L = 50pF (3) T ECR Encoder Clock Rise Time - - 8 ns C L = 50pF (4) T ECF Encoder Clock Fall Time - - 8 ns C L = 50pF (5) F ED Data Rate 0 - 1.0 MHz C L = 50pF (6) T MR Master Reset Pulse Width 150 - - ns C L = 50pF (7) T E1 Shift Clock Delay - - 125 ns C L = 50pF (8) T E2 Serial Data Setup 75 - - ns C L = 50pF (9) T E3 Serial Data Hold 75 - - ns C L = 50pF (10) TE4 Enable Setup 90 - - ns C L = 50pF (11) TE5 Enable Pulse Width 100 - - ns C L = 50pF HD-6408

(12) TE6 Sync Setup 55 - - ns C L = 50pF (13) TE7 Sync Pulse Width 150 - - ns C L = 50pF (14) TE8 Send Data Delay 0 - 50 ns C L = 50pF (15) TE9 Bipolar Output Delay - - 130 ns C L = 50pF (16) TE10 Enable Hold 10 - - ns C L = 50pF (17) TE11 Sync Hold 95 - - ns C L = 50pF DECODER TIMING (18) FDC Decoder Clock Frequency 0 - 12 MHz C L = 50pF (19) TDCR Decoder Clock Rise Time - - 8 ns C L = 50pF (20) TDCF Decoder Clock Fall Time - - 8 ns C L = 50pF (21) FDD Data Rate 0 - 1.0 MHz C L = 50pF (22) TDR Decoder Reset Pulse Width 150 - - ns C L = 50pF (23) TDRS Decoder Reset Setup Time 75 - - ns C L = 50pF (24) TDRH Decoder Reset Hold Time 10 - - ns C L = 50pF (25) TMR Master Reset Pulse Width 150 - - ns C L = 50pF (26) TD1 Bipolar Data Pulse Width T DC +10 - - ns Note 1, C L = 50pF (27) TD2 Sync Transition Span - 18T DC - ns Note 1, C L = 50pF (28) TD3 One Zero Overlap - - T DC -10 ns Note 1, C L = 50pF (29) TD4 Short Data Transition Span - 6T DC - ns Note 1, C L = 50pF (30) TD5 Long Data Transition Span - 12T DC - ns Note 1, C L = 50pF (31) TD6 Sync Delay (ON) -20 - 110 ns C L = 50pF (32) TD7 Take Data Delay (ON) 0 - 110 ns C L = 50pF (33) TD8 Serial Data Out Delay - - 80 ns C L = 50pF (34) TD9 Sync Delay (OFF) 0 - 110 ns C L = 50pF (35) TD10 Take Data Delay (OFF) 0 - 110 ns C L = 50pF (36) TD11 Valid Word Delay 0 - 110 ns C L = 50pF NOTE: 1. TDC = Decoder Clock Period =1/FDC . (These parameters are guaranteed but not 100% tested). Capacitance TA = +25oC SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS C IN Input Capacitance - 15 - pF FREQ = 1MHz, all mea- surements are referenced to device GNDC O Output Capacitance - 15 - pF SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS HD-6408

AC Testing Input, Output Waveform NOTE: AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt. Encoder Timing INPUT VIH 50% VIL 50% VOH VOL SCI VALID (7) TE1 TE3 (9) VALID ESC SDI SC ESC EE SS ESC SD SC BOO OR BZO TE2 (8) (7) TE1 TE10 (16) (10) TE4 (17) TE11 VALID (14) TE8 (15) TE9 (11) TE5 TE7 (13) (12) TE6 HD-6408

BIT PERIOD BIT PERIOD BIT PERIOD TD2 (27) (26) (26) COMMAND SYNC TD2 (27) (28)TD3 TD3 TD2 (28) TD2 (27) (26) (26) (28) (28) (28) (26) (28) (29) (26) (29) TD4 ONEONE ZERO TD1 TD1 TD1 TD3 TD3 (28)TD1 TD1TD1 TD3 TD3 TD3 TD3 TD1 TD4 TD5TD5 TD2TD2 (27) COMMAND SYNC (27) TD2 TD2 (27) (27) TD4 TD5 TD5 TD4 TD4 (29) (29) (29) (30)ZERO ONE ONEONE DATA SYNC (30) BOI BZI BOI BZI BOI BZI UI UI UI (28) (26) (27) TD3 (28) (30) (30) NOTE: UI = 0, FOR NEXT DIAGRAMS NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS HD-6408

Decoder Timing (Continued) (31) TD6 TD7 (32) DSC CDS TD DSC SDO (33) TD8 DATA BIT TD9 (34) (35) TD10 DSC CDS TD VW DSC DR (36) TD11 (22) TDR (23) TDRS (24) TDRH HD-6408

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Decoder Timing (Continued) (31) TD6 TD6 (32) DSC CDS TD DSC SDO (33) TD8 DATA BIT TD8 (34) (35) TD10 DSC CDS TD VW DSC DR (34) TD11 (34) TD11 HD-6408