HD-15531 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • This Circuit is Processed in Accordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
  • Support of MIL-STD-1553
  • Variable Frame Length to 32-Bits
  • Sync Identification and Lock-In
  • Separate Manchester II Encode, Decode

Description

The Intersil HD-15531/883 is a high performance CMOS device intended to service the requirements of MIL-STD- 1553 and similar Manchester II encoded, time division multi- plexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections oper- ate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirements of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identi- fies it as well as decoding the data bits and checking parity. The HD-15531/883 also surpasses the requirements of MIL- STD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531/883 can also be used in many party line digi- tal data communications applications, such as a local area network or an environmental control system driven from a single twisted pair or fiber optic cable throughout a building.

Ordering Information

PACKAGE TEMPERATURE RANGE 1.25MBIT/SEC 2.5MBIT/SEC PKG. NO. CERDIP -55 oC to +125oC HD1-15531/883 HD1-15531B/883 F40.6 File Number 2962.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

HD-15531/883 (CERDIP) TOP VIEW TAKE DATA’ VCC VALID WORD TAKE DATA SERIAL DATA OUT SYNCHR DATA SYNCHR DATA SEL SYNCHR CLK BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLK SYNCHR CLK SEL DECODER CLK TRANSITION SEL NC COMMAND SYNC DECODER PARITY SEL DECODER RESET COUNT C0 COUNT C1 DATA SYNC ENCODER CLK COUNT C4 NC ENCODER SHIFT CLK SEND CLK IN SEND DATA ENCODER PARITY SEL SYNC SEL ENCODER ENABLE SERIAL DATA IN COUNT 2 MASTER RESET GND COUNT C3 ÷ 6 OUT BIPOLAR ONE OUT BIPOLAR ZER O OUT OUTPUT INHIBIT Block Diagrams ENCODER ÷ 2 ÷ 6 VCC BIPOLAR ONE OUT BIPOLAR ZER O OUT SYNC SELECT ENCODER ENABLE ENCODER SHIFT CLK SEND DATA SERIAL DATA IN 34 28 29 31 ENCODER CLK37 GND MASTER RESET SEND CLK IN

6 OUT

Block Diagrams (Continued) BIPOLAR ONE IN BIPOLAR DECODER MASTER

15 SYNCHRONIZER

3 TAKE DATA

7 8SYNCHRONOUS SYNCHRONOUS C0 C1 C2 C3 C4 TRANSITION FINDER DATA SELECT GATE PARITY CHARACTER IDENTIFIER BIT UNIPOLAR DATA IN ZERO IN CLK CLK SELECT CLK CLK SELECT RESET DATA OUT SELECT SHIFT CLK CHECKRATE CLK SELECT DATA DATADATA SELECT HD-15531/883

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. HD-15531/883, HD-15531B/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. TDC = Decoder clock period = 1/FDC.
  2. Interchanging of force and sense conditions is permitted.
  3. Tested as follows: f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH≥ VCC/2 and VOL≤ VCC/2.

TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)

  1. TDC = Decoder Clock Period = 1/FDC.
  2. AC Testing as follows: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing reference levels: VCC/2;

TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) TABLE 3. HD-15531/883, HD-15531B/883 ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major

process and/or design changes.

  1. Guaranteed but not 100% tested.

TABLE 4. APPLICABLE SUBGROUPS

NOTES: 1. VCC = 5.5V±0.5V. 2. VIH = 4.5V±10%. 3. VIL = -0.2V to +0.4V. 4. R = 47kΩ± 5%. VCC A A A A VCC GND VCC FO GND GND A VCC NC A GND GND VCC VCC VCC A FO GND A A VCC GND VCC GND VCC A VCC GND GND R R R R R R R R R R R R R NC R R A VCC GND R R R R R R R R R R HD-15531/883

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 155 x 195 x 19±1mils METALLIZATION: Type: Si-Al Thickness: 11kÅ ±2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 Metallization Mask Layout HD-15531/883 VALID WORD COUNT C1 TAKE DATA’ COUNT C4VCC ENCODER CLK COUNT C3 ENCODER SHIFT CLK SEND CLK IN SEND DATA ENCODER PARITY SEL SYNC SEL ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT OUTPUT INHIBIT COUNTMASTERCOUNT DECODER GND ÷ 6 OUT COMMAND SYNC TRANSITION SEL DECODER SHIFT CLK UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ZERO IN SYNCHR CLK SEL DECODER CLK SYNCHR CLK SYNCHR DATA SEL SYNCHR DATA SERIAL DATA OUT BIPOLAR ZER O OUT 2RESETC0 DECODER PARITY SEL RESET TAKE DATA DATA SYNC HD-15531/883