HD-15531_02 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Support of MIL-STD-1553
- Variable Frame Length to 32 Bits
- Sync Identification and Lock-In
- Separate Manchester II Encode, Decode
Ordering Information
Description
The Intersil HD-15531 is a high performance CMOS device intended to service the requirements of MIL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sec- tions, an Encoder and a Decoder. These sections operate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirements of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identi- fies it as well as decoding the data bits and checking parity. The HD-15531 also surpasses the requirements of MIL- STD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531 can also be used in many party line digital data communications applications, such as a local area net- work or an environmental control system driven from a single twisted pair of fiber optic cable throughout a building. PACKAGE TEMP. RANGE (oC) 1.25MBIT /SEC 2.5MBIT /SEC PKG. NO. PDIP -40 to 85 - HD3-15531B-9 E40.6 CERDIP -40 to 85 HD1-15531-9 HD1-15531B-9 F40.6 -55 to 125 HD1-15531-8 HD1-15531B-8 F40.6 DESC (CERDIP) -55 to 125 5962- 9054901MQA HD1-15531 F40.6 -55 to 125 5962- 9054902MQA HD1-15531B F40.6 FN2961.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HD-15531 (CERDIP, PDIP) TOP VIEW Block Diagrams ENDODER TAKE DATA’ VCC VALID WORD TAKE DATA SERIAL DATA OUT SYNCHR DATA SYNCHR DATA SEL SYNCHR CLK BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLK SYNCHR CLK SEL DECODER CLK TRANSITION SEL NC COMMAND SYNC DECODER PARITY SEL DECODER RESET COUNT C0 COUNT C DATA SYNC ENCODER CLK COUNT C4 NC ENCODER SHIFT CLK SEND CLK IN SEND DATA ENCODER PARITY SEL SYNC SEL ENCODER ENABLE SERIAL DATA IN COUNT C2 MASTER RESET GND COUNT C3 ÷ 6 OUT BIPOLAR ONE OUT BIPOLAR ZERO OUT OUTPUT INHIBIT ÷ 2 ÷ 6 VCC BIPOLAR ONE OUT BIPOLAR ZERO OUT SYNC SELECT ENCODER ENABLE ENCODER SHIFT CLK SEND DATA SERIAL DATA IN 34 28 29 31 ENCODER CLK37 GND MASTER RESET SEND CLK IN ÷ 6 OUT OUTPUT INHIBIT CHARACTER BIT COUNTER ENCODER PARITY SELECT 20 40 23 36 39 C0 C1 C2 C3 C4 FORMER HD-15531
NUMBER TYPE NAME SECTION DESCRIPTION 1V CC Both Positive supply pin. A 0.1 µF decoupling capacitor from VCC (pin 1) to GROUND (pin 21) is recommended.
2 O VALID WORD Decoder Output high indicates receipt of a valid word, (valid parity and no Manchester
errors). 3 O TAKE DATA’ Decoder A continuous, free running signal provided for host timing or data handling. When data is present on the bus, this signal will be synchronized to the incoming data and will be identical to TAKE DATA. 4 O TAKE DATA Decoder Output is high during receipt of data after identification of a valid sync pulse and two valid Manchester bits. 5 O SERIAL DATA OUT Decoder Delivers received data in correct NRZ format.
6 I SYNCHRONOUS
Decoder Input presents Manchester data directly to character identification logic. SYNCHRONOUS DATA SELECT must be held high to use this input. If not used, this pin must be held high.
7 I SYNCHRONOUS
Decoder In high state allows the synchronous data to enter the character identification logic. Tie this input low for asynchronous data.
8 I SYNCHRONOUS
Decoder Input provides externally synchronized clock to the decoder, for use when re- ceiving synchronous data. This input must be tied high when not in use. 9 I DECODER CLOCK Decoder Input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the decoder. Input a frequency equal to 12X the data rate.
10 I SYNCHRONOUS
Decoder In high state directs the SYNCHRONOUS CLOCK to control the decoder char- acter identification logic. A low state selects the DECODER CLOCK. 11 I BIPOLAR ZERO IN Decoder A high input should be applied when the bus is in its negative state. This pin must be held high when the unipolar input is used. 12 I BIPOLAR ONE IN Decoder A high input should be applied when the bus is in its positive state. This pin must he held low when the unipolar input is used. 13 I UNIPOLAR DATA IN Decoder With pin 11 high and pin 12 low, this pin enters unipolar data into the transition finder circuit. If not used this input must be held low. BIPOLAR ONE IN BIPOLAR DECODER MASTER
15 SYNCHRONIZER
3 TAKE DATA’
7 8SYNCHRONOUS SYNCHRONOUS C0 C1 C2 C3 C4 TRANSITION FINDER DATA SELECT GATE PARITY CHARACTER IDENTIFIER BIT UNIPOLAR DATA IN ONE IN CLK CLK SELECT CLK CLK SELECT RESET DATA OUT SELECT SHIFT CLK CHECKRATE CLK SELECT DATA DATADATA SELECT HD-15531
14 O DECODER SHIFT
Decoder Output which delivers a frequency (DECODER CLOCK + 1 2), synchronous by the recovered serial data stream.
15 I TRANSITION SE-
Decoder A high input to this pin causes the transition finder to synchronize on every tran- sition of input data. A low input causes the transition finder to synchronize only on mid-bit transitions. 16 NC Blank Not connected.
17 O COMMAND SYNC Decoder Output of a high from this pin occurs during output of decoded data which was
preceded by a Command (or Status) synchronizing character.
18 I DECODER PARITY
Decoder An input for parity sense, calling for even parity with input high and odd parity with input low.
19 I DECODER RESET Decoder A high input to this pin during a rising edge of DECODER SHIFT CLOCK resets
the decoder bit counting logic to a condition ready for a new word.
20 I COUNT C0 Both One of five binary inputs which establish the total bit count to be encoded or de-
coded. 21 GROUND Both Supply pin.
22 I MASTER RESET Both A high on this pin clears 2:1 counters in both encoder and decoder, and resets
the ÷ 6 circuit. 23 I COUNT C2 Both See pin 20. 24 O ÷ 6 OUT Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.
25 O BIPOLAR ZERO
Encoder An active low output designed to drive the zero or negative sense of a bipolar line driver. 26 I OUTPUT INHIBIT Encoder A low on this pin forces pin 25 and 27 high, the inactive states. 27 O BIPOLAR ONE OUT Encoder An active low output designed to drive the one or positive sense of a bipolar line driver. 28 I SERIAL DATA IN Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. 29 I ENCODER ENABLE Encoder A high on this pin initiates the encode cycle. (Subject to the preceding cycle be- ing complete). 30 I SYNC SELECT Encoder Actuates a Command sync for an input high and Data sync for an input low.
31 I ENCODER PARITY
Encoder Sets transmit parity odd for a high input, even for a low input. 32 O SEND DATA Encoder Is an active high output which enables the external source of serial data. 33 I SEND CLOCK IN Encoder Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6 output.
34 O ENCODER SHIFT
Encoder Output for shifting data into the Encoder. The Encoder samples SDI pin-28 on the low-to-high transition of ESC. 35 NC Blank Not connected. 36 I COUNT C3 Both See pin 20. 37 I ENCODER CLOCK Encoder Input to the 6:1 divider, a frequency equal to 12 times the data rate is usually input here.
38 O DATA SYNC Decoder Output of a high from this pin occurs during output of decoded data which was
preceded by a data synchronizing character. 39 I COUNT C4 Both See pin 20. 40 I COUNT C1 Both See pill 20. Pin Description (Continued) PIN NUMBER TYPE NAME SECTION DESCRIPTION HD-15531
high during a falling edge of ENCODER SHIFT CLOCK . words will be encoded without an interframe gap. internal counters and initializes the Encoder for a new word.
- The UNIPOLAR DATA input can only accept nonin-
FIGURE 1. ENCODER
time that TAKE DATA goes high. valid Manchester bits as shown . tialize the Decoder to start looking for a new sync character.
012345678 N - 3 N - 2 N - 1 N
FIGURE 2. DECODER
(BIT PERIODS) PIN WORD C4 C3 C2 C1 C0
26 L L H L H
37 L L H H L
NOTE: 1. The above table demonstrates all possible combinations of frame lengths ranging from 6 to 32 bits. The pin word described her e is com- mon to both the Encoder and Decoder. HD-15531
Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range (TA) Thermal Resistance (Typical) θJA θJC Maximum Junction Temperature Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. TA = -55oC to +125Co (HD-15531-8) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input LOW Voltage V IL VCC = 4.5V and 5.5V - 0.2 V CC V Input HIGH Voltage V IH VCC = 4.5V and 5.5V 0.7 V CC -V Input LOW Clock Voltage V ILC VCC = 4.5V and 5.5V - GND +0.5 V Input HIGH Clock Voltage V IHC VCC = 4.5V and 5.5V V CC -0.5 - V Output LOW Voltage V OL IOL = +1.8mA, VCC = 4.5V (Note 2) - 0.4 V Output HIGH Voltage V OH IOH = -3.0mA, VCC = 4.5V (Note 2) 2.4 - V Input Leakage Current I I VI = VCC or GND, VCC = 5.5V -1.0 +1.0 µA Standby Supply Current I CCSB VIN = VCC = 5.5V, Outputs Open -2 m A Operating Power Supply Current ICCOP V IN = VCC = 5.5V, f = 15MHz, Outputs Open -1 0 m A Functional Test F T (Note 3) - - - NOTES: 1. TDC = Decoder clock period = 1/FDC. 2. Interchanging of force and sense conditions is permitted. 3. Tested as follows: f = 15MHz, V IH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH ≥ VCC/2 and VOL ≤ VCC/2. Capacitance TA = +25oC, Frequency = 1MHz SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 25 pF All measurements are referenced to device GND COUT Output Capacitance 25 pF HD-15531
TA = -55oC to +125oC (HD-15530-8) SYMBOL PARAMETER HD-15531 HD-15531B UNITS TEST CONDITIONS (NOTE 2)MIN MAX MIN MAX ENCODER TIMING FEC Encoder Clock Frequency - 15 - 30 MHz V CC = 4.5V and 5.5V, CL = 50pF FESC Send Clock Frequency - 2.5 - 5.0 MHz V CC = 4.5V and 5.5V, CL = 50pF FED Encoder Data Rate - 1.25 - 2.5 MHz V CC = 4.5V and 5.5V, CL = 50pF TMR Master Reset Pulse Width 150 - 150 - ns V CC = 4.5V and 5.5V, CL = 50pF TE1 Shift Clock Delay - 125 - 80 ns V CC = 4.5V and 5.5V, CL = 50pF TE2 Serial Data Setup 75 - 50 - ns V CC = 4.5V and 5.5V, CL = 50pF TE3 Serial Data Hold 75 - 50 - ns V CC = 4.5V and 5.5V, CL = 50pF TE4 Enable Setup 90 - 90 - ns V CC = 4.5V and 5.5V, CL = 50pF TE5 Enable Pulse Width 100 - 100 - ns V CC = 4.5V and 5.5V, CL = 50pF TE6 Sync Setup 55 - 55 - ns V CC = 4.5V and 5.5V, CL = 50pF TE7 Sync Pulse Width 150 - 150 - ns V CC = 4.5V and 5.5V, CL = 50pF TE8 Send Data Delay 0 50 0 50 ns V CC = 4.5V and 5.5V, CL = 50pF TE9 Bipolar Output Delay - 130 - 130 ns V CC = 4.5V and 5.5V, CL = 50pF TE10 Enable Hold 10 - 10 - ns V CC = 4.5V and 5.5V, CL = 50pF TE11 Sync Hold 95 - 95 - ns V CC = 4.5V and 5.5V, CL = 50pF DECODER TIMING FDC Decoder Clock Frequency - 15 - 30 MHz V CC = 4.5V and 5.5V, CL = 50pF FDS Decoder Sync Clock - 2.5 - 5.0 MHz V CC = 4.5V and 5.5V, CL = 50pF FDD Decoder Data Rate - 1.25 - 2.5 MHz V CC = 4.5V and 5.5V, CL = 50pF TDR Decoder Reset Pulse Width 150 - 150 - ns V CC = 4.5V and 5.5V, CL = 50pF TDRS Decoder Reset Setup Time 75 - 75 - ns V CC = 4.5V and 5.5V, CL = 50pF TDRH Decoder Reset Hold Time 10 - 10 - ns V CC = 4.5V and 5.5V, CL = 50pF TMR Master Reset Pulse 150 - 150 - ns V CC = 4.5V and 5.5V, CL = 50pF TD1 Bipolar Data Pulse Width TDC + 10 (Note 1) - TDC + 10 (Note 1) -n s V CC = 4.5V and 5.5V, CL = 50pF TD3 One Zero Overlap - TDC - 10 (Note 1) - TDC - 10 (Note 1) ns V CC = 4.5V and 5.5V, CL = 50pF TD6 Sync Delay (ON) -20 110 -20 110 ns V CC = 4.5V and 5.5V, CL = 50pF TD7 Take Data Delay (ON) 0 110 0 110 ns V CC = 4.5V and 5.5V, CL = 50pF TD8 Serial Data Out Delay - 80 - 80 ns V CC = 4.5V and 5.5V, CL = 50pF TD9 Sync Delay (OFF) 0 110 0 110 ns V CC = 4.5V and 5.5V, CL = 50pF TD10 Take Data Delay (OFF) 0 110 0 110 ns V CC = 4.5V and 5.5V, CL = 50pF TD11 Valid Word Delay 0 110 0 110 ns V CC = 4.5V and 5.5V, CL = 50pF TD12 Sync Clock to Shift Clock Delay -7 5-7 5 n s V CC = 4.5V and 5.5V, CL = 50pF TD13 Sync Data Setup 75 - 75 - ns V CC = 4.5V and 5.5V, CL = 50pF NOTES: 1. TDC = Decoder clock period = 1/FDC. 2. AC Testing as follows: Input levels: V IH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference levels: VCC/2; Output load: CL = 50pF. HD-15531
FIGURE 10. ENCODER TIMING
FIGURE 11. DECODER TIMING NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS. NOTE: BIPOLAR ONE IN = 0, BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.
FIGURE 12. DECODER TIMINGS
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TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 Test Load Circuit NOTE: 1. Includes stray and jig capacitance. AC Testing Input, Output Waveform NOTE: 1. AC Testing: All input signals must switch between V IL and VIH, input rise and fall times are driven at 1ns per volt. DUT CL (NOTE 1) FIGURE 13. INPUT 50% 50% OUTPUT VOL VOHVIH VIL FIGURE 14. HD-15531