HCTS161AMS RENESAS | Alldatasheet
Document overview
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- PDF pages: 9
Technical content
Features
- 3 Micron Radiation Hardened CMOS SOS
- Total Dose 200K RAD (Si)
- Minimum LET for SEU Upsets: >100 MEV-cm 2/mg
- Single Event Upset (SEU) Immunity < 2 x 10 -9 Errors/ Bit-Day (Typ)
- Dose Rate Survivability: >1 x 1012 RAD (Si)/s
- Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
- Latch-Up Free Under Any Conditions
- Military Temperature Range: -55 oC to +125oC
- Significant Power Reduction Compared to LSTTL ICs
- DC Operating Voltage Range: 4.5V to 5.5V
- Input Logic Levels -VIL = 0.8V Max -VIH = VCC/2V Min
- Input Current Levels Ii 5A at VOL, VOH
Description
The Intersil HCTS161AMS high-reliability high-speed preset- table four-bit binary synchronous counter features asynchro- nous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR . A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (P0 - P3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCTS161AMS has two count enable pins, PE and TE. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count. The HCTS161AMS utilizes advanced CMOS/SOS technol- ogy to achieve high-speed operation. This device is a mem- ber of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS161AMS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW CP GND PE TE TC MR VCC SPE 11 6 CP GND PE MR TE TC VCC SPE
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCTS161ADMSR -55 oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP HCTS161AKMSR -55 oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack HCTS161AD/Sample +25 oC Sample 16 Lead SBDIP HCTS161AK/Sample +25 oC Sample 16 Lead Ceramic Flatpack HCTS161AHMSR +25 oCD i e D i e
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages reference to device GND.
- Force/measure functions may be interchanged.
- For functional tests VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
- The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- For functional tests VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) TABLE 6. APPLICABLE SUBGROUPS
- Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
- Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
- Each pin except VCC and GND will have a resistor of 10k 5% for static burn-in
- Each pin except VCC and GND will have a resistor of 1k 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS NOTE: Each pin except VCC and GN D will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
FN2144 Rev 2.00 Page 7 of 9 September 1995 HCTS161AMS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents:
- Cover Sheet (Intersil Name and/or Logo, P .O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
- Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
- GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
- X-Ray report and film. Includes penetrometer measurements.
- Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
- Lot Serial Number Sheet (Good units serial number and lot number).
- Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
- The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
FN2144 Rev 2.00 Page 8 of 9 September 1995 Propagation Delay Timing Diagram Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger Propagation Delay Load Circuit AC Load Circuit AC VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V GND 0 V VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V GND 0 V VS INPUT OUTPUT VIH VSS VOH VOL TPLH TPHL VS TW TH VS TSU INPUT VIH VIL INPUT CP VIH VIL TW VS TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH DUT TEST CL RL POINT CL = 50pF RL = 500 DUT TEST CL RL POINT CL = 50pF RL = 500
FN2144 Rev 2.00 Page 9 of 9 September 1995 Die Characteristics DIE DIMENSIONS: 86 x 104mils 2.19 x 2.65mm METALLIZATION: Type: AlSi Metal Thickness: 11kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ 2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 x 4 mils Metallization Mask Layout HCTS161AMS NOTE: The die diagram is a generic plot form a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS161A is TA14446A. CP MR VCC P0 (3) P1 (4) P2 (5) P3 (6) (9) (10) (11) Q3 (12) Q2 (13) Q1 (2) (1) (16) SPE TE (8) GND (14) Q0 PE (7) (15) TC