HCTS14MS RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • 3 Micron Radiation Hardened SOS CMOS
  • Total Dose 200K RAD (Si)
  • SEP Effective LET No Upsets: >100 MEV-cm 2/mg
  • Single Event Upset (SEU) Immunity < 2 x 10 -9 Errors/ Bit-Day (Typ)
  • Dose Rate Survivability: >1 x 1012 RAD (Si)/s
  • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
  • Cosmic Ray Upset Rate 2 x 10-9 Errors/Bit Day
  • Latch-Up Free Under Any Conditions
  • Military Temperature Range: -55 oC to +125oC
  • Significant Power Reduction Compared to LSTTL ICs
  • DC Operating Voltage Range: 4.5V to 5.5V
  • Input Current Levels Ii  5A at VOL, VOH

Description

The Intersil HCTS14MS is a Radiation Hardened HEX Inverting Schmitt trigger. A high on any input forces the out- put to a Low state. The HCTS14MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS14MS is supplied in a 14 lead Ceramic flatpack Package (K suffix) or a 14 lead SBDIP Package (D suffix). Pinouts

14 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14 TOP VIEW

14 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14 TOP VIEW Functional Diagram

Ordering Information

HCTS14DMSR -55 oC to +125oC Intersil Class S Equivalent

14 Lead SBDIP

HCTS14KMSR -55 oC to +125oC Intersil Class S Equivalent

14 Lead Ceramic

+25oC Sample 14 Lead SBDIP HCTS14K/ Sample +25oC Sample 14 Lead Ceramic Flatpack HCTS14HMSR +25 oCD i e D i e TRUTH TABLE INPUTS An OUTPUTS Yn LH HL NOTE: L = Logic Level Low, H = Logic level High GND VCC 1A1 GND VCC YnAn DB NA NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at1-888-INTERSIL or www.intersil.com/tsc

under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages reference to device GND.
  2. For functional tests, VO  4.0V is recognized as a logic “1”, and VO  0.5V is recognized as a logic “0”.

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly

tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
  3. For functional tests, VO  4.0V is recognized as a logic “1”, and VO  0.5V is recognized as a logic “0”.

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) TABLE 6. APPLICABLE SUBGROUPS

  1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised.

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

TABLE 7. TOTAL DOSE IRRADIATION

  1. Except FN test which will be performed 100% Go/No-Go.

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS

  1. Each pin except VCC and GND will have a resistor of 10k  5% for static burn-in.
  2. Each pin except VCC and GND will have a resistor of 1k  5% for dynamic burn-in.

TABLE 9. IRRADIATION TEST CONNECTIONS NOTE: Each pin except VCC and GN D will have a resistor of 47k  5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.

FN3205 Rev 2.00 Page 6 of 8 March 2007 Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019,

4 Samples/Wafer, 0 Rejects

100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C,

10 Cycles

100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1 and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents:

  • Cover Sheet (Intersil Name and/or Logo, P .O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
  • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
  • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
  • X-Ray report and film. Includes penetrometer measurements.
  • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
  • Lot Serial Number Sheet (Good units serial number and lot number).
  • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
  • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.

FN3205 Rev 2.00 Page 8 of 8 March 2007 Die Characteristics DIE DIMENSIONS: 87 x 88 mils 2,20 x 2.24mm METALLIZATION: Type: AlSi Metal Thickness: 11kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ  2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 x 4 mils Metallization Mask Layout HCTS14MS NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS14 is TA14443A. A1 VCC A6 Y1 (2) A2 (3) Y2 (4) A3 (5) (6) (7) (8) (9) A4 (10) Y5 (11) A5 (12) Y6 (1) Y3 GND Y4 (14) (13)