HTCS138MS INTERSIL | Alldatasheet
Document overview
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- PDF pages: 9
Technical content
Features
- 3 Micron Radiation Hardened SOS CMOS
- Total Dose 200K RAD (Si)
- SEP Effective LET No Upsets: >100 MEV-cm2/mg
- Single Event Upset (SEU) Immunity < 2 x 10 -9 Errors/Bit- Day (Typ)
- Latch-Up Free Under Any Conditions
- Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads
- Military Temperature Range: -55 oC to +125oC
- Significant Power Reduction Compared to LSTTL ICs
- DC Operating Voltage Range: 4.5V to 5.5V
- LSTTL Input Compatibility - VIL = 0.8V Max -V I H = V C C / 2 M i n
- Input Current Levels Ii ≤ 5µA at VOL, VOH GND VCC GND VCC 11 6
Ordering Information
+125oC Intersil Class S Equivalent
16 Lead SBDIP
+125oC Intersil Class S Equivalent
16 Lead Ceramic
HCTS138HMSR +25 oCD i e D i e HCTS138MS Data Sheet FN2462.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1995, 1999, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. September 12, 2005
2 FN2462.3 September 12, 2005 HCTS138MS Functional Diagram TRUTH TABLE INPUTS OUTPUTSENABLE E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 XXHXXXHHHHHHHH LXXXXXHHHHHHHH XHXXXXHHHHHHHH HL L L L L LHHHHHHH HL L L LHHLHHHHHH HL L LHLHHLHHHHH HL L LHHHHHLHHHH HL LHL LHHHHLHHH HL LHLHHHHHHLHH HL LHHLHHHHHHLH HL LHHHHHHHHHHL H = High Level, L = Low Level, X = Don’t Care
cal Performance Characteristics” are the only conditions recommended for satisfactory device operation.. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages reference to device GND.
- For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500 Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
- The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested.
These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500 Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
- For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 TABLE 6. APPLICABLE SUBGROUPS
- Alternate group A inspection in accordance with method 5005 of MIL-STD-883 may be exercised.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
TABLE 7. TOTAL DOSE IRRADIATION
- Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
- Each pin except VCC and GND will have a resistor of 10K Ω ± 5% for static burn-in
- Each pin except VCC and GND will have a resistor of 680 Ω ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS NOTE: Each pin except VCC and GN D will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
7 FN2462.3 September 12, 2005 Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents:
- Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
- Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
- GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
- X-Ray report and film. Includes penetrometer measurements.
- Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
- Lot Serial Number Sheet (Good units serial number and lot number).
- Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
- The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS138MS
8 FN2462.3 September 12, 2005 AC Timing Diagrams AC Load Circuit AC VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V GND 0 V VS INPUT OUTPUT OUTPUT TTHL 80% 20% 80% 20% VIH VIL VOH VOL VOH VOL TPLH TPHL VS TTLH DUT TEST CL RL POINT CL = 50pF RL = 500Ω HCTS138MS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2462.3 September 12, 2005 HCTS138MS Die Characteristics DIE DIMENSIONS: 85 x 101 mils METALLIZATION: Type: SiAl Metal Thickness: 11k Å ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ ± 2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100µm x 100µm 4 x 4 mils Metallization Mask Layout HCTS138MS NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS138 is TA14461A. A1 A0 VCC A2 (3) E1 (4) E2 (5) E3 (6) (8) (9) (10) (11) Y4 (12) Y3 (13) Y2 (14) Y1 (2) (1) (16) GND Y6 Y5 (7) (15) NC NC NC NC