HCTL-2032 HP | Alldatasheet
Document overview
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Technical content
Features
- Interfaces Encoder to Microprocessor 33 MHz Clock Operation Programmable Count Modes (1x, 2x or 4x) Single or Dual Axis Support Index Channel Support High Noise Immunity: Schmitt Trigger Inputs and Digital Noise Filter 32-Bit Binary Up/Down Counter Latched Outputs 8-Bit Tristate Interface 8, 16, 24, or 32-Bit Operating Modes Quadrature Decoder Output Signals, Up/Down and Count Cascade Output Signals, Up/Down and Count Substantially Reduced System Software
- 5V Operation (V DD − VSS) TTL/CMOS Compatible I/O Operating Temperature: -40°C to 100°C 32-Pin PDIP, 32-Pin SOIC, 20-Pin PDIP
Applications
Interface Quadrature Incremental Encoders to Microprocessors Interface Digital Potentiometers to Digital Data Input Buses Agilent HCTL-2032, HCTL-2032-SC, HCTL-2022 Quadrature Decoder/Counter Interface ICs Data Sheet ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL- 2032 family ICs.
Package Dimensions (dimension in inches) 1) HCTL-2032 Part Number Description Package Drawing HCTL-2032 32-bit counter, dual axis, decoder an d cascade outputs, index channel support, programmable count modes, and 33 Mhz clock operation. A HCTL-2032-SC All features of HCTL-2032. B HCTL-2022 Most of the HCTL-2032 features. Th e device supports single axis, and no decoder output and cascade signals. The programmable count mode is set to 4x internally. C PINOUT A PINOUT B PINOUT C HCTL-2032 VDD EN1 EN2 CLK SEL1 OE U/DX U/DY RSTY RSTX CHBY CHBX CHAX CHAY X/Y CNTDECX CNTDECY SEL2 CNTCASX CNTCASY TEST CHIY VSS CHIX HCTL-2032-SC VDD EN1 EN2 CLK SEL1 OE U/DX U/DY RSTY RSTX CHBY CHBX CHAX CHAY X/Y CNTDECX CNTDECY SEL2 CNTCASX CNTCASY TEST CHIY VSS CHIX HCTL-2022 VDD CLK SEL1 OE U/D RST CHA CHB SEL2 TEST INDEX VSS
ii) HCTL-2032-SC 3) HCTL-2022
Table 1. Absolute Maximum Ratings Table 2. Recommended Operating Conditions Table 3. DC Characteristics VDD = 5V ± 5%; TA = -40 to 100°C
- In general, for any V DD between the allowable limits (+4.5V to +5.5V), VIL = 0.3VDD and
- Including package capacitance
Table 4. Functional Pin Descriptions. CLK 5 3 CLK is a Schmitt-trigger input for the external clock signal. are the 1st axis and CHAY and CHBY are the 2nd axis. from an incremental optical shaft encoder. to reset the 2nd axis counter. control the loading of the internal position data latch. control the internal inhibit logic. bit enables the 2nd axis data. rising edge of the CNTDEC and CNTCAS outputs.
A pulse is presented on this LSTTL-compatible output when the HCTL-2032 / 2032-SC internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter. TEST 23 16 This pin is used for internal testing. Tied it to ground or leave it floating for normal operation. D0 4 2 These LSTTL-compatible tri-state outputs form an 8-bit output ports through which the contents of the 32-bit position latch may be read in 4 sequential bytes. The MSB is read first followed by the rest of the bytes with the LSB is read last. D1 31 20 D2 30 19 D3 29 18 D4 22 15 D5 21 14 D6 20 13 D7 10 7
Table 5. Switching Characteristics
- tclk − max delay (item 20/21) + min delay (item 22/23)
- tclk − max delay (item 22/23) + min delay (item 20/21)
Figure 10. The operation of Figure 10. Simplified Logic Diagram
32 Bits Binary
32 Bits Latch Octal 4 bit
provide better system control. Figure 12. Signal Propagation through Digital Noise Filter
4 Valid State
inhibit logic, enabling the latch. affected by the inhibit logic. of count and up/down outputs. Figure 15. Four Bytes Read Sequence
1 L H L 1 Set inhibit; Read MSB
2 H H L 1 Read 2nd Byte
3 L L L 1 Read 3rd Byte
4 H L L 1 Read LSB
5 X X H 0 Completes inhibit logic reset
the rising clock edge (t CHD). external counters and registers. external counter and is not lost. Figure 16. Decode and Cascade Output Diagram (4x)
the program that interfaces with an Atmel AVR 90S8535. Figure 17. An HCTL-2032-to-Atmel AVR Interface
Figure 18. Typical Program for Reading HCTL-2032 with Atmel AVR
Figure 18 Cont. Typical Program for Reading HCTL-2032 with Atmel AVR ACTIONS 1. At first, Port B4, B5, and B6 are setu p for 4X encoding and X/Y axis selection. 2. The HCTL-2032 detects that OE/ are low on the next falling edge of the CLK and asserts the internal inhibit signal. Data can be read without regard for the phase of the CLK. 3. SEL1 and SEL2 are setup to select the a ppropriate bytes. The "Get_hi" subroutine is called and the data is read into the AVR. 4. Step 3 is repeated by changing the SEL1 and SEL2 combinations and specific subroutine is called to read in the appropriate data. 5. The HCTL-2032 detects OE/ high on the next falling edge of the CLK. The program set OE/ high by writing the correct value to the respective Port. This causes the data lines to be tristated. On the next rising CLK edge new data is transferred from the counter to the position data latch. 6. For displaying purposes, the data is ar ranged in 32-bit data by shifting the MSB to the left through multiplication. Get_2nd: 2nd_old = Pina 'Get current data 2nd_new = Pina 'Get 2nd Data If 2nd_new = 2nd_old Then Result_2nd = 2nd_new 'Get stable data Return Else Goto Get_2nd End If Get_3rd: 3rd_old = Pina 'Get current data 3rd_new = Pina 'Get 2nd Data If 3rd_new = 3rd_old Then Result_3rd = 3rd_new 'Get stable data Return Else Goto Get_3rd End If Get_lo: Lo_old = Pina 'Get current data Lo_new = Pina 'Get 2nd Data If Lo_new = Lo_old Then Result_lo = Lo_new 'Get stable data Return Else Goto Get_lo End If
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