HCTL-2000 HP | Alldatasheet
Document overview
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Technical content
Features
- Interfaces Encoder to Microprocessor
- 14 MHz Clock Operation
- Full 4X Decode
- High Noise Immunity: Schmitt Trigger Inputs Digital Noise Filter
- 12 or 16-Bit Binary Up/ Down Counter
- Latched Outputs
- 8-Bit Tristate Interface
- 8, 12, or 16-Bit Operating Modes
- Quadrature Decoder Output Signals, Up/Down and Count
- Cascade Output Signals, Up/ Down and Count
- Substantially Reduced System Software ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX family ICs. Devices Part Number Description Package Drawing HCTL-2000 12-bit counter. 14 MHz clock operation. A HCTL-2016 All features of the HCTL-2000. 16-bit counter. A HCTL-2020 All features of the HCTL-2016. Quadrature decoder output B signals. Cascade output signals.
Description
The HCTL-2000, 2016, 2020 are CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-20XX family is designed to improve system performance
Applications
- Interface Quadrature Incremental Encoders to Microprocessors
- Interface Digital Potentiom- eters to Digital Data Input Buses 5965-5894E
Table 1. Absolute Maximum Ratings Table 2. Recommended Operating Conditions
Table 4. Functional Pin Descriptions CLK 2 2 CLK is a Schmitt-trigger input for the external clock signal. asynchronous with respect to any other input signals. SEL also controls the internal inhibit logic.
0 High
1 Low
quadrature decoder has detected a state transition. on this waveform may be used to trigger an external counter. NC 6 Not connected - this pin should be left floating. HCTL-2000, the most significant 4 bits of this byte are set to 0 internally). The lower byte, bits 0-7, is read second.
Table 5. Switching Characteristics Min/Max specifications at VDD = 5.0 ± 5%, TA = -40 to + 85°C.
- tCD specification and waveform assume latch not inhibited.
- tSS, tOS, tSH, tOH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup
and hold times do not need to be observed. Figure 3. Tri-State Output Timing.
interpolate within the cycle. case counter rollover occurs.
- The IC can be put in 8-bit
Figure 9. 4x Quadrature Decoding.
output bus is in the high-Z state.
2020 Only)
of count and up/down outputs. Figure 11. Simplified Inhibit Logic.
1 L L 1 Set inhibit; read high byte
2 H L 1 Read low byte; starts reset
3 X H 0 Completes inhibit logic reset
Figure 10. Two Byte Read Sequence.
after the rising clock edge (t CHD). external counters and registers. a cascade pulse will be generated.
- The external latch should
Figure 12. Decode and Cascade Output Diagram. OF THE DIGITAL NOISE FILTER (SEE FIGURES 7 AND 8).
low on OE during a falling clock edge. 6. When OE goes high, the data lines change to a high imped- ance state. 7. The IC detects a logic high on OE during a falling clock edge. This satisfies the second reset condition for the inhibit logic. Actions 1. On the rising edge of the clock, counter data is transferred to the position data latch, provided the inhibit signal is low. 2. When OE goes low, the outputs of the multiplexer are enabled onto the data lines. If SEL is low, then the high order data bytes are enabled onto the data lines. If SEL is high, then the low order data bytes are enabled onto the data lines. 3. When the IC detects a low on OE and SEL during a falling clock edge, the internal inhibit signal is activated. This blocks new data from being transferred from the counter to the position data latch. 4. When SEL goes high, the data outputs change from the high byte to the low byte. 5. The first of two reset condi- tions for the inhibit logic is met when the IC detects a logic high on SEL and a logic
Figure 14. A Circuit to Interface to the 6802/8.
made to locations 4XXX or 2XXX. clock E enables the 74LS138. used to clock the HCTL-2020.
- This line selects the low or
connected for easy expansion. interface timing for the circuit. Figure 15. Memory Addresses and Read Example.
- With the first negative edge
- OE goes high and the data
- OE is low and SEL is high
- With the first negative edge
- The data bus returns to the
- With the first negative edge
- With the positive going edge
Figure 16. Interface Timing for the 6802/8.
Figure 17. An HCTL-20XX-to-Intel 8748 Interface.
- NOTE: PIN NUMBERS ARE DIFFERENT FOR THE HCTL-2020.
003 A8 MOVE R0, A Move data to register 0
008 A9 MOV R1, A Move data to register 1
Figure 18. A Typical Program for Reading HCTL-20XX with an 8748.
- ANL P1, 00H has just been
- The HCTL-20XX detects that
bits are read into the 8748.
- ORL P1, 03H has just been
Figure 19. 8748 READ Cycle from Figure 18.