HCT652

74HC652 PHILIPS | Alldatasheet

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Technical content

Product specification File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HC/HCT652 Octal bus transceiver/register; 3-state For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652

FEATURES

• Multiplexed real-time and stored data
• Independent register for A and B buses
• Independent enables for A and B buses
• 3-state
• Output capability: Bus driver
• Low power consumption by CMOS technology
• ICC category: MSI.

APPLICATIONS

• Bus interfaces.

DESCRIPTION

The 74HC/HCT652 are high-speed SI-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with Jedec standard no. 7A. The 74HC/HCT652 consist of 8 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and central circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the “A” or “B” or both buses, will be stored in the internal registers, at the appropriate clock pins (CP AB or CP BA ) regardless of the select pins (SAB and SBA ) or output enable (OEAB and OE BA ) control pins. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the output enable pins this operating mode permits. The output enable pins OE AB and OE BA determine the operation mode of the transceiver. When OE AB is LOW, no data transmission from An to Bn is possible and whenOE BA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OE AB and OE BA . In this configuration each output reinforces its input. Thus when all other data sources to the two sets of bus lines are at high-impedance, each set of the bus lines will remain at its last state. This type differs from the HC/HCT646 in one extra bus-management function. This is the possibility to transfer stored “A data to the “B” bus and transfer stored ”B” data to the ”A” bus at the same time. The examples at the application information demonstrate all bus management functions. Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; T amb =2 5°C; tr =tf= 6 ns; VCC = 4.5 V; CL = 50 pF. Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi+ ∑ (CL × VCC 2 ×fo) where: fi= input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; ∑ (CL × VCC 2 × fo) = sum of the outputs 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPLH /tPZL propagation delay An/Bn to Bn /An C L = 15 pF; VCC =5 V 13 13 ns propagation delay CPAB /CPBA to Bn /An 18 20 ns propagation delay SAB /SBA to Bn /An 20 23 ns tPHZ /tPZL 3-state output enable time OEAB /OE BA to Bn/An 14 15 ns tPHZ /tPLZ 3-state output disable time OEAB /OE BA to Bn/An 12 13 ns fmax maximum clock frequency 92 92 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per channel notes 1 and 2 26 28 pF

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 ORDERING AND PACKAGE INFORMATION PINNING TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE 74HC/HCT652N 24 DIL plastic SOT101L 74HC/HCT652D 24 SO plastic SOT137A SYMBOL PIN DESCRIPTION CP AB 1 A to B clock input SAB 2 select A to B source input OE AB 3 output enable A to B input A0..A7 4..11 A data inputs/outputs GND 12 ground (0 V) B 7..B0 13..20 B data inputs/outputs OE BA 21 output enable B to A input SBA 22 select B to A source input CP BA 23 B to A clock input VCC 24 positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH transition 2. The data output functions may be enabled or disabled by various signals at OE AB and OE BA inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. INPUTS (1) DATA I/O(2) OPERATION OR FUNCTION OE AB OE BA CP AB CP BA SAB SBA A 1 THRU A 8 B 1 THRU B 8 HC/HCT652 L H H or L H or L X X Input Input Isolation LH ↑↑ X X Store A and B data XH ↑ H or L X X Input Not specified Store A, Hold B HH ↑↑ L X Input Output Store A in both registers L X H or L ↑ X X Not specified Input Hold A, Store B LL ↑↑ X L Ouput Input Store B in both registers LLXX X L Ouput Input Real Time B Data to A Bus L L X H or L X H Stored B Data to A Bus HHX X L X Input Output Real Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus Fig.4 Functional diagram.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 Fig.5 Logic diagram.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver I CC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL = 50 pF. SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS+25 −40 to+85 −40 to+125 tPHL /tPLH propagation delay An, Bn to Bn, An 135 170 205 ns 2.0 4.5 6.0 Fig.6 t PHL /tPLH propagation delay CP AB , CPBA to Bn, An 190 240 285 ns 2.0 4.5 6.0 Fig.7 t PHL /tPLH propagation delay SAB , SBA to Bn, An 195 245 295 ns 2.0 4.5 6.0 Fig.8 t PZH /tPZL 3-state output enable time OE AB ,OE BA to An, Bn 150 190 225 ns 2.0 4.5 6.0 Fig.9 t PHZ /tPLZ 3-state output disable time OE AB ,OE BA to An, Bn 150 190 225 ns 2.0 4.5 6.0 Fig.9 t THL /tTLH output transition time− ns 2.0 4.5 6.0 Figs 6, 8 t W clock pulse width HIGH or LOW CP AB or CPBA 100 120 ns 2.0 4.5 6.0 Fig.7 t su set-up time An, Bn to CPAB , CPBA 100 125 150 ns 2.0 4.5 6.0 Fig.7 t h hold time An, Bn to CPAB , CPBA ns 2.0 4.5 6.0 Fig.7 f max maximum clock pulse frequency 6.0 4.8 4.0 MHz 2.0 4.5 6.0 Fig.7

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver I CC category: MSI. Note to the HCT types The value of additional quiescent supply current (ΔICC ) for unit a load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL = 50 pF. INPUT UNIT LOAD COEFFICIENT SAB , SBA 0.75 A0 to A7 and B0 to B7 0.75 CP AB , CPBA 1.50 OE AB 1.50 OE BA 1.50 INPUT PARAMETER Tamb (°C) UNIT TEST CONDITIONS +25 −40 to+85 −40 to+125 VCC (V) WAVEFORMS tPHL /tPLH propagation delay An, Bn to Bn, An − 16 27 − 34 − 41 ns 4.5 Fig.6 tPHL /tPLH propagation delay CP AB , CPBA to Bn, An − 23 39 − 49 − 59 ns 4.5 Fig.7 tPHL /tPLH propagation delay SAB , SBA to Bn, An − 27 46 − 55 − 66 ns 4.5 Fig.8 tPZH /tPZL 3-state output enable time OE AB ,OE BA to An, Bn − 18 33 − 41 − 50 ns 4.5 Fig.9 tPHZ /tPLZ 3-state output disable time OE AB ,OE BA to An, Bn − 16 35 − 44 − 53 ns 4.5 Fig.9 tTHL /tTLH output transition time− 51 2 − 15 − 18 ns 4.5 Fig.6, 8 tW clock pulse width HIGH or LOW CP AB or CPBA 16 6 − 20 − 24 − ns 4.5 Fig.7 tsu set-up time An, Bn to CPAB , CPBA 10 5 − 13 − 15 − ns 4.5 Fig.7 th hold time An, Bn to CPAB , CPBA 5 −2 − 6 − 8 − ns 4.5 Fig.7 fmax maximum clock pulse frequency 30 83 − 24 − 20 − MHz 4.5 Fig.7

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delay times and the output transition times. (1) HC: VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.7 Waveforms showing the An, Bn to CPAB , CP BA set-up and hold times, clock CPAB , CP BA pulse width, maximum clock pulse frequency and the CPAB , CPBA to output Bn, An propagation delays. (1) HC: VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.8 Waveforms showing the input SAB , SBA to output Bn, An propagation delay times and the output transition times. (1) HC: VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.9 Waveforms showing the output enable inputs (OEAB ,OE BA ) to outputs An, Bn enable and disable times and the input rise and fall times. (1) HC: VM = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652

APPLICATION INFORMATION

Fig.10 Application information.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.